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IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 1, JANUARY 2009

High Performance 70-nm Germanium pMOSFETs With Boron LDD Implants Geert Hellings, Jerome Mitard, Geert Eneman, Brice De Jaeger, David P. Brunco, Denis Shamiryan, Tom Vandeweyer, Marc Meuris, Marc M. Heyns, and Kristin De Meyer

Abstract—Ge pMOSFETs with gate lengths down to 70 nm are fabricated in a Si-like process flow. Reducing the LDD junction depth from 24 to 21 nm effectively reduces short-channel effects. In addition, a reduced source/drain series resistance is obtained using pure boron LDD implants over BF2 , resulting in a significant ION boost. Benchmarking shows the potential of Ge to outperform (strained) Si, well into the sub-100-nm regime. The 70-nm devices outperform the ITRS requirements for ION by 50%, maintaining similar IOFF , as measured at the source. Index Terms—Benchmarking, germanium, LDD, MOSFETs.

I. I NTRODUCTION

G

ERMANIUM has emerged as a promising high mobility channel material for future nanoscale pMOS [1]. Previously, we published high performance 125-nm high-k/metal gate Ge pMOS devices in a Si-compatible process flow [2], [3]. Other groups reported 60-nm Ge devices with full NiGe source/drain (S/D) regions [4] or 70-nm devices on Ge-oninsulator (GOI) substrates [5], [6]. In this letter, we present high performance Ge pMOSFETs with physical LG down to 70 nm. Different LDD (or extensions) implant conditions are compared, and the performance of the 70-nm device is benchmarked to (strained) Si and ITRS. Section II describes the device fabrication. Section III discusses electrical results and different LDD implant conditions. Section IV focuses on benchmarking and Ge pMOS scalability.

Manuscript received October 8, 2008. Current version published December 24, 2008. The review of this letter was arranged by Editor A. Chatterjee. G. Hellings is with the Interuniversity Microelectronics Center, 3001 Leuven, Belgium, and with ESAT-INSYS, University of Leuven, 3000 Leuven, Belgium, and receives a PhD grant from the Institute for the Promotion of Innovation by Science and Technology in Flanders (IWT-Vlaanderen), 1000 Brussels, Belgium (e-mail: [email protected]). J. Mitard and K. De Meyer are with the Interuniversity Microelectronics Center, 3001 Leuven, Belgium, and also with ESAT-INSYS, University of Leuven, 3000 Leuven, Belgium. G. Eneman is with the Interuniversity Microelectronics Center, 3001 Leuven, Belgium, and with ESAT-INSYS, University of Leuven, 3000 Leuven, Belgium, and also with Research Foundation-Flanders (FWO), 1000 Brussels, Belgium. B. De Jaeger, D. Shamiryan, T. Vandeweyer, and M. Meuris are with the Interuniversity Microelectronics Center, 3001 Leuven, Belgium. D. P. Brunco is an Intel asignee to the Interuniversity Microelectronics Center, 3001 Leuven, Belgium. M. M. Heyns is with the Interuniversity Microelectronics Center, 3001 Leuven, Belgium, and also with MTM, University of Leuven, 3000 Leuven, Belgium. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2008.2008824

Fig. 1.

TEM image of an LG = 70 nm Ge pMOSFET.

II. D EVICE F ABRICATION pMOSFET devices were fabricated on 200-mm Ge-onsilicon wafers from ASM America, consisting of a 1.5-µm relaxed epitaxial Ge layer grown directly on Si. The wafers were first annealed at 850 ◦ C for 3 min to reduce the threading dislocation density to ∼107 cm−2 [1]. The basic Si-compatible process flow is described in [3]. A phosphorus channel doping of ∼3 × 1017 cm−3 was implanted, followed by deposited SiO2 isolation. The Ge surface is passivated by an ultrathin partially oxidized epitaxial Si layer, as described in [1] and [7], and capped with 4-nm HfO2 , after which a TaN/TiN metal gate is deposited. Arsenic halos are implanted (80 keV; 15◦ tilt; 5 × 1013 cm−2 ). BF2 (11 keV; 8 × 1014 cm−2 ), BF2 (9 keV; 8 × 1014 cm−2 ), and pure boron (2.47 keV; 8 × 1014 cm−2 ) LDDs were implanted. The LDD junction depths are estimated to be 24, 21, and 24 nm, respectively, based on process simulations [8]. Spacer definition and HDD implants are followed by NiGe S/D formation (5-nm Ni deposited and 2-RTP flow [1]) and TiN/Ti/Al/TiN back-end processing [9]. Fig. 1 shows a Ge pMOS with a physical gate length of ∼70 nm. It is noted that, during the NiGe module, small voids are formed next to the spacers, probably resulting in increased S/D series resistance. Their cause is still under investigation. III. R ESULTS AND D ISCUSSION This section focuses on the evaluation of Ge pMOSFETs and on the smallest devices (LG = 70 nm) in particular. Fig. 2 shows the IS –VG and ID –VG characteristics for a 70-nm Ge pMOSFET with pure boron LDDs for different VDS ’s. A saturation drive current of 467 µA/µm is obtained for VG −VT = −0.66 V and VDS = −1 V, with an OFF-state current of

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HELLINGS et al.: HIGH PERFORMANCE 70-nm GERMANIUM pMOSFETs WITH BORON LDD IMPLANTS

Fig. 2. Source and drain currents as a function of VG for an LG = 70 nm Ge pMOSFET.

2 × 10−8 A/µm at VG −VT = 0.34 V, evaluated at the source. While IOFF is conventionally measured at the drain, Ge, with its smaller bandgap, suffers from higher diode leakage at the drain/well junction than equivalent Si devices [1], [10] due to increased trap-assisted-tunneling mechanisms. Unfortunately, our test devices typically have drain areas of AA = 148 µm2 , which are decades larger than those used for deep submicrometer devices. Measurements on devices with different drain areas have shown that the drain leakage varies with this area. Thus, evaluating IOFF at the drain for our devices would result in a gross overestimation for realistic device dimensions. Therefore, IOFF is measured at the source rather than estimating its value for small active areas (an extrapolation over several orders of magnitude). Nevertheless, the drain measurements are also included in further benchmarking in this work. In addition, alternative architectures with Ge channel were demonstrated, reducing diode leakage at the drain, e.g., GOI [5], [6]. The effective oxide thickness (EOT) of the gate stack is 1.4 nm while gate leakage is less than 10−3 A/cm2 at VG = VT + 0.6 V. The VT is ∼0 V for long-channel devices and on target for logic applications at ∼−0.2 V for 70-nm devices (Fig. 2). This lower VT is the result of halo implants, which dominate for the short devices. Long-channel VT can be lowered by increasing the well doping. Halo implants and well doping can thus be optimized together to obtain a flat VT [1]. Fig. 3 shows the ION –IOFF relationship for Ge pMOSFETs evaluated at the source. To allow off-target VT , the VG swing is shifted such that ION and IOFF are measured at VG −VT = −2/3 |VDD | and +1/3 |VDD |, as suggested by [11] (VDD = −1 V). A comparison with our previously published 125-nm devices shows successful scaling. Other references were added for comparison, including Ge pMOSFETs with full NiGe-S/D (LG = 60 nm) [4] and on GOI substrates [5], [6]. Comparing the different LDD implant conditions, two effects can be observed. First, reducing the BF2 LDD energy from 11 to 9 keV results in a decrease of IOFF , with similar ION and reduced DIBL (from 186 to 124 mV/V), indicating better shortchannel behavior. Second, changing the LDD species from BF2 to boron results in 8% ION boosts and slightly reduced IOFF . DIBL is also lower (138 mV/V) for the pure boron LDD, indicating that the ION boost does not result from a reduced electrical LG . To pinpoint the cause, the series resistance Rs

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Fig. 3. ION –IOFF for the Ge pMOSFETs at VDD = 1 V, evaluated at the source, and comparison with literature. A boost in ION by using pure boron for the LDD implants can be observed.

Fig. 4. Intrinsic gate delay as a function of ION /IOFF ratio and (inset) gate length for Ge and strained Si pMOSFETs.

was extracted using the method described in [12]. It was found that using the 2.47-keV pure boron implant instead of the 11-keV BF2 decreased Rs from 145 to 100 Ω · µm. The same has been reported for FinFETs in [13]: The higher amorphization by BF2 with respect to B causes increased Rs . Using a linear approximation, the Rs decrease accounts for an ∼5% ION increase, which is quite close to the observed boost. From these experiments, it is clear that careful LDD engineering can significantly improve short-channel effects and general device performance. For the remainder of this letter, we will focus on the Ge pMOSFET with pure boron LDDs. IV. B ENCHMARKING AND S CALABILITY An important question for Ge is whether its high mobility translates into high performing short-channel devices, as compared to Si. For aggressively scaled devices, carrier saturation can be a key limiter for device performance. However, [14] has shown that velocity is higher in Ge compared to Si (maintaining similar parasitic effects). Here, our Ge pMOSFETs are compared with strained Si using benchmarks proposed in [11]. Fig. 4 shows the intrinsic gate delay as a function of the ION /IOFF ratio for our devices, in our previous work [3], and a strained Si reference [15] (ION = 422 µA/µm; EOT = ∼1.2 nm). Our 70-nm Ge device offers a significant improvement over the 80-nm strained Si device for any ION /IOFF ratio up to 4 × 104 . A second metric is the intrinsic gate delay as a function of LG (inset of Fig. 4). Also here, a benefit of Ge

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IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 1, JANUARY 2009

TABLE I COMPARISON OF KEY PARAMETERS FOR A Ge pMOSFET AND THE ITRS SPECIFICATION FOR A PHYSICAL LG = 65 nm

with respect to strained Si can be observed. A third metric is the (linear) subthreshold slope (SS) as a function of LG (not shown). For our Ge devices, the SS is constant at ∼120 mV/dec. The high constant value indicates that further optimization of the gate stack is required, while it prevents drawing conclusions in the short-channel control of the SS at present. The fourth benchmark is the energy-delay product as a function of LG . An additional plot for this metric is not provided, as it will show a similar trend as in Fig. 4 (inset) but with slightly more benefit for Ge: The energy-delay product equals the gate delay times CV 2 , a factor which equals 1.4 × 10−15 , 2 × 10−15 , and 2.5 × 10−15 FV2 /µm for the 70-nm Ge, 80-nm strained Si, and 125-nm Ge device, respectively. The significance of this benchmarking exercise is that it indicates that the higher mobility of Ge translates into more ION and faster devices, even for sub-100-nm LG . This suggests that Ge devices can still be scaled further while maintaining an advantage over strained Si. Comparing our Ge pMOS with ITRS specifications (LG = 65 nm, i.e., 130-nm node) demonstrates the performance advantage. Table I summarizes the data and conditions of this comparison. The Ge device exceeds the ION requirement by almost 50%, maintaining similar IOFF . A second comparison shows that the Ge pMOSFET can reach these ITRS specifications (ION = 432 µA/µm) at a reduced VDD of 0.95 V, resulting in an ∼40% reduction in active power dissipation, owing to VDD scaling (P = f CV 2DD ). This performance is obtained despite the still slightly larger physical LG for the Ge devices. Further enhancements to the Ge device such as the introduction of strain can still be undertaken, suggesting that there is still plenty of headroom for future improvements. V. C ONCLUSION Ge pMOSFETs with gate lengths down to 70 nm were presented. Reducing the LDD junction depth from 24 to 21 nm effectively reduces short-channel effects. In addition, a reduced S/D series resistance was obtained using pure boron LDD implants over BF2 , resulting in a significant ION boost. Benchmarking shows the potential of Ge to outperform (strained) Si, well into the sub-100-nm regime. The 70-nm devices outperform the ITRS requirements for ION by 50%, maintaining a similar IOFF , as measured at the source. In addition, the Ge device matched these ITRS specifications at a reduced VDD of 0.95 V, resulting in an ∼40% reduction in active power dissipation, owing to VDD scaling.

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