High Voltage MOSFET model in ADMS By Kerwin O. Khu B.S. in Electronics and Communications Engineering University of the Philippines, 2000

SUBMITTED TO THE SMA OFFICE IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF

MASTER OF SCIENCE IN HIGH PERFORMANCE COMPUTATION FOR ENGINEERED SYSTEMS AT THE SINGAPORE-MIT ALLIANCE JULY 2004

Signature of author: _____________________________________________________________ HPCES Programme June 2004 Certified by: ___________________________________________________________________ Assoc. Prof. Le-Wei Li SMA Fellow, NUS Dissertation Supervisor Accepted by: __________________________________________________________________ Assoc. Prof. Boo Cheong Khoo Programme Co-Chair HPCES Programme Accepted by: __________________________________________________________________ Prof. Anthony T. Patera Programme Co-Chair HPCES Programme

ACKNOWLEDGEMENTS: I would like to acknowledge the following: My supervisor at the Institute of Microelectronics, Dr. Lin Fujiang, for all his help. Chartered Semiconductor Manufacturing, for providing a sample wafer. Laurent Lemaitre of Motorola, for his help with using ADMS. Cadence Design Systems, for sharing their CMI code. My friends and colleagues at the SMA Atheneum, who made life more bearable. And of course, SMA, which made all this possible.

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TABLE OF CONTENTS: Abstract ............................................................................................................................... 4 Chapter 1: Introduction ....................................................................................................... 5 1.1 High Voltage MOSFET Model in ADMS ................................................................ 5 1.2 Motivation of the work ............................................................................................. 5 1.3 Objectives of the work .............................................................................................. 5 1.4 Organization of the report......................................................................................... 5 Chapter 2: Model Equations ............................................................................................... 6 2.1 Overview................................................................................................................... 6 2.2 Ids-Vgs relationship...................................................................................................... 6 2.3 Ids-Vds relationship...................................................................................................... 6 2.4 Smoothing Function .................................................................................................. 7 2.5 Self-heating ............................................................................................................... 7 2.6 Temperature Effects................................................................................................... 7 Chapter 3: Model Implementation ...................................................................................... 8 3.1 Verilog-A .................................................................................................................. 8 3.2 Automatic Device Model Synthesizer (ADMS) ....................................................... 8 3.3 Code for High Voltage MOSFET model .................................................................. 8 Chapter 4: Parameter Extraction....................................................................................... 10 4.1 Overview................................................................................................................. 10 4.2 Measurements ......................................................................................................... 10 4.3 Parameter extraction ............................................................................................... 10 Chapter 5: Results ............................................................................................................. 11 5.1 Typical Result ......................................................................................................... 11 5.2 Ids-Vgs curve and its derivative ................................................................................ 11 5.3 Ids-Vds curve............................................................................................................. 11 5.4 Supported simulators .............................................................................................. 12 Chapter 6: Discussion of Scalability................................................................................. 13 6.1 Overview................................................................................................................. 13 6.2 Simple scaling rule.................................................................................................. 13 6.3 More complicated scaling rule................................................................................ 14 Chapter 7: Future Work .................................................................................................... 18 7.1 Model Improvements .............................................................................................. 18 7.2 Stochastic modeling ................................................................................................ 18 7.3 Small-signal modeling ............................................................................................ 18 Chapter 8: Conclusion....................................................................................................... 19 References......................................................................................................................... 19 Appendix A....................................................................................................................... 20 Appendix B ....................................................................................................................... 23

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High Voltage MOSFET Model in ADMS By Kerwin O. Khu Submitted to the SMA Office on June 2004 In Partial Fulfillment of the Requirements for the Degree of Master of Science in High Performance Computation for Engineered Systems

ABSTRACT An analytical model of a high voltage MOSFET device is presented in this paper. The model is simple and efficient, requiring only a few easily extracted parameters, which makes it suitable for CAD applications. The model is implemented with the new tool, Automatic Device Model Synthesizer (ADMS), for ease of integration into existing simulators. Keywords High voltage MOSFET, analytical model, ADMS

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CHAPTER 1 INTRODUCTION 1.1 High Voltage MOSFET Model in ADMS High voltage MOSFETS are used in driving liquid crystal displays (LCD’s). With increasing popularity of LCD’s in personal computers and in consumer electronics, there is a corresponding need for a better HVMOS model for use in computer-aided circuit design. In this paper, we will develop a custom CAD model using an analytical approach. That is, we will build a model empirically from measured characteristics, with the objective of keeping the equations simple while minimizing the number of parameters. 1.2 Motivation of the work Currently, industry standard models such as BSIM3 provide a poor fit when modeling HVMOS devices. In addition, the parameter extraction procedure required for BSIM3 is very complex. Developing a new model from scratch or making modifications to such a model is often difficult and time-consuming [3]. Another approach is to change the physical meanings of the parameters of a standard model and reinterpret them in a nonstandard way [4]. The main problem of custom models, however, is that they are difficult to integrate into commercial simulators. Our approach addresses this problem by implementing our model using the up-and-coming Automatic Device Model Synthesizer (ADMS) tool [2]. ADMS is based on the open high-level language Verilog-A, from which it generates C code for specific simulators. 1.3 Objectives of the work To demonstrate a technique for rapidly develop models for new devices or other devices which do not have standard models. Specifically, we develop a simple and efficient model for a HVMOS large-signal transistor. We also show that the ADMS tool can be used to easily integrate such new models into popular simulators. 1.4 Organization of the report Model Equations Model Implementation Parameter Extraction Results Discussion of Scalability Future Work Conclusion

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CHAPTER 2 MODEL EQUATIONS 2.1 Overview The model equations are based on a previously developed empirical model for HVMOS devices [1]. This model assumes that the source and bulk nodes are shorted. The equations and our modifications are briefly described below. 2.2 Ids-Vgs relationship We start with a variation of the well-known square-law characteristic of the inversion region:

[

]

I dso (V gs ) = A{ln 1 + exp( B (V gs − Vth ) }

2

(1)

Our measured characteristics show however that the Ids-Vgs relationship is highly linear in our sample transistors. Thus, we generalize (1) to this form:

[

]

I dso (V gs ) = A{ln 1 + exp( B (V gs − Vth ) }

Q

(2)

With parameter Q restricted to values between 1 and 2, inclusive, and with the threshold voltage Vth related linearly to Vds,

Vth = Vtho − σ (V ds − V dso )

(3)

Where Vtho is the threshold voltage measured at Vds = Vdso. If we define parameters Ith and Sth such that: I th = I ds

V gs =Vtho

and S th = ∂I ds

∂V gs

(4) V gs =Vtho

Then we can express A and B as:

A = I th /(ln 2) Q and B = 2S th (ln 2) / Q ⋅ I th

(5)

Thus, (2) can be defined with three easily extracted physical parameters Vtho, Ith, and Sth. 2.3 Ids-Vds relationship On the other hand, the saturation region of the Ids-Vds curve can be approximated with the hyperbolic tangent function: 6

I max (Vds ) = I sat (1 + λVds ) tanh(αVds )

(6)

The saturation current term Isat can be treated as a physical parameter by extrapolating the maximum Ids for Vds = Vdso; however, we find that we generally get better results by treating it weakly as a fitting parameter. 2.4 Smoothing Function A smoothing function for combining the terms in (2) and (6) is the following [1]: −1 −1 I ds (V gs , Vds ) = ( I dso + I max ) −1

(7)

We add a parameter n to (7) for better fitting: −n − n −1 / n I ds (V gs , Vds ) = ( I dso + I max )

(8)

n n I ds (V gs , Vds ) = I dso I max /( I dso + I max )1 / n

(9)

or

The form of (9) is preferred since it provides continuity when the drain voltage Vds = 0. 2.5 Self-heating We provide a simplified treatment of the self-heating effect by adding a fitting parameter pT as the self-heating coefficient:

I ds ( pT ) = I ds1 /(1 + p T V ds I ds1 )

(10)

This term adjusts the current downwards when Vds is high. 2.6 Temperature Effects The temperature dependence can be modeled by the following modifications to the threshold voltage and saturation current equations: Vth (T ) = Vth (Tnom ) + VT 1 (T − Tnom ) + VT 2 (T − Tnom ) 2

(11)

I sat (T ) = I sat (Tnom ) + I T (T − Tnom )

(12)

Where Tnom is the temperature at which measurements were taken.

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CHAPTER 3 MODEL IMPLEMENTATION 3.1 Verilog-A The model equations are encoded in the Verilog-A language, which is the analog-only subset of the Verilog-AMS language [5]. Verilog-A is a high level language for modeling the behavior of analog systems. There are 2 important reasons for choosing this language: First, Verilog-A is an industry standard language. There is no danger of being locked into a proprietary format. Second, it is the language used by the ADMS tool [2], described next. 3.2 Automatic Device Model Synthesizer (ADMS) ADMS is a model compiler. It takes as input a Verilog-A description of a model and produces C code that compiles directly into a target simulator [3]. The generated C code is then compiled with the simulator interface, the end result of which is a model which can be treated as a built-in model of the target simulator. Most commercial simulators already have a mechanism for adding new, user-defined models into the simulation environment. Typically, these models take the form of C files. However, each simulator has its own distinct interface, such as the CMI interface of the Cadence Spectre simulator. Thus, it would require a lot of unnecessary work to port a new model to different simulators. We will get around this problem by using the ADMS tool. 3.3 Code for High Voltage MOSFET model Verilog-A is a high-level language, which means that model equations can easily be coded in a compact form, as shown in the sample description in Fig. 1. // VerilogA for mylib, hvmos1, veriloga `include "constants.h" `include "discipline.h" `define T_nominal 27 module hvmos1(g, s, d); inout g, s, d; electrical g, s, d; parameter parameter parameter parameter

real real real real

ith=4.806u, sth=47.67u, vth=1.583; isat=3.54m, n=3.392, vdso=10; alpha=0.1359, lambda=0, sigma=3.047m, q=1.31; T=27, vT1=0, vT2=0, iT=0, pT=0;

real vgs, vds, vgd; //voltages //temporary vars

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real idso, imax, delta_T, vth1, isat1, ids1, tmp; analog begin vgs = V(g,s); vds = V(d,s); vgd = V(g,d); // DC I-V part delta_T = T - `T_nominal; vth1 = (vth-sigma*(vds-vdso))+vT1*delta_T+vT2*pow(delta_T,2); isat1 = isat + iT*delta_T; inot = (ith/pow(ln(2),q))* pow(ln(1+exp(2*sth*ln(2)*(vgs-vth1)/(q*ith))),q); tmp = alpha*vds; imax = isat1*(1+lambda*vds)* (exp(tmp)-exp(-tmp))/(exp(tmp)+exp(-tmp)); //tanh ids1 = (inot*imax)/pow(pow(inot,n)+pow(imax,n),1/n); I(d,s) <+ ids1/(1+pT*vds*ids1); end endmodule

Fig. 1. Verilog-A description of HVMOS model

Note that it is possible to read the model equations from the previous chapter directly from the model code.

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CHAPTER 4 PARAMETER EXTRACTION 4.1 Overview The process of parameter extraction begins with detailed measurement of the device to be modeled. For MOSFET’s, the quantities measured are typically the Ids-Vgs and Ids-Vds characteristics. Next, appropriate parameters to the model equations must be found that will match the measured characteristics as closely as possible. This is the process known as parameter extraction [6]. Note that the model for a particular device is defined solely by its set of model parameters. 4.2 Measurements Measurements were done using the Agilent Semiconductor Parametric Analyzer (4156C). For Ids-Vgs, the drain voltage Vds was kept constant at 10 V, while the gate voltage Vgs was swept from 0 to 20 V in steps of 0.5 V. This measurement was kept simple since we only intend to extract initial parameter values from it. For Ids-Vds, the drain voltage Vds was swept from 0 to 20 V in steps of 0.5 V, while the gate voltage Vgs was set to values ranging from 0 to 16 V in steps of 1 V. This generates the familiar Ids-Vds family of curves for transistors. This is the main measurement to which we wish to match our model. We also calculate the transconductance Gm (= ∂Ids/∂Vgs) from the Ids-Vgs curve and treat it as data to be matched. This is useful since matching the derivative of the measured data implies a very good match for the model. 4.3 Parameter extraction First step of parameter extraction is to extract initial values for the physical model parameters Vtho, Ith, and Sth from the Ids-Vgs data. The value for Vtho is determined by using the linear method; that is, projecting the linear part of the Ids-Vgs curve to the x-axis. The point of intersection is taken to be Vtho. Ith and Sth are then taken to be the Ids and Gm values, respectively, at Vgs = Vtho. The extraction of the rest of the parameters, as well as optimization of the physical parameters, is done by means of the commercial software Agilent IC-CAP [7]. This software uses the Levenberg-Marquardt (LM) algorithm, which seeks to minimize the sum of squares of the error between the measured and modeled data. The LM method is in fact a combination of Gauss-Newton and steepest descent, which has been found to be effective in solving the least squares problem [8]. The first step is important though because the optimization problem is nonconvex, and hence might not converge or would converge to very strange values if the initial guess is not close enough.

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CHAPTER 5 RESULTS 5.1 Typical Result Here we show typical results obtained from modeling 0.35-μm technology 12.5V HVMOS devices. The particular device is a W = 10 μm NMOS transistor. The parameters were computed using IC-CAP for the particular device. Table 1. Simulated Parameter Values (gate width 10 μm)

Vtho, V Ith, A Sth, A/V Isat, A Vdso, V α, 1/V λ, 1/V n Q σ pT

1.707 2.08 x 10-5 5.006 x 10-5 3.732 x 10-3 10 1.206 x 10-1 0 4.193 1.258 1.77 x 10-2 1.832

5.2 Ids-Vgs curve and its derivative

Our model’s Ids-Vgs and Gm characteristics shows a reasonable match to the actual data using the parameters listed in Table 1 above. A good match of the transconductance Gm is important both because it implies a good DC match and because it is an important property in itself in analog design. 5.3 Ids-Vds curve 11

The Ids-Vds curve shows that our model is a good match in the saturation region, but is not as good in the triode region. Note also that at low Vgs and high Vds, we start to see the breakdown effect of the transistor. Some modification of the model equations needs to be done to extend the accuracy of the model. 5.4 Supported simulators Currently, the C model generated by ADMS for the Cadence Spectre simulator has been verified. C models for the Agilent ADS simulator and other popular simulators will also be verified.

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CHAPTER 6 DISCUSSION OF SCALABILITY 6.1 Overview We wish to show how the model scales with regards to a change in length (L) or width (W) parameters of a modeled transistor. This is particularly important for circuit design, since the L and W parameters are the chief design tools for a circuit designer. An alternative method to implement scalability is to measure and extract parameters for many different-sized transistors. These parameters can then be placed in the form of a lookup table, referenced by different L and W parameters. The circuit designer can then interpolate the parameters for the desired transistor size based on the table. However, this method is quite cumbersome, and does not necessarily produce accurate results. We explore other methods to incorporate the size parameters into the model equation. 6.2 Simple scaling rule A simple rule that can be derived from device physics is to use a simple scale ratio of the width (W) and length (L) parameters with the output current Ids [9]. That is, if the dimensions vary only by a few factors, we can say that the drain current Ids is roughly proportional to the factor (W/L). To show how the model scales using this rule, we compare our previous results with the results for a device with half the gate width (5 μm). Thus, we expect that for the same parameters, drain current of the 5 μm gate width device would be half of the 10 μm width device. Or, equivalently, halving the current-related parameters should give the correct simulation result. Table 2. Simulated Parameter Values (gate width 5 μm)

Ith, A Sth, A/V Isat, A

1.04 x 10-5 2.503 x 10-5 1.866 x 10-3

The parameters in Table 2 are obtained simply by multiply the Ith, Sth, and Isat parameters in Table 1 by 0.5. All other parameters remain unchanged from Table 1. We then compare the modeled values using the parameters in Table 2 with the measured characteristics of the device, obtaining the results below:

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The figures above show the measured vs. simulated data for a 5 μm width transistor obtained by halving Ith, Sth, and Isat parameters of the 10 μm width model, while maintaining the values of the other parameters. Clearly, the fit is not as good, but that’s expected from using a simple scale rule. The model parameters are at least roughly scalable and should provide a good starting point for optimization. Note though that this might not be valid for a large change in dimensions; i.e. small-dimension effects for example won’t necessarily be accounted for by this scaling rule. 6.3 More complicated scaling rule We try to add or modify parameters to take the L and W effects into account. We change 3 parameters to be functions of length L as follows:

Vth ' = Vth ⋅ (1 + A ⋅ L ) Q ' = Q ⋅ (1 + B / L )

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(13) (14)

α ' = α ⋅ (1 + C / L )

(15)

Substituting these new values to equations (2), (5), (6), and (9), we now get: I dso

⎧⎪ ⎡ ⎤ ⎫⎪ 2 ⋅ ln 2 ⋅ S th = I th ⎨ ln ⎢1 + exp( (V gs − Vth ' ) ⎥ ⎬ Q '⋅I th ⎪⎩ ⎣ ⎦ ⎪⎭

Q'

(16)

I max = I sat tanh(α 'Vds )

(17)

n n I ds (V gs ,Vds ) = W ⋅ I dso I max /( I dso + I max )1 / n

(18)

The W factor in (18) comes from the simple scaling rule. Put together, these are now the “scalable” form of the model equation. Note that 3 parameters were added (A, B, C) and some redundant ones (λ, σ, pT) were removed. The last 3 were considered redundant since their fitted values became 0. The new parameters (as computed by IC-CAP) fitted over several devices are listed below. Table 3. Simulated Parameter Values

Vth, V Ith, A Sth, A/V Isat, A α, 1/V n Q A B C

7.147 x 10-2 4.507 x 10-7 4.726 x 10-6 3.320 x 10-6 1.203 x 10-1 3.011 1.166 9.475 7.884 x 10-2 5.966 x 10-1

Results for several different-sized devices are shown next: Id-Vg curves:

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Gm-Vg curves:

Id-Vd curves:

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The results show good matching for 4 different devices with dimensions (WxL): 25x3, 5x3, 10x1.1, and 10x3, using the parameters listed in Table 3. The main disadvantage of using this technique is that the physical meaning of the parameters Vth, Ith, and Sth have been lost. The modification in the equations was done numerically, rather than through sound physics. This leads to a second disadvantage, which is that the model equation/model parameters might not capture the behaviors which are not measured. The technique can in fact be thought of as using the measured devices’ characteristics as basis functions or basis characteristics by which all other devices are based. If the set of measured devices is incorrectly chosen, the model equation might not be valid over a wide range of devices.

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CHAPTER 7 FUTURE WORK 7.1 Model Improvements As noted in the previous section, the accuracy of the model can still be improved. One area of improvement is to take into account the substrate current induced body effect (SCBE), which is the effect responsible for avalanche breakdowns in MOSFET’s. As suggested in [10], this effect can be modeled as a substrate current Isub which is added to the drain current Ids. Furthermore, to model the snapback effect of the substrate current, [11] suggests that we can set the breakdown parameter as a linear function of Vgs. Another area of improvement is the triode region of the Ids-Vds curves. The measured data shows that the "knee" voltages of the Ids-Vds curves are more strongly a function of gate voltage Vgs than the model currently indicates. 7.2 Stochastic modeling The parameter extraction process described previously uses measurements from one device only. However, there are typically process variations in different transistors from the same wafer. A model that matches one transistor exactly might not match a transistor from the same batch. The standard approach is to make many measurements, and to use the average of the measurements as the data to be matched. This, however, is a tedious process. An alternative method is to generate variations of “measured” data using Monte Carlo simulations. Another possible method is to use a stochastic form of LM optimization to match the model to a range of data values instead of a single set of data. 7.3 Small-signal modeling In addition to the DC characteristics modeled, the CV characteristics can also be measured and modeled using the same approach for use in RF circuits. However, RF parameter extraction is significantly more difficult than the DC extraction already done [12]. The task is further complicated by the lack of RF test structures in the sample wafer being used.

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CHAPTER 8 CONCLUSION An efficient, simple, scalable HVMOS large-signal model has been developed. The technique used here can be generalized to rapidly develop models for other devices which do not have standard models. The ADMS tool can be used to easily integrate such new models into popular simulators. It must be noted though that there are many different MOSFET models available [13]. Depending on the application, development of a custom model may not be necessary, and it might be easier to simply adapt an existing model.

REFERENCES [1] A. V. Grebennikov and F. Lin, "An Efficient CAD-Oriented Large-Signal MOSFET Model," IEEE Trans. Microwave Theory and Techniques, Vol. 48, No. 10, October 2000. [2] L. Lemaitre, C. McAndrew, S. Hamm, "ADMS - Automatic Device Model Synthesizer," IEEE Custom Integrated Circuits Conference, 2002. [3] K. Kundert, "Automatic Model Compilation: An Idea Whose Time Has Come," http://designers-guide.com/Opinion/modcomp.pdf, May 2002. [4] T. Myono, et al, "High-Voltage MOS Device Modeling with BSIM3v3 SPICE Model," IEICE Trans. Electronics, Vol. E82-C, No. 4, 1999. [5] Verilog-AMS Language Reference Manual, Open Verilog International, 1999. [6] M. Keser and K. Joardar, “Genetic Algorithm Based MOSFET Model Parameter Extraction,” International Conference on Modeling and Simulation of Microsystems, pp. 341-344, 2000. [7] IC-CAP 2002 Device Modeling Software, Agilent Technologies, http://eesof.tm.agilent.com/products/85190a-a.html. [8] D. W. Marquardt, “An algorithm for least-squares estimation of nonlinear parameters,” Journal of the Society for Industrial and Applied Mathematics, 11:431-441, 1963. [9] M. Shur, T. Fjeldly, T. Ytterdal, and K. Lee, “Unified MOSFET Model,” SolidState Electronics, Vol. 35, No. 12, pp.1795-1802, 1992. [10] BSIM3v3.2.2 Manual, University of California, Berkeley, 2001. [11] F. Lin, B. Chen, T. Zhou, B. L. Ooi, and P. S. Kooi, "Characterization and modeling of avalanche multiplication in HBTs," Microelectronics Journal 33, pp. 39-43, 2002. [12] M. Je, I. Kwon, H. Shin, and K. Lee, "MOSFET Modeling and Parameter Extraction for RF IC's," International Journal of High Speed Electronics and Systems, Vol. 11, No. 4, 2001. [13] P. Bendix, “Detailed Comparison of the SP2001, EKV, and BSIM3 Models,” International Conference on Modeling and Simulation of Microsystems, pp. 649-652, 2002.

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APPENDIX A “How to Create Models in Verilog-A and ADMS” Manual I. Create Verilog-A model Declare input/output pins Declare parameters Determine relationship of output values to inputs and parameters Example Verilog-A models: Simple resistor: `include “disciplines.vams” module res1 (p, n); inout p, n; electrical p, n; parameter real R = 100; //default value analog begin V(p, n) <+ R * I(p, n); end endmodule

Simple capacitor: `include “disciplines.vams” module cap1 (p, n); inout p, n; electrical p, n; parameter real C = 1n; //default value analog begin I(p, n) <+ ddt(C*V(p, n)); end endmodule

These models are very simple. More complicated models possible include VCO’s, PLL’s, amplifiers, Laplace domain filters, as well as combinations of simpler elements (such as RLC networks, filter banks, etc.) References: Analog Modeling with Verilog-A, Cadence Lecture Manual ver. 5.0 Agilent Verilog-A Reference Manual

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II. Test the Verilog-A model NOTE: If ADMS will be used (Step III), this step is optional. It is still very useful though for verifying new models. A) Cadence In Cadence, create cellview of type veriloga (reference: Analog Modeling with Verilog-A, Cadence Lab Book ver. 4.4.6) Steps: 1) Create new cellview (File –> New –> Cellview) 2) In Create New File form, set Tool to VerilogA-Editor 3) Cancel the Modelwriter form 4) Copy and paste Verilog-A code into the text window. Save and close. 5) If there are errors, a message will appear and will ask if you want to fix your errors. 6) The Symbol Generation form appears after this step. Optionally, the associated symbol can be added by using File –> New –> Cellview with the tool set to Symbol Editor. The Verilog-A model can now be added to the design in the schematic editor. B) Agilent ADS In ADS (must use verilog license of ADS 2003), create veriloga file using any editor, then place in autocompile path (reference: Using Verilog-A in Advanced Design System, Agilent Manual) III. Using ADMS Why use ADMS? For Cadence – Cadence Design Environment already supports Verilog-A. However, the Verilog-A model is interpreted. The performance may be better if the model is compiled. ADMS provides this functionality. For ADS – Verilog-A support requires a separate license. If it is not desired to use the additional license, ADMS can used to provide the same functionality Disadvantage of ADMS 1) Requires additional step by the user (no integrated support) 2) Graphical support (symbol creation) NOT supported. To use, must put in Spice/Spectre netlist file. 3) No syntax checking – if there is an error in Verilog-A file, then ADMS will return strange errors. 4) ADMS still has many bugs.

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Commands to use: (for Cadence Spectre) create_spectre_model The file create_spectre_model is a script file in /home/kerwin/adms. If the install location of ADMS or the Spectre ADMS header file location should change, this file must be edited. The output is the CMI file for the new model, named .so (for ADS) /home/kerwin/ads2002-1.7.1.2/adms-ads2002 hpeesofmake -f hpeesofdynamic.mak The output is the CML file for the new model, named .so IV. Using the new ADMS model in a design For Cadence, one of the generated files is named cmiConfig. In order to use the new model, Spectre must be invoked with the -cmiconfig switch: spectre -cmiconfig cmiConfig. For ADS, the generated CML file should be placed in the following path: /hpeesof/circuit/lib.sun57/ And it will be automatically loaded. For both cases, the new model can only be used with netlist files. Neither Cadence nor ADS has easy built-in support for adding symbols for new models, but it is possible with some effort.

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APPENDIX B IC-CAP routines for optimizing over several devices 1. dc_aggreg/id_vd ! This puts together the measured Id-Vd of 4 devices COMPLEX COMPLEX COMPLEX COMPLEX COMPLEX

Id10_3[33*41] Id10_1_1[33*41] Id25_3[33*41] Id5_3[33*41] Id[4*33*41]

Id10_3 = hvmos/new_dc_10_3/id_vd/Id.m Id10_1_1 = hvmos/new_dc_10_1_1/id_vd/Id.m Id25_3 = hvmos/new_dc_25_3/id_vd/Id.m Id5_3 = hvmos/new_dc_5_3/id_vd/Id.m i = 0 WHILE i < Id[i] = i = i + END WHILE WHILE i < Id[i] = i = i + END WHILE WHILE i < Id[i] = i = i + END WHILE WHILE i < Id[i] = i = i + END WHILE

33*41 Id10_3[i] 1 33*41*2 Id25_3[i-33*41] 1 33*41*3 Id5_3[i-33*41*2] 1 33*41*4 Id10_1_1[i-33*41*3] 1

!ICCAP_FUNC("/","Status WIndow") !PRINT "sim Id values" !i = 0 !WHILE i < SIZE(Id) ! PRINT "Id[";i;"] = ";Id[i] ! i = i + 1 !END WHILE return Id

2. dc_aggreg/sim_id_vd ! This puts together the simulated Id-Vd of 4 devices COMPLEX COMPLEX COMPLEX COMPLEX

sim_Id10_3[33*41] sim_Id10_1_1[33*41] sim_Id25_3[33*41] sim_Id5_3[33*41]

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COMPLEX sim_Id[4*33*41] sim_Id10_3 = hvmos/new_dc_10_3/id_vd/sim_id_vd sim_Id10_1_1 = hvmos/new_dc_10_1_1/id_vd/sim_id_vd sim_Id25_3 = hvmos/new_dc_25_3/id_vd/sim_id_vd sim_Id5_3 = hvmos/new_dc_5_3/id_vd/sim_id_vd i = 0 WHILE i < 33*41 sim_Id[i] = sim_Id10_3[i] i = i + 1 END WHILE WHILE i < 33*41*2 sim_Id[i] = sim_Id25_3[i-33*41] i = i + 1 END WHILE WHILE i < 33*41*3 sim_Id[i] = sim_Id5_3[i-33*41*2] i = i + 1 END WHILE WHILE i < 33*41*4 sim_Id[i] = sim_Id10_1_1[i-33*41*3] i = i + 1 END WHILE !ICCAP_FUNC("/","Status WIndow") !PRINT "sim Id values" !i = 0 !WHILE i < SIZE(sim_Id) ! PRINT "sim_Id[";i;"] = ";sim_Id[i] ! i = i + 1 !END WHILE return sim_Id

3. dc_aggreg/opt - Optimizes dc_aggreg/id_vd vs. dc_aggreg/sim_id_vd - This generates the parameters which are optimal over a range of devices

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