ICTEd_515_1st semester

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Course Title: Computer Architecture Course No. : ICT. Ed 515 Level: M.Ed. Semester: First

Computer Architecture

Nature of course: Theoretical Credit Hour: 3 hours Teaching Hour: 75 hours(45+30)

1. Course Description This course is an introduction to computer architecture and organization. It covers topics in both the physical design of the computer (organization) and the logical design of the computer (architecture). This course discusses the basic structure of a digital computer and deals with the detail study of the organization of the Control unit, the Arithmetic and Logical unit, the Memory unit and the I/O unit.

2. General Objectives The general objectives of this course are as follows: 

  

to provide the organization, architecture and designing concept of computer system including processor architecture, computer arithmetic, memory system, I/O organization and multiprocessors. to discuss in detail the operation of the arithmetic unit including the algorithms & implementation of fixed-point and floating-point addition, subtraction, multiplication & division. to study in detail the different types of control and the concept of pipelining. to study the hierarchical memory system including cache memories and virtual memory. To study the different ways of communicating with I/O devices and standard I/O interfaces.

3.

Course Outlines



Specific Objectives 

Contents

Explain basic of SSI, MSI, LSI circuits, computer families, organization and future trends

Unit I: Introduction

5

1.1 1.2 1.3

 

Explain Arithmetic and Logic unit, instruction sets, addressing modes and formats. Understand processor and register organization, instruction cycle, Pentium processor and Power PC processor.

SSI and MSI circuits VLSI Technology Mile stone in computer organization 1.4 Examples of computer families 1.5 Future trends in computer Unit II: Central Processing unit: Case Study

T

3.1 3.2 3.3 3.4 3.5

ICTEd_515_1st semester

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Arithmetic and Logic unit (ALU) Instruction sets Addressing modes and formats Stack Processor organization

Computer Architecture

ICTEd_515_1st semester

 

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Understand Micro-operations and control of CPU. Explain hardwired implementation, micro-instruction sequencing and execution as well as application of microprogramming.

Computer Architecture

3.6 Register organization 3.7 Instruction cycle 3.8 Pentium processor 3.9 Power PC processor Unit III: Control Unit Design 3.1 3.2 3.3 3.4 3.5 3.6

 

 

 

 

 

Explain addition, subtraction, multiplication and division algorithms. Elaborate different logical operations.

Explain the external devices and I/O modules Elaborate programmed I/O, Interrupt driven I/O direct memory access, I/O channels and processors as well as the external interfaces.

Explain the organization of main, auxiliary, associative, virtual and cache memory. Elaborate on cache memory driving forces and cache design issues including placement, fetch, replacement and update policies

Differentiate between RISC and CISC systems. Explain RISC instructions, processor to memory movement, pipelining with RISC as well as RISC and Cache.

Illustrate parallel processing and pipelining. Explain different pipelining techniques and their hazards.

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Micro-operations Control of CPU Hardwired implementation, Micro-instruction sequencing Micro-instruction execution Application of microprogramming

Unit IV: Computer Arithmetic 4.1 Addition algorithm 4.2 Subtraction algorithm 4.3 Multiplication algorithm 4.4 Division algorithm 4.5 Logical operation Unit V: Input/ Output Organization External devices I/O modules Programmed I/O Interrupt Driven I/O Direct memory access 5.5 I/O channels and processors 5.6 External interfaces Unit VI: Memory Organization

15

12

5.1 5.2 5.3 5.4

Main memory, Auxiliary memory, Associative memory, Virtual memory, Cache memory, Cache memory driving forces, 6.7 Cache design issues, 6.8 Placement, Fetch, Replacement & Update policies. Unit VII: RISC

12

6.1 6.2 6.3 6.4 6.5 6.6

RISC and CISC systems RISC instructions Processor to memory movement 7.4 Pipelining with RISC 7.5 RISC and Cache Unit VIII: Pipelining Techniques

8

7.1 7.2 7.3

8.1 8.2

ICTEd_515_1st semester

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Parallel processing Introduction to pipelining

Computer Architecture

ICTEd_515_1st semester

icted.org.np

Computer Architecture

8.3 8.4 8.5 8.6 

Arithmetic pipelining Instruction pipelining RISC pipelining Pipelining Hazards

Unit IX: Multiprocessors

Illustrate different types of network architecture and their applications.

9.1 9.2 9.3 9.4 9.5

6

Characteristics of multiprocessors Flynn's classification Enslow's classification Interconnection structures Cache coherence

Note: The figure in the parenthesis indicate approximate number of periods allocated for respective units. Part II: Practical Laboratory Work: 1. 2. 3. 4. 5. 6. 7.

Add of two unsigned integer binary number Multiplication of two unsigned integer binary numbers by Partial-Product method Subtraction of two unsigned integer binary number Division using restoring Division using non-restoring methods To simulate a direct mapping cache The student should develop a project on computer Architecture. The topic could be either initiated by the student or selected from a list provided by the instructor. An oral presentation with a demonstration should be part of the laboratory project report.

4

Instructional Techniques The instructional techniques for this course are divided into two groups. First group consists of general instructional techniques applicable to most of the units. The second group consists of specific instructional techniques applicable to specific units.

4.1 General Techniques  

Providing the reading materials to the students to familiarize the units. Lecture, question-answer, discussion, brainstorming, practical, and buzz session.

4.2 Specific Instructional Techniques Unit

Activity and instructional techniques

I to IX

Lecture, Discussion, Practical

ICTEd_515_1st semester

Teaching Hours (30)

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Computer Architecture

ICTEd_515_1st semester

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Computer Architecture

Note: Specific Instructional Techniques may or may not require for each of the units mentioned in course outline.

5 5.1

Evaluation Internal Evaluation 30% Internal evaluation will be conducted by course teacher based on following activities: 1) Attendance 4 points 2) Participation in learning activities 6 points 3) First assignment/midterm exam 10 points 4) Second assignment/assessment (1 or two) 10 points Total 30 points Note: First assignment/assessment might be mid-term exam + assigns or book review or article review or first term paper on specific issue/topic, mid-term exam or unit test and quiz etc according to nature of course. Second assignment/assessment might be project work, case study, seminar, survey/field study and individual/group report writing, term paper based on secondary data or review of literature and documents etc.

First and second assignment/assessment may include one or two types of assessment. For instance, one home assignment/book/article review + mid-term exam or only mid-term exam. In the second assessment may include only one project work/term paper or two type of assignment according to nature of the course.

5.2

External Evaluation (Final Examination) 70% Examination Division, office of the Dean, Faculty of Education will conduct final examination at the end of semester (proposed). 1) Objective type question (Multiple choice 11x11) 11 points 2) Short answer questions (5 questions x 7 points) 35 points 3) Long answer questions (2 questions x 12 points) 24 points Total

6

70 points

Recommended books and reading materials (including relevant published articles in national and international journals) 1. W. Stalling, Computer Organization and Architecture 17 edition, Prentice-Hall India Limited, New Delhi.

ICTEd_515_1st semester

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Computer Architecture

ICTEd_515_1st semester

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Computer Architecture

2. A.J Vande Goor, Computer Architecture and Design, Addison Wesley; Wokingham, UK, 1989 3. A.S Tanenbaum, Structured Computer Organization, Prentice Hall India Limited, new Delhi. 4. M.Morris Mano: Computer System Architecture, Latest Edition. 5. John P. Hayes: Computer Architecture and Organization, Latest Edition. Author (Year of publication). Title of books. Place and publisher. (……… chapter for ….unit). Author (Year of publication). Title of article, Name of Journal. Vol. Number, Page number (For ….. unit) 7

Reference materials Note: Curriculum designers are requested to provide copies of books and reading materials referred in the courses.

ICTEd_515_1st semester

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Computer Architecture

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