(IJEECS) International Journal of Electrical, Electronics and Computer Systems. Vol: 02 Issue: 02, June 2011

Simulation and Implementation of Multilevel Inverter Fed Induction Motor for Performance Improvement Mr. Yogesh S. Bais#1, Dr. S.B.Deshpande*2 #

Lecturer, Electrical Department, Nagpur University Priyadarshini College of Engineering, Digdoh Hills, Hingna Road, Nagpur (INDIA) 1 [email protected] * Principal, Govindrao Wanzari College of Engineering, Salai Godhani, Hudkeshwar Road, Nagpur (INDIA) 2 [email protected]

Abstract— Multilevel inverter (MI) starts from three level. The poor quality of voltage and current of a Conventional Inverter fed Induction machine is due to the presence of harmonics and hence there is significant level of energy losses. The inverters with large number of steps can generate high quality voltage waveforms. In the proposed scheme, a 3-level Diode Clamped Inverter fed induction motor is simulated using SPWM technique to give the 3-level output voltage with lesser distortion resulting in better drive performance. Also the Hardware circuit is prepared using MOSFET as the switching device and Sinusoidal Pulse Width Modulation (SPWM) for Gate triggering circuit. This generates output voltages with less distortion and lesser dv/dt. The multilevel inverter output has reduced harmonics and higher torque. It also reduces the heat generated in the stator winding of the induction motor. The simulation results reveal that the proposed circuit effectively controls the motor speed and enhances the drive performance through reduction in Total Harmonic Distortion (THD). Keywords— Diode clamped, Multilevel Inverter, Induction motor, SPWM technique, THD.

I. INTRODUCTION The inverters which produce an output voltage or a current with levels either 0 or +/- V are known as two level inverters. In high-power and high-voltage applications, these two-level inverters, however, have some limitations in operating at high frequency mainly due to switching losses and constraints of device rating. This is where multilevel inverters are advantageous. Increasing the number of voltage levels in the inverter without requiring higher rating on individual devices can increase power rating. The unique structure of multilevel voltage source inverter’s allows them to reach high voltages with low harmonics without the use of transformers or series-connected synchronized-switching devices. The harmonic content of the output voltage waveform decreases significantly The concept of multilevel inverter control has opened a new possibility that induction motors can be controlled to achieve dynamic performance equally that of dc motors. The performance of the multilevel inverter is better than a classical inverter.

II. MULTILEVEL INVERTERS A multilevel converter has several advantages over a conventional two-level converter that uses high switching frequency pulse width modulation (PWM). The attractive features of a multilevel converter can be briefly summarized as follows. ● Staircase waveform quality: Multilevel converters not only can generate the output voltages with very low distortion, but also can reduce the dv/dt stresses; therefore electromagnetic compatibility (EMC) problems can be reduced. ● Common-mode (CM) voltage: Multilevel converters produce smaller CM voltage; therefore, the stress in the bearings of a motor connected to a multilevel motor drive can be reduced. Furthermore, CM voltage can be eliminated by using advanced modulation strategies such as that proposed in. ● Input current: Multilevel converters can draw input current with low distortion. ● Switching frequency: Multilevel converters can operate at both fundamental switching frequency and high switching frequency PWM. It should be noted that lower switching frequency usually means lower switching loss and higher efficiency. Unfortunately, multilevel converters do have some disadvantages. One particular disadvantage is the greater number of power semiconductor switches needed. Although lower voltage rated switches can be utilized in a multilevel converter, each switch requires a related gate drive circuit. This may cause the overall system to be more expensive and complex. Some inconvenient features can be derived from the increased number of switching devices and voltage sources which means a more complex control strategy. The continuous price reduction in power electronics components and also in digital signal processors can lead to the extension of multilevel technologies to low power applications. The extra number of devices might not necessarily mean an increment of conduction losses. Finally, among the wide variety of proposed MI circuits, the following classification is the most broadly accepted: diode-clamped, capacitor-clamped (flying capacitors) and cascaded multiple-cells (with separate DC sources). There are three basic multilevel converter topologies: diode clamped, flying capacitor, and cascaded H-

©IJEECS

(IJEECS) International Journal of Electrical, Electronics and Computer Systems. Vol: 02 Issue: 02, June 2011 bridge with separate dc sources. Among these topologies, diode-clamped converters are especially interesting because of their simplicity: the multiple voltage levels are generated passively through a set of series-connected capacitors. The diode clamped inverter provides multiple voltage levels from a series bank of capacitors. The voltage across the switches is only half of the DC bus voltage. These features effectively double the power rating of voltage source inverter for a given semiconductor device. III. PROJECT SCHEME A. Overall Simulation Circuit MATLAB Simulink is used to check the performance of Three-level Inverter. Fig. 1 shows the block diagram of 3Level Inverter Fed Induction Motor. It consists of DC source, 3- level Inverter, Induction motor, Gate pulse generator.

Fig. 2 Three level inverter circuit (Subsystem 1)

C. Gate Pulse for the MOSFET

Fig. 1 Simulink Diagram of Three Level Inverter Fed Induction Motor Fig. 3 Circuit Diagram for supplying Gate pulse to Inverter.

B. Subsystem 1—Three Level Inverter Circuit Fig. 2 shows the 3-level diode-clamped inverter. Ports 4 and 6 are the D.C. supply ports. Port 5 is for neutral. Ports 1, 2 and 3 are the output ports for the inverter. There are 12 MOSFETs in the inverter. Each phase has three MOSFET as shown in the figure. Port 1(g) is for the supply of gate signal.

Fig. 4 shows the circuit diagram for supplying of gate pulse for single leg of three legs of inverter. Each leg of inverter consists of four MOSFETs. For the generation of gate signal, the carrier signal (triangular) and the reference signal (sinusoidal) are compared. The carrier signal has frequency 1 KHz. For m-level inverter, the number of triangular wave is (m-1). So, there are two triangular waves one is upper half and another is lower half which is modulated with sine wave to get the gate signal.

©IJEECS

(IJEECS) International Journal of Electrical, Electronics and Computer Systems. Vol: 02 Issue: 02, June 2011

Fig. 5 Generated Gate Pulse for the MOSFETs of Three-Level Inverter for R-phase. ( 0 degree phase shift )

Fig. 4 Gate triggering pulses for inverter (Subsystem 2)

IV. PULSE WIDTH MODULATION (PWM) The gate pulse for MOSFET 1 and MOSFET 3 are compliment of each other. Similarly, the gate pulse for MOSFET 2 and MOSFET 4 are compliment of each other. Similarly for Y and B phases in which reference wave (sine wave) is 120 and 240 degree phase shift with R-phase which are shown as following

Fig. 6 Generated Gate Pulse for the MOSFETs of Three-Level Inverter for

©IJEECS

Y-phase. (120 degrees phase shift)

(IJEECS) International Journal of Electrical, Electronics and Computer Systems. Vol: 02 Issue: 02, June 2011

Fig. 7 Generated Gate Pulse for the MOSFETs of Three-Level Inverter for B-phase. (240 degrees phase shift)

Instead of maintaining the width of all pulses the same as in case of Multiple Pulse Width Modulation, the width of each pulse is varied in proportion to the amplitude of a Sine wave evaluated at the centre of the same pulse. The distortion factor and lower order harmonics are reduced significantly. The gating signals are generated by comparing a sinusoidal reference signal with a triangular carrier wave of frequency Fc. The frequency of reference signal Fr, determines the inverter output frequency and its peak amplitude Ar, controls the modulation index M, and rms output voltage Vo. The number of pulses per half cycle depends on carrier frequency.

Fig. 8 shows the complete circuit of Three-Level Inverter with Gate Triggering Circuit. There are two triangular waves one is upper and the other is lower which is modulated with sine wave to get the gate signal. The gate signal generated on modulation with upper triangular and sine wave is given to MOSFET 1 and MOSFET 3. The gate signal of MOSFET 1 and MOSFET 3 are compliment of each other as shown in the above circuit diagram. Similarly the modulation of lower triangular wave and sine wave gives the gate signal for MOSFET 2 and MOSFET 4. The gate signal of MOSFET 2 and MOSFET 4 are compliment of each other as shown in the above circuit diagram. Same procedure of gate signal is done for other phases. The output of the inverter is given to the three phase induction motor as shown in figure.

Fig. 8 Complete Circuit Diagram of Three-Level Inverter with supply of Gate Signal.

V. HARDWARE DESIGN The hardware design for proposed scheme i.e. for ThreeLevel Inverter is given in this chapter. The complete system will consist of two sections, a Power circuit and a Control circuit. The power section consists of 3-phase DiodeClamped Multilevel Inverter. The motor is connected to it. The pure dc voltage is applied to the Three Phase Multilevel Inverter. The Multilevel Inverter has 12 MOSFET switches that are controlled in order to generate an ac output voltage from the DC input voltage. The control circuit of the proposed system consists of three blocks namely gate signal circuit, opto-coupler and gate driver circuit. To drive the power switches satisfactorily the optocoupler and driver circuit are necessary in between the gate signal generator and multilevel inverter. The block Diagram is as shown.

©IJEECS

(IJEECS) International Journal of Electrical, Electronics and Computer Systems. Vol: 02 Issue: 02, June 2011

Fig. 12 Sine Wave Generator circuit

Fig. 9 Basic block diagram

A. Hardware Design of Gate Signal For generation of gate signal there is need of two triangular waves one is upper triangular wave another is lower triangular of frequency 1 KHz. Then a sinusoidal wave of frequency 50 Hz is needed for the modulation. The proposed hardware is as shown:

Fig. 13 Gate Signal Generator circuit

The IC used for generation of gate signal is LM324.

Fig 10 Upper Triangular Wave Generator circuit

Fig. 13 Pin Configuration for LM324

Fig. 11 Lower Triangular Wave Generator circuit

©IJEECS

(IJEECS) International Journal of Electrical, Electronics and Computer Systems. Vol: 02 Issue: 02, June 2011 VI. RESULTS A. Phase Voltage for 3-Level Inverter

Fig. 14 General LM324 IC (14 Pin)

B. Complete Hardware Design of Gate Signal.

Fig. 16 Phase Voltage of Three Level Inverter Va, Vb and Vc respectively

B. Line Voltage for 3-Level Inverter

Fig. 15 Breadboard circuit of Gate Signal

Now the generated gate signal is given to optocoupler. Optocoupler is used to break the electrical contact. Through optocoupler, each MOSFET of each leg of inverter is individually triggered. Now the signal from the optocoupler is given to Gate Drive circuit which gives the gate signal of that level which is required for turning on the MOSFET. The voltage level of gate triggering for turning on the MOSFET is nearly 12V to 15V which is given by the Gate Drive circuit.

Fig. 17 The Line Voltage of Three-level Inverter Vab, Vbc and Vca respectively

©IJEECS

(IJEECS) International Journal of Electrical, Electronics and Computer Systems. Vol: 02 Issue: 02, June 2011

C. FFT Analysis

From this observation, we conclude that the Total Harmonic Distortion for a 3-level inverter (35.48 %) is considerably less than that of a conventional 2-level inverter (68.64 %). D. Characteristics of Induction Motor

Fig. 18 shows the FFT analysis for Line Voltages of Three-Level Inverter

The THD percentage is 35.48%. Fig. 20 shows the Stator Current, Rotor Speed and Electromagnetic Torque of Induction Motor respectively.

E. Gate Pulse Output

Fig. 19 FFT analysis for Line Voltage of Two-level Inverter

Fig. 21 Gate Pulse on Modulation of Sine Wave with Lower Triangular Wave

The THD percentage is 68.64% ©IJEECS

(IJEECS) International Journal of Electrical, Electronics and Computer Systems. Vol: 02 Issue: 02, June 2011 [6] Nashiren F. Mailah, Senan M. Bashi, Ishak Aris, Norman Mariun. “Neutral-Point-Clamped Multilevel Inverter Using Space Vector Modulation” European Journal of Scientific Research ISSN 1450-216X Vol.28 No.1 (2009), pp.82-91 [7] Mr. G. Pandian and Dr. S. RamaReddy. “Simulation and Analysis of Multilevel Inverter Fed Induction Motor Drive.” Indian Journal of Science and Technology Vol. 2, No. 2, Feb-2009 [8] G. Pandian, S. Rama Reddy, K.N.Srinivasarao. “Performance of 3-level Neutral Clamped PWM Inverter Fed Induction Motor Drive.” International Journal of Electrical and Power Engineering 1(1): 108-113, 2007 [9] C. K. Lee, S. Y. Ron Hui, and Henry Shu-Hung Chung. “A 31-Level Cascade Inverter for Power Applications.” IEEE Transactions on Industrial Electronics, Vol. 49, No. 3, June 2002

[10] Jose Rodríguez, Steffen Bernet, BinWu, Jorge O. Pontt, and Samir Kouro, “Multilevel Voltage-Source-Converter Topologies for Industrial MediumVoltage Drives”. IEEE Transactions on Industrial Electronics, Vol. 54, No. 6, December 2007 [11] P. N. Tekwani, R. S. Kanchan, and K. Gopakumar. “A Dual Five-Level Inverter-Fed Induction Motor Drive with Common-Mode Voltage Elimination and DC-Link Capacitor Voltage Balancing Using Only the Switching-State Redundancy—Part II” IEEE Transactions on Industrial Electronics, Vol. 54, No. 5, October 2007

Fig. 22 Gate Pulse on Modulation of Sine Wave with Upper Triangular Wave

VII. CONCLUSIONS As the results show, the harmonic content is low as compared to Two-level Conventional Type. FFT analysis shows total THD in conventional method and in Three-Level Inverter. From this, it is easily seen that Three-Level converter offers an output voltage with low THD. Multilevel converter can be applied to motor drives. The proposed circuit is intended to effectively control the Drive Performance through reduction in Total Harmonic Distortion. The main advantages of Multilevel Inverter include the following: 1) They are suitable for high-voltage and high current applications. 2) They have higher efficiency because the devices can be switched at low frequency. 3) The harmonics content is low in the output voltage. 4) Generate output voltages with extremely low distortion and lower dv/dt. REFERENCES [1] Brian A. Welchko, Mauricio Beltrao de Rossiter Correa, and Thomas A. Lipo. “A Three-Level MOSFET Inverter for Low-Power Drives”. IEEE Transactions on Industrial Electronics, Vol. 51, NO. 3, June 2004 [2] Samir Kouro, Rafael Bernal, Hernan Miranda., Cesar A. Silva, Jose Rodríguez. “High-Performance Torque and Flux Control for Multilevel Inverter Fed Induction Motors”. IEEE Transactions on Power Electronics, Vol. 22, No. 6, November 2007. [3] Samir Kouro, Jaime Rebolledo, and Jose Rodríguez. “Reduced Switching-Frequency-Modulation Algorithm for High-Power Multilevel Inverters.” IEEE Transactions on Industrial Electronics, Vol. 54, No. 5, October 2007 [4] K. Ramani and Dr. A. Krishnan SMIEEE “An Estimation of Multilevel Inverter Fed Induction Motor Drive.” International Journal of Reviews in Computing. E-ISSN: 2076-331X© 2009 IJRIC. [5] Sergio Busquets-Monge, Salvador Alepuz, Joan Rocabert, and Josep Bordonau. “Pulse Width Modulations for the Comprehensive Capacitor Voltage Balance of n-Level Two-Leg Diode-Clamped Converters.” IEEE Transactions on Power Electronics, Vol. 24, No. 8, August 2009

[12] B. Biswas, S. Das, P. Purkait, M. S. Mandal and D. Mitra. “Current Harmonics Analysis of Inverter-Fed Induction Motor Drive System under Fault Conditions.” Proceedings of the International MultiConference of Engineers and Computer Scientists 2009 Vol. II IMECS 2009, March 18-20, 2009, Hongkong. [13] Narain G. Hingorani and Laszlo gyugvi. Understanding FACTS: Concept and Technology of Flexible AC Transmission System. [14] Muhammad H. Rashid. Power Electronics Circuits, Devices and Applications -- Third edition. [15] Ramakant A. Gayakwad. Op-Amps and Linear Integrated Circuits.

Yogesh S. Bais was born in Yavatmal in May, 1976. He has done his Bachelors in Electrical Engg. in 1997 from RKNEC, Nagpur University, India. He is carrying out his Masters in Electrical Engg. from PCEA, Nagpur University, India. He is currently working as a Lecturer in Electrical Engg. Dept. at PCEA, Nagpur from May 2009 onwards. He has published papers in International and National Conferences. His research interest involves in Power Electronics, Multilevel Inverter, Modelling of Induction Motor and optimization Techniques. He has a total experience of 14 years of working in various positions in Industrial and Teaching fields. He has guided UG students in various projects.

Dr. S.B.Deshpande has done his B.E.(Electrical), M.Tech (Integrated Power Systems) and Ph.D (Engg. & Tech) from Nagpur University, India. He is currently working as Principal in Govindrao Wanzari College of Engg., Nagpur. He has a total Teaching, Research and Industrial experience of 26 years. His areas of specialization are in Power Electronics, Drives and Power System. He has guided 25 UG and PG level Projects till date. He has been Member and Chairman , Board of Studies in Electrical Engineering , RTM Nagpur University. He has also been Member of Academic Council and Member of Research Recognition Committee from 2005- till date. He is a life member of ISTE and Institution of Engineers and a Senior Member IEEE.

©IJEECS

IJEECS Paper Template

Increasing the number of voltage levels in the inverter without requiring higher rating on individual devices can increase power rating. The unique structure of multilevel voltage source inverter's allows them to reach high voltages with low harmonics without the use of transformers or series-connected synchronized-switching.

3MB Sizes 1 Downloads 313 Views

Recommend Documents

IJEECS Paper Template
virtual OS for users by using unified resource. Hypervisor is a software which enables several OSs to be executed in a host computer at the same time. Hypervisor also can map the virtualized, logical resource onto physical resource. Hypervisor is som

IJEECS Paper Template
Department of Computer Science & Engineering ... The code to implement mean filter in java language is as,. //smoothing ... getPixel(r,c); //get current pixel.

IJEECS Paper Template
thin client Windows computing) are delivered via a screen- sharing technology ... System administrators. Fig. 1 Cloud Computing. IDS is an effective technique to protect Cloud Computing systems. Misused-based intrusion detection is used to detect ...

IJEECS Paper Template
Department of Computer Science & Engineering. Dr. B R Ambedkar .... To compute the value that express the degree to which the fuzzy derivative in a ..... Now she is working as a Associate Professor in Computer Science &. Engineering ...

IJEECS Paper Template
not for the big or complex surface item. The example based deformation methods ... its size as it moves through the limb. Transition from each joint, the ellipsoid ...

IJEECS Paper Template
number of power semiconductor switches needed. Although lower voltage rated switches can be utilized in a multilevel converter, each switch requires a related gate drive circuit. This may cause the overall system to be more expensive and complex. Som

IJEECS Paper Template
accidents. Automatic recognition of traffic signs is also important for automated intelligent driving vehicle or driver assistance systems. This paper presents a new ...

IJEECS Paper Template
rise to many type of security threats or attacks. Adversary can ... data transmission. The message is sent ... in realizing security services like: authenticity, integrity,.

IJEECS Paper Template
B. M. Alargani and J. S. Dahele, “Feed Reactance of. Rectangular Microstrip Patch Antenna with Probe. Feed,” Electron letters, Vol.36, pp.388-390, 2000. [6].

Transactions Template - IJEECS
trol flow. There are two types of slicing namely static and dynamic slicing [7] .A static program slice comprises of those program statements that affects the value of a variable at some program point of interest which is referred as 'slicing cri- te

Transactions Template - IJEECS
The face space is defined by the “eigen-faces”, which are the eigen vectors of the set of faces. The block .... eigenvector and eigenvalue of WTW respective- ly,.

Transactions Template - IJEECS
Abstract—The resonant modes and characteristics of an equilateral triangular microstrip patch antenna with a variable air gap are theoretically and experimentally examined. Effect of varying parameters like dielectric constant of substrate, size of

Transactions Template - IJEECS
ISSN: 2221-7258(Print) ISSN: 2221-7266 (Online) www.ijeecs.org. Modified ..... vanced Information Networking and Applications Workshops. (AINAW 07), vol. 2.

Transactions Template - IJEECS
client server model doesn't support the slicing over the object oriented programs on ... slicing, Slice, Distributed System, Finite State Machine, Java Programming.

Transactions Template - IJEECS
INTERNATIONAL JOURNAL OF ELECTRICAL, ELECTRONICS AND COMPUTER SYSTEMS (IJEECS),. Volume ... ployed to validate the present theory for various .... Journal of Radio and Space Physics, vol. 35, pp. 293-. 296, 2006.(Journal).

Transactions Template - IJEECS
Dr. Harsh K Verma, Head, Department of Computer Science and Engi- neering,NIT jalandhar, E-mail: [email protected]. • Vaibhaw Dixit with the National Institute of Technology, Jalandhar,. Jalandhar, 144011. E-mail: [email protected]. The face

Paper Template - SAS Support
of the most popular procedures in SAS/STAT software that fit mixed models. Most of the questions ..... 10 in group 2 as shown with the following observations of the printed data set: Obs. Y ..... names are trademarks of their respective companies.

PMC2000 Paper Template - CiteSeerX
Dept. of Civil and Environmental Eng., Stanford University, Stanford, CA ... accurately follow the observed behavior of a large California ground motion database. .... rate of phase change, conditional on the amplitude level, to have a normal ...

Paper Template - SAS Support
Available support.sas.com/rnd/scalability/grid/gridfunc.html. Tran, A., and R. Williams, 2002. “Implementing Site Policies for SAS Scheduling with Platform JobScheduler.” Available support.sas.com/documentation/whitepaper/technical/JobScheduler.p

Paper Template - SAS Support
SAS® Simulation Studio, a component of SAS/OR® software, provides an interactive ... movement by shipping companies, and claims processing by government ..... service engineers spent approximately 10% of their time making service calls ...

CiC Paper Template
From Echocardiographic Image Sequence In Long-Axis View. Anastasia Bobkova, Sergey Porshnev, Vasiliy Zuzin. Institute of radio engineering, Ural Federal University of the First President of Russia B.N. Yeltsin. Ekaterinburg, Russia. ABSTRACT. In this

PMC2000 Paper Template
accurately follow the observed behavior of a large California ground motion database. ..... over a (coarse) grid, and various methods have been investigated to ...

IEEE Paper Template in A4 (V1) - icact
the SE-EE trade-off in multi-user interference-limited wireless networks ... International Conference on Advanced Communications Technology(ICACT).

I/ITSEC Author's Paper Template
MIST and INSPYRED are both free software available under GPL license and can ..... from this work, the implementation is offered under General Public License that allows ... Population - The Reference Model Runs with MIST Over the Cloud!