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IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 4, APRIL 2003 Silicon Devices

Influence of High Channel Doping on the Inversion Layer Electron Mobility in Strained Silicon n-MOSFETs Hasan M. Nayfeh, Student Member, IEEE, Christopher W. Leitz, Arthur J. Pitera, Eugene A. Fitzgerald, Judy L. Hoyt, Member, IEEE, and Dimitri A. Antoniadis, Fellow, IEEE

Abstract—In this letter, we investigate the dependence of electron inversion layer mobility on high-channel doping required for sub-50-nm MOSFETs in strained silicon (Si), and we compare it to co-processed unstrained Si. For high vertical effective electric field e , the electron mobility in strained Si displays universal behavior and shows enhancement of 1.5–1.7X compared to unstrained Si. For low e , the mobility for strained Si devices decreases toward the unstrained Si data due to Coulomb scattering by channel dopants. Index Terms—Heterostructure, mobility enhancement, MOS devices, MOSFET, MOSFET mobility, scattering, semiconductor device doping, SiGe, silicon, strained-si MOSFETs.

I. INTRODUCTION

S

CALING of unstrained silicon (Si) (bulk-Si) CMOS transistors to sub-50-nm gate length requires increased channel doping to control short-channel effects. Experimental measurements and theoretical predictions of deeply scaled, unstrained Si n-MOSFETs show degraded electron mobility due to high channel doping and is attributed to increased Coulomb interactions [1], [2]. Degraded mobility in deeply scaled, unstrained Si devices necessitates the study of new materials with superior performance and capability for device fabrication that closely follows a typical bulk Si CMOS process. One promising candidate is strained Si where mobility enhancements in the 1.7–2X range have been reported in relatively lightly doped channels [3], [4], motivating this study of dependence of electron mobility on channel doping. In this letter, we report inversion layer electron mobility measurements in strained Si n-MOSFETs fabricated using a typical MOSFET process, with channel doping concentration ranging from 1 10 –6 10 cm . II. DEVICE FABRICATION The strained Si substrates used in this work were grown epitaxially on relaxed silicon germanium (SiGe) in a vertical, hot-wall ultrahigh vacuum chemical vapor deposition Manuscript received January 20, 2003. This work was supported by DARPA, the SRC and the staff of the Microsystems Technology Laboratory (MTL). The review of this letter was arranged by Editor E. Sangiorgi. H. M. Nayfeh, J. L. Hoyt, and D. A. Antoniadis are with the Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139 USA (e-mail: [email protected]). C. W. Leitz, A. J. Pitera, and E. A. Fitzgerald are with the Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, MA 02139 USA. Digital Object Identifier 10.1109/LED.2003.810885

(UHVCVD) reactor using silicon hydrogen (SiH ) and germanium hydrogen (GeH ) precursors [5]. The SiGe virtual substrates were grown on Si to a Ge content of 20% confirmed by secondary ion mass spectrometry (SIMS) at 900 C and were topped by a 1.5- m uniform composition cap. The slow grading rate and high growth temperature results in completely relaxed, graded layers with threading dislocation densities and low surface roughness [5]. of approximately 10 cm The reactor temperature was then dropped to 650 C for the deposition of the strained Si device layer. Strained Si thickness less than the equilibrium critical thickness of about 20 nm for 20% Ge substrate was chosen to minimize misfit dislocation introduction during elevated processing temperatures [6]. The samples were doped in situ p-type to concentrations of using boron hydrogen (B H ) for all layers. 1 10 cm High-resolution cross-sectional transmission electron microscopy (XTEM) showed the strained Si thickness to be 180-Å-thick. Next, a typical MOSFET process followed where active-area isolation was achieved using a field ion implant followed by a 2000-Å-thick deposited low-temperature field oxide. Boron channel ion implantation with energy of 10 keV and dose followed. At equal doping ranging from 1–7 10 cm is reduced in strained Si levels, the threshold voltage n-MOSFETs compared to unstrained by 100 mV for 20% Ge substrate, due to strain-induced energy band splitting [7]. In order to closely match , the channel boron ion implant doses were chosen to be 1.5 to 2X larger for the strained Si devices. Next, the gate stack was formed by growth of a 5-nm dry oxide at 800 C for 30 min, followed by the deposition of polysilicon gate at 625 C. The gate stack was then patterned and etched, followed by source/drain and gate ion implant and activation using a high-temperature 1000 C spike anneal. Metal contacts were formed using 1000-Å Ti/1- m Al followed by sinter in forming gas at 425 C for 30 min. XTEM of the gate stack that shows 8-nm-thick strained-Si layer remains. This indicates that 10 nm was lost due to process cleaning and gate oxide growth steps. Ge diffusion into the strained-Si device layer was confirmed by SIMS measurement to be negligible. III. RESULTS AND DISCUSSION Electron mobility measurements on 50 50 m devices nm were extracted with electrical oxide thickness, using the split-C–V method. The mobility was calculated for greater than the linearly extrapolated threshold gate voltage

0741-3106/03$17.00 © 2003 IEEE

NAYFEH et al.: INFLUENCE OF HIGH CHANNEL DOPING ON THE INVERSION LAYER ELECTRON MOBILITY

Fig. 1. Effective electron mobility versus vertical effective electric field, E , for various channel doping concentrations for unstrained- and strained-Si n-MOSFETs.

voltage so that the drain current per width is drift-dominated. As a result, the expression can be used, where is measured at a drain voltage of 10 mV, and is the inversion layer charge. The lateral is often set to , though this is valid electric field only in strong inversion. To improve accuracy in weak inversion near threshold, a correction factor was used to calculate , where is is the capacitance the gate-to-channel capacitance, and results in at in strong inversion [8]. This correction to . It most a 15% increase in the mobility values for should be noted that the correction has no influence on the extracted ratio of strained-to-unstrained Si mobilities. The was calculated using the expression effective vertical field , where was determined to the applied , and the bulk charge by integrating was determined using the depletion approximation. The was determined using an channel-doping concentration inverse modeling technique [9] and using measured SIMS profile as an initial guess. The mobility data presented in , the strained-Si mobility data Fig. 1 show that at high display universal behavior independent plotted versus of doping with enhancement of 1.5–1.7X over unstrained Si. The unstrained Si data also show universal behavior and agree and high closely with previously reported data [10]. At low doping where Coulomb scattering is important, the mobility enhancement for the strained Si devices is reduced. This is likely due to Coulomb scattering by channel dopants, agreeing with theoretical predictions that the enhancement of strained Si electron mobility over unstrained Si is reduced when Coulomb scattering is the dominant carrier scattering mechanism [11]. It should be noted that the strength of the Coulomb interaction encountered by inversion layer electrons in the devices reported in this letter is stronger than in advanced sub-50-nm devices that would have carefully tailored two-dimensional (2-D) halo-doping profiles that result in reduced surface doping to achieve maximum performance.

249

Fig. 2. Coulomb limited mobility in strained Si plotted on a log-log scale versus inversion charge areal density N calculated for three different channel doping concentrations N . The Coulomb mobility was calculated using a Matthiessen’s rule summation for the total mobility based on the measurement data. The data show a power-law dependence on N and N .

The departure from universal behavior in the Coulomb scattering dominant regime allows for accurate extraction of the Coulomb mobility for strained and unstrained (relaxed) Si n-MOSFETs for various doping concentration. The total for relaxed and strained Si, respectively, is mobility assumed to follow a two-term model (Matthiessen’s rule), where and , where is the Coulomb-limited mobility, and comprehends phonon and surface scattering for the respective on material, as discussed later. The dependence of and (shown in Fig. 2) is a power law dependence and where is a constant, where , is expressed in 2.89 10 cm/Vs with units of cm , and the inversion charge areal density is expressed in cm . Theoretical calculations of Coulomb scattering for inversion-layer carriers in relaxed Si MOSFETs that assume Coulomb scattering is an elastic mechanism, resulting in the deflection of carriers through small angles and exponents predict a power-law dependence of and close to one agreeing with the experimental for findings in this letter [12]. Moreover, it is hypothesized that [11]. We test this by using our analytical to calculate and (using expression for Matthiessen’s rule as above) for unstrained- and strained-Si cm and with channel doping concentrations cm , respectively, resulting in similar . Good agreement of calculated and measured data for both cases is shown in Fig. 3. Analytical universal mobility expressions , where phonon for strained and unstrained devices at high and surface-roughness are the dominant scattering mechanisms for electron transport, were calculated by fitting the expression to the high measurement data in this work for all doping concentrations. The fitting parameters found that provide reasonable fit are for relaxed Si , , and for strained Si ,

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IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 4, APRIL 2003 Silicon Devices

REFERENCES

Fig. 3. Comparison of measured data with calculated inversion in relaxed- and strained-Si n-MOSFETs electron mobility versus E = 3:9 10 cm and with channel-doping concentration N N = 5:5 10 cm respectively. The analytical expression for the Coulomb mobility component was the same for both strained and relaxed Si, while the “universal” component was extracted by fitting to the high Q portion of the experimental data for the two cases as described in the text.

2

2

, . The fitting parameters for unstrained Si closely follow those published by Liang et al. [13]. The ratio is 1.75, equal to the observed mobility enhancement. IV. CONCLUSIONS In summary, for the relatively large range corresponding to various channel dopings, we have demonstrated universal electron inversion-layer mobility in strained Si enhanced by 1.5–1.7X relative to unstrained Si. At low , it is found that the Coulomb-scattering mobilities for unstrained and strained Si are closely matched, and are inversely proportional to and proportional to , due to screening. The results found in this letter should be useful in the design of sophisticated two-dimensional (2-D) channel doping profiles in sub-50-nm strained-Si n-MOSFETs that would provide maximum performance benefit.

[1] A. Lochtefeld and D. A. Antoniadis, “On experimental determination of carrier velocity in deeply scaled NMOS: How close to the thermal limit?,” IEEE Electron Device Lett., vol. 22, pp. 95–97, Feb. 2001. [2] M. V. Fischetti and S. E. Laux, “Long-range coulomb interactions in small Si devices. Part I: Performance and reliability,” J. Appl. Phys., vol. 89, no. 2, pp. 1205–1231, Jan. 2001. [3] K. Rim, J. L. Hoyt, and J. F. Gibbons, “Fabrication and analysis of deep submicron strained-Si n-MOSFETs,” IEEE Trans. Electron Devices, vol. 47, pp. 281–286, July 2000. [4] J. Welser, J. L. Hoyt, and J. F. Gibbons, “Electron mobility enhancement in strained-Si n-Type metal-oxide-semiconductor field-effect transistors,” IEEE Electron Device Lett., vol. 15, pp. 100–102, Mar. 1994. [5] E. A. Fitzgerald, Annu. Rev. Mater. Sci., pp. 417–454, 1995. [6] J. W. Matthews and A. E. Blakeslee, “Defects in epitaxial multilayers. I. Misfit dislocation,” J. Crys. Growth, vol. 27, pp. 118–125, 1974. [7] T. Vogelsang and K. R. Hofmann, “Electron transport in strained Si Ge substrates,” Appl. Phys. Lett., vol. 63, no. 2, pp. layers on Si 186–188, July 1993. [8] C. G. Sodini, T. W. Ekstedt, and J. L. Moll, “Charge accumulation and mobility in thin dielectric MOS transistors,” Solid-State Electron., vol. 25, no. 9, pp. 833–841, 1982. [9] I. J. Djomehri and D. A. Antoniadis, “Inverse modeling of sub-100 nm mosfets using I –V and C –V ,” IEEE Trans. Electron Devices, vol. 49, pp. 568–575, Apr. 2000. [10] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the universality of the inversion layer mobility in Si MOSFETs: Part I: Effects of substrate impurity concentration,” IEEE Trans. Electron Devices, vol. 41, pp. 2357–2362, Dec. 1994. [11] F. Gamiz, J. B. Roldan, J. A. Lopez-Villanueva, and P. Cartujo, “Coulomb scattering in strained-silicon inversion layers on Si Ge substrates,” Appl. Phys. Lett., vol. 69, no. 6, pp. 797–799, Aug. 1996. [12] A. Mujtaba, S. Takagi, and R. Dutton, “Accurate modeling of coulombic scattering, and its impact on scaled MOSFETs,” in Proc. Symp. VLSI Technol., 1995, pp. 797–799. [13] M.-S. Liang, J. Y. Choi, P.-K. Ko, and C. Hu, “Inversion-layer capacitance and mobility of very thin gate-oxide MOSFETs,” IEEE Electron Device Lett., vol. ED-33, pp. 409–413, Mar. 1986.

Influence of high channel doping on the inversion layer ...

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