Intel® Curie™ Module Design Guide March 2017
Revision 1.3
March 2017 Rev. 1.3
Intel® Curie™ Module Design Guide 1
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Intel® Curie™ Module Design Guide 2
March 2017 Rev. 1.3
Revision History Revision
Description
Date
1.0 1.1 1.2
Initial release Minor fixes Added reference to the Intel® Curie™ Power Sequence Considerations application note in the power on sequence section Updated Power and Energy chapter
August 2016 September 2016 November 2016
1.3
March 2017
§
March 2017 Rev. 1.3
Intel® Curie™ Module Design Guide 3
Contents 1
Introduction ..................................................................................................................8 1.1 Audience and purpose ............................................................................................. 8 1.2 References............................................................................................................. 9 1.3 Terminology..........................................................................................................10
2
System Fundamentals .................................................................................................11 2.1 Block diagrams......................................................................................................11 2.2 Electrical specifications ...........................................................................................14 2.3 Intel® Curie™ module footprint ...............................................................................14 2.3.1 Breakout pitch of module ..........................................................................14
3
Power and Energy .......................................................................................................15 3.1 Overview ..............................................................................................................15 3.2 Intel® Curie™ module electrical specifications ...........................................................16 3.3 Power inputs .........................................................................................................18 3.3.1 VSYS......................................................................................................18 3.3.2 AON LDO power.......................................................................................18 3.3.3 AON IO power (AON_IO_VCC) ...................................................................18 3.3.4 Comparator power ...................................................................................18 3.3.5 ADC power..............................................................................................18 3.3.6 Bluetooth® low energy controller and 6-axis sensing device power.................18 3.4 System power architecture......................................................................................19 3.4.1 Power controller.......................................................................................19 3.4.2 Load switch selection................................................................................21 3.4.3 System using internal battery charger ........................................................21 3.4.4 System using external battery charger........................................................23 3.5 USB port design and detection.................................................................................24 3.5.1 USB port charging source..........................................................................24 3.5.2 Non-USB DC charging source.....................................................................25 3.6 Battery charging and management ..........................................................................26 3.6.1 Built-in battery charger.............................................................................26 3.6.2 Built-in power regulators...........................................................................29 3.7 Power sequencing ..................................................................................................32 3.7.1 Measured timings for reference ..................................................................33 3.8 Unused pins ..........................................................................................................34
4
Subsystems .................................................................................................................35 4.1 Analog power and input routing ...............................................................................35 4.1.1 ADC ground ............................................................................................35 4.2 Bluetooth® low energy controller and antenna ..........................................................37 4.2.1 Antenna placement ..................................................................................37 4.3 I2C interface design guidelines .................................................................................38 4.3.1 I2C connections on the functional reference circuits.......................................38 4.3.2 I2C interface signals .................................................................................38 4.4 LED driver example................................................................................................39 4.5 I2S interface design guidelines .................................................................................40 4.5.1 Signals for the I2S interface .......................................................................40 4.5.2 I2S interface routing guidelines..................................................................41 4.6 Sensors ................................................................................................................41 4.6.1 Integrated 6-axis sensing device interfaces .................................................41 4.6.2 Environmental inputs................................................................................41 4.7 Haptics.................................................................................................................43 4.7.1 Device driver...........................................................................................43
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4.8 4.9 4.10 4.11 4.12 4.13 4.14
4.7.2 Reference Eccentric Rotating Mass (ERM) device .......................................... 44 SPI interface......................................................................................................... 44 4.8.1 SPI interface signals on the Intel® Curie™ module ...................................... 46 Flash memory....................................................................................................... 46 Display panel and touch controller ........................................................................... 47 Near Field Communication (NFC) ............................................................................. 49 4.11.1 NFC controller features............................................................................. 49 4.11.2 ARM* SecurCore microcontroller features ................................................... 49 UART0 for Bluetooth® low energy controller ............................................................. 51 UART1 interface signals.......................................................................................... 51 USB interface design considerations......................................................................... 52 4.14.1 USB 1.1 length matching .......................................................................... 53
5
Circuit Board Recommendations ................................................................................. 54 5.1 Fundamental design rules....................................................................................... 54 5.2 PCB thickness and stack-up .................................................................................... 54 5.2.1 Two-layer boards..................................................................................... 54 5.2.2 Four-layer stack-up ................................................................................. 55 5.2.3 Six-layer stack-up ................................................................................... 55
6
Debug and Production Options.................................................................................... 57 6.1 JTAG connector or test pads ................................................................................... 57 6.2 Power rail test pads ............................................................................................... 58 6.3 UART test pads ..................................................................................................... 58 6.4 Bluetooth® low energy controller test pads .............................................................. 58
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Intel® Curie™ Module Design Guide 5
Tables 1-1 1-2 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 5-1 5-2 5-3
References.......................................................................................................... 9 Terminology .......................................................................................................10 Electrical specifications ........................................................................................16 Valid input ranges ..............................................................................................16 Output power values ...........................................................................................17 Maximum capacity of the regulators ......................................................................17 SILEGO SLGNT41502V power controller pinout .......................................................20 Timing parameters ..............................................................................................33 I2C interface signals............................................................................................38 I2S interface signals ............................................................................................40 I2S routing guidelines..........................................................................................41 6-axis sensing device interface signals ...................................................................41 Intel® Curie™ module SPI interface signals............................................................46 UART interface signals .........................................................................................51 USB 1.1 differential pair length matching table........................................................52 USB 1.1 differential pair length matching table........................................................53 Two-layer stack-up design ...................................................................................54 Four-layer stack-up design ...................................................................................55 Six-layer stack-up design .....................................................................................55
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Figures 2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 5-1 6-1 6-2
March 2017 Rev. 1.3
Intel® Curie™ module block diagram....................................................................... 12 Conceptual device block diagram ............................................................................. 13 Top-level power architecture for typical Intel® Curie™ module-based system................ 15 Bluetooth® low energy controller and 6-axis sensing device power .............................. 19 System using internal battery charger...................................................................... 22 System using external battery charger ..................................................................... 23 USB used as charging source .................................................................................. 25 Non-USB DC charging source .................................................................................. 26 Battery charging profile with thermal regulation ........................................................ 27 Battery charger - Example circuit ............................................................................ 28 No battery application - Example circuits .................................................................. 29 ESR3 regulator ..................................................................................................... 30 Integrated bulk regulator ....................................................................................... 30 ESR1 and ESR2 regulator connections ...................................................................... 31 Intel® Curie™ module power sequence .................................................................... 32 Timing relationship between VIN, OPM2P6_VOUT and LDO1P8_VOUT ........................... 33 Timing relationship between LDO1P8_VOUT, VDD_HOST_1P8 and VDD_HOST_1P8PG....................................................................................................................... 34 ADC ground example ............................................................................................. 36 Pad dimensions for the antenna device..................................................................... 37 Example of I2C connection for a typical device ........................................................... 38 LED driver block diagram for a tricolor module .......................................................... 39 LED driver example circuit for a tricolor module......................................................... 40 Extended environmental sensor block diagram .......................................................... 42 External environmental sensor example circuit .......................................................... 42 Haptic driver block diagram .................................................................................... 43 Haptic driver - example circuit ................................................................................ 44 SPI simplified topology example .............................................................................. 45 SPI Flash - use example ......................................................................................... 46 Flash memory circuit for SPI interface ...................................................................... 47 External display topology example ........................................................................... 48 NFC connections ................................................................................................... 50 NFC example circuit............................................................................................... 50 UART interface topology ......................................................................................... 51 USB 1.1 port topology............................................................................................ 52 Thickness of a six layer stack-up ............................................................................. 56 Block diagram of the debug ports on the Intel® Curie™ module .................................. 57 Debug ports on the Intel® Curie™ module ............................................................... 58
Intel® Curie™ Module Design Guide 7
Introduction
1
Introduction This document provides design recommendations for the Intel® Curie™ module, which is based on the Intel® Quark™ SE microcontroller C1000 system on a chip. The technical implementation examples provided in this document are derived from the functional reference circuits.
Note:
The guidelines provided in this document are based on preliminary simulation work done at Intel® corporation while developing systems based on the Intel® Curie™ module and the Intel® Quark™ SE microcontroller C1000 micro-controller. This work is ongoing, and the recommendations are subject to change.
Note:
All third party components shown in this document are for reference example purpose only. Customers have to evaluate and choose the right components based on their application use case.
Caution:
If the guidelines listed in this document are not followed, it is very important that the designers perform thorough signal integrity and timing simulations. Even when following these guidelines, Intel® corporation recommends some simulations with the critical signals to ensure proper signal integrity and flight time.
1.1
Audience and purpose The Intel® Curie™ Module Design Guide is provided as an aid for hardware designers and system integrators. The functional reference circuits were created to provide information and guidance on the following subjects: • Block diagrams of the system level communications and functional reference circuits interface configurations • System mechanicals and board topology, routing requirements, and layout recommendations • Power distribution, reset logic, boot sequencing, and energy management • Factory test, debug, recovery, and troubleshooting • Alternate implementation options
Note:
This design guide has been developed to ensure the maximum flexibility for board designers while reducing the risk of board-related issues. The design recommendations are based on Intel® corporation's simulations and lab experience and are strongly recommended, if not necessary, to meet the timing and signal quality specifications. They should be used as an example but may not be applicable to particular designs. The guidelines recommended in this document are based on experience, simulation, and preliminary validation work done at Intel® corporation while developing the Intel® Curie™ module processor-based design. This work is ongoing, and recommendations are subject to change. Metric units are used in some sections in addition to the standard use of U.S. customary system of units (USCS). If there is a discrepancy between the metric and USCS units, assume the USCS unit is most accurate. The conversion factor used is 1 inch (1000 mils) = 25.4 mm.
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Introduction
1.2
References
Table 1-1.
References Document Name Intel® Curie™ Module Datasheet Intel® Curie™ Module Application Note: Intel® Curie™ Module Power Sequencing Considerations Intel® Curie™ Module Specification Update
March 2017 Rev. 1.3
Intel® Curie™ Module Design Guide 9
Introduction
1.3
Terminology
Table 1-2.
Terminology Term
Definition
ADC
Analog-to-digital converter
ANT
Antenna
AON
Awake-ON
SoC
Intel® Quark™ SE microcontroller C1000 system on chip
BALUN
Balanced-unbalanced
BLE
Bluetooth® low energy
CTS
Clear to send
Intel® Curie™ module
Intel’s highly integrated module based on the Intel® Quark™ SE microcontroller C1000 SoC
DSP
Digital signal processor
ERM
Eccentric Rotating Mass
Impedance
The effective resistance of a trace, circuit or component
NFC
Near field communication
PCB
Printed circuit board
POR
Power-on reset
PWM
Pulse width modulation
RAM
Random-access memory
RF
Radio frequency
Solder mask
An electrically insulating material covering traces on the external layers of a PCB
SW
Software
Space
The distance between copper features (such as traces) on the PCB
SRAM
Static random-access memory
Trace
A copper line on the PCB used to connect components
UART
Universal asynchronous receiver transmitter
VIA
Plated hole in the PCB used to connect layers
Intel® Curie™ Module Design Guide 10
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System Fundamentals
2
System Fundamentals
2.1
Block diagrams The next two block diagrams show the Intel® Curie™ module and then the module within a typical design.
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Intel® Curie™ Module Design Guide 11
System Fundamentals
Figure 2-1.
I2C0_SS I2C1_SS SPI0_SS
ATP_INT/GPIO
Intel® Curie™ module block diagram
External_PAD External_PAD External_PAD
Intel® Quark™ SE C1000
AON_GPIO_PAD_5/ GPIO_AON[5]
BLE_ATP_INT
EXTERNAL_PAD_05/ GPIO[5]
ATP_BLE_INT
UART_0
32MHz In External_PAD
32MHz XTAL
I2C1 SPI0_M/GPIO SPI1_M/GPIO SPI0_SS/GPIO I2S/GPIO UART1/GPIO_SS GPIO/AIN
6AXIS_INT1 External_PAD External_PAD
AON_GPIO_PAD_4/AON_GPIO_4 EXTERNAL_PAD
External_PAD
SPI1_SS VUSB_EN
EXTERNAL_PAD_62/GPIO[28] External_PAD External_PAD
EXTERNAL_PAD_07/GPIO[7]/AIN[7] VCC_USB_3P3
5V_BUS_SENSE
External_PAD BUCK_EN
External_PAD
PLT_CLK[1]
External_PAD
VCC_SRAM_1P8
32/16/8/4 MHz External_PAD
ESR1_LX
1P8
ESR2_LX
1P8
ESR3_LX
VDD_PLAT_1P8 VDD_PLAT_3P3 VDD_HOST_1P8 ADC_3P3_VCC CMP_3P3_VCC IO_AON_VCC
BLE_I2C
16MHz XTAL
VCC_RTC_1P8
Bosch* BMI160 6-AXIS SENSOR
VDD_6AXIS
LDO 3.3V Microchip* MIC5504-3.3YMT
VDD_USB
BUCK_VOUT
1.8V/3.3V BUCK REGULATOR Texas Instrument* TPS62743
BUCK_VSEL
LDO1P8_VOUT
VCC_BATT_ESR3_3P7/ VCC_BATT_OPM3_3P7
VCCOUT_ESR1_3P3 EXTERNAL_PAD_17/GPIO_SS[9]/AIN[17]
VSYS OPM2P6_VOUT
VCCOUT_AVD_OPM_2P6
VCCOUT_ESR3_1P8
VSYS
POWER SUPERVISOR Maxim* MAX16074RS29D3+
VCCOUT_QLR2_1P8 VCCOUT_QLR1_3P3/VCC_VSENSE_ESR1 VCCOUT_HOST_1P8
6-AXIS_AUX_I2C 6AXIS_INT2
LDO 1.8V ON Semiconductor* NCP170AMX180TCG
VCC_AON_1P8
PLT_CLK/GPIO_SS 3P3
BLE_DEBUG
External_PAD
JTAG PWM/GPIO_SS
BALUN STMicroelectronics* BAL-NRF02D3
VDD_BLE_SEN
32KHz OSC
32kHz In I2C0
Nordic* Bluetooth® low energy controller NRF51822
MRESET_B POR_B ATP_RST_B
RST_N_PAD VIN
1.8-3.3V 2.0-3.3V 1.8V
EXTERNAL_PAD_15/ GPIO_SS[7]/AIN[15]
CHG_STATUS
PV_BATT
BATTERY CHARGER (Optional) Texas Instruments* BQ25101H
BATTERY_ISET CHG_STATUS
VCC_HOST_1P8_PG
POWER SUPERVISOR RICOH* R3117K161C
BATTERY_TEMP
SENSOR SUBSYSTEM CLOCK
Intel® Curie™ Module Design Guide 12
POWER
March 2017 Rev. 1.3
BLE_RF
System Fundamentals
Figure 2-2.
Conceptual device block diagram
I2C1_M_SCL HOST
NFC
I2C1_M_SDA SPI1_M_CS2
SECURE ELEMENT
STMicroelectronics* ST54D
SPI1_M_SCK SPI1_M_MOSI SPI1_M_MISO NFC_INT NFC_RST NFC_GPIO
3
I2C1_SCL
I2C1_SCL
I2C1_SDA
I2C1_SCA SPI1_M_CS2
GPIO[1] / AIN[1] / SPI_S_MISO
I2C1_M_SCL I2C1_M_SDA HAPTICS_IN/TRG/PWM
HAPTICS Texas instrument* DRV2605
SPI1_M_SCK SPI1_M_MOSI
I2C0_SS_SCL
SPI1_M_MISO GPIO[2] / AIN[2] / SPI_S_SCK
I2C0_SS_SDA
I2C0_SS_SCL I2C0_SS_SDA
PRESSURE ,TEMP & HUMIDITY SENSOR Bosch* BME280
GPIO[15] / I2S_RXD GPIO[20] / I2S_TXD
GPIO_SS[3] / AIN[11]
LED DRIVER
I2C1_SCL
SPI1_M_CS1
Texas Instrument* LP5562
I2C1_SDA
SPI1_M_SCK
COMPASS_INT
COMPASS Bosch* BMM150
SPI1_M_MOSI I2C0_SCL
6
I2C GPIO EXPANDER
I2C0_M_SCL
I2C0_SDA GPIO_EXP_INT
PUSH_BUTTON
WC_EN
Wireless Charger
WC_CHG_STATUS
Broadcom* BQ51003
I2C0_M_SDA
GPIO[0] / AIN[0] / SPI_S_CS_B
GPIO[19] / I2S_TWS
GPIO[24] / SPI0_M_CS_B[0]
ATP_INT2
ATP_INT3
GPIO[17] / I2S_RWS GPIO_SS[12] / PWM[2]
TEMP_ADC
THERMISTOR
TM
LNA
GPS
TOUCH_INT DISPLAY_ON/OFF TOUCH_RESET
GPIO_SS[2] / AIN[10] SPI0_M_CS1
FILTER
DISPLAY_GPIO/ LCD_EXTCOMIN
DISPLAY / TOUCH HEADER
C O N N E C T O R
SPI0_M_SCK SPI0_M_MOSI SPI0_M_MISO GPS_HOST_REQ GPS_HOST_WAKE
GPS_ON
SPI0_M_CS1 SPI0_M_SCK SPI0_M_MOSI SPI0_M_MISO GPIO[16] / I2S_RSCK
SPI0_SS_CS0 SPI0_SS_SCK SPI0_SS_MOSI SPI0_SS_MISO
SENSOR HEADER
I2C1_SS_SCL I2C1_SS_SDA GPIO_SS[6]/AIN_14 GPIO_SS[3]/AIN_11
ATP_INT1
UART1_RTS/AIN[9]/GPIO_SS[1]
GPIO[18] / I2S_TSCK
UART1_CTS/AIN[8]/GPIO_SS[0]
SPI0_M_CS2
SEN_GPIO_1 SEN_GPIO_2 SEN_GPIO_3 SEN_GPIO_4
SPI0_M_CS2
SPI0_M_SCK
SPI0_M_SCK
SPI0_M_MOSI
SPI0_M_MOSI
SPI0_M_MISO
SPI0_M_MISO
GPIO[14] / SPI1_M_CS_B[3] GPIO[3] / AIN[3] / SPI_S_MOSI
4 OPTIONAL GPIO s TO SENSOR HEADER
FLASH_WP
SPI FLASH Macronix* MX25U12835F
FLASH_RESET
W3008C BLE_RF JTAG,UART,BLE GPIO shared GPIO (not available default)
(3 separate headers)
GPIO_SS[14]/PLT_CLK[0] ATP_INT0 GPIO[11] / SPI1_M_CS_B[0]
March 2017 Rev. 1.3
JTAG/DEBUG/BLE
SW_FUEL_GAUGE_EN/TEMP_EN ON-OFF SWITCH BATTERY_CTRL
Intel® Curie™ Module Design Guide 13
System Fundamentals
2.2
Electrical specifications Refer to Intel® Curie™ Module Datasheet for the complete electrical specifications.
2.3
Intel® Curie™ module footprint Refer to the chapter related to manufacturing in Intel® Curie™ Module Datasheet for more information.
2.3.1
Breakout pitch of module Due to the lateral pitch (0.0224” or 0.57 mm) on the Intel® Curie™ module package, there is a space of 0.0124” between the pads that requires a Trace and Space of 0.004” / 0.1” for breakout of the package on the external layer.
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Power and Energy
3
Power and Energy The power input of the Intel® Curie™ module is intended to be supplied by direct USB power, a charging device, or a battery as selected from a priority basis of those available.
3.1
Overview The Intel® Curie™ module has on-chip regulators which are meant to power the Intel® Curie™ module’s internal blocks and also to provide power to the platform components. This section provides guidelines on how to power the Intel® Curie™ module and also how to use the regulators and the electrical specification of the input and output power pins. The main power source can be from the USB power or from any other 5V power supply. The power controller (based on SILEGO SLG7NT41502V) is suggested for proper power up of Intel® Curie™ module. The USB detection circuit should also be protected against any voltage surges on the USB power. The protection scheme is also suggested to protect the Intel® Curie™ module from any USB voltage surges and to ensure reliable detection of the USB. The power architecture of a typical Intel® Curie™ module-based system is shown in Figure 3-1.
Figure 3-1.
Top-level power architecture for typical Intel® Curie™ module-based system
Intel® CURIE POWER
USB 5V6
USB CON
VIN[1], VIN[2] POWER CONTROLLER BLOCK Load Switch
USB WAKE USB Detection
PV_BATT
ESR3 (Buck Regulator)
VSYS AVD_OPM_2P61
Discharge Control
Battery charger
OPM Power Monitor
Ship Mode Control
4
LDO1P8_VOUT 1.8V @ 50mA Optional3 AON_IO_VCC
LDO
AON BLOCK AON IO
Platform Regulators
ADC_3P3_VCC ADC
CMP_3P3_VCC
VDD_USB
Notes:
VDD_HOST_1P82 1.8V @ 100mA
Host Block (Cores) PLATFORM POWER BUCK REGULATOR (1.8/3.3V) BLE & 6 axis Sensor
BUCK_VOUT5 1.8V @ 200mA
VDD_BLE_SEN
Comparartor
USB core
Platform Devices
AVD_OPM_2P6 power output from Intel® Curie™ module should not be used anywhere else. VDD_HOST_1P8 should not be used anywhere else.
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Intel® Curie™ Module Design Guide 15
Power and Energy
LDO1P8_VOUT can be used to power the AON_IO_VCC of the Intel® Curie™ module. The total current drawn from LDO1P8_VOUT output can be 50mA maximum. BUCK_VOUT voltage should be configured for the system IO voltage. Both AON_IO_VCC and BUCK_VOUT should be of same voltage level. IN[1] and VIN[2] can also be supplied from other DC sources. If the power is supplied from some non-USB DC source, do not connect to USB detection circuit and the USB detection circuit should be removed.
3.2
Intel® Curie™ module electrical specifications Table 3-1 shows a summary of Intel® Curie™ module electrical specifications.
Table 3-1.
Electrical specifications
Input Power
Min
VIN[1], VIN[2]
4.45
5
6.45
VSYS
2.1
-
4.4
VDD_HOST_1P8 (Source ESR3 Regulator)
1.62
1.8
1.98
AON_IO_VCC (1.8V)
1.62
1.8
1.98
AON_IO_VCC (3.3V)
2.97
3.3
3.43
ADC_3P3_VCC
Typ
Max
AON_IO_VCC
CMP_3P3_VCC - --- AON_IO_VCC=1.8V
2.0
3.63
CMP_3P3_VCC ---- AON_IO_VCC=3.3V
AON_IO_VCC
3.63
VDD_BLE_SEN (1.8V)
1.62
1.8
1.98
VDD_BLE_SEN (3.3V)
2.97
3.30
3.63
VDD_USB ----AON_IO_VCC = 1.8V
3.5
VDD_USB ---- AON_IO_CC = 3.3V
3.5
BLE_DEC2
Notes:
Unit
Volts (DC)
4.5 5.0
5.25
VDD_BLE_SEN = 1.8V
Tie BLE_DEC to VCCDD_BLE_SEN
VDD_BLE_SEN = 3.3V
Leave BLE_DEC unconnected
ADC_3P3_VCC should be at the same voltage level as AON_IO_VCC. ADC supply should be from a clean supply like LDCO output for better noise performance. CMP_3P3_VCC should meet the condition in the above table. If the comparators and the USB port are not used, CMP_3P3_VCC can be tied to AON_IO_VCC irrespective of the AON_IO_VCC voltage. The analog input pins should not exceed the AON_IO_VCC voltage. Table 3-2 shows the valid input voltage ranges.
Table 3-2.
Valid input ranges
VCC_IO_AON
VCC_ADC_3P3
VCC_CMP_3P3
Condition
3.3V
3.3V
3.3V
0 < AIN < 3.3V
1.8V
1.8V
2.0-3.3V
0 < AIN < 1.8V
1.8V
1.8V
1.8V
0 < AIN < 1.8V; Comparator not used; USB not used.
Intel® Curie™ Module Design Guide 16
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Power and Energy
Table 3-3 shows the output power values. Table 3-3.
Output power values Output Power
Min
Typ
Max
ESR3 DC-DC Converter
1.62
1.8
1.98
BUCK_VOUT (BUCK_VSEL = LOW)
1.76
1.8
1.84
BUCK_VOUT (BUCK_VSEL = HIGH)
3.22
3.3
3.38
OPM2P6_VOUT (Internal rail)
VSYS
-
2.6
LDO1P8_VOUT
1.76
-
1.84
Unit
Volt (DC)
Table 3-4 shows the maximum capacity values of the regulators. The maximum capacity is the maximum current that can be drawn by the platform components. Table 3-4.
Maximum capacity of the regulators
Regulator
Maximum Capacity
ESR3 DC-DC Converter
100
BUCK_VOUT
300
OPM2P6_VOUT
Do Not use
LDO1P8_VOUT
50
Note:
March 2017 Rev. 1.3
Unit
mA
LDO1P8_VOUT is used by the AON block internal to the Intel® Curie™ module. The value listed in the table is the maximum current that can be drawn by the platform components.
Intel® Curie™ Module Design Guide 17
Power and Energy
3.3
Power inputs
3.3.1
VSYS VSYS is the main system power input for the Intel® Curie™ module. VSYS supplies the OPM2P6 regulator, AON block, ESR3 and BUCK regulator. VSYS uses a 4.7uF bulk and 0.1uF decoupling capacitor. This pin should be powered by the power controller block.
3.3.2
AON LDO power AON is the internal LDO power output pin. AON powers the AON core of Intel® Curie™ module. It can be used to power AON_IO_VCC. It is recommended not to use this power for any device outside Intel® Curie™ module. If necessary, a maximum of 50mA can be drawn from this regulator.
3.3.3
AON IO power (AON_IO_VCC) AON_IO_VCC pin powers all the IO pins of the Intel® Curie™ module. The timing of this power should match the power sequence requirement. If the IO voltage is 1.8 V, it is recommended to use LDO1P8_VOUT to power this pin. It can be fed by other power supplies also, provided it meets the power sequence requirements. If the IO voltage is 3.3 V, an external regulator should be used. In all cases, the power sequence requirements should be met.
3.3.4
Comparator power CMP_3P3_VCC is the comparator block power input pin. It uses a 0.1 uF decoupling capacitor and a clean power supply for good performance. Keep the power supply traces away from high frequency signals, DC-DC converters and RF.
3.3.5
ADC power ADC_3P3_VCC is the ADC block power input pin. It uses a 0.1uF decoupling capacitor and a clean power supply for good performance. Keep the power supply traces away from high frequency signals, DC-DC converters and RF.
3.3.6
Bluetooth® low energy controller and 6-axis sensing device power The Bluetooth® low energy controller and the 6-axis sensing device in Intel® Curie™ module are powered by a common input power. The power to these blocks can be 1.8 V or 3.3 V based on the systems requirements. The voltage levels of VDD_BLE_SEN should match with AON_IO_VCC which is the IO power supply of Intel® Quark™ SE microcontroller C1000. It is recommended to use the BUCK_VOUT of the Intel® Curie™ module to power the VDD_BLE_SEN.
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Figure 3-2.
Bluetooth® low energy controller and 6-axis sensing device power
3 .3 V O p e ratio n
1 .8 V O p e ratio n
Intel® Curie Curie™ module
Intel® Curie Curie™ module
REG_OUT
REG_OUT BUCK_VOUT
BLE_DEC2 VDD_BLE_SEN
BUCK_VOUT
K1
G23
BLE_DEC2
H24
VDD_BLE_SEN
K1
G23 H24 VDD_IO_3.3V
VDD_IO_1.8V AON_IO_VCC
E21 C12 0.1uF
BUCK_VSEL
BUCK_VSEL
K22
GND
R8 0
3.4
C14 0.1uF
C13 0.1uF
.
C15 0.1uF
K22
GND
AON_IO_VCC
E21
VSY S
R9 0
P ull up to V S YS ra il
System power architecture This section provides information on the power architecture for a system based on the Intel® Curie™ module. The power controller block has the following characteristics: • Load switch selection • System design using the Intel® Curie™ module’s internal charger • System design using an external charger
3.4.1
Power controller The power controller block is based on a SILEGO power controller (SLG7NT41502V) and a load switch. The power controller is required for the proper start up condition for a reliable power on. The load switch is used in the VSYS path and controlled by the power controller. The power controller does the following: • Discharges any residual voltage if present on the OPM2P6_VOUT to ensure proper power on. This guarantees the OPM2P6_VOUT to be below 100mV when powering Intel® Curie™ module. • Monitors the input voltage during startup to ensure that the power input level is good to turn on the system. The internal threshold is 3.58 V. If a different threshold is necessary, the internal voltage can be disabled and an external power supervisor can be used. • Monitors the system voltage for brownout condition and turns off the system if it occurs to avoid any system misbehavior. The power controller uses the Intel® Curie™ module’s internal power supervisor for this feature. The default brownout threshold is 2.9 V. If a different threshold is needed, an external power supervisor has to be used.
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• Controls the ship mode to keep the system in the lowest power mode. Entering ship mode is activated by software and ship mode is exited upon a user button press or when attaching the charging source. The user button can be a multi-function user button. Note:
Please refer to Section 3.4.2 for information on how to choose the right load switch.
Table 3-5.
SILEGO SLGNT41502V power controller pinout
Pin
Pin Name
Type
Pin Description
1
VDD
PWR
Power supply input
2
nBUTTON_IN
Digital Input
Schmitt trigger input. Falling edge on this pin will bring the system out of ship mode and output high on LS_ON. Internally pulled high to VDD using 100K resistor. The purpose of pin is to connect to a push button.
3
nEXIT_SHIPMODE
Digital Input
Schmitt trigger input. Falling edge on this pin will bring the system out of ship mode and output high on LS_ON. Internally pulled high to VDD using 100K resistor. The purpose of pin is to connect to the USB_WAKE signal in USB detection circuit to bring the system out of ship mode when USB / DC input is attached.
4
POR_B
Digital Input
Intel® Curie™ module POR_B signal monitor.
5
SHIPMODE_EN
Digital Input
Ship mode enable signal. Latched by SHIPMODE_STROBE. Latching high will put the system in SHIP MODE
6
SHIPMODE_STROBE
Digital Input
Strobe signal to latch the SHIPMODE_EN.
7
DISCHARGE_0
Open Drain Output
Optional discharge control for VDD_HOST_1P8. Connect to VDD_HOST_1P8 using a 280 ohm series resistor.
8
GND
GND
Ground
9
nPG_IN
Digital Input
Active low power good input. Driving this pin low indicates that the power input to power controller block is good and disables internal voltage monitor. To use internal voltage monitor, connect this to VDD.
10
PG_IN
Digital Input
Active high power good input. Driving this pin high indicates that the power input to power controller block is good and disables internal voltage monitor. To use internal voltage monitor, connect this to GND.
11
nBUTTON_MONITOR
Open Drain Output
Reflects the nBUTTON_IN. Connect this pin to Intel® Curie™ module GPIO with a pull up resistor to AON_IO_VCC.
12
OPM2P6_DISCHARGE
Open Drain Output
Discharge control for OPM2P6_VOUT. Connect to OPM2P6_VOUT using a 280 ohm series resistor.
13
DISCHARGE_1
Open Drain Output
Discharge control for CMP_3P3_VCC. Connect to CMP_3P3_VCC using a 280 ohm series resistor.
14
LS_ON
Digital Output
Load switch Enable signal.
If you want to implement an equivalent method to ensure the startup condition, please make sure that the above requirements are met by the custom method.
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3.4.2
Load switch selection The selection of the right load switch is important for an Intel® Curie™ module-based system. Below are the requirements to be considered when choosing the load switch. • Active high enable load switch • Quick active output discharge (when disabled) • Working voltage range (2.5 V (Min) to 5 V (Max) • Controlled slew rate. Please select the load switch based on the total capacitance system power • Low quiescent current for low power applications Below are a few references of load switches. Select the one which the specification that best suits the application. • Texas Instruments TPS22915 • Texas Instruments TPS22913 • Silego SLG5NT1593V Consider the following important system parameters when choosing the load switch: • Total capacitance on the output of the load switch • Battery internal resistance • Parasitic resistance in the path • Rise time of the load switch • Possible inrush current The power controller monitors the input power and turns on the load switch when the system voltage crosses 3.58 V. When the load switch is turned on, it is likely to have a higher inrush current and the voltage can drop because of the above parameters. Select the total capacitance and battery so that the voltage does not drop below 3.0 V during the inrush current. If the voltage drops below 3.0 V, the power controller turns off the load switch and waits for the voltage to go higher than 3.58 V. If the voltage drops below 3.0 V during turn on, the system could be stuck and may not boot. To avoid this condition, select appropriately the total capacitance on the output of the load switch and the battery.
3.4.3
System using internal battery charger The Intel® Curie™ module has a built-in battery charger which can support 3.8 V Li-ion batteries. This section details how to design a system using the internal battery charger. The output of the battery charger is fed to the power controller block and the power controller block takes care of powering the system. A typical implementation of a system using the internal battery charger is shown in Figure 3-3.
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Figure 3-3.
System using internal battery charger AON_IO_VCC
Intel® Curie Module USB VBUS / DC 5V
K24 VIN[1] N21 VIN[2] M1 PV_BATT N22 BATT_TEMP
100K
POR_B E23 ESR3_LX P4 VDD_HOST_1P8 P3
L22 BATT_ISET
Battery Pack
100K
22uH 4.7uF
OPM2P6_VOUT J1 ATP_INT0 F22 GPIO[11] D22
SLG5NT1593V VOUT 3
2 VIN
L4 VSYS
GPIO[14] C22
CMP_3P3_VCC
CMP_3P3_VCC H22
CONTROL
D23 MRESET_B
GND
GND
ON
4
1
Power Cycle Button (Note1)
10M
SLG7NT41502V 1 VDD
LS_ON 14
9 nPG_IN 10 PG_IN
OPM2P6_DISCHARGE 12
2 nBUTTON_IN 3 nEXIT_SHIPMODE 280
13 DISCHARGE_1
DISCHARGE_0 7 POR_B 4 SHIPMODE_EN 5 SHIPMODE_STROBE 6
280 280 DNI
Optional (Note2)
10M
nBUTTON_MONITOR 11
8 GND
USB Detect Circuit VCC_COMP_3V3 nUSB_WAKE Please refer to the USB detection circuit for exact circuit
Notes:
Pressing the optional power cycle button will initiate the power cycle of the Intel® Curie™ module. Pull down POR_B using the 10M resistor to reduce the power leakage in SLG7NT41502V while in ship mode. If POR_B is pulled down there will be a current through this resistor when the system is powered on.
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3.4.4
System using external battery charger The Intel® Curie™ module’s internal charger is aimed for use in very low-power systems like wearable devices. It can still be used for high-power systems however, if an external charger is needed, the internal charger can be left unconnected and Intel® Curie™ module can be hooked to an external charger. It is safe to leave all the pins of the internal charger unconnected. Figure 3-4 shows how to use an external charger with the Intel® Curie™ module. Using either a single path or a power path charger depends on the system requirements.
Figure 3-4.
System using external battery charger AON_IO_VCC
Intel® Curie Module
External Battery Charger
USB VBUS / DC 5V
K24 VIN[1] N21 VIN[2] M1 PV_BATT N22 BATT_TEMP
INPUT
ESR3_LX P4 VDD_HOST_1P8 P3
L22 BATT_ISET
OUTPUT
100K
100K
POR_B E23 22uH 4.7uF
OPM2P6_VOUT J1 MAX 4.4V (Note 3)
ATP_INT0 F22 GPIO[11] D22
SLG5NT1593V VOUT 3
2 VIN
L4 VSYS
GPIO[14] C22
CMP_3P3_VCC
CMP_3P3_VCC H22
CONTROL
D23 MRESET_B
GND
GND
ON
4
1
Power Cycle Button (Note1)
10M
SLG7NT41502V 1 VDD
LS_ON 14
9 nPG_IN 10 PG_IN
OPM2P6_DISCHARGE 12
2 nBUTTON_IN 3 nEXIT_SHIPMODE 280
13 DISCHARGE_1
DISCHARGE_0 7 POR_B 4 SHIPMODE_EN 5 SHIPMODE_STROBE 6
280 280 DNI
Optional (Note2)
10M
nBUTTON_MONITOR 11
8 GND
USB Detect Circuit VCC_COMP_3V3 nUSB_WAKE Please refer to the USB detection circuit for exact circuit
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Below are some recommendations regarding Figure 3-4: • Pressing the optional power cycle button will initiate the power cycle of the Intel® Curie™ module. • Pull down POR_B using 10M resistor to reduce the power leakage in SLG7NT41502V while in ship mode. If POR_B is pulled down, there will be a current through this resistor when the system is powered on. • If an external charger is used, the output of the charger should not exceed 4.4 V. If the charger output voltage can exceed 4.4 V, an LDO or buck regulator should be used to limit the voltage to a maximum of 4.4 V.
3.5
USB port design and detection This section provides information on the protection scheme that should be implemented to protect the Intel® Curie™ module against voltage surges from power sources and also for Intel® Curie™ module to reliably detect a USB connect and disconnect. It is strongly recommended to add protection devices to the USB _VBUS and the D+ and D- lines. Add 22 ohms in series to the data line close to the connector for impedance matching and to reduce the EMI. Below is a guideline for such protection. The designers can choose the devices based on their system requirements. The standard USB port and non-USB power DC power source such as a wall adapter are the two typical power sources that can be used to power the system.
3.5.1
USB port charging source If the USB is used as a charging source, the scheme shown in Figure 3-5 should be implemented. The Intel® Curie™ module’s comparator is used to detect the presence of USB_VBUS. The circuit shown below ensures that the USB_VBUS is applied to Intel® Curie™ module only when the comparator power supply is present. The LDO is used to filter voltage surges on the USB_VBUS. This scheme can still be used even if the system is expected to be charged using either USB or a wall adapter. The USB_WAKE signal is connected to the power controller to exit ship mode upon a charger attachment. If this feature is not necessary, EXIT_SHIPMODE on the power controller can be left unconnected.
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Figure 3-5.
USB used as charging source Curie Intel®Curie™ Curie™module module Intel® Internal battery InternalCharger battery charger (if internal battery (if internal battery charger charger used)is used)
USB_5V VBUS DD+ GND
1 IN
2
LP2985AIM5-4.5 OUT
4 BYPASS
3 4
GND
5
2
ON/OFF
0.1uF 2.2uF 1.07K
K4 VDD_USB VDD_USB
5
2.2uF
1K
3
ID
1
1uF
0.01uF
LFTVS10-1F3
100K 22
GND
J23 USB_DM USB_DM J24 USB_DP USB_DP
22
GND
VCC_COMP_3V3
VCC_COMP_3V3
CSD233 81F4
Connects to SILEGO PWR controller
100K
nUSB_WAKE
NSR01L30MXT5G
10K CSD17382F4 4K7
3.5.2
0.1uF
Non-USB DC charging source If the product uses a non-USB DC power source for charging, the USB detection scheme can be eliminated and the simple scheme shown in Figure 3-6 can be used to exit the ship mode when attaching the charger.
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Figure 3-6.
Non-USB DC charging source
USB_5V To power Input of Charger nUSB_WAKE
0.1uF 2.2uF 1.07K LFTVS10-1F3
Connects to SILEGO circuit
10K CSD17382F4 4K7
0.1uF
3.6
Battery charging and management
3.6.1
Built-in battery charger The Intel® Curie™ module has a built-in, low-leakage, single-path, Li-ion / Li-Po battery charger. This battery charger supports 3.8 V batteries with a charging voltage of 4.35 V. The charge current supported by the charger is 10 mA to 250 mA which is hardware configurable using BATT_ISET pin. The charger has three phases of charging: the pre-charge to recover a fully discharged battery, the fast-charge constant current to supply the charge safely, and the voltage regulation to safely reach the full capacity. The fast-charge current is programmable and the pre-charge current is 20% of the fast charge while the termination current is 10% of the fast charge current. If the battery voltage is below 2.5 V, the battery is considered discharged and a preconditioning cycle begins. The charging happens at the pre-charge current level. Once the battery voltage has charged to the 2.5 V threshold, the fast charge is initiated and the fast charge current is applied. The typical circuit of the battery charger is illustrated in Figure 3-7. For low power or smaller size battery applications, use a load switch on the VBATT to VSYS path to implement a ship mode circuit. The ship mode circuit will help increase the shelf life of the product. VIN should be connected to the charging source (for example USB_VBUS). The battery should be connected to the PV_BATT. CHG_STATUS indicates the charging status and LOW indicates charging while HIGH indicates that the charging completed. Connect the BATT_TEMP to the NTC of the battery if available. If not, connect it to a 10K resistor and it will disable the temperature monitor. BATT_ISET is used to configure the battery charger current (also called as fast charge current) by connecting an external resistor to GND. The charge current can be in the range of 10 mA to 250 mA. The formula to calculate the value of resistor is:
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RISET = KISET/IOUT Where: IOUT is the desired fast charge current KISET is the gain factor whose value is 135 Aohm typical. (Min 129 and Max 145) BATT_TEMP is also used by the battery charger to detect the presence of the battery. When a battery presence is detected, the current drawn from the power source is limited to the charging current. If the BATT_TEMP is left floating, the battery charger assumes that there is no battery connected and enters the bypass mode where the current limit from the power source is 250 mA, which is also the limit on the current on the PV_BATT. The charging profile of the inbuilt battery charger is shown in Figure 3-7. Figure 3-7.
Battery charging profile with thermal regulation
Figure 3-8 illustrates a usage example of the internal battery charger. The LED used to indicate the charge status is optional. If this LED is not required, CHG_STATUS should be pulled high to the AON_IO_VCC. The NCP334 load switch is highly recommended for
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the low power device to save power. The Intel® Curie™ module will turn on the load switch momentarily to run the software-based fuel gauging and keep it turned off otherwise. Figure 3-8.
Battery charger - Example circuit
BATTERY APPLICATION From USB or Power Supply VIN_5V K24 VIN[1] C1 1uF 25V
N21 VIN[2]
Intel® Curie™ module
M1
IN
PV_BATT
Silego* Power Controller Block
OUT
+
R1 3K
3.8V Li-ion Battery
. 2
AON_IO_VCC GREEN
1
R2 100k
L4 VSYS
2
C2 0.1uF
Q1 S M22
1
R3 10K
CHG_STATUS
A1
G
P21 SW_FG_VBATT
15K R4
D 3
C3 4.7uF
R5 8.2K
CSD23381F4
OUT B1
GND
U2 IN EN NCP334
A2 B2 C4 0.1uF
L22 BATT_ISET GPIO N22
RISET R6 1.3k
BATT_TEMP
GND
R7 10K
For a NO battery application, one of the two following schemes shown in Figure 3-9 can be used based on the system design. Leaving BATT_TEMP open puts the charger in NO BATTERY mode where the charger does not attempt to charge the battery. The VIN[1:2] BATT_ISET, CHG_STATUS and the PVT_BATT can be left open if no battery is present in the system. The battery should not be connected without a 10K NTC or a 10K resistor on BATT_TEMP as this can damage the battery. Two methods can be followed to power the system for no battery application: • Method1: The internal battery charger can be used as a power regulator, but the PV_BATT current is limited to 250 mA. The internal battery charger behaves like an LDO in this case and outputs 4.4 V at PV_BATT.
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• Method2: An external LDO / Buck regulator is used to power the Intel® Curie™ module. The user selects the necessary output voltage. Figure 3-9.
No battery application - Example circuits
NO BATTERY APPLICATION - Method1 Intel® Curie™ Curiemodule VIN_5V K24 C7 1uF 25V
N21
VIN[1]
PV_BATT
NO BATTERY APPLICATION - Method2 Intel® Curie™ Curiemodule
Max 250mA output M1
IN
VIN_5V
Silego Power Controller Block
VIN[2]
K24 N21
VIN[1]
PV_BATT
M1
Silego Power Controller Block
VIN[2]
L4
VSY S C29 0.1uF
M22
SW_FG_VBATT
L22
C32 0.1uF
P21
CHG_STATUS SW_FG_VBATT
L22
BATT_ISET
P21
GPIO
GND
3.6.2
Built-in power regulators
3.6.2.1
OPM2P6_VOUT
BATT_TEMP
GND
N22
BATT_TEMP
C31 4.7uF.
BATT_ISET
GPIO N22
C11 1uF
L4
C28 4.7uF. M22
CHG_STATUS
LDO
OUT
OUT
VSY S
IN
OPM2P6 is Intel® Curie™ module’s internal power output. Connect this rail only to the power controller. Please refer to the System power architecture section. The residual voltage on this rail should be less than 100 mV when applying power to VSYS for a reliable startup. The power controller shown in the architecture section ensures that any residual voltage on OPM2P6_VOUT is discharged before turning on the system. For more details, please refer to Intel® Curie™ Power Sequence Considerations application note.
3.6.2.2
ESR3 regulator The purpose of the ESR3 regulator is to power the processor cores of the Intel® Curie™ module. The maximum capacity of the ESR3 regulator is 100 mA and the typical output is 1.8 V +/-10%. Use this power to power the cores only and DO NOT use the power for any other purpose. The recommended application diagram of ESR3 regulator is shown in Figure 3-10.
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Figure 3-10. ESR3 regulator
VSY S L1 VSY S C19 0.1uF
1
ESR3_LX
VDD_HOST_1V8
22uH 2
C20 4.7uF
C21 0.1uF
Intel® Curie™ Curie module
C22 4.7uF .
GND
VDD_HOST_1P8
3.6.2.3
Integrated buck regulator The Intel® Curie™ module includes a buck regulator which is hardware configurable for 1.8 V or 3.3 V operation. The regulator is based on Texas instruments TPS62743* lowleakage, high-efficiency regulator. The purpose of this regulator is to power the Bluetooth® low energy controller and 6-axis sensing device circuit of Intel® Curie™ module. The maximum current output of this regulator is 300 mA. This can also power the module components provided that the total current does not exceed 300 mA. As the Intel® Curie™ module has an integrated inductor, the capacitor and external components are not necessary. A low-value capacitor of 0.1uF can be added outside the Intel® Curie™ module for better noise performance.
Figure 3-11. Integrated bulk regulator
Curie module Intel® Curie™ VSY S
BUCK_VOUT L4
C17 4.7uF
REG_OUT K1 C16 0.1uF
VSY S
C18 0.1uF VDD_IO
GND
BUCK_VSEL
K22
R10 0 DNI R11 0
1.8V Output, BUCK_VSEL = LOW 3.3V Output, BUCK_VSEL = HIGH
.
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3.6.2.4
ESR1 and ESR2 regulator ESR1 and ESR2 are built-in switching regulators. If the regulators ESR1 and ESR2 are not used, connect the pins as shown in Figure 3-12 to reduce leakage current. Consider also the following: • Connect ESR1_VBATT and ESR2_VBATT to Ground. • Leave ESR1_LX and ESR2-LX open. • Connect VDD_PLAT_3P3 and VDD_PLAT_1P8 to Ground using a 10K resistor.
Figure 3-12. ESR1 and ESR2 regulator connections
Intel® Curie™ Curie module ESR1_VBATT ESR1_LX VDD_PLAT_3P3
P2 N1 N2 R12 10K
ESR2_VBATT ESR2_LX
GND
VDD_PLAT_1P8
Note:
March 2017 Rev. 1.3
N4 M4 M2 R13 10K
If you plan to use these regulators, we recommend that you measure the power.
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3.7
Power sequencing Figure 3-13 shows the power sequence diagram for the Intel® Curie™ module. The timings are the typical measured values. All the rails except VSYS and AON_IO_VCC are outputs. VIN is the system power supply. AON_IO_VCC has to be supplied externally. It is recommended to use LDO1P8_VOUT to power the AON_IO_VCC. If it is fed by any other source, please make sure that the timings are met. The internal TPS62743 buck regulator is fed by VSYS and its enabling is controlled by SoC GPIO. The internal buck regulator is turned on by default at startup. The software can turn it off after booting.
Note:
AON_IO_VCC should be applied at the same time or before LDO1P8_VOUT rises.
Figure 3-13. Intel® Curie™ module power sequence
Intel® Curie™ module sequence A
VSYS tPWR_OPM
B
AVD_OPM_2P6 tPWR_AON_1P8
C
VCCOUT_AON_1P8 (INT) tPWR_AON_PWR
D
VCC_AON_PWR tPWR_ESR3
F
VCCOUT_ESR3_1P8 tPWR_IO_VCC
AON_IO_VCC
E tHOST_1P8_PG
G
VCC_HOST_1P8_PG
Internal buck timing BUCK_EN tPWR_BUCK_VOUT
BUCK_VOUT
Table 3-6 shows the timing parameters.
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Table 3-6.
Timing parameters
Parameter
Min
Typ
Max
Units
tLDO1P8_VOUT
-
6.2
-
ms
tPWR_ESR3
-
925
-
µs
tPWR_IO_VCC
0
-
-
ms
tHOST_1P8_PG
-
100
-
µs
tPWR_BUCK_VOUT
-
10
25
ms
3.7.1
Measured timings for reference Figure 3-14 and Figure 3-15 present the waveforms obtained with measurements in the lab. They are provided for reference only.
Figure 3-14. Timing relationship between VIN, OPM2P6_VOUT and LDO1P8_VOUT
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Figure 3-15. Timing relationship between LDO1P8_VOUT, VDD_HOST_1P8 and VDD_HOST_1P8-PG
3.8
Unused pins All the IO pins that are not used must be handled properly to reduce the leakage power and avoid some system misbehavior. We recommend the following to ensure the proper state of the unused IO pins: • Input only pin – must be pulled high or low using a resistor. • Output only pin – can be left unconnected but must always be driven low or high • Bi directional pins – must be configured as output pins. These pins must always be driven low or high by the software.
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Subsystems
4
Subsystems
4.1
Analog power and input routing
4.1.1
ADC ground The inputs to the Intel® Curie™ module Analog to Digital Converter (ADC) are multiplexed with the IO pins of the Intel® Curie™ module and a separate analog GND plane is highly recommended for the return path of the analog signals. The following analog guidelines are good practices to follow: • Provide dedicated GND planes for the analog ground, and connect these to the digital ground at a single point. • Keep the analog signals and analog GND away from the following: — high speed digital signals — switching mode power supplies — crystals and oscillators — other design specific components which can generate noise across traces or through planes.
4.1.1.1
ADC power ADC_3P3_VCC is the ADC block power input pin. Use a 0.1 uF decoupling capacitor. Use a clean power supply for good performance. Keep the power supply traces away from high frequency signals, DC-DC converters, and RF. Figure 4-1 shows a large analog ground around the Intel® Curie™ module ADC input pins and bridge to digital ground.
March 2017 Rev. 1.3
Intel® Curie™ Module Design Guide 35
Subsystems
Figure 4-1.
ADC ground example
Intel® Curie™ Module Design Guide 36
March 2017 Rev. 1.3
Subsystems
4.2
Bluetooth® low energy controller and antenna
4.2.1
Antenna placement The Bluetooth® low energy controller utilizes a Pulse W3008C ceramic chip antenna that can enable a host circuit board to radiate at 2.4-2.48 GHz frequencies in an omnidirectional pattern. Refer to the manufacturer datasheet for more details. This solution requires a ground clearance of 4.00 mm x 6.25 mm under the SMT antenna with all metalization removed from all circuit board layers under the antenna. As EMI shields and rings can limit the antenna performance, place the battery away from the antenna. An example of matching network is shown on Figure 4-2.
Figure 4-2.
March 2017 Rev. 1.3
Pad dimensions for the antenna device
Intel® Curie™ Module Design Guide 37
Subsystems
I2C interface design guidelines
4.3
There are four I2C ports for Intel® Curie™ module. Two ports are for generic use and two are dedicated ports for the sensor subsystem. These operate in both master and slave mode. Both 7-bit and 10-bit addressing modes are supported and they support the standard mode (100 kbps), fast mode(400 kbps) and fast mode plus (1 Mbps).
4.3.1
I2C connections on the functional reference circuits Figure 4-3 shows an example I2C interface for a Intel® Curie™ module-based design.
Figure 4-3.
Example of I2C connection for a typical device
Intel® Curie™ module
Haptics Texas Instruments DRV2605* Led driver Texas Instruments LP5562*
I2C1_M_SCL
Display and touch support board
I2C0_SS_SCL
I2C1_M_SDA I2C0_SS_SDA
Near field communications STMicroelectronics ST54D*
6-AXIS_I2C_SS_SCL 6-AXIS_I2C_SS_SDA
Sensor header
4.3.2
Pressure and humidity sensor Bosch BME280*
Compass Bosch BMM150*
I2C0_SS
I2C interface signals Table 4-1 shows the maximum speeds for the I2C interface signals.
Table 4-1.
I2C interface signals
Name
Type
Max Frequency / Data Rate
Description
I2C[0:1]_SCL I2C[0:1]_SDA
I/O
1 MHz
Main I2C[0:1] clock and data
I2C_SS[0:1]_CLK I2C_SS[0:1]_DATA
I/O
400 kHz
Sensor Subsystem I2C clock and data
Intel® Curie™ Module Design Guide 38
March 2017 Rev. 1.3
Subsystems
4.4
LED driver example Figure 4-4 shows the I2C interface connections with an external LED driver module. The maximum current drawn from Intel® Curie™ module must be less than 25 mA. The functional reference circuits includes a Texas Instruments LP5562* LED driver connected through I2C1_M (address 0) to provide the features to Intel® Curie™ module-based devices: • Four independently programmable LED outputs with 8-bit current setting (from 0 mA to 25.5 mA with 100 uA steps) • Flexible PWM control for LED outputs • SRAM program memory for lighting pattern • Three program execution engines with flexible instruction set
Figure 4-4.
LED driver block diagram for a tricolor module
V_SYSTEM
V_SYSTEM
Intel® Curie™ module
I2C1_M_SCL
LED DRIVER Texas Instrument* LP5562
I2C1_M_SDA HSMF-C113
March 2017 Rev. 1.3
Intel® Curie™ Module Design Guide 39
Subsystems
Figure 4-5.
LED driver example circuit for a tricolor module
4.5
I2S interface design guidelines The following I2S interface signals are not implemented on the functional reference circuits; these ports are connected to J1200 connector and can be used externally if needed. Leave the ports unconnected if not used.
4.5.1
Signals for the I2S interface Table 4-2 lists the I2S interface signals.
Table 4-2.
I2S interface signals
Name
Type
Maximum Audio Sample Rate
Description
I2S_RSCK I2S_TSCK
I/O
48 kHz
Clock signal for I2S
I2S_RXD I2S_RWS
I
48 kHz
RX Data for I2S
I2S_TXD I2S_TWS
O
48 kHz
TX Data for I2S
Intel® Curie™ Module Design Guide 40
March 2017 Rev. 1.3
Subsystems
4.5.2
I2S interface routing guidelines Table 4-3 lists the I2S routing guidelines.
Table 4-3.
4.6
I2S routing guidelines I2S Interface
Max Drive Strength
I2S_RSCK
4mA (1.8V IO), 7.6mA (3.3V IO)
I2S_TSCK
8mA (1.8V IO), 7.6mA (3.3V IO)
I2S_RXD
4mA (1.8V IO), 7.6mA (3.3V IO)
I2S_RWS
4mA (1.8V IO), 7.6mA (3.3V IO)
I2S_TXD
8mA (1.8V IO), 7.6mA (3.3V IO)
I2S_TWS
8mA (1.8V IO), 7.6mA (3.3V IO)
Sensors The Intel® Curie™ module has an integrated 6-axis sensing device that interfaces with the Intel® Quark™ SE microcontroller C1000 processor by exclusive use of SPI1_SS. This 6-axis sensing device includes the 6-AXIS_AUX_I2C port for the connection to an external environmental sensor. Powering the sensors with an Awake-ON rail will allow them to generate interruptbased wake events to the processor.
4.6.1
Integrated 6-axis sensing device interfaces The I2C master interface from the six axis sensing device can be connected to an external digital compass.
Table 4-4.
6-axis sensing device interface signals Name
Type
Maximum Frequency / Data Rate
Description
6Axis_SCL 6Axis_SDA
I/O
1 MHz
Clock and Data
6Axis_int2
I/O
400Hz
GPIO
Note:
The 6-axis sensing device is powered in common with the Bluetooth® low energy controller.
4.6.2
Environmental inputs This section presents application examples where additional sensors communicate with the Intel® Curie™ module over I2C to provide additional data.
4.6.2.1
Pressure and humidity sensor The concept shows the usage of Bosch* BME280 pressure/humidity/temperature sensor connected with Intel® Curie™ module over I2C0_SS, which supports up to 400 kHz. Consult the manufacturer’s datasheet for the latest details on specific features, including: • I2C digital interface
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Intel® Curie™ Module Design Guide 41
Subsystems
• Operating pressure range of 300-1100 hPa and relative humidity of 0 to 100% • Up to 16 over-sampling rate
4.6.2.2
Magnetometer (Geo Compass) Figure 4-6 shows the usage of Bosch* BME150 3-axis magnetometer connection through the Bosch* BMI160 6-axis sensing device I2C for synchronized operation with the accelerometer and gyroscope. Consult the manufacturer’s datasheet for the latest details on specific features, including: • I2C digital interface • On-chip interrupt controller • Magnet field resolution of ~ 0.3uT
Figure 4-6.
Extended environmental sensor block diagram
VDDIO
I2C0_SS_SCL I2C0_SS
I2C0_SS_SDA
Pressure and humidity Bosch BME280*
Intel® Curie™ module VDDIO
6-AXIS_AUX_I2C_SCL 6AXIS_I2C GPIO_SS[3]/AIN[11]
Figure 4-7.
6-AXIS_AUX_I2C_SDA COMPASS_INT
Compass Bosch BMM150*
External environmental sensor example circuit
Intel® Curie™ Module Design Guide 42
March 2017 Rev. 1.3
Subsystems
4.7
Haptics Haptics are often used to confirm user actions and provide subtle feedback, alerts and prompts to the end use or partner device.
4.7.1
Device driver Figure 4-8 shows the example of Intel® Curie™ module connected to a Texas Instrument* DRV2605 haptic driver using I2C1_M. The Texas Instrument* DRCV2605 is powered by V_SYSTEM while providing interrupts on a multiplexed GPIO. Consult the manufacturer’s datasheet for the latest details on specific features, including: • I2C digital interface • On-chip interrupt controller • Magnet field resolution of ~ 0.3uT
Figure 4-8.
Haptic driver block diagram
V_SYSTEM
Intel® Curie™ module VDDIO HAPTICS_EN
I2C1_M_SCL I2C1_M
I2C1_M_SDA
HAPTIC Texas Instruments DRV2605*
M
ERM GPIO[1]/AIN[1]/SPI_S_MISO
March 2017 Rev. 1.3
HAPTICS_PWM_AIN_TRG
Intel® Curie™ Module Design Guide 43
Subsystems
Figure 4-9.
Haptic driver - example circuit
4.7.2
Reference Eccentric Rotating Mass (ERM) device The functional reference circuits is configured with an ERM unit from Precision Microdrives (304-103)*. Consult the manufacturer’s datasheet for the latest details on specific features, including: • Rated operating voltage of 2.7V • Rated vibration speed of 14000rpm [+/-3000] • Maximum rated operating current of 75mA
4.8
SPI interface Intel® Curie™ module has four SPI interfaces, three are available externally and only two are used on the functional reference circuits. Figure 4-10 shows a simplified block diagram of typical SPI connections for flash memory, display/touch and NFC solutions.
Intel® Curie™ Module Design Guide 44
March 2017 Rev. 1.3
Subsystems
Figure 4-10. SPI simplified topology example
VDD_PLAT_1V8
module FLASH_RST GPIO[3] / AIN[3] / SPI_S_MOSI
SPI FLASH FLASH_WP MACRONIX MX25U12835F*
NFC use SPI1_M as the secure microcontroller communication and Curie mulitplexed GPIO for interrupt signaling
GPIO[14] / SPI1_M_CS_B[3]
27.12MHz VDD_PLAT_1V8
SPI1_M_CS2
SPI0_M_CS2
VPS_IO
SPI0_M_MISO SPI0_M_MOSI
V_SYSTEM
SPI1_M_SCK SPI0_M
SPI1_M
SPI1_M_MOSI
SPI0_M_SCK SPI1_M_MISO
SPI0_M_CS1
NFC_INT GPIO[2] / AIN[2] / SPI_S_SCK
VBAT
NFC
ANT
NFC_RST
GPIO[15] / I2S_RXD GPIO[20] / I2S_TXD
Display and Touch system
DISPLAY ON/OFF GPIO[17] / I2S_RWS DISPLAY GPIO
NFC_GPIO
AFE
STMicroelectronics ST54D*
GPIO[19] / I2S_TWS
TOUCH INT ATP INT2 TOUCH RST GPIO_SS[12] / PWM[2]
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Intel® Curie™ Module Design Guide 45
Subsystems
4.8.1
SPI interface signals on the Intel® Curie™ module Table 4-5 lists Intel® Curie™ module SPI interface signals.
Table 4-5.
Intel® Curie™ module SPI interface signals
Name
Input / Output
Maximum Frequency / Data Rate
Description
SPI0_M_SCK
Output
16 MHz
SPI Serial Clock
SPI0_M_CS[2:0]_N
Output
8 MHz
SPI Chip Select
SPI0_M_MISO
Input
8 Mbps
SPI Slave Output Master Input
SPI0_M_MOSI
Output
8 Mbps
SPI Master Output Slave Input
SPI1_M_SCK
Output
16 MHz
SPI Serial Clock
SPI1_M_CS[3:0]_N
Output
8 MHz
SPI Chip Select
SPI1_M_MISO
Input
8 Mbps
SPI Slave Output Master Input
SPI1_M_MOSI
Output
8 Mbps
SPI Master Output Slave Input
4.9
Flash memory Intel® Curie™ module supports up to 128 MB of Flash memory to hold on-board applications and the collected data. The functional reference circuits use a Macronix MX25U12835F* serial flash memory for additional storage. A maximum of 128 MB can be connected with the Intel® Curie™ module SPI0_M interfaces. Figure 4-11 illustrates the connection between SPI Flash and the Intel® Curie™ module.
Figure 4-11. SPI Flash - use example
VDDIO
SPI0_M_CS2
SPI0_M_SCK
SPI Flash MACRONIX MX25U12835F*
SPI0_M_MOSI
Intel® Curie™ module
SPI0_M_MISO
POR
Intel® Curie™ Module Design Guide 46
March 2017 Rev. 1.3
Subsystems
Figure 4-12. Flash memory circuit for SPI interface
4.10
Display panel and touch controller Intel® Curie™ module can be connected to an external display using SPI and I2C interfaces while GPIO handles the panel controls. Figure 4-13 shows an application example with Sharp* S010B7DH02 display panel and a Cypres* (I2C) CY8CTST241 capacitive touch screen controller. Consult the Sharp* LS010B7DH02 datasheet for additional information on the following features: • Transflective panel of white and black • Digital SPI interface • 1.02 inch screen with 96 x 150 resolution • 1 bit internal memory for data storage within the panel Consult the Cypress* CY8CTST241 datasheet for additional information on the following features: • Up to 32 sense pins • Large object detection • Resistance to LCD noise • Wide supply voltage range from 1.71 V to 5.5 V • Integrated voltage regulator
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Intel® Curie™ Module Design Guide 47
Subsystems
Figure 4-13. External display topology example
SPI1_M_CS1 VDDIO VDDIO
SPI1_M_SCK SPI1_M_CS1 SPI1_M_MOSI SPI1_M_SCK SPI1_M_MISO
V_SYSTEM
SPI1_M_MOSI I2C0_SCL
V_SYSTEM
Intel® Curie™ module
module
I2C0_SDA SPI1_M_MISO
VDD_PLAT_3V3
I2C0_SCL DISPLAY ON/OFF I2C0_SDA DISPLAY GPIO
VDD_PLAT_3V3
Display panel and touch controller system
TOUCH INT TOUCH RST
DISPLAY_ON/OFF 5V_EN GPIO[17]/I2S_RWS I2C EXPANDER DISPLAY_GPIO GPIO[19]/I2S_TWS TOUCH_INT ATP_INT2 TOUCH_RST ATP_SPI_S_MOSI/AIN[3]/GPIO[3]
5V_EN
Intel® Curie™ Module Design Guide 48
I2C expander
March 2017 Rev. 1.3
Subsystems
4.11
Near Field Communication (NFC) Intel® Curie™ module connects to an NFC controller secure element through I2C1-M (NFC router communication) and SPI1_M (for secure micro controller communication) interface. The specific functionality, including power management and the NFC card emulation are dependent upon software (not provided). The example shown in Figure 4-15 is designed around STMicroelectronics ST54D* NFC controller with built-in secure element. The NFC controller is connected to Intel® Curie™ module on I2C1-M (NFC router communication) and SPI1_M (for secure micro-controller communication) interface. The NFC support card emulation mode is supported and a dedicated interrupt pin is connected to Intel® Curie™ module GPIO.
4.11.1
NFC controller features • Integrated AFE • Optimized power consumption modes • I2C slave interface up to 1Mbps • Integrated 36 kB EEPROM • Support up to three external secure element
4.11.2
ARM* SecurCore microcontroller features • ARM SecurCore SC300* 32-bit RISC core • 1280 kbytes of flash memory available • Single wire protocol (SWP) interface for communications with NFC router in SIM/ NFC application • SPI slave interface for non-SIM application
March 2017 Rev. 1.3
Intel® Curie™ Module Design Guide 49
Subsystems
Figure 4-14. NFC connections
VDDIO
I2C1_M_SCL VPS_IO
I2C1_M_SDA SPI1_M_SC2
V_SYSTEM
SPI1_M_SCK VBAT SPI1_M_MOSI ANT
AFE
NFC controller with secure elements STMicroelectronics ST54D*
Intel® Curie™ module SPI1_M_MISO NFC_INT NFC_RST NFC_GPIO
GPIO[2]/AIN[2]/SPI_S_CLK GPIO[15]/I2S_RXD GPIO[20]/I2S_TXD
Figure 4-15. NFC example circuit
Intel® Curie™ Module Design Guide 50
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Subsystems
4.12
UART0 for Bluetooth® low energy controller Intel® Curie™ module contains two instances of UART controllers, UART0 is dedicated to the integrated Nordic nRF51822* Bluetooth® low energy controller while UART1 is available for use with mobile data systems and debug tools.
Figure 4-16. UART interface topology
Intel® Curie™ module UART0_RX UART0_TX UART0_CTS# UART0_RTS#
Bluetooth® low energy controller Nordic nRF51822*
Intel® Quark™ SE C1000 UART1_RX UART1_TX UART1_CTS#
Debug connector
UART1_RTS#
4.13
UART1 interface signals Table 4-6. lists the UART1 interface signals.
Table 4-6. Name
UART interface signals Type
Max Data Rate
Description
UART1_RX
I
2 MHz
High-speed receive data input
UART1_TX
O
2 MHz
High-speed transmit data
UART1_RTS
I
2 MHz
High-speed request to send
UART1_CTS
O
2 MHz
High-speed clear to send
Note:
March 2017 Rev. 1.3
The UART signals that are not implemented on a design can be left unconnected.
Intel® Curie™ Module Design Guide 51
Subsystems
4.14
USB interface design considerations Consider these general routing and placement guidelines when laying out a new design to optimize the signal quality and EMI: • The maximum trace length is 4 inches. • Do not route traces under crystals, oscillators, clock synthesizers, magnetic devices, or ICs with strong clocks. • Follow the 20 × h rule by keeping traces at least [20 × (height above the plane)] mils away from the edge of the plane (VCC or GND, depending on the plane the trace is over). • For an example stackup, the height above the plane is 4.5 mils (0.114 mm). There is a 90-mil (2.286 mm) spacing requirement from the edge of the plane. This prevents the coupling of the signal onto adjacent wires and also prevents free radiation of the signal from the edge of the PCB. • Avoid stubs on high-speed USB signals because stubs cause signal reflections and affect the signal quality. If a stub is unavoidable in the design, the total of all the stubs on a particular line should not be greater than 200 mils (5.08 mm). • We recommend placing a low ESR 1 µF ceramic capacitor close to the VDD_USB pin. • If a USB port is not implemented on the design, the USB_DP/N[x] signals can be left unconnected. • Protect the USB lines with ESD diodes for safe performance. • Adding a 1.07K bleeding resistor to the USB power line can provide an immediate discharge path for the USB power.
Table 4-7.
USB 1.1 differential pair length matching table
Signal Name
Type
Max Frequency / Data Rate
Description
USB_DP
Input / Output
12 Mbps
Universal serial bus port differential (USB Data+)
USB_DM
Input / Output
12 Mbps
Universal serial bus port differential (USB Data-)
Figure 4-17. USB 1.1 port topology
USB_DPO Intel® Curie™ module
Intel® Curie™ Module Design Guide 52
CMC USB_DNO
ESD
USB micro-B connector
March 2017 Rev. 1.3
Subsystems
4.14.1
USB 1.1 length matching
Table 4-8.
USB 1.1 differential pair length matching table
March 2017 Rev. 1.3
Signal
Total intra pair screw
USB_DP
150 mils
USB_DM
150 mils
Intel® Curie™ Module Design Guide 53
Circuit Board Recommendations
5
Circuit Board Recommendations
5.1
Fundamental design rules All the routing guidelines (W/S, isolation, length requirement) are modeled around a 4layer, Type II printed circuit board. If a different PCB stack-up is implemented, the electrical guidelines (impedance, insertion loss) provided in this design guide must be followed to ensure that the layout meets the design recommendations. The following rules pertain to all the subsystems discussed in this chapter. • The length values are tested and measured as package-pin-to-package-pin. • The break-out and break-in minimum spacing ratio is 1:1 for all interfaces. • The trace width/intra-spacing for differential pairs and trace width for single-ended signals depend on the impedance. • For analog signals, it is important to keep the analog ground return path clean from digital noise to maintain a high signal-to-noise ratio. • All inputs, tristate buses and signals that are not connected must be pulled up or down by the firmware or hardware to prevent oscillation. This is especially important for enable or control signals like JTAG TMS signal. • Unused and reserved signals are terminated as no connection, unless otherwise specified. • The power sources and input regulation components must remain stable across the entire operating range of voltage and device systems.
5.2
PCB thickness and stack-up Stackup refers to the thickness as comprised of the number of layers, the PCB technology (and via details), the thickness of each layer and the Cu weights on each layer. Fab drawings have a stack-up or cross section figure. The concept referenced in this document uses high density interconnect, and type 3, 4layer board technology. The trace width for radio frequency and high speed signal driver impedance must be determined per the selected stack-up.
5.2.1
Two-layer boards The Intel® Curie™ module can be placed on a two-layer board for simple designs that have limited buses susceptible to interference noise, or when the footprint is not a primary constraint and signals can be physically separated to improve noise tolerance.
Table 5-1.
Two-layer stack-up design
Layer
Type
Material
Thickness (mm)
Dielectric Constant
Trace Width (mm)
-
Surface
Air
-
1
-
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Circuit Board Recommendations
Table 5-1. Layer
Two-layer stack-up design (continued) Type
Material
Thickness (mm)
Dielectric Constant
Trace Width (mm)
-
Solder Mask
FR-4
0.02
4.2
-
Top
Conductor
Copper
0.036
4.2
0.102
-
Dielectric
FR-4
1.48
4.2
-
Bottom
Conductor
Copper
0.036
4.2
0.102
-
Solder Mask
FR-4
0.02
4.2
-
-
Surface
Air
-
1
-
5.2.2
Four-layer stack-up
Table 5-2.
Four-layer stack-up design
Layer
Type
Material
Thickness (mm)
Dielectric Constant
Trace Width (mm)
-
Surface
Air
-
1
-
-
Solder Mask
FR-4
0.05
4.5
-
Top
Conductor
Copper
0.015
1
0.13
-
Dielectric
FR-4
0.068
4.5
-
L2_GND1
Conductor
Copper
0.015
4.5
0.1
-
Dielectric
FR-4
0.55
4.5
-
L3_GND2
Conductor
Copper
0.015
4.5
0.1
-
Dielectric
FR-4
0.068
4.5
-
Bottom
Conductor
Copper
0.015
1
0.13
-
Solder Mask
FR-4
0.053
4.5
-
-
Surface
Air
-
1
-
Total Thickness: 1.6 mm
5.2.3
Six-layer stack-up Figure 5-1 shows the cross section of a 48 mil thick, 6-layer, HDI type II board with blind vias from 1-2 and 1-3, with additional thruhole vias. The board contains 1.4 oz copper (Cu) on the outer layers and 0.25 – 0.50 oz copper on the inners layers, as detailed in Table 5-3.
Table 5-3.
Six-layer stack-up design
Layer
Type
-
Surface
Air
-
1
-
-
Solder Mask
FR-4
0.05
4.5
-
Top
Conductor
Copper
0.015
1
0.13
-
Dielectric
FR-4
0.068
4.5
-
L2_GND1
Conductor
Copper
0.015
4.5
0.1
-
Dielectric
FR-4
0.55
4.5
-
L3_PWR1
Conductor
Copper
0.015
4.5
0.1
-
Dielectric
FR-4
0.2
4.5
-
March 2017 Rev. 1.3
Material
Thickness (mm)
Dielectric Constant
Trace Width (mm)
Intel® Curie™ Module Design Guide 55
Circuit Board Recommendations
Table 5-3. Layer
Six-layer stack-up design (continued) Type
Material
Thickness (mm)
Dielectric Constant
Trace Width (mm)
L4_CLK1
Conductor
Copper
0.015
4.5
0.1
-
Dielectric
FR-4
0.55
4.5
-
L5_GND2
Conductor
Copper
0.015
4.5
0.1
-
Dielectric
FR-4
0.068
4.5
-
Bottom
Conductor
Copper
0.015
1
0.13
-
Solder Mask
FR-4
0.053
4.5
-
-
Surface
Air
-
1
-
Total Thickness: 1.6 mm
5.2.3.1
Six-layer stack-up cross section Figure 5-1 shows a six-layer stack-up cross section.
Figure 5-1.
Thickness of a six layer stack-up
§
Intel® Curie™ Module Design Guide 56
March 2017 Rev. 1.3
Debug and Production Options
6
Debug and Production Options
6.1
JTAG connector or test pads The usual JTAG connections can be routed to test points or header pins depending on the need and design intent. • JTAG_TDO • JTAG_TDI • JTAG_TCK • JTAG_TMS • JTAG_RST_B Figure 6-1 shows the debug ports on the Intel® Curie™ module.
Figure 6-1.
Block diagram of the debug ports on the Intel® Curie™ module
JTAG
JTAG header
Intel® Curie™ module UART_1 BLE_JTAG
March 2017 Rev. 1.3
Debug AOB
Intel® Curie™ Module Design Guide 57
Debug and Production Options
Figure 6-2.
Debug ports on the Intel® Curie™ module
VDD_IO
1 3 5 7 9
C1005 0.1uF 10% .0201
J1002
R1003 10K 5% . 2 4 6 8 10
R1004 10K 5% .
R1016 10K 5% NO_STUFF
R1010 10K 5% NO_STUFF JTAG_TMS JTAG_TCK JTAG_TDO JTAG_TDI
JTAG_TRST_B
10 Pin Header .
6.2
R1005 10K 5% .
R1008 10K 5% NO_STUFF
R1009 10K 5%.
Power rail test pads The power rail test pads are the test points for the primary voltage rails, LDO outputs, and a clean ground. They are very helpful to debug and for device measurements.
6.3
UART test pads Intel® Curie™ module, when in manufacturing mode, sends out messages on the UART right from power up. Thus access to the UART provides additional access to system functions and information logs. • AIO_05_UART_RX • AIO_05_UART_TX
6.4
Bluetooth® low energy controller test pads A Jlink emulator can be used to program or reprogram the Bluetooth® low energy controller firmware. The board digital ground needs to be connected between the board and the Jlink emulator. Also Vref from the Jlink emulator needs to connect to the same voltage level as the VDD_BLE_SEN signal. This allows the emulator to communicate to the Bluetooth® low energy controller with the correct logic level. • BLE_SWDIO • BLE_SW_CLK
Note:
Jlink software utility allows the users to program a BLE image in .bin or .hex format. Refer to Jlink users manual and Nordic* website for more information.
Intel® Curie™ Module Design Guide 58
March 2017 Rev. 1.3
