Investigation of Scaling Methodology for Strained Si n-MOSFETs Using A Calibrated Transport Model Hasan M. Nayfeh', Judy L. Hoyt and Dimitri A. Antoniadis Department of Electrical Engineering and Computer Science, Microsystems Technology Laboratory Massachusetts Institute of Technology (MIT) 'work performed at MIT, Nayfeh is now with 1BM Semiconductor Research and Development Center (SRDC) 2070 Route 52 Hopewell Junction, NY 12j33 Tel: 845-892-2376,Fax: 845-892-2566',email: navfihmus. ibm.com
I,
ABSTRACT The performance, calculated in terms of on-current vs. off-current Ioe, of strained Si n-MOSFETs is
compared to bulk (unstrained) Si devices with gate lengths down to 22 nm using hydrodynamic simulations with calibrated smined Si transport models. Strain results in I,. enhancement for given Io#. hut increased Coulomb scattering in strained Si super-halo n-MOSFETs with gate lengths approaching 25 nm and surface doping near 6 x IO" cm.? results in reduction of I, enhancement by approximately 10%. Simulations also indicate that the use of a gate electrode material with workfunction larger than n' polysilicon is an attractive approach to achieve desired off-current for strained devices scaled below 25 nm gate length, and for devices with increased strain in the channel (i.e. substrate Ge contents > 20% Ge).
INTRODUCTION It has recently been shown experimentally that the Coulomb scattering-limited mobility associated with ionized channel impurities is not enhanced by strain'. As device gate length is scaled, channel doping concentration increases to maintain well-behaved electrostatics, increasing the influence of Coulomb scattering on performance. In addition, the use of higher channel doping in strained Si devices to match the threshold voltage, Vt; of unstrained Si MOSFETs further exacerbates the Coulomb scattering issue. Due to the changes in band structure, the native threshold voltage of strained Si n-MOSFETs is lower than that of unstrained devices with identical doping profiles. In addition, the reduced diffusivity ofB in SiGe produces steeper B doping profiles and hence tends to further reduce threshold voltages in strained-Si relative to unstrained-Si n-MOSFETs, for the same thermal processing. In this work the impact of Coulomb scattering and threshold voltage differences on performance is quantified. The effects of two different methods of matching loain unstrained and strained Si MOSFETs are compared in the simulations: increasing the halo doping concentration and adjusting the gate workfunction.
TRANSPORT MODEL CALIBRATION A physically-based mobility model that assumes a Matthiessen's rule summation of the various scattering
mechanisms for inversion layer carriers in a MOSFET' was calibrated for unstrained and strained Si devices using electrical measurements on devices described in Ref. [I]. The Channel layer for the strained Si devices was achieved by growth of a thin silicon layer on a relaxed Sio.sGeo.2 virtual substrate using the graded buffer technique?. The screened Coulomb mobility, ,&o,,,omb, shown in Fig. 1 was extracted from inversion layer electron mobility measurements, while the unscreened Coulomb mobility was determined from Ref [4]. Acoustic phonon and surface-roughness-limited mobility, and &,, were determined by fitting draincurrent simulations to electrical measurements by calibrating coefficients in the mobility model (Table I), and resulting fits are shown in Fig. 2. The extracted coefficients for the various mobility terms for strained and unstrained devices are shown in Table 2. The coefficients for & and ,&are 1 . 7 5 larger ~ for strained Si compared to unstrained Si, while they are the same for ,&o,,/om~. High lateral electric-field transport parameters (p and vsa,) in the Caughey-Thomas expression that relates lateral field to carrier mobility were fit to published velocity vs. field characteristics for strained and unstrained Si devices based on numerical solution of the Boltmann transport equations. The key parameter used for nonstationary transport modeling, the energy relaxation time, z, was set to 0.1 ps6 for the unstrained Si devices and was multiplied by a factor of 1.75, i.e. by the long channel mobility strain-induced enhancement factor, for the strained Si devices. The physical rationale for this enhancement in q,, is explained in Ref. 171. Additional support for this can be found in Ref [SI where such enhancement in c,, was found necessaty in order to explain measured results in 100 nm strained Si n-MOSFETs fabricated on Sio.xGeo substrates.'
RESULTS AND DISCUSSION The simulated device structure with super-halo doping profile and an ni polysilicodsilicon dioxide gate stack is shown in Fig. 3. Fig. 4 illustrates the effect of the observed lack of Coulomb mobility enhancement in strained-Si MOSFETs. Relative to hypothetical strainedj& and ,us? equally enhanced Si MOSFETs with there is increasing loss of I,, improvement with decreasing gate length when ,uL7,,,gomh is not enhanced. However, the
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loss does not exceed 10% for devices with gate length greater than 25 nm, and corresponding surface doping less than 6 x I O t 8 cm? Fig. 5 shows that I,* for strained Si devices is larger than for unstrained Si with the same doping profile, while drain induced barrier lowering, DIBL, and sub-threshold swing, SS, are almost identical, as shown in Fig. 6, and thus have negligible impact on the loRdifference. The primary cause of the higher Ion in the simulated strained Si MOSFETs is a V, shift (in this case a reduction of 55 mV) which is due to the band structure differences between strained and unstrained Si devices. The band structure in inversion, taken at the middle of the channel of a sub-100-nm strained device, is shown in Fig. 7. In Fig. 8, simulated and experimentally measured Vt shift for long-channel devices with closely matched doping profiles' is compared demonstrating the accuracy of the simulation. Moreover, simulations indicate a reduced Vt shift with decreased oxide thickness. The oxide thickness influence on the V, shift can be explained in terms of the decreased depletion charge for the strained devices compared to unstrained due to the conduction band offset between the strained Si and relaxed Sio.8Geo.z layers. Two methods were studied to increase V, of the strained Si MOSFETs to match the I.# to that of unstrained Si devices: (a) increased gate workfunction, and (b) increased channel doping concentration. Increased channel doping was achieved by using a 13% larger halo dose for the strained devices. For either method, a significant oncurrent enhancement of 30% for a given lo$ is predicted for 25 nm gate length devices with these idealized super-halo doping profiles as shown in Fig. 9. A 30% increase in I, associated with a 75% increase in low-field mobility is consistent with measurements of a correlation factor R 0.5 between I,,. and low-field mobility changes in deep submicron devices subjected to mechanical bending'.
In this work, a calibrated hydrodynamic transport model for strained Si n-MOSFETs has been presented. The impact of Coulomb scattering and band-offset-induced V, differences on between strained and unstmined devices have been studied. Surface doping concentration should be kept below 6 x 10" cm" to realize the full benefits of strained Si. Gate workhction engineering is an attractive approach to achieve desired off-current in strained Si MOSFETs with sub-25-nm gate lengths, particularly in cases where the V, difference 6om unstrained Si devices is larger than 100 mV. ACKNOWLEDGEMENTS This work was supported by the SRC under contract 2000-NJ-841 and DARPA under contract N66001-00-18954. The authors would like to thank lhsan Djomehri for useful discussions, and Christopher Leitz, Arthur Pitera and Eugene Fitzgerald for strained Si substrate preparation. REFERENCES (I)H. M. Nayfeh, C. W. Leitz, A. 1. Piterq J. L. Hoyt, and D. A. Antoniadis, IEEE Elec. Dev. Lett. Vol. 24. No. 4 D. 248-250.
April 2003. (2) C. Lombardi. S . Manzini. A. Saoorito. and M. Vanzi. IEEE irans. O n C A D V o l . 7 , N o . l i p . 1164-1171 1988 (3) E. A. Fitzgerald,Annu. Rev. Mat. Sei,p. 417-454, 1994 (4) A. Mujtaba, S . Takagi, and R. Dutton, VrSISymp. p. 99-100
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Next we examine the sensitivity of our conclusions to some important simulation parameters. Fig. 10 shows that for equal z,. the calculated enhancement in 1. decreases rapidly as channel length is decreased. Similarly, Fig. 11 shows that for a given gate workfunction (i.e. n' polysilicon) the 1,. enhancement at constant-l,* decreases as the V, difference between strained and unstrained Si, AV,, increases. Given some uncertainty in the band offsets between strained Si and Sil.,Ge,,l0~" and interest in using increased strain, which will increase the AV,, Fig. 1 1 illustrates the need for alternative gate materials with adjustable workfunction.
CONCLUSIONS
1995 ( 5 ) Th. Vogelsang, and K. R. Hofmann, Appl. Phys. Lett. Vol. 63,No. 2 p . 186-188, 1993 (6) D. A. Antoniadis, 1. Djomehri, and A. Lochtefeld, "Electron Velocity in sub-50-nm Channel MOSFETs", SISPAD proceedings, p. 156,2001 (7) P. F. Bagwell, D. A. Antoniadis, T. P. Orlando, VLSI Electronics Microsiruclure Science, Vol. 18, p. 346-355, 1989 (8)K. Rim, I.L. Hoyt, and1.F. Gibbons, IEDM 1998, p. 707. (9) A. Lochtefeld, D. A. Antoniadis, IEEE Elec. Dev. Letr, No. 2, Vol. 22, p. 95-97, Feb 2001 (1O)C. G. Vande Walle,and R. M. Martin, Phys Rev. B Vol. 34, No. 8, p. 5621-5634, 1986 (II ) J. Welser, Ph.D. Thesis, Stanford Univ., 1994 Coulomb
Acoustic Phonon
Surface-roughness
Table 1: Analytical expressions for mobility limited by the three dominant scattering mechanisms for inversion layer carriers in a MOSFET: Coulomb, acoustic phonon, and surface-roughness.Symbols are defined as follows: El is the local vertical field, N,, and n are the doping and toIal electron concentration, and T is the lattice temperature. constants
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IO',
Coulomb screened
A=2700
w.90
Coulomb unscreened
D=3.86x109
qd.386
4.95
Table 2 Calibrated mobility model coefficients for unstrained Si in CGS units. For the strained Si devices. the coefficients for the
acoustic-phonon and surface-roughness limited mobility (a, p, 6) are increased by I .75X over those in Si, while equivalent coefficients are used for Coulomb limited mobility, as explained in the text.
Fig. I: Extracted Coulomb limited mobility in strained Si plotted on a loglog scale versus inversion charge areal density, N;, calculated for three different channel doping concentrations, N, (from Ref [I]). The Coulomb mobility was extracted using a Matthiessen's rule summation to fit the total mobility bared on the measured data The data show a power-law dependence on N, and N,
Fig. 3: Cross-section of a nanoscale n-MOSFET showing a contour map of the channel doping in units of 10'' cm" volume density concentration C'super-halo").Relevant physical dimensions are given by: gate length (25 nm), oxide thickness (1.4 nm) and junction depth (25 nm). The boron doping peaks at a level near 10l9 cm" and drops to 3 x 10'' cmJ at the surface indicating a super-steep rebograde profile.
Fig. 2: Measured (symbols) and simulated (dashed lines) Id-Vg characteristics for strained Si devices. Close agreement IS obtained between simulated and measured drain current for various channel doping concentrations for both unstrained (not shown) and strained Si MOSFETs.
I super-halo doping from Fig. 3.
enhanecd +Coulomb mobilily enhanced 1.75X
/--
22
25
50
250
500
1000
. .
Gate LemUl "~inml ~~
~
Fig. 4 On-current enhancement versus gate length. Two svained Si devices we compared: one with (solid) and one without (dashed) enhancement in the Coulomb mobility.
' -
0
0.5
i
1.5
2
On-currenf [""m]
Fig. 5: I,. vs. lor characteristics for strained and unstrained Si devices with equivalent "super-halo" channel doping. The off-current for strained Si devices is larger than that for unstrained Si for all gate lengths, due to the reduced threshold voltage for strained Si devices.
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-
I
strained si --1.5)
0
22
25
'
10
20
?O
40
50
60
70
DirtaneeInml
36 50 75 100 250 500 Gate Length [nm]
Fig. 6: Sub-threshold slope and DlBL of strained and unstrained Si devices versu gate length. The slope is negligibly larger for the strained devices,
due to a slightly larger depletion region depth, and larger dielectric constant. 150
Fig. I . Energy band smcture for strained and unstrained Si n-type MOSFET versus vcrtical distance from the SilSiOt interface. The strained Si device has a smaller bandgap material (by 100 meV) in the quasi-neutral region compared to unstrained Si. Conduction and valence hand offsets also contribute to the smaller threshold voltage.
1
Gate workfunction
Engineering (strained Si) '090
3 4 5 6 7 oxide thickness Inml Fig. 8: Threshold voltage shift between simulated long-channel &gate = 1") strained and unstrained si devices with identical doping The channel doping is a super-steep with pe* doping rade surface doping of 3 I$ cm-', from Ref. [SI. At 6 nm, of 10'8 ,~3 Simulations are in close agreement with published experimental data on devices with well-matched doaine orofilesfor strained and unstrained MOSFETs (open symbol) from g f . [8]. 1
2
~~
0.5
1
on-current [mtvuml
1.5
Fig. 9: I, vs. I.* for three devices: ( I ) unstrained Si with n+ polysilicon gate, (2) strained Si with gate workfunction incrcased by 55 mV compared to n+polysilicon, and ( 3 ) strained si with n+ poksilicon gate and 13% increase in channel doping Concentration compared unstmincd si. The unstrained si devices have channel doping equivalent to the super-halo shown in Fig. 3. Significant I,. enhancement is predicted for a fixed lorat channel length.
strained Si unstrained Si rw=0.17ps Tw=O.lps T,=o.lps .r,=O.lps -A
rn..'
,o...''
ep''
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P
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100
100
150
Mdifference [my
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'ig. 1 0 On-current enhancement for simulated strained si campared to ""strained ji devices with super.halo channel doping piofile Bs i n ~ i 3. ~ . increase in :nergy relaxation time (from 0.1 to 0.17 ps) is responsible for a large portion he predicted on-current enhancement far channel lengths below 100 nm.
Fig. 11. Perfom"e enhancement versus V, difference between unstra and strained Si MOSFETs. The V,difference was achieved by adjusting conduction band offset between strained Si and SiGe. The off current matched for each point by either increased doping concentration (solid I or increased gate workfunction (dashed line). The piat shows that fo difference larger than 100 mV, gate workfunction engineering is an attrac approach ta achieving maximum performance benefit.
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