USO0RE40773E

(19) United States (12) Reissued Patent

(10) Patent Number:

Hashimoto (54)

(75)

(45) Date of Reissued Patent:

Jun. 23, 2009

DRIVE CIRCUIT FOR DRIVING AN IMAGE

5,250,937 A

* 10/1993 Kikuo et a1. ................ .. 345/89

DISPLAY UNIT

6,107,981 A

*

Inventor:

Yoshiharu Hashimoto’ Tokyo (JP)

8/2000 Fujita .......... ..

345/95

6,437,765 B1 *

8/2002 Kasai et a1.

345/89

6,570,560 B2 *

5/2003 Hashimoto ................ .. 345/211

FOREIGN PATENT DOCUMENTS

(73) Assignee: NEC Electronics Corporation, Kawasaki, KanagaWa (JP)

JP

5-158446

6/ 1993

JP

7-l047l6

4/1995

(21) Appl- Ne-I 11/133,483 (22)

US RE40,773 E

Filed?

OTHER PUBLICATIONS

May 20a 2005

Korean O?ice Action With Japanese Translation and Partial

English Translation. _

_

Related U‘s‘ Patent Documents

Relssue of‘

Color TFTiLCDs”, Society for Information Display (SID)

(64) Patent_NO"

(30)

Saito and Kitamura, “17.3: A 64bit Digital Data Driver for

_

65705“

International Symposium digest of technical papers, vol.

Issued Appl. No.:

May 27’ 2003 09/884,942

XXVI, pp. 2574260 (1995).*

Filed:

Jun. 21, 2001

* Cited by examiner

Foreign Application Priority Data

Jun. 28, 2000

P1’imary Examinerivilay Shankar (74) Attorney, Agent, or FirmiMcGinn IP LaW Group,

(JP) ..................................... .. 2000-194457

(51) Int- ClG09G 5/00

PLLC

(57)

ABSTRACT

(2006.01) A drive circuit has a judgement circuit for judging Whether

(52)

US. Cl. ........................ .. 345/211; 345/89; 345/212;

the magnitude of the input video data resides in a linear

345/690

region or the non-linear region of characteristic of liquid

(58)

Field of Classi?cation Search .......... .. 345/87403,

Crystal transmittance When the vide data resides Within the

3450042213’ 690 See application ?le for Complete Search history

linear region, some of the output gray-scale voltage for the LCD are generated by interpolation of adjacent tWo of the

gray-scale voltages generated by a voltage generator. The (56)

References Cited

reduced gray-scale voltage taps reduces the circuit scale and

Us‘ PATENT DOCUMENTS 5,196,738 A

*

the test procedures for the drrve crrcurt.

3/1993 Takahara et a1. .......... .. 327/530

13 Claims, 12 Drawing Sheets

j B0~B7 .

I B0,B5~B7 I

B0~B7 I

101A S

'

102A S

LSB

103A

CONTROLLER w151A ‘I

V Go o--_>

V0

7‘

1

GRAY-SCALE

;

GRAY-SCALE

VOLTAGE,

;

VOLTAGE

SELECTER

;

v Gn Q—-——>

/\ 1 04A

V22

VW .

Agg?zjgq

v

BLOCK

OUT

BLOCK

5

GEN -

l\/\ 105A

US. Patent

Jun. 23, 2009

Sheet 2 or 12

FIG_ 2 PRIOR ART

V8

V7

US RE40,773 E

US. Patent

Jun. 23, 2009

Sheet 3 0f 12

US RE40,773 E

HQ 3 PRIOR ART

120

100 > . O

.0.

80

O...

v...‘ Q '0

TRPAENSMIC 40

0*

60

\x

\

‘a

20

i.‘ O...0..

0

0

1

2

3

VOLTAGE (v)

5

US. Patent

Jun. 23, 2009

Sheet 4 0f 12

US RE40,773 E

FIG_ 4 PRIOR ART M9044

‘_____!‘L___‘ ‘____,~___ DECODER

0%

FIG_ 5 PRIOR ART

“Q2 v0 MJILJLAJTL

*1 '1 ‘I '1 v1 WQILJFLWJTL

VouT

US. Patent

Jun. 23, 2009

Sheet 7 0f 12

FIG. 8 VIDEO DATA

VOUT

00000000 V0 00000001 V1 00000010 V2 00000011 V3

00011110 00011111

00100000 00100001 00100010 00100011

11011110 P 11011111 -__-------_--1

11100000 11100001

11111110 V254 11111111 V255

US RE40,773 E

US. Patent

Jun. 23, 2009

Sheet 8 0f 12

US RE40,773 E

FIG. 9 104A 151A

I1

(b35132

M ._____ 1sw1

I: P1 P2

P3

‘“—°VouT

TO:LCD PANEL

VINT

301 B5~B7

1 ‘ COINCIDENCE

103A

CIRCUIT

_

302

50

V

151A TO:SW1

US. Patent

Jun. 23, 2009

Sheet 10 0f 12

FIG. 12 VIDEO DATA 00000000 00000001 00000010 0000001 1

00011110 00011111 00100000 00100001 00100010 00100011 00100100

V OUT V0 V1

V2 V3

(3/4)V32+ (1/4)V36 (2/4) V32+ (2/4)V36 (1/4) V32+ (3/4)V36 V36

11011100 V220 11011101 (3/4) V220+ (1/4)V224 11011110 (2/4) V220+ (2/4) V224 11101111 (1/4)v22o+(3/4)v224 11100000 11100001

11111110 V254 11111111 V255

US RE40,773 E

US. Patent

Jun. 23, 2009

Sheet 12 or 12

US RE40,773 E

FIG. 15

B0~B7

321

TH1~§

322

TH2_:§

323

US RE40,773 E 1

2

DRIVE CIRCUIT FOR DRIVING AN IMAGE DISPLAY UNIT

The gray-scale voltage generator 906 is con?gured as shown in FIG. 2, receiving speci?c gray-scale voltages V0 to V8, providing gray-scale voltage at eight tap points of a

Matter enclosed in heavy brackets [ ] appears in the original patent but forms no part of this reissue speci?ca tion; matter printed in italics indicates the additions made by reissue.

resistor ladder or resister string which divides each adjacent two of the speci?c gray-scale voltages V0 to V8, and output

ting intermediate gray-scale voltages through the tap points of the resistor ladder in association with the speci?c gray

scale voltages V0 to V8. Accordingly, the gray-scale voltage generator 906 outputs 64 voltage levels. By using a nonlin ear adjustment of the levels of the gray-scale voltages

BACKGROUND OF THE INVENTION

(a) Field of the Invention

V0-V8 in accordance with the characteristics of the LCD unit to be driven, a nonlinear correction can be obtained for the characteristics of the LCD unit with respect to the rela

The present invention relates to a drive circuit for an

image display unit and, more particularly, to a drive circuit for driving an image display unit to display thereon multi

tion between the voltage and the percent transmission, such

level gray-scale digital video data. The present invention

as shown in FIG. 3.

also relates to a method for operating such a drive circuit.

Referring to FIG. 4, the gray-scale voltage selector block

(b) Description of the Prior Art

904 includes a decoder 904-1 and switches 904-2 for each

pixel, the number of switches being equal to the number of gray scale levels to be displayed. The gray-scale voltage

FIG. 1 illustrates the con?guration of a conventional drive circuit for use in an image display unit such as a liquid

crystal display (LCD) unit. This drive circuit is used for displaying digital video data of 240 pixels each having six bits, or data of 240 pixels by 6 bits/pixel.

20

video data of each of the 240 pixels output from the data latch block 903 in accordance with the value of the 6 bits of video data, to output the resulting voltage as an analog sig nal.

The drive circuit of FIG. 1 includes an 80-bit shift register 901, a data register block 902, a data latch block 903, a

gray-scale voltage selector block 904, an output ampli?er block 905, and a gray-scale voltage generator 906. Power source voltages VDD1 and VSS1 are supplied to the 80-bit

shift register 901, the data register block 902, and the data latch block 903, while power source voltages VDD2 and VSS2 are supplied to the gray-scale voltage selector block

904, and the output ampli?er block 905. The 80-bit shift register 901 shifts an input pulse in the direction speci?ed by an R/L signal at each cycle of the clock (CLK) signal. More speci?cally, if the R/L signal indi cates the right direction, an STHR signal supplied at the

selector block 904 selects one voltage out of the 64 voltages,

supplied from the gray-scale voltage generator 906, for the

30

The ampli?er block 905 outputs the analog signal of the 240 pixels. These analog signals act as pixel signals of a single line selected by a vertical scan circuit (not shown). In addition, since a plurality of drive circuits for displaying the digital video data are arranged in the horizontal direction, all the pixel signals of the single line are made available simul

taneously. The scheme employed by the drive circuit for displaying 35

digital video data is generally referred to as the “resistor string method”. This drive circuit is described in Saito and

cycle of the CLK signal to output the resulting signal to the

Kitamura, “Society for Information Display (SID) Interna tional Symposium digest of technical papers”, Vol. XXVI,

data register block 902 as an STHL signal after 80 cycles of the CLK signal. Since the STHR signal includes a single pulse having a width of one clock pulse, pulses are output

pp.257-260 (1995). It is to be noted that each gray-scale voltage generator, disposed for a single pixel in the gray scale voltage selector block 904 described in the literature,

leftmost end of the 80-bit shift register 901 is shifted at each

40

successively through terminals C1, C2, . . . C79, and C80 of

the shift register 901 while the STHR signal is being shifted. On the other hand, if the R/L signal indicates the left direction, an STHL signal supplied at the rightmost end of the shift register 901 is shifted at each cycle of the CLK signal to output the resulting signal to the data register block

45

In the conventional resistor string method described above, although a 6-bit (64-level gray scale) drive circuit can be implemented without a signi?cant problem, an attempt to realize gray-scale levels higher than 64 levels may cause the

902 as an STHR signal after 80 cycles of the CLK signal. Since the STHL signal includes also a single pulse having a

width of one clock, pulses are output successively through

50

terminals C80, C79, . . . C2, and C1 of the shift register 901

others, the number of gray-scale voltage selectors employed

bits or a storage capacity for 240 pixels, receives video data

minals C1, C2, . . . C79, and C80.

55

64-level gray-scale drive circuit requires 64 gray-scale volt

drive circuit requires 256 gray-scale voltage selectors, four 60

The data latch block 903 latches the 240-pixel video data

capacity of 240-pixel data, and is provided because, while register block 902.

in the resistor string method is doubled and doubled as the level of gray scale increases bit by bit. For example, a age selectors per one output, whereas a 256-level gray-scale

supplied from the data register block 902 at once when a LATCH signal is active. The data latch block 903 has a

the ampli?er block 905 is outputting the video data for one line, the next video data for another line is input to the data

following problems. A ?rst problem is that employing a semiconductor inte grated circuit implementing the drive circuit may cause the chip to signi?cantly increase in siZe. This is because, among

while the STHL signal is being shifted. The data register block 902 has a storage capacity of 1440 D00-D25 for three pixels each including 6 bits in parallel at each cycle of the CLK signal, and successively stores video data in the data register block 902. That is, the video data input to the data register block 902 is successively stored in the data registers of the data register block 902 through ter

includes an enhancement transistor and a depletion transistor, as shown in FIG. 5, and disuses a transistor that is considered necessary to constitute the switch 904-2 shown in FIG. 4.

65

times as many as those of the 64-level gray-scale drive cir cuit. This causes the die area to increase, leading to an increased in its siZe.

A second problem is that longer time may be required for testing the semiconductor integrated circuit after it is fabri cated. The 64-level gray-scale drive circuit has 64 gray-scale voltage selectors per one output, and it is necessary to check

the function of all the voltage selectors. Similarly, in the

US RE40,773 E 3

4

256-level gray-scale drive circuit, it is necessary to check the function of all the 256 voltage selectors per one output. This may cause the testing time to increase four times, leading to

digital video data according to a ?rst embodiment of the

present invention;

SUMMARY OF THE INVENTION

FIG. 7 is a block diagram of the main portion of the drive circuit of FIG. 6. FIG. 8 is a table shoWing the relationship betWeen the

It is therefore an object of the present invention to provide a drive circuit for driving an image display unit, such as a

circuit for displaying multi-level gray-sale digital video data according to the ?rst embodiment of the present invention;

an increase in testing cost.

output voltage and the video data to be received by the drive

TFT (Thin Film Transistor) LCD unit, to display thereon multi-level gray-scale digital video data, especially such as having gray-scale levels of digital video data higher than eight bits per pixel, to realiZe reduction of the circuit scale,

FIG. 9 is a block diagram illustrating the con?guration of the output stage ampli?er block 104A shoWn in FIG. 7; FIG. 10 is a block diagram illustrating the con?guration of the least-signi?cant-bit controller 103A shoWn in FIG. 7; FIG. 11 is a block diagram illustrating the main portion of a drive circuit for displaying multi-level gray-scale digital

the die area, and the cost for testing the drive circuit. The present invention provides a drive circuit for driving a

display unit including: a gray-scale level voltage generator for generating a plurality of gray-scale level voltages, the

video data according to a second embodiment of the present

gray-scale voltages corresponding to magnitudes of possible

invention;

video data in one-to-one correspondence in a non-linear

FIG. 12 is a table shoWing the relationship betWeen the output voltage and the video data to be received by the drive

region of characteristic of liquid crystal transmittance and corresponding to magnitudes of possible video data in one to-n correspondence in a linear region of characteristic of liquid crystal transmittance Where n is an integer larger than one; a gray-scale voltage selector block for responding to input video data to select one of the gray-scale level volt ages; a judgement section for judging Whether a magnitude of an input video data resides Within the non-linear region or

20

invention; 25

the linear region to output a judgement signal indicating the

FIG. 15 is a circuit diagram illustrating the con?guration 30

age selector block When the judgement signal indicates the non-linear region and output one of the gray-scale voltages 35

NoW, the present invention Will be described beloW in more detail With reference to the accompanying draWings in accordance With the preferred embodiments. It is to be noted that similar constitute elements are designated by similar reference numerals or related reference numerals throughout

40

the draWings.

In accordance With the drive circuit of the present invention, use of the intermediate voltage betWeen adjacent

tWo of the gray-scale voltages in the linear region reduces the number of gray-scale voltages to be generated substan

tially Without degrading the image quality of the image dis

[First Embodiment]

play unit to be drive by the drive circuit, and reduces the circuit scale of the drive unit and reduces the test procedures for the drive circuit. The intermediate voltage may be prefer ably obtained by interpolation of the adjacent tWo of the

gray-scale voltages.

FIG. 6 illustrates the con?guration of a drive circuit according to the ?rst embodiment of the present invention. 45

The above and other objects, features and advantages of the present invention Will be more apparent from the folloW

selector block 102A, and an output stage circuit 105A. The 50

scale voltage generator 906 shoWn in FIG. 2. The gray-scale

a conventional drive circuit for displaying multi-level gray

voltage selector block 102A includes a group of 240 gray

scale digital video data;

scale voltage selectors each having a con?guration similar to 55

betWeen the gray-scale voltage and the optical transmittance of the LCD obtained thereby; FIG. 4 is a block diagram illustrating the con?guration of an example of a gray-scale voltage selector block shoWn in FIG. 1; FIG. 5 is a block diagram illustrating the con?guration of another example of a gray-scale voltage selector block shoWn in FIG. 1;

gray-scale voltage generator 101A has a circuit con?gura tion Which is similar to the circuit con?guration of the gray

FIG. 1 is a block diagram illustrating the con?guration of

FIG. 2 is a circuit diagram illustrating the con?guration of a gray-scale voltage generator shoWn in FIG. 1; FIG. 3 is a graph of a LCD unit shoWing the relationship

The drive circuit of the present embodiment includes an 80-bit shift register 901, a data register block 902, and a data latch block 903, Which are similar to those in the conven tional drive circuit of FIG. 1. The drive circuit also includes a

gray-scale voltage generator 101A, a gray-scale voltage

ing description, referring to the accompanying draWings. BRIEF DESCRIPTION OF THE DRAWINGS

of a circuit that can be employed in place of a coincidence circuit 301. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

or an intermediate voltage When the judgement signal indi

cates the linear region, the intermediate voltage residing betWeen tWo of adjacent gray-scale voltages.

FIG. 13 is a block diagram illustrating the con?guration of the output stage ampli?er block 104B shoWn in FIG. 11; FIG. 14 is a block diagram illustrating the con?guration of the least-signi?cant-bit controller 103B shoWn in FIG. 11; and

non-linear region or the linear region; and an output circuit for responding to the judgement signal to output the one of

the gray-scale level voltages selected by the gray-scale volt

circuit for displaying multi-level gray-scale digital video data according to the second embodiment of the present

60

that shoWn in FIG. 4. The output stage circuit 105A includes an ampli?er block 104A and a least-signi?cant-bit (LSB) controller 103A, as shoWn in FIG. 7. The least-signi?cant-bit controller 103A acts as a judgement section Which judges Whether the mag nitude of the video data resides Within a non-linear region or

a linear region. The output stage ampli?er block 104A is someWhat different from the ampli?er block 905 shoWn in FIG. 1. 65

The gray-scale voltage generator 101A divides input gray-scale reference voltages (VG0 to VGn). In general, to

FIG. 6 is a block diagram illustrating a drive circuit for

display 64 levels of gray scale data solely by means of the

driving a LCD unit to display thereon multi-level gray-scale

gray-scale voltage selector block 102A, the selector block

US RE40,773 E 5

6

102A is provided With 63 resistors to generate 64 distinct voltages. Similarly, to display 256 levels of gray scale data

connecting the gate of p-ch transistor to the VDD line by the

solely by means of the gray-scale voltage selector block 102A, the selector block 102A is generally provided With

nected to the output VINT of the gray-scale voltage selector

sWitch SW1. When the gate of p-ch transistor P2 is con

In the present embodiment, hoWever, the gray-scale volt

102A, the differential pair has some unbalance therebetWeen in the ON-current and alloWs the output voltage VOUT to exceed the VINT by a speci?ed minute voltage or the offset

age generator 101A is provided With 159 resistors to gener

voltage 0t. The magnitude of 0t is determined at a half of the

ate 160 gray-scale voltages for displaying 256 gray-scale

difference betWeen adjacent tWo of the gray-scale voltages. If the differential pair are implemented by n-ch transistors, the gate of the parallel transistor is maintained at

255 resistors to generate 256 distinct voltages.

levels on the LCD panel. That is, the gray-scale voltage gen erator 101A generates 64 gray-scale voltages V0, V1, With an 8-bit accuracy in the nonlinear region of characteris

the ground potential or the output VINT of the gray-sale volt age selector 102A by the sWitch SW1.

tic of liquid crystal transmittance With respect to applied voltage. On the other hand, in the linear region of character istic of liquid crystal transmittance With respect to applied voltage, the gray-scale voltage generator 101A generates 96

103A includes a coincidence circuit 301 and an AND gate 302. As can be seen clearly from FIG. 10, When all of the three signi?cant bits B5iB7 of video data assume “0” or “1”,

gray-scale voltages, V32, V34, . . . V220, and V222 With a

the coincidence circuit 301 outputs a high level and the least

V2, . . .V30, V31,V224,V225,V226, . . .V254, and V255

Referring to FIG. 10, the least-signi?cant-bit controller

7-bit accuracy. Therefore, the gray-scale voltage generator

signi?cant bit B0 is disabled, thereby alloWing the AND gate

101A generates 160 different gray-scale voltages in total to output the voltages to the gray-scale voltage selector block

302 to output a loW level control signal 151A. On the other hand, When any one of the three signi?cant bits B5iB7 of the

20

102A.

video data assumes a value different from those of other tWo

The gray-scale voltage selector block 102A is con?gured similarly to the gray-scale voltage selector block in the con ventional drive circuit of FIG. 1. As shoWn in FIG. 8, in accordance With the values of all of the bits B0iB7 of the

signi?cant bits, the coincidence circuit 301 outputs a loW level signal, and thus the AND gate 302 outputs a loW level or a high level control signal 151A depending on the least

digital video data, the gray-scale voltage selector block

signi?cant bit B0. The sWitch SW1 couples the gate of p-ch transistor to the output VINT of the gray-scale voltage selec

102A also selects, as a voltage VIN], one voltage from the

tor 102A When the control signal 151A assumes a loW level,

160 gray-scale voltages that are input from the gray-scale voltage generator 101A. For the magnitudes of digital video data residing Within the range of 0 to 31, voltages V0, V1,

Whereas coupled to the VDD line When the control signal

25

151A assumes a high level. 30

Therefore, as shoWn in FIG. 8, the value of the output

V2, . . . and V31 are selected as voltage VINT. For the magni

voltage VOUT that is provided by the output stage ampli?er

tudes of digital video data residing Within the range of 32 to

block 104A varies depending on the magnitude of the video data. More speci?cally, for the magnitude of digital video data residing Within the range of 0 to 31, the output voltage

223, voltages V32, V34, V36, . . . and V222 are selected as

voltage VINT. For the magnitudes of digital video data resid ing Within the range of 224 to 255, voltages V224, V225,

35 VOUT assumes V0, V1, V2, . . . and V31. For the magnitude

of digital video data residing Within the range of 32 to 223, the output voltage VOUT assumes V32, V32+0t, V34, V34+

V226, . . . and V255 are selected as output voltages VINT.

In accordance With the value of a control signal 151A

input from the least-signi?cant-bit controller 103A, the out

0t, . . . V222, V222+0t. For the magnitude of digital video

data residing Within the range of 224 to 255, the output

put stage ampli?er block 104A selects and outputs, as an

output voltage VOUZ, the voltage VINT input from the gray

40 voltage VOUT assumes V224, V225, V226, . . . and V255. It

scale voltage selector block 102A or the voltage VINT added

is to be noted that the value of the offset voltage 0t is deter mined about one half the difference betWeen the voltages of

by an offset voltage 0t, as detailed beloW.

An output ampli?er in the output stage ampli?er block 104A is con?gured as shoWn in FIG. 9. The output ampli?er has the con?guration of a voltage folloWer modi?ed for con

45

trolling the output voltage VOUT depending on the output signal 151A from the least-signi?cant-bit controller 103A. More speci?cally, the output ampli?er includes a pair of

the p-ch transistor P3 paired thereWith. As a concrete example, the offset voltage 0t is set Within the rage from 5 mV to 10 mV.

Of the voltages to be output by the gray-scale voltage

current sources for generating constant currents l1 and 12, a

pair of p-ch transistors P1 and P2 acting as a differential pair at a speci?ed situation, a pair of n-ch transistors N1 and N2 forming a current mirror, a p-ch transistor connected in par allel With the p-ch transistor P3, and an n-ch transistor hav ing a gate connected to the drain of the p-ch transistors P2

50

and P3, a source connected to the gate of the p-ch transistor P1 and a drain connected to the ground. The gate of p-ch transistor P3 is connected to the output VINT of the gray scale voltage selector 102A. The gate of p-ch transistor P2 is connected to either the VDD line or the output VINT of the

55

gray-scale voltage selector 102A through the sWitch SW1

60

depending on the output 151A of the least-signi?cant-bit controller 103A. The p-ch transistor P2 has a signi?cantly smaller dimension compared to the p-ch transistor P3. With p-ch transistor P2 and the sWitch SW1 being neglected, the output ampli?er acts as a voltage folloWer, Which alloWs the output voltage VOUT to folloW the input

voltage VINT of the output ampli?er. This state is achieved by

V126 and V128, for example, of a typical LCD panel by adjusting the siZe of the p-ch transistor P2, the gate of Which is coupled to the VINT or VDD through the sWitch SW1, and

generator 101A, the voltages to be output in the nonlinear region may be changed from V32, V34, . . . andV222 to V33, V35, . . . and V223. In this case, the least-signi?cant-bit

controller 103A should be con?gured differently to supply a different voltage through the sWitch SW1. This may alloW the output stage ampli?er block 104A to be adapted such

that the voltage VINT input from the gray-scale voltage selec tor block 102A remains unchanged as the output voltage VOUT for the magnitude of digital video data of 33, 35, . . .

and 223. In addition, the output stage ampli?er block 104A may be adapted such that the voltage VIN], input from the gray-scale voltage selector block 102A, subtracted by the offset voltage is output as the output voltage VOUT for the magnitude of digital video data of 32, 34, . . . and 222.

[Second Embodiment] 65

Referring to FIG. 11, there is shoWn the con?guration of the main portion of a drive circuit according to a second

embodiment of the present invention. The overall con?gura

US RE40,773 E 7

8

tion is similar to that shown in FIG. 6. A gray-scale voltage

voltage at any one of the tap points of the resistors or the

generator 101B is similar to the gray-scale voltage generator

voltage VD, and a buffer ampli?er A1 for reducing the output

906. A group of 240 gray-scale voltage selectors 102B con

impedance of the sWitches SW2 to SW5. The sWitches SW2 to SW5 are controlled by the control signal 151B that is

stitutes the gray-scale voltage selector block. A least signi?cant-bit controller 103B is included in the second

output from the least-signi?cant-bit controller 103B. When the control signal 151 B selects the sWitch SW2, the

embodiment. A group of 240 output stage ampli?ers con

voltage VOUT becomes equal to the voltage VD. When the control signal 151B selects the sWitch SW3, the voltage VOUT becomes equal to (3A)VD+(1A)VU. When the control signal 151B selects the sWitch SW4, the voltage VOUT becomes equal to (2A)VD+(%)VU. When the control signal

stituents the output stage ampli?er block 104B. The output stage ampli?er block 104B has a con?guration similar to that the output ampli?er block 905 shoWn in FIG. 1 added by resistors and sWitches.

The gray-scale voltage generator 101B is con?gured simi larly to that shoWn in FIG. 2 and divides input gray-scale reference voltages (VGO to VGn). In general, to display 64 levels of gray scale data solely by means of the gray-scale voltage selector 102B, the selector block 102B is provided With 63 resistors to generate 64 distinct voltages. Similarly, to display 256 levels of gray scale data solely by means of the gray-scale voltage selector 102B, the selector block 102B is provided With 255 resistors to generator 256 distinct

voltages.

151B selects the sWitch SW4, the voltage VOUT becomes

equal to (1/4)VD+(3/4)VU. As shoWn in FIG. 14, the least-signi?cant-bit controller 103B includes a coincidence circuit 301, a 2-to-4 line

20

In the present embodiment, hoWever, the gray-scale volt age generator 101 B is provided With 111 resistors to gener

ate 112 voltages. More speci?cally, the gray-scale voltage generator 101B generates 64 gray-scale voltages V0, V1, V2, . . .V30, V31,V224,V225,V226, . . .V254, and V255 25

With an 8-bit accuracy in the nonlinear region of characteris

tic of liquid crystal transmittance With respect to applied voltage. On the other hand, in the linear region of character istic of liquid crystal transmittance With respect to applied voltage, the gray-scale voltage generator 101B generates 48

signal, thereby causing the OR gate 304 to output a high 30

6-bit accuracy. Therefore, the gray-scale voltage generator 101B generates 112 different gray-scale voltages in total to output the voltages to the gray-scale voltage selector block

signal. Therefore, at this time, of the sWitches SW2 to SW5, only the sWitch SW2 is turned on. On the other hand, When any one of the three signi?cant bits B5iB7 of the video data assumes a value different from the values of other tWo sig ni?cant bits, the coincidence circuit 301 outputs a loW level

signal. Then, the OR gate 304 and the AND gates 305*307 35

The gray-scale voltage selector block 102B is con?gured

output a loW level or a high level control signal 151B depending on the value of the less signi?cant tWo bits B0 and

B1. Therefore, at this time, in accordance With the value of the less signi?cant tWo bits B0 and B1 of the video data, one of the sWitches SW2 to SW5 is turned on and other sWitches

similarly to a combination of tWo of the conventional gray

sale voltage selector block shoWn in FIGS. 4 and 5. As shoWn in FIG. 12, in accordance With the values of all of the

bits B0iB7 of the digital video data, the gray-scale voltage

connected to a control terminal C4 of the sWitch SW4. The output terminal of the AND gate 307 is connected to a con trol terminal C5 of the sWitch SW5. As can be seen clearly from FIG. 14, When all the values of the three signi?cant bits B5iB7 of video data assume “0” or “1”, the coincidence circuit 301 outputs a high level

level signal and the AND gates 305*307 to output a loW level

gray-scale voltages V32, V36, . . . V216, and V220 With a

102B.

decoder 303, an OR gate 304, and AND gates 305 to 307. The output terminal of the OR gate 304 is connected to a control terminal C2 of the sWitch SW2. The output terminal of the AND gate 305 is connected to a control terminal C3 of the sWitch SW3. The output terminal of the AND gate 306 is

40

are turned off.

selector block 102B also selects, as voltages VU, VD, tWo adjacent voltages from the 112 gray-scale voltages that are

voltage VOUT that is provided from the output stage ampli

input from the gray-scale voltage generator 101B. More speci?cally, for the magnitude of digital video data residing

That is, for the magnitude of digital video data residing

Therefore, as shoWn in FIG. 12, the value of the output ?er block 104B varies depending on the value of video data.

Within the range ofO to 31, voltages V0, V1, V2, . . . and V31 45 Within the range of 0 to 31, the output voltage VOUT assumes are selected as voltage VD. For the magnitude of digital V0, V1, V2, . . . and V31. For the magnitudes of digital video

video data residing Within the range of 32 to 223, voltages

data residing Within the range of 32 to 223, the output volt

V32, V36, V40, . . . and V220 are selected as voltage VD. For

age VOUT assumes V32, (%)V32+(%)V36, (2/4)V32+(%)

the magnitude of digital video data residing Within the range

V36, (1/4)V32+(3/4)V36, V36, . . . V220, (3/4)V220+(1/4)

of 224 to 255, voltages V224, V225, V226, . . . and V255 are 50

V224, (2/4)V220+(2/4)V224, and (1A1)V220+(3/4)V224. For

selected as voltage VD. Furthermore, for the magnitude of digital video data residing Within the range of 0 to 31, volt

the magnitude of digital video data residing Within the range of224 to 255, the output voltage VOUT assumes V224, V225,

ages V1, V2, V3, . . . and V32 are selected as voltage VU. For

V226, . . . and V255.

the magnitude of digital video data residing Within the range

Other examples of the output circuit that can be incorpo rated into the output stage ampli?er block include a D/A

of 32 to 223, voltages V36, V40, V44, . . . and V224 are 55

selected as voltage VU. For the magnitude of digital video data residing Within the range of 224 to 255, voltages V225,

converter that can generate, from a plurality of reference

voltages, a plurality of voltages greater in number than the reference voltages such as by a sWitched capacitor method employing capacitors or a R-2R method employing resis

V226, V227, . . . and V255 are selected as voltage VD.

In accordance With the value of a control signal 151B

input from the least-signi?cant-bit controller 103B, the out put stage ampli?er block 104B outputs, as output voltage VOUZ, the voltage generated in accordance With the voltages VU, VD are input from the gray-scale voltage selector block

60 tors.

102B.

As shoWn in FIG. 13, the output stage ampli?er block 104B includes four resistors for dividing the voltage betWeen VU and VD, sWitches SW2 to SW5 for selecting a

65

It is to be noted that, in the ?rst and second embodiments, the least-signi?cant-bit controller 103A or 103B determines Whether or not a gray-scale voltage to be displayed is Within a linear region, using the coincidence circuit 301 to deter mine Whether or not all the three signi?cant bits of video

data coincide With each other. The present invention, hoWever, is not limed thereto. For example, as shoWn in FIG.

US RE40,773 E 9

10

15, instead of the coincidence circuit 301, it is possible to employ a circuit including tWo comparators 321 and 322 and an OR gate 323 for receiving the outputs of these compara

What is claimed is:

1. A drive circuit for driving a display unit comprising: a gray-scale level voltage generator for generating a plu

tors in order to set given threshold values TH1 and TH2

rality of gray-scale level voltages, said gray-scale volt ages corresponding to magnitudes of possible video

indicative of the boundary betWeen the linear and nonlinear

regions.

data in one-to-one correspondence in a non-linear

It is also possible to combine the folloWing components in order to further reduce the scale of the gray-scale voltage selector block. That is,

region of characteristic of liquid crystal transmittance and corresponding to magnitudes of possible video data in one-to-n correspondence in a linear region of charac teristic of liquid crystal transmittance Where n is an

(l) The gray-scale voltage selector block 102A, (2) A decoder that replaces the 2-to-4 line decoder 303 to provide one to four high level outputs in accordance With the value of the bits B0 and B1, and the OR gate 304 or the least-signi?cant-bit controller 103B With the

integer larger than one; a gray-scale voltage selector block for responding to input video data to select one of said gray-scale level volt ages; a judgement section for judging Whether a magnitude of

output thereof eliminated, and (3) The sWitch SW1, and the output stage ampli?er block 104A having three pairs of transistors, the gates of Which are connected to the sWitch SW1.

As described above, according to the preferred embodi ments of the present invention, in the linear region of charac

teristic of liquid crystal transmittance With respect to applied

20

voltage, the gray-scale voltage selector block selects one or tWo voltages in accordance With the value of the signi?cant

selected by said gray-scale voltage selector block When said judgment signal indicates the non-linear region

bits of video data. By using the selected voltages, further divided voltages are generated in accordance With the value of the remaining less signi?cant bits of all the bits of the video data. This makes it possible to signi?cantly reduce the scale of the gray-scale voltage selector block. On the other hand, in the nonlinear region of characteristic of liquid crys tal transmittance With respect to applied voltage, a difference

betWeen gray-sale voltages (a difference in voltage to obtain

and output one of said gray-scale voltages or an inter 25

2. The drive circuit as de?ned in claim 1, Wherein given n 30

mediate voltage, said modi?ed voltage folloWer being con 35

crystal display panel, an image With properly expressed lev

Whether or not a plurality of signi?cant bits of the video 40

45

50

8. The drive circuit as de?ned in claim 5, Wherein said judgement circuit includes a coincidence circuit for judging Whether or not a plurality of signi?cant bits of the video signal coincide With one another. 9. A driver for driving a display in response to a plurality

55

ofinput data, each ofsaid input data comprising a plurality ofbits, said driving circuit comprising: a gray shade voltage generation circuit generating a plu

rality ofgray shade voltages, the number ofsaid gray shade voltages being determined by the number ofsaid bits ofsaid input data, said gray shade voltages being

by the gray-scale voltage selector blocks, the number of gray 60

embodiments and various modi?cations or alternations can 65

be easily made therefrom by those skilled in the art Without departing from the scope of the present invention.

said gray-scale voltages. 7. The drive circuit as de?ned in claim 6, Wherein said

ond embodiment requires that the gray-scale voltage selector

scale levels to be tested is also reduced. This makes it pos sible to carry out the test of the chip in a shorter time and thereby reduce the cost of the chip. It is not necessary to test the output circuit on all levels of gray scale, and instead, it is suf?cient to test all the combinations of the control signals. Since the above embodiments are described only for examples, the present invention is not limited to the above

output circuit includes an interpolation circuit for generating a plurality of intermediate voltages betWeen adjacent tWo of interpolation circuit includes a resistor string.

requires that the gray-scale voltage selector blocks be pro

blocks be provided per one output only With tWo sets of a decoder complaint With 112 levels of gray scale and 112 sWitches. With the reduced number of gray scale levels to be output

signal coincides. 5. The drive circuit as de?ned in claim 1, Wherein given n is four. 6. The drive circuit as de?ned in claim 5, Wherein said

output With a decoder complaint With 256 levels of gray scale and 256 sWitches. In contrast, the ?rst embodiment vided per one output only With a decoder compliant With 160 levels of gray scale and 160 sWitches. Furthermore, the sec

differentiate the input and the output thereof by a speci?ed

voltage. 4. The drive circuit as de?ned in claim 1, Wherein said judgement circuit includes a coincidence circuit for judging

the gray-scale voltage selector block can be reduced. Even With an increase in scale of the output circuit, it is possible to reduce the entire scale of the drive circuit.

The conventional 8-bit resistor string method requires that the gray-scale voltage selector blocks be provided per one

3. The drive circuit as de?ned in claim 1, Wherein said output circuit includes a modi?ed voltage folloWer for gen erating one of said gray-scale voltages or an adjacent inter

trolled to equaliZe the input and output thereof or to

els of gray scale. It is also possible to implement, for example, a full-color display of 16,770,000 colors by using a

liquid crystal panel of three primary colors and three drive circuit systems When employed accordingly. Furthermore, according to the embodiments, the scale of

mediate voltage When said judgement signal indicates the linear region, the intermediate voltage residing betWeen tWo of adjacent gray-scale voltages. is tWo.

the same difference in gray scale) is greater than in the linear

region and not even. However, the nonlinear region is deter mined in accordance With part of the signi?cant bits to gen erate and then select gray-scale voltages With an 8-bit accu racy. Thus, this makes it possible to display, on a liquid

an input video data resides Within the non-linear region or the linear region to output a judgement signal indi cating the non-liner region or the linear region; and an output circuit for responding to said judgement signal to output said one of said gray-scale level voltages

divided into first and second groups of gray shade

voltages, said first group of gray shade voltages being generated by a resistance string circuit and said second group ofgray shade voltages being generated based on at least two diferent ones offirst group of gray shade

voltages; a plurality of output terminals coupled to said display device; and

US RE40,773 E 11

12 group of gray shade voltages, said resistor string hav ing a third portion between said first and second por tions producing a third group ofgray shade voltages;

a plurality of selector circuits, each of said selector cir cuits selecting one of said gray shade voltages in response to information of an associated one of said

input data, said one ofsaid gray shade voltages being

a selector selecting an associated one of said first and

supplied to an associated one of said output terminals. 10. The driver as claimed in claim 9, further comprising

third groups of gray shade voltages when said display device is driven with a first input data corresponding to

at least two resistors for voltage dividing by using selected two voltages from first group of gray shade voltages to pro duce said second group ofgray shade voltages.

said non-linear region of characteristic of liquid transmittance, selecting an associated one ofsaid third

1]. The driver as claimed in claim 10, wherein said selec tor selecting an associated one ofsaid?rst group ofgray

group ofgray shade voltages when said display device

shade voltages when said display device is driven with a first input data corresponding to a non-linear region ofcharac teristic of liquid transmittance, selecting an associated one

linear region of characteristic of liquid transmittance,

is driven with a second input data corresponding to a

selecting a gray shade voltage produced from associ ated two ones ofsaid third group ofgray shade voltages when said display device is driven with a third input

ofsaid?rst group ofgray shade voltages when said display device is driven with a second input data corresponding to a

linear region of characteristic of liquid transmittance, selecting an associated one of said second group ofgray shade voltages when said display device is driven with a

third input data corresponding to said linear region ofchar acteristic of liquid transmittance. 12. A driverfor driving a display device, comprising:

20

13. The driver as claimed in claim 12, said selector

including at least two resistors to perform a voltage dividing

by using adjacent two gray shade voltages to generate said gray shade voltage producedfrom associated two ones.

a gray shade voltage generating circuit having a resistor

string, said resistor string having a first portion pro ducing a first group of gray shade voltages, said resis tor string having a secondportion producing a second

data corresponding to said linear region of character istic of liquid transmittance; and an amplifier amplijying a gray shade voltage outputted from said selector to apply the amplified gray shade voltage to said display device.

25

j B0~B7

_ Related U's' Patent Documents. Saito and Kitamura, “17.3: A 64bit Digital Data Driver for. Relssue of'. _. Color TFTiLCDs”, Society for Information Display (SID).

1MB Sizes 1 Downloads 511 Views

Recommend Documents

J A W A J A
That year the National Institute of Design, NID, Ahmedabad was invited to be involved with The Rural University .... and more predictable tanning for instance, followed in consultation with organizations like the Central Leather Research Institute. .

J&J Universal Placement ID
Business Impact. It is important to note J&J are not a retailer, and as such their websites offered no e-commerce purpose or functionality. As such, their brand experience is paramount to them. Their advertising, POS material,. DM, flyers, websites -

I; Jaw' J j 4 Z
Be it known that we, LOUIS ScHnLMAN and JOSEPH SCHULMAN, citizens of the. United States, residing in the borough of. Brooklyn, city of New York, county of.

J
A cardiac rhythm management device that utilizes blanking .... accounting for the complex polarization voltages and after ..... software in a known manner.

._ I” j
Dec 4, 2000 - (10) Patent Number: US RE41,169 E. Arthun. (45) Date of Reissued Patent: Mar. 30, 2010. (54) SEALING APPLIANCE. (56). References Cited.

J - GitHub
DNS. - n~OTHOCTb aamiCI1 Ha IAJI i. FILE - CllHCOK HOUepOB OCipaCiaTbiBaeu~ tlJai'i~OB i. RCBD - KO~HqecTBO OCipaCiaTbiB86Y~ ~E3;. PRT.

$ YLO£J
8. Jesse Robredo. 9. Myrtle. 10. Jamich. )HONDSRWW. 3ROLWLNXVRN. 1. Jesse Robredo. 2. Corona. 3. Barack Obama. 4. Iggy Arroyo. 5. Romney. 6. Shalani Soledad. 7. Miriam Defensor Santiago. 8. Juan Ponce Enrile. 9. Tito Sotto. 10. Serafin Cuevas. /HJNHU

$ YLO£J
Was ist Wirtschaft. 6. Was ist KONY. 7. Was ist LTE. 8. Was sind Kapern. 9. Was ist Zumba. 10. Was ist MS. )HONDSRWW. ‹WHOHN «V LWDORN. 1. Red Bull. 2. ...... Boris Johnson. 3. Justine Greening. 4. Alex Salmond. 5. Michael Gove. 6. George Osborne.

044., j
Aug 17, 2015 - MANUELA S. TOLENTINO, Ed.D. 01C, Schools Division Superintendent. Subject. : Crafting of first Division GAD Magazine-type newsletter and.

ESApetition2009final Glowa, J., W.L. Pepperman, C.L. Schadler, J ...
The eighty miles between Gananoque and Cornwall, Ontario contain one or more ... 2009.pdf. ESApetition2009final Glowa, J., W.L. Pepperman, C.L. Sc ... ves ...

pdf-54\tracers-by-j-j-howard.pdf
DOWNLOAD EBOOK : TRACERS BY J. J. HOWARD PDF. Page 1 of 40 ... TRACERS BY J. J. HOWARD PDF ... and Tiffin University with an MH in Humanities.

Employment, Hours and Optimal Monetary Policy j Online appendix j
j Online appendix j .... degree of increasing marginal disutility of hours. ... variety i, final good firms choose optimally the inputs Y

\J-“M
Oct 29, 2009 - Sun: “Intra-Prediction Mode Ordering and Coding”, ITU Study ... 1 of 1 -7 of7, [online], 07.10.02, H.264/MPEG-4 Part 10 White Paper,. [retrieved on Sep. ..... across computer networks because of bandwidth limitations. In addition .

\J-“M
Oct 29, 2009 - 1 of 6-6 of 6, [online], Apr. 30,. 2008. ... SC29/WG11 and ITU-T SG-16 Q.6), Document JVT-G013, 'Online! Mar. .... amount of storage space.

@» [28 j
Jul 24, 2012 - the vehicle consumer or after-market technician rather than relying on the ... 2 is an illustration of an automotive dash assembly illustrating an ...

J'\ “5
Aug 5, 2010 - See application ?le for complete search history. (56) ..... of Experiments Techniques in Optimisation of Supported Reagent. Chemistry”.

J
A second analy- sis was perfonned to estimate the effect of data missing ..... Data on the primary end point of the B-blocker ..... ical Center; New York, N.Y. Principal Investigator: ..... De Geest H: Reduction in infarct size and enhanced recovery.

cameron j. bytheway - GitHub
Incorporated video streaming/recording in BYU's Digital Dialog, a web discussion application. iOS Developer. August 2010-Present. Bytheway Apps, Provo, UT.

J Boulton - Broadlands Academy
Jul 14, 2017 - small amount of change for these would be good. The school day will finish ... Tel: 0117 986 4791. Email: [email protected].

J
Many software development methodologies including the water-fall .... It allows us to define continuous mapping among spaces. ... between companies A and B.

I J. .1
R. O'Hara and A. Petrick, The IEEE 802.11 HandbookiA Design er's Companion ... Protocol”, Technical Study Report of The Institute of Electronic,. Information and ...... While the Web broWsing CCls could be sent every 200 milli second, or ...

J
Section, Baylor College of Medicine, The Methodist Hospital,. 6535 Fannin—MS ..... Roberts et al immediate Versus Delayed fl-Blockade 427. TABLE 2. Cllnleal ...... Wackcrs FIT, Terrin ML, Kayden DS, Knattcrud G, Forman. S, Braunwald E ...

.tt-t- J 0
Dec 27, 2017 - -ft-:S( £3 Jl"ij : tP ~ t\ 1m 106lf=-12 Jl 25 £3. -ft-:S(~!t: *t/;-ft-ff5~~1060523077!t. 11ft 1t- : -ko:£. ~. £ l§ : ~% r [email protected]!n5Mt.~~45 .tt-t- J 0. *.:.j!~

YLO£J
9. Nokia Lumia. 10. Nokia Lumia 800. /HJNHUHVHWWHEE. 0£UN£N. 1. Apple. 2. Toyota. 3. Blackberry. 4. Nokia ...... Software Developer. 10. Financial Analyst.