Junction Field Effect Transistor for Nanoelectronics

Mini Project Report

Supervisor: Dr. M. Jagadesh Kumar

Rupesh Gupta 2006EE50413

INDEX

Topic

Page No.

1. Introduction

3

2. Objective

3

3. Literature Review

3

4. Reproducing the Results

4

5. Scope for Improvement

6

6. A Device with P+ Drain

6

7. Device with P+ Source

9

8. Device with a Thin P+ Strip

11

9. Conclusion

16

10. Result

16

11. Appendix

17

1. INTRODUCTION This project aims at the analysis of the JFET characteristics at extremely scaled down dimensions and performance enhancement through design modifications. It is an extension to the paper titled ‘Junction Field Effect Transistors for Nanoelectronics’ authored by Justin B. Jackson, Divesh Kapoor and Mark S. Miller. Here we investigate several modified structures and draw important conclusions. 2. OBJECTIVE The project has been divided broadly into two main objectives 1. Developing an understanding of the JFET at extremely scaled down dimensions and reproduction of the results published by Jackson et al. 2. Design modifications in an attempt to improve the characteristics.

3.

LITERATURE REVIEW

The literature presents the scaling analysis of JFET vis-à-vis MOSFET.

Fig. 1. Scaling model for JFET The gate leakage currents for MOSFTEs have exponentially increased with scaling due to increasing electric fields in the oxide layer. However for JFET, the gate current has followed a reverse trend.

Fig. 2. Gate current density scaling of MOSFETs and JFETs versus gate length

As can be seen from the above fig. (Fig. 2.) the gate current density for JFET has always been orders of magnitude greater than MOSFET gate current at dimensions greater than or equal to the current 45 nm technology node. But a crossover point is likely to occur at gate lengths of approximately 25nm and thus JFET may prove to be a potential replacement for MOSFET for future technology nodes. The literature also presents the simulation results for a 25nm JFET which turn out to be competitive with the MOSFET of similar dimension. 4. REPRODUCING THE RESULTS The 25nm JFET simulation results have been reproduced on Silvaco Atlas to serve as reference for future comparisons. 10nm

10nm

22.5nm

Fig. 3. The 25nm JFET structure Refer to Code 1 in Appendix. Key features of the structure include a threshold voltage of 150 mV which must be held constant for a constant voltage scaling regime. Hence, the channel doping of 5* 1018 /cm3 must not been changed in any of the structure modifications. SIMULATION RESULTS FOR 25nm JFET (a) Gate current vs. Gate voltage Some important conclusions can be drawn from the current voltage plots obtained.

A/µm

Fig.4. Gate current vs. gate voltage plot

From the above graph we observe that at VG=0 and VD=0.7V, IG is due to the reverse biased gatedrain band to band tunneling current. This gate current is of the order of 10-3 µA/µm. At VG=0.7V and VD=0.8V, IG is due to forward biased gate- source junction and of the order of 10-1 µA/µm. (b) Channel current vs. Gate voltage Log scale A/µm

A/µm

VD=0.7V

VD=50mV

Fig.5. Drain current vs. Gate voltage plot

At VD=0.7V and VG=0V the IDS value is very high due to subthreshold diffusion and is of the order of 10-1 µA/µm (c) Channel current vs. Drain voltage

A/µm

VG=0.8V

VG=0.6V

VG=0.4V

VG=0.2V

Fig.6. Channel current vs. Drain voltage plot From the above graph we observe that the channel current is quite high in the ON state (VG=0.8V) and of the order of 102 µA/µm.

5. SCOPE FOR IMPROVEMENT Certain areas of the basic JFET structure can be improved upon for better performance. Some of the areas can be identified as reducing subthreshold diffusion current (10-1 µA/µm), gate- drain band to band tunneling (10-3 µA/µm) and forward bias gate- source current (10-1 µA/µm) with numbers in parentheses indicating their orders. However we must ensure that channel current is maintained at its high level in the ON state (102 µA/µm). We have analysed several different structures in an attempt to improve the device performance and reduce the unwanted leakage currents. 6. A DEVICE WITH P+ DRAIN The main motivation behind this structure was to reduce Gate-Drain band to band tunneling current and also achieve a high Source-Drain channel current using a forward biased diode at the drain end in the ON state.

Fig.7. JFET with P+ drain

Refer to code 2 in Appendix. The above structure was simulated in Silvaco Atlas and the important results are presented here for discussion.

P+ drain

Fully depleted n channel

N+source

Fig.8. Band diagram at VG=VD=0V

At VG=VD=0V, the n channel region is fully depleted and hence the channel is closed, device is OFF.

P+ drain

N channel N+source

Fig.8. Band diagram at VG=0.8V, VD=0V On applying 0.8V to gate, the channel opens and can conduct.

P+ drain

P+ drain

P+ gate N channel

N+source

Fig.9. Band diagrams at VG=0.8V, VD=0.8V

N channel

The problem arises on application of 0.8V to drain when the channel is open. It was found that no current flows in the channel towards the source and a large current flow from gate to drain. This can be very easily explained by taking a horizontal cutline from gate to drain. Comparing the two band diagrams in Fig.9, it can be easily noticed that the barrier for flow of electrons is lesser from gate to drain as compared to that between source and drain. It becomes very difficult to prevent drain current from flowing into the gate. Hence, this device fails to yield the desired results in the ON state and we move on to investigate another structure. 7. DEVICE WITH P+ SOURCE This structure was analyzed with an expectation of reduced forward biased Gate-Source junction currents in the ON state.

Fig.10. JFET with P+ source The idea here is to use Zener tunnelling channel current of the reverse biased source- channel diode in ON state. This requires optimization of the tunnelling current. The source- channel diode has been analysed first in seclusion. Refer to code 3 in Appendix. The required channel current is of the order of 100 µA/µm in ON state for competitive performance compared to the original structure. It is very difficult to achieve such high levels of tunneling currents. Ours simulations have shown that tunneling current is insignificant for tunneling widths > 5nm and applied reverse bias < 1V. The current has been increased to significant levels (~ 10 µA/µm) using narrow band gap material SiGe. The complete structure is then analysed using SiGe material and the results are presented here. Refer to code 4 in Appendix.

P+ source

Fully depleted n channel

N+ drain

Fig.10. Band diagram at VG=VD=0V At VG=VD=0V, the channel is fully depleted and closed.

P+ source

N channel N+ drain

Fig.11. Band diagram at VG=0.8V, VD=0V On applying VG=0.8V, the channel opens up and as can be seen from Fig.11, the band alignment is almost about to occur.

P+ source

Fully depleted N channel

N+ drain

Fig.12. Band diagram at VG=0.8V, VD=0.8V On applying 0.8V to the drain, the whole of n channel gets depleted, as effectively the reverse bias across the source- channel diode has increased. This results in extremely low values of source- drain current as thin depletion regions favour tunnelling. Even if we somehow manage to control this, the Gate-Drain BTBT current would be high owing to the use of narrow band gap material. Thus, the structure fails in the ON state. 8. DEVICE WITH A THIN P+ STRIP We reckon the need for such kind of a change in the structure, which would not affect the channel much and at the same time shape the band diagram in a positive way. This led to another structure described now.

Fig.13. JFET with thin P+ strip

The idea here is to keep the P+ strip very thin so that it is fully depleted even with zero bias at drain. A strip of 3nm thickness has been used here and the width of n+ drain has been reduced by 3nm to 22nm. We have used SiGe for the P+ strip and wide band gap material for the N+ drain for optimum performance. Refer to Code 5 in Appendix. The results for this structure turn out to be promising and are discussed next in detail.

P+

Fully depleted N channel N+ drain N+ source

Fig.14. Band diagram at VG=VD=0V The band diagram at VG=VD=0V depicts that the channel is completely depleted. At the same time, we can observe a peak in the band diagram which is likely to serve as a potential barrier for electron movement from source to drain.

N+ source

N channel

P+

N+ drain

Fig.15. Band diagram at VG=0.8V, VD=0V On applying a positive voltage at the gate, the gate- channel depletion region shrinks leading to flattening of the band diagram and hence resistance to flow of electrons from source to drain.

N+ source

N channel P+

N+ drain

Fig.16. Band diagram at VG=0.8V, VD=0.8V

When 0.8V is applied to the drain end, the bands at the drain are pulled down and as a result the n channel bands also become down sloping just like in the case of resistor. Hence the electrons can easily roll down from source to drain giving a reasonable value of channel current in ON state. A significant improvement can be observed in the OFF state (VG=0V, VD=0.8V) subthreshold diffusion current which is shown in the next figure. Log scale A/µm

VD=0.7V

VD=50mV

Fig.17. Drain current vs. Gate voltage plot Comparing Fig.17. with the graph obtained for the original JFET structure Fig.5. we notice that the order of subthreshold diffusion current (at VG=0V and VD=0.8V) has been significantly reduced from 10-1 µA/µm to 10-3 µA/µm. This can be explained from Fig.14. and its discussions.

Log scale A/µm

VD=0.7V

VD=50mV

Fig.18. Gate current vs. Gate voltage plot The gate current vs. gate voltage plot shows an unexpected behaviour with peaks and troughs. This can be explained only by analysing the band diagrams at each step of gate voltage. But, the values of gate current are of the same order as that in the original device (Fig.4.) at the extreme ends i.e. gate voltages of 0 and 0.8V.

A/µm

VG=0.8V

Fig.19. Drain current vs. Drain voltage plot

Comparing the graph obtained above with the original orange curve in Fig.6., it can be seen that the channel current is an order of magnitude lesser in the new device compared to the original one at drain voltage of 0.8V. These magnitudes are of the order of 10-4 A/µm in the original device and 10-5 A/µm in the modified device. We see from Fig.19 that for a comparable channel current, the device must be operated at higher drain voltages of approximately 1.3V. This aspect has to be looked into in order to make the device competitive. Here we must point out that the current obtained is not a tunneling current and hence switching off the tunneling model leaves the characteristic unchanged. A closer look at the graph obtained in Fig.19. would also reveal that the graph is almost flat in the range of 0.1 to 0.8volts of drain voltage. This implies low value of output conductance and high value of output resistance which is desirable. 9. CONCLUSION The whole exercise of structure modification has brought forth several conclusions. Firstly, an attempt to improve one factor may cost degradation of another factor. Thus, optimization is a necessary aspect in design modifications. Secondly, tunnelling current can be raised up to an order of maximum 101µA/µm but can’t compete with resistor current with similar device dimensions. Thirdly, the new design must preserve the threshold voltage and hence the channel doping which largely hinders the use of tunneling phenomenon for channel current. Fourthly, the new design proposed needs to be investigated further for better understanding of it working principle and comprehend the peculiar shape of the Gate current vs. Gate voltage plot (Fig.18) 10. RESULT The JFET has been methodically studied and the reported results reproduced. Several design modifications have been tried of which only one turned out to be of interest. The new design has favourable drain current vs. gate voltage characteristics in terms of subthreshold diffusion current. The only shortcoming of this device is an unfavourable ON state channel current which needs to be looked into in further course of research.

APPENDIX

CODE 1 go atlas # # original structure # mesh # x.mesh loc=0.000 x.mesh loc=0.020 x.mesh loc=0.075 x.mesh loc=0.095

spac=0.002 spac=0.001 spac=0.001 spac=0.002

# y.mesh loc=0.000 y.mesh loc=0.008 y.mesh loc=0.026 y.mesh loc=0.100 y.mesh loc=0.300

spac=0.001 spac=0.0001 spac=0.001 spac=0.01 spac=0.05

# region region region region region #

num=1 x.min=0.0 x.max=0.025 y.min=0.00 y.max=0.0225 material=Silicon num=2 x.min=0.025 x.max=0.07 y.min=0 y.max=0.0225 material=silicon num=3 x.min=0.070 x.max=0.095 y.min=0.00 y.max=0.0225 material=Silicon num=4 x.min=0.0 x.max=0.095 y.min=0.0225 y.max=0.100 oxide num=5 x.min=0.0 x.max=0.095 y.min=0.1 y.max=0.3 silicon

#*electrodes * # 1-GATE #2-SOURCE #3-DRAIN #4-SUBSTRATE # electrode name=gate x.min=0.040 x.max=0.055 y.min=0.0 y.max=0.0 electrode name=source x.min=0.000 x.max=0.015 y.min=0.0 y.max=0.0 electrode name=drain x.min=0.080 x.max=0.095 y.min=0.0 y.max=0.0 electrode substrate # #*doping concentrations * # doping uniform conc=1e20 n.type x.min=0.000 x.max=0.025 y.min=0.00 y.max=0.0225 doping uniform conc=5e18 n.type x.min=0.025 x.max=0.070 y.min=0.00 y.max=0.0225 doping uniform conc=1e20 n.type x.min=0.070 x.max=0.095 y.min=0.00 y.max=0.0225 doping uniform conc=1e20 p.type x.min=0.035 x.max=0.060 y.min=0.00 y.max=0.010 doping uniform conc=1e17 p.type x.min=0.0 x.max=0.095 y.min=0.100 y.max=0.300 # # * models* models conmob srh bbt.std auger bgn fldmob fermi print # solve init output con.band val.band e.field

save

outf=nanojfetSilicon_ref.str

# # IdVg characteristic # method newton gummel trap solve solve solve

vgate=0 vsource=0 vdrain=0

solve vdrain=0.05 outf=solve_Silicondrain_0.05 solve vdrain=0.7 outf=solve_Silicondrain_0.7 load infile=solve_Silicondrain_0.05 log outf=nanojfetSilicon_drain_0.05.log solve name=gate vgate=0 vfinal=0.8 vstep=0.01 load infile=solve_Silicondrain_0.7 log outf=nanojfetSilicon_drain_0.7.log solve name=gate vgate=0 vfinal=0.8 vstep=0.01

# plot resultant IDVG threshold voltage curve tonyplot -overlay nanojfetSilicon_drain_0.05.log nanojfetSilicon_drain_0.7.log # # IdVd solve vgate=0.001 outf=solve_Silicongate_0.001 solve vgate=0.2 outf=solve_Silicongate_0.2 solve vgate=0.4 outf=solve_Silicongate_0.4 solve vgate=0.6 outf=solve_Silicongate_0.6 solve vgate=0.8 outf=solve_Silicongate_0.8 # load infile=solve_Silicongate_0.001 log outf=nanojfetSilicon_0.001.log solve name=drain vdrain=0 vfinal=0.8 vstep=0.01 load infile=solve_Silicongate_0.2 log outf=nanojfetSilicon_0.2.log solve name=drain vdrain=0 vfinal=0.8 vstep=0.01 load infile=solve_Silicongate_0.4 log outf=nanojfetSilicon_0.4.log solve name=drain vdrain=0 vfinal=0.8 vstep=0.01 load infile=solve_Silicongate_0.6 log outf=nanojfetSilicon_0.6.log solve name=drain vdrain=0 vfinal=0.8 vstep=0.01 load infile=solve_Silicongate_0.8 log outf=nanojfetSilicon_0.8.log solve name=drain vdrain=0 vfinal=0.8 vstep=0.01 #

tonyplot -overlay nanojfetSilicon_0.001.log nanojfetSilicon_0.2.log nanojfetSilicon_0.4.log nanojfetSilicon_0.6.log nanojfetSilicon_0.8.log # save outf=nanojfetSilicon_final.str # quit

CODE 2 go atlas

# p+ drain mesh # x.mesh loc=0.000 x.mesh loc=0.020 x.mesh loc=0.065 x.mesh loc=0.070 x.mesh loc=0.095

spac=0.002 spac=0.001 spac=0.001 spac=0.0005 spac=0.002

# y.mesh loc=0.000 y.mesh loc=0.008 y.mesh loc=0.030 y.mesh loc=0.100 y.mesh loc=0.300

spac=0.001 spac=0.0005 spac=0.0005 spac=0.05 spac=0.05

# region region region #

num=1 x.min=0.0 x.max=0.095 y.min=0.00 y.max=0.0225 material=silicon num=2 x.min=0.0 x.max=0.095 y.min=0.0225 y.max=0.100 material=oxide num=3 x.min=0.0 x.max=0.095 y.min=0.1 y.max=0.3 material=silicon

# electrodes # # #1-gate #2-source #3-drain #4-substrate electrode electrode electrode electrode

name=gate x.min=0.040 x.max=0.050 y.min=0.0 y.max=0.0 name=source x.min=0.000 x.max=0.010 y.min=0.0 y.max=0.0 name=drain x.min=0.085 x.max=0.095 y.min=0.0 y.max=0.0 substrate

# # doping concentrations # # doping doping doping doping

uniform conc=1e20 n.type uniform conc=5e18 n.type uniform conc=1e20 p.type uniform conc=1e20 p.type

x.min=0.000 x.max=0.025 y.min=0.00 y.max=0.0225 x.min=0.025 x.max=0.070 y.min=0.00 y.max=0.0225 x.min=0.070 x.max=0.095 y.min=0.00 y.max=0.0225 x.min=0.035 x.max=0.060 y.min=0.00 y.max=0.010

doping

uniform conc=1e17 p.type x.min=0.000 x.max=0.095 y.min=0.100 y.max=0.300

# # selecting models models conmob fldmob bgn srh bbt.std auger fermi print # method

newton gummel trap

solve init output con.band val.band e.field save

outf=mynanojfet.str

# # band diagrams # solve solve solve

vgate=0 vsource=0 vdrain=0

save outf=fet_drain0_gate0.str solve vgate=0.8 save outf=fet_drain0_gate0.8.str solve vgate=0.8 solve vdrain=0.8 save outf=fet_drain0.8_gate0.8.str # #Id Vd # solve vgate=0.8 outf=mysolve_gate_0.8 # load infile=mysolve_gate_0.8 log outf=myIdVd_gate_0.8.log solve name=drain vdrain=0 vstep=0.05 vfinal=0.8 save outf=myIdVd_gate_0.8.str

# quit

CODE 3 go atlas mesh # x.mesh loc=0.000 spac=0.002

x.mesh loc=0.017 spac=0.0001 x.mesh loc=0.033 spac=0.0001 x.mesh loc=0.070 spac=0.002 # y.mesh loc=0.000 spac=0.001 y.mesh loc=0.0225 spac=0.001 # region

num=1 x.min=0 x.max=0.070 y.min=0.00 y.max=0.0225 material=SiGe x.comp=0.3

# electrodes # # #1-p #2-n electrode name=source x.min=0.0 x.max=0.02 y.min=0.0 y.max=0.0 electrode name=drain x.min=0.03 x.max=0.07 y.min=0.0 y.max=0.0 # # doping concentrations # # doping uniform conc=1e20 p.type x.min=0.00 x.max=0.025 y.min=0.00 y.max=0.0225 doping uniform conc=5e18 n.type x.min=0.025 x.max=0.070 y.min=0.00 y.max=0.0225 # regrid log doping ratio=6 smooth.key=2 max.level=4 # selecting models models conmob fldmob bgn srh auger bbt.std fermidirac print # method

newton gummel trap

solve init output con.band val.band e.field save

outf=mydiode.str

# # IV characteristic solve solve

vdrain=0 vsource=0

log outf=myIV.log solve name=drain vdrain=0 vstep=0.05 vfinal=2 save outf=myIV.str quit

CODE 4

go atlas

# p+ source mesh # x.mesh loc=0.000 x.mesh loc=0.020 x.mesh loc=0.065 x.mesh loc=0.070 x.mesh loc=0.095

spac=0.002 spac=0.001 spac=0.001 spac=0.0005 spac=0.002

# y.mesh loc=0.000 y.mesh loc=0.008 y.mesh loc=0.030 y.mesh loc=0.100 y.mesh loc=0.300

spac=0.001 spac=0.0005 spac=0.0005 spac=0.05 spac=0.05

# region region region #

num=1 x.min=0.0 x.max=0.095 y.min=0.00 y.max=0.0225 material=SiGe x.comp=0.2 num=2 x.min=0.0 x.max=0.095 y.min=0.0225 y.max=0.100 material=oxide num=3 x.min=0.0 x.max=0.095 y.min=0.1 y.max=0.3 material=silicon

# electrodes # # #1-gate #2-source #3-drain #4-substrate electrode electrode electrode electrode

name=gate x.min=0.040 x.max=0.050 y.min=0.0 y.max=0.0 name=source x.min=0.000 x.max=0.010 y.min=0.0 y.max=0.0 name=drain x.min=0.085 x.max=0.095 y.min=0.0 y.max=0.0 substrate

# # doping concentrations # # doping doping doping doping doping

uniform conc=1e20 p.type uniform conc=5e18 n.type uniform conc=1e20 n.type uniform conc=1e20 p.type uniform conc=1e17 p.type

x.min=0.000 x.max=0.025 y.min=0.00 y.max=0.0225 x.min=0.025 x.max=0.070 y.min=0.00 y.max=0.0225 x.min=0.070 x.max=0.095 y.min=0.00 y.max=0.0225 x.min=0.035 x.max=0.060 y.min=0.00 y.max=0.010 x.min=0.000 x.max=0.095 y.min=0.100 y.max=0.300

# # selecting models models conmob fldmob bgn srh bbt.std auger fermi print # method

newton gummel trap

solve init output con.band val.band e.field

save

outf=mynanojfet.str

# # band diagrams # solve solve solve

vgate=0 vsource=0 vdrain=0

save outf=fet_drain0_gate0.str solve vgate=0.8 save outf=fet_drain0_gate0.8.str solve vgate=0.8 solve vdrain=0.8 save outf=fet_drain0.8_gate0.8.str # #Id Vd # solve vgate=0.8 outf=mysolve_gate_0.8 # load infile=mysolve_gate_0.8 log outf=myIdVd_gate_0.8.log solve name=drain vdrain=0 vstep=0.05 vfinal=0.8 save outf=myIdVd_gate_0.8.str

# quit

CODE 5

go atlas

# thin p+ strip mesh # x.mesh loc=0.000 spac=0.002 x.mesh loc=0.020 spac=0.001 x.mesh loc=0.065 spac=0.0005

x.mesh loc=0.080 spac=0.0005 x.mesh loc=0.095 spac=0.002 # y.mesh loc=0.000 spac=0.001 y.mesh loc=0.0225 spac=0.0005 y.mesh loc=0.100 spac=0.05 y.mesh loc=0.300 spac=0.05 #

region region region region region #

num=1 x.min=0.0 x.max=0.070 y.min=0.00 y.max=0.0225 material=silicon num=2 x.min=0.07 x.max=0.073 y.min=0.00 y.max=0.0225 material=SiGe x.comp=.2 num=3 x.min=0.073 x.max=0.095 y.min=0.00 y.max=0.0225 material=Silicon num=4 x.min=0.0 x.max=0.095 y.min=0.0225 y.max=0.100 material=oxide num=5 x.min=0.0 x.max=0.095 y.min=0.1 y.max=0.3 material=silicon

# electrodes # # #1-gate #2-source #3-drain #4-substrate elec elec elec elec

name=source x.min=0.000 x.max=0.015 y.min=0.0 y.max=0.0 name=drain x.min=0.080 x.max=0.095 y.min=0.0 y.max=0.0 name=gate x.min=0.040 x.max=0.055 y.min=0.0 y.max=0.0 substrate

# # doping concentrations # # doping uniform conc=1e20 n.type doping uniform conc=5e18 n.type doping uniform conc=1e20 p.type doping uniform conc=1e20 p.type doping uniform conc=1e20 n.type doping uniform conc=1e17 p.type

x.min=0.000 x.max=0.025 y.min=0.00 y.max=0.0225 x.min=0.025 x.max=0.070 y.min=0.00 y.max=0.0225 x.min=0.070 x.max=0.073 y.min=0.00 y.max=0.0225 x.min=0.035 x.max=0.060 y.min=0.00 y.max=0.010 x.min=0.073 x.max=0.095 y.min=0.00 y.max=0.0225 x.min=0.0 x.max=0.095 y.min=0.100 y.max=0.300

# material material=silicon region=3 eg300=1.2 # selecting models models conmob fldmob bbt.hurkx bgn srh auger print regrid log doping ratio=6 smooth.key=2 max.level=4 # method newton gummel trap output con.band val.band e.field solve init

save solve solve solve

outf=mynanojfet.str vgate=0 vsource=0 vdrain=0

save outf=fet_drain0_gate0.str solve vgate=0.8 save outf=fet_drain0_gate0.8.str solve vgate=0.8 solve vdrain=0.8 save outf=fet_drain1.5_gate0.8.str

# # IdVg characteristic # solve solve solve

vgate=0 vsource=0 vdrain=0

solve vdrain=0.05 outf=mysolve_drain_0.05 solve vdrain=0.7 outf=mysolve_drain_0.7 load infile=mysolve_drain_0.05 log outf=myIdVg_drain_0.05.log solve name=gate vgate=0 vfinal=0.8 vstep=0.02 save outf=myIdVg_drain_0.05.str load infile=mysolve_drain_0.7 log outf=myIdVg_drain_0.7.log solve name=gate vgate=0 vfinal=0.8 vstep=0.02 save outf=myIdVg_drain_0.7.str tonyplot -overlay myIdVg_drain_0.05.log myIdVg_drain_0.7.log # # plot resultant IdVd curve # solve vgate=0.001 outf=mysolve_gate_0.001 solve vgate=0.4 outf=mysolve_gate_0.4 solve vgate=0.8 outf=mysolve_gate_0.8 # load infile=mysolve_gate_0.001 log outf=myIdVd_0.001.log solve name=drain vdrain=0 vfinal=0.8 vstep=0.02 save outf=myIdVd_0.001.str load infile=mysolve_gate_0.4 log outf=myIdVd_0.4.log solve name=drain vdrain=0 vfinal=0.8 vstep=0.02

save outf=myIdVd_0.4.str

load infile=mysolve_gate_0.8 log outf=myIdVd_0.8.log solve name=drain vdrain=0 vfinal=0.8 vstep=0.02 save outf=myIdVd_0.8.str tonyplot -overlay myIdVd_0.001.log myIdVd_0.4.log myIdVd_0.8.log # quit