8
7
6
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
5
4
2
3
REV
1 ECN
DESCRIPTION OF REVISION
CK APPD DATE
SCHEM,FLYING_DUTCHMAN,MLB,K91F
2010-10-12
REV B RELEASE, 01/31/11 (.csa)
D
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
2 3 4 5 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 45 46 48 49 50
Date
Contents
Sync
Table of Contents System Block Diagram Power Block Diagram Revision History BOM Configuration Functional / ICT Test Power Aliases Signal Aliases CPU DMI/PEG/FDI/RSVD CPU CLOCK/MISC/JTAG CPU DDR3 INTERFACES CPU POWER CPU POWER AND GND CPU DECOUPLING-I CPU DECOUPLING-II PCH SATA/PCIE/CLK/LPC/SPI PCH DMI/FDI/GRAPHICS PCH PCI/FLASHCACHE/USB PCH MISC PCH POWER PCH GROUNDS PCH DECOUPLING CPU & PCH XDP USB HUBS Chipset Support DDR3 SO-DIMM Connector A DDR3 Byte/Bit Swaps DDR3 SO-DIMM Connector B CPU Memory S3 Support FSB/DDR3/FRAMEBUF Vref Margining X19/ALS/CAMERA CONNECTOR SD READER CONNECTOR T29 Host (1 of 2) T29 Host (2 of 2) T29 Power Support ETHERNET PHY (CAESAR IV) Ethernet Connector FireWire LLC/PHY (FW643) FireWire Port & PHY Power FireWire Connector SATA/IR/SIL Connectors External USB Connectors Front Flex Support SMC SMC Support
MASTER
(.csa)
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K17_REF 06/30/2009
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K17_REF MASTER
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MASTER 05/28/2009
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K17_REF 04/27/2010
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K18_MLB 04/27/2010
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K18_MLB 04/27/2010
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K18_MLB 06/21/2010
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K92_SUMA 08/03/2010
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K92_MLB 06/15/2010
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K92_SUMA 08/03/2010
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K92_MLB 06/15/2010
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K92_SUMA 08/19/2010
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K92_MLB 08/19/2010
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K92_MLB 10/19/2010
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K91_MLB 07/06/2010
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K92_MLB 07/06/2010
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K92_MLB 10/20/2010
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K91_MLB 07/06/2010
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K92_MLB 04/30/2010
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K92_MLB 07/06/2010
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K92_MLB 10/17/2010
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K91_MLB 10/08/2010
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K91_ERIC 07/06/2010
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K92_MLB 06/23/2010
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K92_SUMA 05/10/2010
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K92_SUMA 06/23/2010
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K92_SUMA 04/27/2010
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K18_MLB 04/27/2010
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K18_MLB 10/08/2010
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K91_MARY 10/08/2010
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K91_ERIC 10/12/2010
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T29_REF 10/12/2010
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T29_REF 10/12/2010
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T29_REF 10/11/2010 K91_ERIC 05/26/2010 K91_TRINHNI 04/27/2010 K18_MLB 06/10/2010 T27_REF 06/10/2010 T27_REF 11/08/2010 K91_ERIC 10/08/2010 K91_ERIC 04/27/2010 K18_MLB 07/12/2010 K91_BEN 07/12/2010 K91_BEN
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46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
51 52 53 54 55 56 57 58 59 61 62 63 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 84 85 86 87 88 89 90 92 93 94 95 96 97 99 100
Date
Contents
Sync 04/27/2010
LPC+SPI Debug Connector K18_MLB 04/27/2010 SMBus Connections K18_MLB 08/16/2010 Voltage & Load Side Current Sensing K91_DINESH 10/29/2010 High Side and CPU/AXG Current Sensing K91_DINESH 09/22/2010 Thermal Sensors K91_DINESH 04/27/2010 Fan Connectors K18_MLB 10/08/2010 WELLSPRING 1 K91_ERIC 07/14/2010 WELLSPRING 2 K91_ERIC 08/06/2010 Digital Accelerometer K91_DINESH 06/08/2010 SPI ROM K91_BEN 09/30/2010 AUDIO: CODEC/REGULATOR K91_AUDIO 07/12/2010 AUDIO: LINE INPUT FILTER K91_AUDIO 07/12/2010 AUDIO: HEADPHONE FILTER K91_AUDIO 07/12/2010 AUDIO: SPEAKER AMP K91_AUDIO 09/30/2010 AUDIO: JACKS K91_AUDIO 09/21/2010 AUDIO: JACK TRANSLATORS K91_AUDIO 10/08/2010 DC-In & Battery Connectors K91_ERIC 07/20/2010 PBus Supply & Battery Charger K91_CHANG 10/08/2010 System Agent Supply K91_ERIC 10/08/2010 5V / 3.3V Power Supply K91_ERIC 10/08/2010 1.5V DDR3 Supply K91_ERIC 10/08/2010 CPU IMVP7 & AXG VCore Regulator K91_ERIC 09/22/2010 CPU IMVP7 & AXG VCore Output K91_ERIC 10/08/2010 CPU VCCIO (1.05V) Power Supply K91_ERIC 11/01/2010 Misc Power Supplies K91_ERIC 10/14/2010 Power FETs K91_MARY 07/22/2010 Power Control 1/ENABLE K91_MARY 06/15/2010 Whistler PCI-E K92_SUMA 06/15/2010 Whistler CORE/FB POWER K92_SUMA 08/03/2010 Whistler FRAME BUFFER I/F K92_MLB 08/19/2010 GDDR5 Frame Buffer A K92_MLB 08/19/2010 GDDR5 Frame Buffer B K92_MLB 12/01/2010 Whistler LVDS/DP/GPIO K92_MLB 11/23/2010 Whistler GPIOs & STRAPs K92_MLB 06/15/2010 Whistler DP PWR/GNDs K92_SUMA 12/21/2010 GPU (Whistler) CORE SUPPLY K91_ERIC 04/27/2010 LVDS Display Connector K18_MLB 11/21/2010 Muxed Graphics Support K92_MLB 10/16/2010 DisplayPort/T29 A MUXing T29_REF 10/16/2010 DisplayPort/T29 A Connector T29_REF 10/08/2010 1V0 GPU / 1V5 FB Power Supply K91_ERIC 08/03/2010 Graphics MUX (GMUX) K91_MARY 06/25/2010 LCD Backlight Driver K90I_KIRAN 08/03/2010 Power Sequencing EG/PCH S0 K91_MARY 08/09/2010 CPU Constraints K92_MLB
(.csa)
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91 92 93 94 95 96 97 98 99 100 101
102 103 104 105 106 107 108 109 130 132
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Memory Constraints PCH Constraints 1 PCH Constraints 2 Ethernet/FW Constraints T29 Constraints SMC Constraints GPU (Whistler) CONSTRAINTS Project Specific Constraints PCB Rule Definitions DEBUG SENSORS AND ADC Power Supplies BIST
04/27/2010 K18_MLB 08/09/2010 K92_MLB 08/09/2010 K92_MLB 08/03/2010 K91_ERIC 10/16/2010 T29_REF 04/27/2010 K18_MLB 08/09/2010 K92_MLB 04/27/2010 K18_MLB 04/27/2010 K18_MLB 08/06/2010 K91_DINESH 08/18/2010 K91_DINESH
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ALIASES RESOLVED
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Contents
A DRAWING TITLE
SCHEM,MLB,K91
Schematic / PCB #’s PART NUMBER
DRAWING NUMBER
Apple Inc.
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
051-8620
1
SCHEM,MLB,K91
SCH
CRITICAL
820-2915
1
PCBF,MLB,K91
PCB
CRITICAL
BOM OPTION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING
TITLE=MLB ABBREV=DRAWING LAST_MODIFIED=Mon Jan 31 12:49:37 2011
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1
J2500,J2550
INTEL CPU
U8000
GRAPHICS
2.X GHZ
AMD WHISTLER
SANDY BRIDGE
XDP CONN PG 23
J2900
PG 9 PG 73
J3100
2 DIMMS DDR3-1067/1333MHZ
DIMM J6950
D
D
PG 26,28
DC/BATT
POWER SUPPLY
PG 63
U2700
GPIO
FDI
DMI
RTC
PG 19
PG 17
PG 17
PG 16
U4900
U6100
SPI Boot ROM
CLOCK CK5G05
Misc
TEMP SENSOR
PG 55
PG 44
CLK PG 19
POWER SENSE PG 44
BUFFER
PG 24
PG 16 J5650,5660
FAN CONN AND CONTROL
SPI J4501
5
PG 51
SATA2.0/3(GB/S)
4
ODDSATA CONN
PG 16
SATA2.0/3(GB/S)
PG 41
INTEL
3
SATA SATA2.0/3(GB/S)
J4500
2
PG 16 SATA2.0/3(GB/S)
1
HDDSATA CONN
C
J5100
LPC + SPI CONN Port80,serial
COUGAR-POINT MOBILE
SATA3.0/6(GB/S)
LPC
B,0
ADC
BSB
Fan
SMC PG 44
U4900
C
PG 16
U1800
0
PG 41
PG 46
Ser Prt
SATA3.0/6(GB/S)
U3600
PWR CTRL
DP OUT
J3402
CAMERA PG
J4501
USB HUB 2
PG 17 U9320
HDMI OUT
PG 83
PG 18
MINI DP PORT PG 84
PCI
PG 18
USB
TMDS OUT
J9400
(UP TO 14 DEVICES)
DVI OUT LVDS OUT
PG 18
0 1 2 3 4 5 6 7 8 9 10 11 12 13
RGB OUT
DP MUX XP25-5G
IR
PG 41
EXTERNALPG B33 EXTERNAL C
PG 33
PG 33 (RESERVATION)
U3700
USB HUB 1
J5713
TRACKPAD/KEYBOARD PG 53
J3401
J4600
U9370
B
J4610
31
PG 34
BLUETOOTH PG 31 EXTERNALPG A34
B
JTAG SMB
DDC MUX PG 16
SMBUS CONNECTION
PG 16
PG 83
PCI-E
PEG
PG 47
HDA
(UP TO 16 LINES) PG 16
PG 16
DIMM
PG 16
LCD PANEL
PG 26,28
U9600 U6201
AUDIO CODEC
GMUX PG 86
PG 56
U6610,6620,6630
U4100
U3900
GB E-NET
FW643
A J3401
BCM57765 PG 38
LINE TIN FILTER
HEADPHONE FILTER
SPEATKER AMP
PG 57
PG 58
PG 59
SYNC_MASTER=K17_REF
System Block Diagram
AirPort
DRAWING NUMBER
PG 31
J4310
J4000
FIREWIRE CONN PG 40
Apple Inc.
J3500 R
E-NET CONN PG 37
SDCARD READER CONN
AUDIO CONN
NOTICE OF PROPRIETARY PROPERTY: SPEATKER
7
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
PG 37 PG 63
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J6700,J6750
PG 60
8
SYNC_DATE=06/30/2009
PAGE TITLE
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1
A
8
7
6
5
K91 POWER SYSTEM ARCHITECTURE PP18V5_DCIN_CONN
4
3
D6990
SMC PWRGD NCP303LSN U5000 (PAGE 45)
R6990
SMC AVREF SUPPLY
3.425V G3HOT
D
V
F7040
PP3V3_S5_SMC SMC_TPAD_RST_L
IN
PPVBAT_G3H
A
VIN
VOUT
PP5V_S3_GFXIMVP6_VDD VDD
ISL6259HRTZ
VOUT
PPVCORE_GPU
PP5V_S0_CPUVTTS0 VIN
A
R7050
SMC_RESET_L
1.05V
EN
(PAGE 70) FW_PWR_EN
A
CPU VCORE VOUT VIN ISL95831 CPUIMVP7_VR_ON U7400 VR_ON
A
CHGR_BGATE
SMC_CPU_VSENSE
V
R5388/U5388 SMC_CPU_HI_ISENSE
PPVCORE_S0_CPU
COUGAR_POINT PM_PWRBTN_L PWRBTN#
SMC_CPU_ISENSE
SYS_RERST# RSMRST#
CPUIMVP7_AXG_PGOOD
PGOOD
(PAGE 67)
ACPRESENT
PM_PCH_PWRGD
PLT_RERST_L
PS_PWRGD
PLTRST#
U1800
GMUX U9600 XP25-5
EG_RAIL1_EN
PB17A
EG_RAIL2_EN
P3V3GPU_EN
PB17B
EG_RAIL3_EN
GPUVCORE_EN
PB18A
EG_RAIL4_EN
P1V1GPU_EN PP5V_S3_DDRREG
DDRREG_EN
PM_ALL_GPU_PGOOD
P1V0GPU_EN
(PAGE 86)
PP1V0_S0GPU_REG
VIN
EN1
DDRVTT_EN
VOUT1
SMC U4900 (PAGE 44)
A
VOUT2
EN2 1.503V(R/H) ISL6236 U9500 (PAGE 85)
P3V3S5_EN
DELAY
SMC_PM_G2_EN
C
1.5V
A
PPDDR_S3_REG
VOUT1
(PAGE 16~21)
V
SMC_DDR_ISENSE VLDOIN
S3 0.75V VOUT2
R5413
1.003V(L/H)
P1V5FB_EN
S5
U2850
SMC_CPU_DDR_VSENSE
R7350
RC
PROCPWRGD DRAMPWROK
U5440
VIN
P60
CPU_PWRGD
PM_MEM_PWRGD
PB16B
PL32A
PP1V0_FW_FWPHY
(PAGE 39)
EN
(PAGE 82)
PPVBAT_G3H_CHGR_R
U4202
CPUVTTS0_PGOOD
PGOOD
GPUVCORE_PGOOD
GPUVCORE_EN
Q7055 PPVBATT_G3H_CONN
CPUVTTS0_EN
PPCPUVTT_S0
SMC_CPU_FSB_ISENSE TPS22924
ISL95870 U7600
SMC_GPU_ISENSE
PGOOD
VR_ON
SMC_BATT_ISENSE
(PAGE 64)
A
VOUT
U5410
ISL6263C U8900
U5001
R7640
SMC_GPU_VSENSE
GPU VCORE
PBUS SUPPLY/ BATTERY CHARGER
J6950
V
8A FUSE
U7000
VIN
SMC_DCIN_ISENSE
C
D
SMC_ONOFF_L
A
ADAPTER
3S2P
REF3333VOUT (PAGE 45)
R7020
DCIN(16.5V)
(9 TO 12.6V)
VIN
PPBUS_G3H
F6905 6A FUSE
AC
Q5315
PP3V3_S5_AVREF_SMC
PP3V42_G3H
PM6640 U6990 (PAGE 62)
SMC_PBUS_VSENSE
1
SMC_RESET_L
ENABLE
PPBUS_G3H
J6900
2
PP1V5_S3
PPVTT_S0_DDR_LDO
CPU
PP1V5_GPU_REG TPS51116 DDRREG_PGOOD U7300 PGOOD (PAGE 66)
SMC_GPU_1V8_ISENSE
POK1
P1V0GPU_PGOOD
POK2
P1V5FB_PGOOD
VIN
ON
RESET* (PAGE 9~14)
Q7860
Q7801
P1V5CPU_EN
U1000 VCCCPUPWRGD
4.5V PP4V5_AUDIO_ANALOG VIN MAX8840 VOUT EN U6200 PP3V3_S0
PP1V5_S3
SM_DRAMPWROK
PP5V_S0
PP1V5_S3RS0 G
SLG5AP020 U7801
P5VS3_EN
COUGAR-POINT
VIN EN1
5V
VREG5 VOUT1
(L/H)
MOBILE
PM_SLP_S5_L
SLP_S5#(E4)
P3V3S5_EN Q9806
B
RC
BKLT_PLT_RST_L && LCD_BKLT_NO
DDRREG_EN
DELAY
U1800 P3V3S3_EN
PM_ALL_GPU_PGOOD
PP3V3_S5
PP3V3_S5
U7980
PP1V8_S0
(R/H)
Q7870
VIN ON
PP3V3_S0GPU
VIN LP8550
PP1V8_GPUIFPX
RSMRST_PWRGD
U9701
BKLT_EN
VOUT
PP3V3_ENET
PP3V3_S0_PWRCTL
P5V3V3_PGOOD
PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN
Q7830
SLP_S5_L(P95)
PM_SLP_S4_L
RES*
(PAGE 16~21)
U4201
S0PGOOD_PWROK
PP3V3_FW_FWPHY
PM_SLP_S3_L SLP_S3_L(P93)
EN
H8S2117 U4900 (PAGE 45)
PP3V3_S0
P3V3S0_EN FW_PWR_EN
SMC_ADAPTER_EN&&PM_SLP_S3_L
V2MON
VIN
PM_SLP_S3_L_R
P1V8_S0_EN EN
ISL8014A
RC DELAY
P1V2S0_EN
RC DELAY
CPUVTTS0_EN
RC DELAY
P1V5CPU_EN
V3MON
PP1V05_S0
P1V8S0_PGOOD
V4MON (PAGE
Q7850 PP1V2_S0
P5VS0_EN
RST*
72)
TRST = 200mS
SYNC_MASTER=K17_REF
SYNC_DATE=06/30/2009
PAGE TITLE
Power Block Diagram P3V3S0_EN
P1V2ENET_EN
EN
8
PGOOD
U7971
ISL88042IRTJJZ
PP1V5_S0
PP1V8_S0
VOUT
U7720 (PAGE 70)
P1V8S0_EN
VCC
PP3V3_S0
R7978
RC DELAY
SMC_RESET_L
SLP_S4_L(P94)
TPS22924 PP3V3_S0_FET
PM_PWRBTN_L
P17(BTN_OUT)
PM_SLP_S5_L
(PAGE 39)
A
CPUIMVP_VR_ON
SYSRST(PA2)
Q7922
P1V8S0_PGOOD
PFWBOOST
SLP_S3#(P12)
99ms DLY
PM_SYSRST_L PP3V3_S3
Q4260
PM_RSMRST_L RSMRST_OUT(P15)
PWR_BUTTON(P90)
IMVP_VR_ON(P16)
P3V3S3_EN
PM_SLP_S3_L
RSMRST_IN(P13)
SMC_ONOFF_L
(PAGE 87)
PM_SLP_S4_L
(P64)
Q7810
PPVOUT_S0_LCDBKLT
B
SMC_ADAPTER_EN
PWRGD(P12)
G
SLG5AP020 U7880
P3V3GPU_EN
P5V3V3_PGOOD
SMC
ALL_SYS_PWRGD
Q7880
P1V8FB_EN
P1V8GPUIFPXFET_GATE
ENA SLP_S4#(H7)
P5VS0_EN
P1V5S0FET_GATE
VOUT2
TPS51125 U7201 (PAGE 65) PGOOD
P5VS3_EN
DELAY
RC
EN2
3.3V
PP5V_S3
P1V2S0_EN
VIN
ISL8014A
DRAWING NUMBER
PP1V2_ENET
U7760 VOUT (PAGE 70) PGOOD
Apple Inc.
P1V2ENET_PGOOD R
PBUSVSENS_EN
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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D
D
C
C
B
B
A
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
PAGE TITLE
Revision History DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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8
7
6
5
4
3
BOM Variants
2
1
Bar Code Labels / EEEE #’s TABLE_BOMGROUP_HEAD
-
BOM NUMBER
BOM NAME
BOM OPTIONS
639-1468
PCBA,MLB,K91F,DG64
K91_COMMON,SODIMM:FOXCONN,CPU:2_2GHZ,GPU:WHISTLER,FB_1G_HYNIX,VRAM_DVP1,VRAM_DVP0,EEEE:DG64
|
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DDKG]
CRITICAL
EEEE:DDKG
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DG63]
CRITICAL
EEEE:DG63
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DG64]
CRITICAL
EEEE:DG64
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DG65]
CRITICAL
EEEE:DG65
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DG66]
CRITICAL
EEEE:DG66
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DG67]
CRITICAL
EEEE:DG67
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DHMV]
CRITICAL
EEEE:DHMV
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DHMW]
CRITICAL
EEEE:DHMW
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DL81]
CRITICAL
EEEE:DL81
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DL82]
CRITICAL
EEEE:DL82
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DL83]
CRITICAL
EEEE:DL83
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DL84]
CRITICAL
EEEE:DL84
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DL85]
CRITICAL
EEEE:DL85
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DL86]
CRITICAL
EEEE:DL86
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DL87]
CRITICAL
EEEE:DL87
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DL88]
CRITICAL
EEEE:DL88
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DL89]
CRITICAL
EEEE:DL89
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DL7Q]
CRITICAL
EEEE:DL7Q
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DL7R]
CRITICAL
EEEE:DL7R
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DL7T]
CRITICAL
EEEE:DL7T
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DL7V]
CRITICAL
EEEE:DL7V
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DL7W]
CRITICAL
EEEE:DL7W
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DL7Y]
CRITICAL
EEEE:DL7Y
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DL80]
CRITICAL
EEEE:DL80
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
639-1972
PCBA,MLB,K91F,DL83
K91_COMMON,SODIMM:HYBRID,CPU:2_2GHZ,GPU:WHISTLER,FB_1G_HYNIX,VRAM_DVP1,VRAM_DVP0,EEEE:DL83 TABLE_BOMGROUP_ITEM
639-1971
PCBA,MLB,K91F,DL82
K91_COMMON,SODIMM:MOLEX,CPU:2_2GHZ,GPU:WHISTLER,FB_1G_HYNIX,VRAM_DVP1,VRAM_DVP0,EEEE:DL82 TABLE_BOMGROUP_ITEM
639-1469
PCBA,MLB,K91F,DG65
K91_COMMON,SODIMM:FOXCONN,CPU:2_2GHZ,GPU:WHISTLER,FB_1G_SAMSUNG,VRAM_DVP0,EEEE:DG65 TABLE_BOMGROUP_ITEM
639-1970
PCBA,MLB,K91F,DL86
K91_COMMON,SODIMM:HYBRID,CPU:2_2GHZ,GPU:WHISTLER,FB_1G_SAMSUNG,VRAM_DVP0,EEEE:DL86 TABLE_BOMGROUP_ITEM
D
639-1956
PCBA,MLB,K91F,DL7W
K91_COMMON,SODIMM:MOLEX,CPU:2_2GHZ,GPU:WHISTLER,FB_1G_SAMSUNG,VRAM_DVP0,EEEE:DL7W
D
TABLE_BOMGROUP_ITEM
639-1470
PCBA,MLB,K91F,DG66
K91_COMMON,SODIMM:FOXCONN,CPU:2_3GHZ,GPU:WHISTLER,FB_1G_HYNIX,VRAM_DVP1,VRAM_DVP0,EEEE:DG66 TABLE_BOMGROUP_ITEM
639-1974
PCBA,MLB,K91F,DL87
K91_COMMON,SODIMM:HYBRID,CPU:2_3GHZ,GPU:WHISTLER,FB_1G_HYNIX,VRAM_DVP1,VRAM_DVP0,EEEE:DL87
639-1976
PCBA,MLB,K91F,DL88
K91_COMMON,SODIMM:MOLEX,CPU:2_3GHZ,GPU:WHISTLER,FB_1G_HYNIX,VRAM_DVP1,VRAM_DVP0,EEEE:DL88
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
639-1471
PCBA,MLB,K91F,DG67
K91_COMMON,SODIMM:FOXCONN,CPU:2_3GHZ,GPU:WHISTLER,FB_1G_SAMSUNG,VRAM_DVP0,EEEE:DG67 TABLE_BOMGROUP_ITEM
639-1973
PCBA,MLB,K91F,DL81
K91_COMMON,SODIMM:HYBRID,CPU:2_3GHZ,GPU:WHISTLER,FB_1G_SAMSUNG,VRAM_DVP0,EEEE:DL81 TABLE_BOMGROUP_ITEM
639-1954
PCBA,MLB,K91F,DL7T
K91_COMMON,SODIMM:MOLEX,CPU:2_3GHZ,GPU:WHISTLER,FB_1G_SAMSUNG,VRAM_DVP0,EEEE:DL7T TABLE_BOMGROUP_ITEM
639-1573
PCBA,MLB,K91,DHMV
K91_COMMON,SODIMM:FOXCONN,CPU:2_0GHZ,GPU:SEYMOUR,FB_256_HYNIX,EEEE:DHMV
639-1945
PCBA,MLB,K91,DL7Q
K91_COMMON,SODIMM:HYBRID,CPU:2_0GHZ,GPU:SEYMOUR,FB_256_HYNIX,EEEE:DL7Q
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
639-1953
PCBA,MLB,K91,DL7R
K91_COMMON,SODIMM:MOLEX,CPU:2_0GHZ,GPU:SEYMOUR,FB_256_HYNIX,EEEE:DL7R TABLE_BOMGROUP_ITEM
639-1574
PCBA,MLB,K91,DHMW
K91_COMMON,SODIMM:FOXCONN,CPU:2_0GHZ,GPU:SEYMOUR,FB_256_SAMSUNG,EEEE:DHMW TABLE_BOMGROUP_ITEM
639-1959
PCBA,MLB,K91,DL80
K91_COMMON,SODIMM:HYBRID,CPU:2_0GHZ,GPU:SEYMOUR,FB_256_SAMSUNG,EEEE:DL80 TABLE_BOMGROUP_ITEM
639-1960
PCBA,MLB,K91,DL7Y
K91_COMMON,SODIMM:MOLEX,CPU:2_0GHZ,GPU:SEYMOUR,FB_256_SAMSUNG,EEEE:DL7Y TABLE_BOMGROUP_ITEM
085-1901
K91/K91F DEVELOPMENT BOM
K91_DEVEL:ENG
K91 BOM GROUPS TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
K91_COMMON
ALTERNATE,COMMON,K91_COMMON1,K91_COMMON2,K91_PROGPARTS,K91_PROGPARTS1,UVGLUE_K91_K91F,K91_PVT
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
C
K91_COMMON1
CPUMEM_S0,SMC_DEBUG_YES,HUB1_2NONREM,HUB2_2NONREM,USBHUB_2513B
K91_COMMON2
GPUVID_1P11V,KB_BL,T29:YES,ENET_SD:B0,T29BST:Y,SDRV_PD,SDRVI2C:MCU,T29_DP_HPD:ALL_OR
TABLE_BOMGROUP_ITEM
C
TABLE_BOMGROUP_ITEM
K91_PVT
BMON:PROD,VREFMRGN_NOT,XDP,XDP_CPU_BPM,BKLT:PROD,ISNS_ON:NO,LPCPLUS_R:YES
K91_PROGPARTS
GMUX_PROG,IR_PROG,TPAD_PROG:PVT,ENETROM_PROG:PVT,T29ROM:PROG,T29MCU:PROG
K91_PROGPARTS1
SMC_PROG:PVT,BOOTROM_PROG:PVT
K91_DEVEL:ENG
SNB_CPT_XDP,BMON:ENG,GMUX_JTAG_CONN,VREFMRGN,LPCPLUS_CONN:YES,LPCPLUS_R:YES,BKLT:ENG,S0PGOOD_ISL,CPURIPPLE_ENG,IMVPISNS_ENG,ISNS_ON:YES,DEBUG_ADC,DIGI_MIC
Programmables - All Builds
Alternate Parts
TABLE_BOMGROUP_ITEM
(Alternate)
(Primary)
TABLE_BOMGROUP_ITEM
TABLE_ALT_HEAD
PART NUMBER TABLE_BOMGROUP_ITEM
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
341S2830
1
IC,CPLD,LATTICE,GMUX,K91/K91F
U9600
CRITICAL
GMUX_PROG
336S0042
1
IC,PLD,LATTICE,LFXP2-5E-5,132 BALL CSBGA
U9600
CRITICAL
GMUX_BLANK
341S2384
1
IR,ENCORE II,CY7C63833-LFXC
U4800
CRITICAL
IR_PROG
341S3129
1
IC,T29 EEPROM,PVT,K9x
U3690
CRITICAL
T29ROM:PROG
335S0777
1
IC,EEPROM,SERIAL,8KB,SOIC
U3690
CRITICAL
T29ROM:BLANK
341S3128
1
IC,PROGRMD,LPC1112A,T29 PORT MCU,PVT,HVQFN25
U9330
CRITICAL
T29MCU:PROG
337S3997
1
IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25
U9330
CRITICAL
T29MCU:BLANK
341S2957
1
IC,GPU ROM,K91/F,K92,PROG
U8701
CRITICAL
GPUROM:PROG
335S0724
1
IC,GPU ROM,K91/F,K92,BLANK
U8701
CRITICAL
GPUROM:BLANK
COMMENTS: TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
K91_DEVEL:PVT
SNB_CPT_XDP,LPCPLUS_CONN:YES,LPCPLUS_R:YES
157S0058
157S0055
ALL
Delta alt to TDK Magnetics
152S0896
152S0518
ALL
MAG LAYERS ALT TO CYNTEC
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
SNB_CPT_XDP
XDP,XDP_CONN,XDP_CPU_BPM,XDP_PCH
TABLE_ALT_ITEM
155S0457
155S0329
ALL
MAG LAYERS ALT TO MURATA
353S2805
353S2603
ALL
Fairchild wafer option
TABLE_ALT_ITEM
Module Parts
TABLE_ALT_ITEM
128S0264
128S0257
ALL
Sanyo alt to Kemet TABLE_ALT_ITEM
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
128S0303
128S0282
ALL
Panasonic alt to Sanyo
353S3085
353S1658
ALL
ST Micro alt to LT
TABLE_ALT_ITEM
337S4031
1
IC,CPU,SNB,SR030,PRQ,D2,2.0,45W,4+2,1.20,6M,BGA
U1000
CRITICAL
CPU:2_0GHZ
TABLE_ALT_ITEM
337S4032
1
IC,CPU,SNB,SR00W,PRQ,D2,2.2,45W,4+2,1.30,6M,BGA
U1000
CRITICAL
CPU:2_2GHZ
376S0972
376S0612
ALL
337S4033
1
IC,CPU,SNB,SR00U,PRQ,D2,2.3,45W,4+2,1.30,8M,BGA
U1000
CRITICAL
CPU:2_3GHZ
376S0855
376S0613
ALL
Diodes alt to Toshiba dual N-FET
337S4029
1
IC,PCH,COUGARPOINT,SLH9D,PRQ,BD82HM65
U1800
CRITICAL
138S0676
138S0691
ALL
Murata alt to Samsung cap
337S3936
1
IC,GPU,AMD,WHISTLER,962FCBGA,40NM,ES
U8000
CRITICAL
GPU:WHISTLER
138S0652
138S0648
ALL
Samsung / Murata alt for Taiyo Yuden
337S3979
1
IC,GPU,AMD,SEYMOUR,M2 LP,ES1,962BGA
U8000
CRITICAL
GPU:SEYMOUR
138S0681
138S0638
ALL
Taiyo Yuden alt for Samsung
338S0945
1
IC,ASSP,LIGHTRIDGE,S LHAJ,PRQ,FCBGA,15X15MM
U3600
CRITICAL
T29:YES
152S0685
152S0796
ALL
Dale/Vishay/TDK
343S0534
1
IC,ASIC,GBIT ETHNET&SD CTRLR,686 QFN8X8,B0
U3900
CRITICAL
ENET_SD:B0
376S0977
376S0859
ALL
Diodes alt for Rohm
ROHM alt to Toshiba N-FET TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
B
B
alt for Cyntec TABLE_ALT_ITEM
TABLE_ALT_ITEM
343S0494
1
IC,ASIC,GBIT ETHNET&SD CTRLR,686 QFN8X8,A0
U3900
CRITICAL
338S0753
1
IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12
U4100
CRITICAL
ENET_SD:A0
353S2592
353S3199
ALL
U6201 AUDIO CODEC OLD REV IS ALTERNATE FOR NEW REV
335S0550
335S0777
ALL
add 4K byte as alternative to 2K
SMC
TABLE_ALT_ITEM
TABLE_ALT_ITEM
333S0543
4
IC,SGRAM,GDDR5,32MX32.1.25GHz,E-DIE,HF
U8400,U8450,U8500,U8550
CRITICAL
FB_512_SAMSUNG
371S0679
371S0652
ALL
NXP alternate for pin diodes
333S0564
4
IC,SDRAM,GDDR5,32MX32,1.25GHz,A-DIE1.35V
U8400,U8450,U8500,U8550
CRITICAL
FB_512_HYNIX
138S0671
138S0673
ALL
Taiyo Yuden alt for Murata 10 uF caps
333S0571
4
IC,SGRAM,GDDR5,64MX32,3.6GBPS,C-DIE,HF
U8400,U8450,U8500,U8550
CRITICAL
FB_1G_SAMSUNG
333S0572
4
IC,SGRAM,GDDR5,64MX32,3.6GBPS,M-DIE,HF
U8400,U8450,U8500,U8550
CRITICAL
FB_1G_HYNIX
TABLE_ALT_ITEM
A
338S0895
1
IC,SMC,HS8/2117,9MMX9MM,TLP
U4900
CRITICAL
SMC_BLANK
341S2854
1
IC,SMC,DEVELOPMENT-PROTO0,K91
U4900
CRITICAL
SMC_PROG:PROTO0
341S2935
1
IC,SMC,DEVELOPMENT-PROTO1,K91
U4900
CRITICAL
SMC_PROG:PROTO1
341S2994
1
IC,SMC,DEVELOPMENT-PROTO2,K91
U4900
CRITICAL
SMC_PROG:PROTO2
341S2861
1
IC,SMC,DEVELOPMENT-EVT,K91
U4900
CRITICAL
SMC_PROG:EVT
341S2864
1
IC,SMC,DEVELOPMENT-DVT,K91
U4900
CRITICAL
SMC_PROG:DVT
341S2867
1
IC,SMC,DEVELOPMENT-PVT,K91
U4900
CRITICAL
SMC_PROG:PVT
333S0543
2
IC,SGRAM,GDDR5,32MX32.1.25GHz,E-DIE,HF
U8500,U8550
CRITICAL
FB_256_SAMSUNG
333S0564
2
IC,SDRAM,GDDR5,32MX32,1.25GHz,A-DIE1.35V
U8500,U8550
CRITICAL
FB_256_HYNIX
353S3055
1
IC,PI3VEDP212,X2 DISPLAYPORT 2:1 MUX,QFN
U9390
CRITICAL
725-1479
1
MLB LOCTITE UV EB CPU,PCH,T29,GPU,K91
UV_GLUE_K91_K91F
CRITICAL
UVGLUE_K91_K91F
335S0740
1
64 MBIT SPI SERIAL DUAL I/O FLASH
U6100
CRITICAL
BOOTROM_BLANK
516S0806
1
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,FOXCONN
J3100
CRITICAL
SODIMM:FOXCONN
341S2893
1
IC,EFI,ROM,PROTO0, K90/K90I/K91/K91F/K92
U6100
CRITICAL
BOOTROM_PROG:PROTO0
516-0246
1
CONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,FOXCONN
J2900
CRITICAL
SODIMM:FOXCONN
341S2934
1
IC,EFI,ROM,PROTO1, K90/K90I/K91/K91F/K92
U6100
CRITICAL
BOOTROM_PROG:PROTO1
516S0805
1
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX
J3100
CRITICAL
SODIMM:MOLEX
341S2991
1
IC,EFI,ROM,PROTO2, K90/K90I/K91/K91F/K92
U6100
CRITICAL
BOOTROM_PROG:PROTO2
516-0245
1
CONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,MOLEX
J2900
CRITICAL
SODIMM:MOLEX
341S2894
1
IC,EFI,ROM,EVT, K90/K90I/K91/K91F/K92
U6100
CRITICAL
BOOTROM_PROG:EVT
516S0805
1
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX
J3100
CRITICAL
SODIMM:HYBRID
341S2895
1
IC,EFI,ROM,DVT, K90/K90I/K91/K91F/K92
U6100
CRITICAL
BOOTROM_PROG:DVT
516-0246
1
CONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,FOXCONN
J2900
CRITICAL
SODIMM:HYBRID
341S2896
1
IC,EFI,ROM,PVT, K90/K90I/K91/K91F/K92
U6100
CRITICAL
BOOTROM_PROG:PVT
EFI ROM
SYNC_MASTER=K17_REF
PSOC
ETHERNET ROM 335S0663 341S2685
1 1
U3990
IC,FLASH,SERIAL,SPI,1MBIT,2V7,8P,SOIC
U3990
IC,ENET,1MBITFLASH,CIV REV01,K74/K75,K40
341S2973
1
IC,ENET,1MBITFLASH,CIV REV01,K60/K62
U3990
341S3026
1
IC,ENET,1MBITFLASH,CIV REV01,K90i/K91/K92
341S3096
1
IC,ENET ROM,1MBIT,DVT,PVT,K90i/K91x
8
7
CRITICAL CRITICAL
SYNC_DATE=05/28/2009
PAGE TITLE
341S2902
1
IC,TP PSOC,K9x,PROTO0
U5701
CRITICAL
TPAD_PROG:PROTO0
341S2940
1
IC,TP PSOC,K9x,PROTO1
U5701
CRITICAL
TPAD_PROG:PROTO1
BOM Configuration DRAWING NUMBER
ENETROM_BLANK
Apple Inc.
ENETROM_PROG:A0_SD
CRITICAL
ENETROM_PROG:B0_SD
U3990
CRITICAL
ENETROM_PROG:EVT
U3990
CRITICAL
ENETROM_PROG:PVT
6
5
341S3001
1
IC,TP PSOC,K9x,PROTO2
U5701
CRITICAL
TPAD_PROG:PROTO2
341S3024 341S3099
1
IC,TP PSOC,K9x,EVT
U5701
CRITICAL
TPAD_PROG:EVT
1
IC,TP PSOC,K9x,DVT,PVT
U5701
CRITICAL
TPAD_PROG:PVT
4
3
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
SIZE
D REVISION
BRANCH
PAGE
5 OF 132 SHEET
5 OF 101
1
A
8
7
6
Functional Test Points
USB PORTS
I1038 TRUE
J5650 (LEFT FAN CONN) FUNC_TEST 101 67 68 PP5V_S0 TRUE 6 7 8
I1039 TRUE
69 71 22 41 46 51 53 64 72 86 88
TRUE TRUE
FAN_LT_PWM FAN_LT_TACH
3 TPs per Fan
D
TRUE TRUE TRUE TRUE
TRUE
I1103
PP5V_S3_RTUSB_A_F USB2_LT1_N USB2_LT1_P GND
I1102
42 42 98 42 98
I1105 I1107
51
I1108
51
2 TPs
PP5V_S0 FAN_RT_PWM FAN_RT_TACH GND
I1104
I1106
J5660 (RIGHT FAN CONN) I1493
I1040 TRUE
5
101 6 7 8 22 41 46 51 53 64 67 68 69 71 72 86 88
I1042 TRUE I1043 TRUE I1044 TRUE TRUE
PP5V_S3_RTUSB_B_F USB_LT2_N USB_LT2_P GND
42
I1109
42 98
I1110
42 98
I1111 I1112 I1113
51
I1114
51
I1115
5 TPs per Fan
I1117
J6780 (MIC CONN)
I1116 I1118
TRUE TRUE TRUE
I557 I558 I559
BI_MIC_N BI_MIC_SHIELD BI_MIC_P
60 61
I1119
J3401 & J3402 (AIRPORT/BT/CAMERA CONN) I1120 16 31 93 I1051 TRUE PCIE_AP_D2R_P I1122 16 31 93 I1050 TRUE PCIE_AP_D2R_N I1121 PCIE_AP_R2D_P TRUE 31 93 I1053 I1123 31 93 I1052 TRUE PCIE_AP_R2D_N I1124 I1054 TRUE PCIE_CLK100M_AP_CONN_P 31 I1125 98 PCIE_CLK100M_AP_CONN_N 31 I1056 TRUE I1127 98 AP_CLKREQ_Q_L TRUE 31 I1055 I1126 17 25 31 84 I1058 TRUE PCIE_WAKE_L I1128 TRUE WIFI_EVENT_L 31 44 45 I1496 I1129 AP_RESET_CONN_L TRUE 31 I1057 I1130 31 45 I1059 TRUE PP3V3_WLAN I1061 TRUE PP5V_S3_ALSCAMERA_F 31 I1060 TRUE SMBUS_SMC_A_S3_SDA 6 31 44 47 53 54 96 J6950 (BIL CABLE CONN) I1063 TRUE SMBUS_SMC_A_S3_SCL 6 31 44 47 53 54 96 I1150 TRUE PP5V_S3_IR_R I1062 TRUE USB_CAMERA_CONN_P 31 92 I1149 TRUE SMC_LID_R I1064 TRUE USB_CAMERA_CONN_N 31 92 I1151 TRUE IR_RX_OUT 98 I1066 TRUE CONN_USB2_BT_P I1152 TRUE SYS_LED_ANODE 98 I1065 TRUE CONN_USB2_BT_N GND TRUE SMBUS_SMC_0_S0_SCL 31 44 47 50 79 96 TRUE I1497 TRUE SMBUS_SMC_0_S0_SDA 31 44 47 50 79 96 I1498
60 61 60 61
J6781 & J6782 (SPEAKERS CONN) I989 I990 I992 I991 I994 I993
TRUE TRUE TRUE TRUE TRUE TRUE
C
SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N SPKRCONN_S_OUT_P SPKRCONN_S_OUT_N
59 60 98 59 60 98 59 60 98 59 60 98 59 60 98 59 60 98
J9000 (LVDS CONN)
4
J5713 (KEY BOARD CONN) 72 87 31 32 47 48 TRUE PP3V3_S3 6 7 8 18 19 24 25 29 30 49 53 54 71 TRUE PP3V42_G3H 6 7 25 42 44 45 46 47 52 5262 63 72 TRUE WS_KBD1 52 TRUE WS_KBD2 52 TRUE WS_KBD3 TRUE WS_KBD4 52 WS_KBD5 TRUE 52 52 TRUE WS_KBD6 TRUE WS_KBD7 52 TRUE WS_KBD8 52 TRUE WS_KBD9 52 52 TRUE WS_KBD10 TRUE WS_KBD11 52 TRUE WS_KBD12 52 TRUE WS_KBD13 52 52 TRUE WS_KBD14 TRUE WS_KBD15_CAP 52 TRUE WS_KBD16_NUM 52 TRUE WS_KBD17 52 TRUE WS_KBD18 52 TRUE WS_KBD19 52 TRUE WS_KBD20 52 TRUE WS_KBD21 52 TRUE WS_KBD22 52 WS_KBD23 TRUE 52 TRUE WS_KBD_ONOFF_L 52 TRUE WS_LEFT_SHIFT_KBD 52 TRUE WS_LEFT_OPTION_KBD 52 52 TRUE WS_CONTROL_KBD
TRUE I732 TRUE I731 TRUE I734 TRUE I733 TRUE I735 TRUE TRUE I737 TRUE I739 TRUE I738 TRUE I740 TRUE I741 TRUE I742 TRUE I743 TRUE I744 TRUE I751 TRUE I752 TRUE TRUE I760 I756 TRUE I1292 TRUE I1288 TRUE
I996 I997 I998 I1000 I1001 I1002 I1004 I1003 I1005 I1007 I1006 I1009 I1008 I1010 I1011 I1012 I1014 I1013 I1015 I1016 I1017 I1018
B
I1019 I1020 I1022 I1021
62
I1477
41 43
I1478
41 45
I1479 I1480 I1481
I1024 I1026 I1025 I1028 I1027 I1029 I1494 I1495
I1509
I1086 I1508
I1273 I1089 I1088 I1090 I1464
I1098 I1097 I1095 I1096
I1101
GND J4501 (SATA HDD CONN) PP5V_S0_HDD_FLT SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_C_N SATA_HDD_D2R_C_P
I1032 TRUE I1031 TRUE I1033 TRUE I1035 TRUE I1034 TRUE
I1099 I1100
TRUE
TRUE
44 47 53 54 96 44 47 53 54 96
62
I1590
41 92
6 44 47 62 63 96
I1610 I1611
6 44 47 62 63 96
I1613
6
I1612 I1614
GND
I1615
I1591
J5815 (KBD BACKLIGHT CONN) KBDLED_ANODE 53 SMC_KDBLED_PRESENT_L 53
I1145 TRUE
I1142
GND
TRUE
J6995 (BAT LED CONN) PP3V42_G3H TRUE SMBUS_SMC_BSA_SDA TRUE SMBUS_SMC_BSA_SCL TRUE SMC_BIL_BUTTON_L
I1140 TRUE
I1146 TRUE
I1141 I1143
I1593 I1594 6 7 25 42 44 45 46 47 52 62 63 72
I1595
6 44 47 62 63 96
I1596 6 44 47 62 63 96
I1617 44 45 62
I1616 I1618
FUNC_TEST TRUE
TRUE
GND
GND
I1619 I1620
TRUE 6 TPs
8
GND
I1622 I1621
7
TP_CPU_RSVD<43..32>
TP_CPU_RSVD<24..15>
17 44 46
TP_CPU_RSVD<2..1>
17 25 44 44 46
TP_CPU_RSVD_NCTF<8..5>
44 46
6
NC_TP_CPU_RSVD<65..62> TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD<58..45> TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD<43..32> TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD<27..26> TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD<24..15> TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD<2..1> TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD_NCTF<8..5> TRUE MAKE_BASE=TRUE
NC NO_TESTs
44 45 52 44 45 46 63
17 6 44 45 46 17 6 44 45 46 17 6
38 6
NC_CRT_IG_BLUE NC_CRT_IG_GREEN NC_CRT_IG_RED
NC_CRT_IG_BLUE TRUE MAKE_BASE=TRUE NC_CRT_IG_GREEN TRUE MAKE_BASE=TRUE NC_CRT_IG_RED TRUE MAKE_BASE=TRUE
44 45 46 44 45 46 17 6 44 46 17 6
17 6 46 17 6
17 6 6 17 17 6
NC_CRT_IG_DDC_CLK 6 TRUE MAKE_BASE=TRUE NC_CRT_IG_DDC_DATA TRUE MAKE_BASE=TRUE
NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC
NC_CRT_IG_HSYNC TRUE MAKE_BASE=TRUE NC_CRT_IG_VSYNC TRUE MAKE_BASE=TRUE
NC_LVDS_IG_CTRL_CLK NC_LVDS_IG_CTRL_DATA NC_PCH_LVDS_VBG
NC_LVDS_IG_CTRL_CLK TRUE MAKE_BASE=TRUE NC_LVDS_IG_CTRL_DATA TRUE MAKE_BASE=TRUE NC_PCH_LVDS_VBG TRUE
46
17
18 6 46 18 6 41 18 6
6 16 16 6 33 84 95 16 6 33 84 95
MAKE_BASE=TRUE
T29_D2R_P<1..0> T29_D2R_N<1..0> T29_D2R_C_P<1..0> 84 85 95 T29_D2R_C_N<1..0> 84 85 95 T29_R2D_C_P<1..0> 33 84 95 T29_R2D_C_N<1..0> 33 84 95 T29_R2D_P<1..0> 84 95 T29_R2D_N<1..0> 84 95 T29DPA_ML_P<3..0> 84 85 95 T29DPA_ML_N<3..0> 84 85 95 DP_T29SNK0_AUXCH_C_P 33 78 DP_T29SNK0_AUXCH_C_N 33 78 DP_T29SNK0_AUXCH_P 33 95 DP_T29SNK0_AUXCH_N 33 95 DP_T29SNK0_ML_C_P<3..0> DP_T29SNK0_ML_C_N<3..0> DP_T29SNK0_ML_P<3..0> 33 DP_T29SNK0_ML_N<3..0> 33
TRUE TP_FW643_NAND_TREE TRUE TP_FW643_OCR10_CTL TRUE TP_FW643_SCIFCLK TRUE TP_FW643_SCIFDAIN TRUE TP_FW643_SCIFDOUT TRUE TP_FW643_SCIFMC TRUE TP_FW643_SDA TRUE TP_FW643_SE TRUE TP_FW643_SM TRUE TP_FW643_CE TRUE TP_FW643_FW620_L TRUE TP_FW643_JASI_EN TRUE DMI_S2N_N<1> TRUE DMI_S2N_P<1> TRUE FDI_DATA_N<1> TRUE FDI_DATA_P<1> TRUE FDI_FSYNC<1..0> TRUE FDI_LSYNC<1..0> TRUE FDI_INT
6 17 17 6 17 6
6 17
6 18
I1598
38
I1600
38
I1601
38
I1602
38
I1599
38
I1603
38
I1605
38
I1604
38 38
I1606 I1607
38
I1631
38 90 9 17
I1630 I1624 I1623
90 9 17 90 17 9 90 9 17 9 17 90
5
I1625 I1626 I1627 I1629 I1628
I1632 I1634 I1633 I1636 I1635 I1637
95
I1638
95
I1639 I1641 I1640
33 78 95
I1642
33 78 95
I1644 I1643
95
DP_T29SNK1_AUXCH_C_P 33 DP_T29SNK1_AUXCH_C_N 33 DP_T29SNK1_AUXCH_P 33 95 DP_T29SNK1_AUXCH_N 33 95
TRUE TP_FW643_VAUX_ENABLE 38 TRUE TP_FW643_VBUF 38 TRUE TP_FW643_TCK 38 TRUE TP_FW643_TDO 38 TRUE TP_FW643_TMS 38 TRUE TP_SMC_P10 44 45 TRUE TP_P7_7 52 45 TRUE TP_PSOC_SCL 52 TRUE TP_PSOC_SDA 52 TRUE TP_SMC_P24 44 45 TRUE DC_TEST_BH1_BG2 12 TRUE DC_TEST_BH3_BJ2 12 TRUE TP_USB_HUB1_OCS1 24 TRUE TP_USB_HUB1_PRTPWR1 24 TRUE TP_USB_HUB2_OCS1 24 TRUE TP_USB_HUB2_PRTPWR1 24 TP_DC_TEST_A62 TRUE 12 TRUE TP_DC_TEST_D65 12 TRUE TP_SMC_PF5 44 45
16 6 16 6
I1645
78 95
NC_HDA_SDIN1 NC_HDA_SDIN2 NC_HDA_SDIN3
I766 I769 I768 I770 I772 I771 I774
17 6
6 18
17 6 6 16 6 16 17 6 6 16 17 6
17 6 17 6
TP_AUD_GPIO_2 TP_AUD_GPIO_1 TP_AUD_LO1_L_N TP_AUD_LO1_L_P TP_BKL_FAULT
TRUE 56 TRUE 56 TRUE 56 TRUE 56 TRUE 88 TRUE TP_SPI_DESCRIPTOR_OVERRIDE_L 44 TRUE TP_XDPPCH_HOOK2 23 TP_XDPPCH_HOOK3 TRUE 23 87 TRUE TP_GMUX_PL6B 17 72 TRUE PM_RSMRST_L TRUE CPUIMVP_BOOT1 67 68 67 68 TRUE CPUIMVP_BOOT2 TRUE CPUIMVP_UGATE2 67 68 TRUE TP_1V05_S0_PCH_VCCAPLLEXP 20
17 6 17 6
NC_SDVO_TVCLKINN NC_SDVO_TVCLKINP
TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
NC_SDVO_STALLN NC_SDVO_STALLP NC_SDVO_INTN NC_SDVO_INTP
6
6
6
6 18 8 18 8 18 8
6 18 6
NC_PCI_PME_L NC_PCI_CLK33M_OUT3
NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7P NC_PSOC_P1_3 NC_SATA_B_D2RN NC_SATA_B_D2RP NC_SATA_B_R2D_CN NC_SATA_B_R2D_CP NC_SATA_D_D2RN NC_SATA_D_D2RP NC_SATA_D_R2D_CN NC_SATA_D_R2D_CP NC_SATA_E_D2RN NC_SATA_E_D2RP NC_SATA_E_R2D_CN NC_SATA_E_R2D_CP NC_SATA_F_D2RN NC_SATA_F_D2RP NC_SATA_F_R2D_CN NC_SATA_F_R2D_CP
NC_PCI_PME_L TRUE 6 18 I1514 MAKE_BASE=TRUE NC_PCI_CLK33M_OUT3 18 6 TRUE I1515 MAKE_BASE=TRUE I1516 NC_PCIE_CLK100M_PE4N 6 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE4P 6 I1517 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE5N I1518 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE5P I1519 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE6N I1520 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE6P I1529 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE7N I1530 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE7P 619 I1536 TRUE MAKE_BASE=TRUE NC_PSOC_P1_3 TRUE 6 52 I1535 MAKE_BASE=TRUE NC_SATA_B_D2RN 6 TRUE I1534 MAKE_BASE=TRUE NC_SATA_B_D2RP 6 TRUE I1533 MAKE_BASE=TRUE NC_SATA_B_R2D_CN 6 TRUE I1537 MAKE_BASE=TRUE NC_SATA_B_R2D_CP 6 TRUE I1539 MAKE_BASE=TRUE NC_SATA_D_D2RN 6 16 TRUE I1558 MAKE_BASE=TRUE NC_SATA_D_D2RP 6 16 TRUE I1540 MAKE_BASE=TRUE NC_SATA_D_R2D_CN 6 16 TRUE I1541 MAKE_BASE=TRUE NC_SATA_D_R2D_CP 6 16 TRUE I1542 MAKE_BASE=TRUE NC_SATA_E_D2RN 6 16 TRUE I1543 MAKE_BASE=TRUE NC_SATA_E_D2RP TRUE 6 16 I1544 MAKE_BASE=TRUE NC_SATA_E_R2D_CN 6 16 TRUE I1545 MAKE_BASE=TRUE NC_SATA_E_R2D_CP 6 16 TRUE I1560 MAKE_BASE=TRUE NC_SATA_F_D2RN 6 16 TRUE MAKE_BASE=TRUE NC_SATA_F_D2RP 6 16 TRUE MAKE_BASE=TRUE I1436 NC_SATA_F_R2D_CN 6 16 TRUE MAKE_BASE=TRUE I1437 NC_SATA_F_R2D_CP 6 16 TRUE MAKE_BASE=TRUE I1438 I1439 I1440 I1441 I1442
TP_SMC_P41
44
NC_SMC_P41 TRUE MAKE_BASE=TRUE
I1443
PCH ALIASES
6 17 6 17 6 17 17 17 6 17 6 17
6 17 6 17 6 17 17 17 6 17 6 17
NC_SDVO_TVCLKINN NC_SDVO_TVCLKINP
6 17 6 17
NC_SDVO_STALLN NC_SDVO_STALLP
6 17 6 17
NC_SDVO_INTN NC_SDVO_INTP
6 17
NC_GPU_BUFRST_L 6 TRUE MAKE_BASE=TRUE NC_GPU_GSTATE<0> TRUE MAKE_BASE=TRUE NC_GPU_GSTATE<1> 6 TRUE MAKE_BASE=TRUE NC_GPU_MIOA_D<9..0> TRUE MAKE_BASE=TRUE NC_GPU_MIOA_DE 6 TRUE MAKE_BASE=TRUE
NC_LVDS_EG_BKL_PWM TP_LVDS_IG_B_CLKN TP_LVDS_IG_B_CLKP TP_LVDS_IG_BKL_PWM
NC_LVDS_EG_BKL_PWM TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_CLKN TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_CLKP TRUE MAKE_BASE=TRUE NC_LVDS_IG_BKL_PWM TRUE MAKE_BASE=TRUE
NC_SMC_BS_ALRT_L
NC_SMC_BS_ALRT_L TRUE MAKE_BASE=TRUE
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
MEM_A_BA<2..0> 11 26 91 MEM_A_CKE<1..0> 11 26 91 MEM_A_CLK_N<1..0> 11 MEM_A_CLK_P<1..0> 91 26 MEM_A_CS_L<1..0> 11 26 91 MEM_A_ODT<1..0> 11 26 91 MEM_A_SA<1..0> 26 MEM_A_DQ<63..0> 11 26 91 27 11 MEM_A_DQS_N<7..0> 27 26 11 MEM_A_DQS_P<7..0> 9127 26
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
FB_A0_DQ<31..0> 75 76 97 FB_A0_A<8..0> 75 76 97 FB_A0_ABI_L 75 76 97 FB_A0_EDC<3..0> 75 76 97 FB_A0_WCLK_N<1..0> 75 FB_A0_WCLK_P<1..0> 97 76 75 76 FB_A0_DBI_L<3..0> 97 FB_A1_DQ<31..0> 75 76 97 FB_A1_A<8..0> 75 76 97 FB_A1_ABI_L 75 76 97 FB_A1_EDC<3..0> 75 76 97 75 FB_A1_WCLK_N<1..0> 97 76 FB_A1_WCLK_P<1..0> 75 76 97 FB_A1_DBI_L<3..0> 75 76 97
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
MEM_A_A<15..0> MEM_A_CAS_L MEM_A_RAS_L MEM_A_WE_L MEM_B_A<15..0> MEM_B_CAS_L MEM_B_RAS_L MEM_B_WE_L
I1524 I1523 I1522 I1521 I1525 I1526 I1527 I1528 I1531 I1532
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
6
6
MEM_B_BA<2..0> 11 28 91 MEM_B_CKE<1..0> 11 28 91 MEM_B_CLK_N<1..0> 91 11 28 MEM_B_CLK_P<1..0> 91 11 28 MEM_B_CS_L<1..0> 11 28 91 MEM_B_ODT<1..0> 11 28 91 MEM_B_SA<1..0> 28 MEM_B_DQ<63..0> 11 27 28 91 MEM_B_DQS_N<7..0> 11 27 28 91 MEM_B_DQS_P<7..0> 11 27 28 91
NC_LPC_DREQ0_L
I1546 I1547 I1548 I1549 I1550 I1551 I1559 I1552 I1554 I1553 I1555 I1557 I1556 I1561
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
FB_B0_DQ<31..0> 75 77 97 FB_B0_A<8..0> 75 77 97 FB_B0_ABI_L 75 77 97 FB_B0_EDC<3..0> 97 75 77 97 77 FB_B0_WCLK_N<1..0> 75 FB_B0_WCLK_P<1..0> 97 75 77 75 77 FB_B0_DBI_L<3..0> 97 FB_B1_DQ<31..0> 75 77 97 FB_B1_A<8..0> 75 77 97 FB_B1_ABI_L 75 77 97 FB_B1_EDC<3..0> 97 75 77 97 77 FB_B1_WCLK_N<1..0> 75 75 FB_B1_WCLK_P<1..0> 97 77 75 77 FB_B1_DBI_L<3..0> 97
11 26 91 11 26 91 11 26 91 11 26 91 11 28 91 11 28 91 11 28 91 11 28 91
SYNC_MASTER=K18_MLB NC_LPC_DREQ0_L
MAKE_BASE=TRUE
SYNC_DATE=04/27/2010
Functional / ICT Test
6 16
DRAWING NUMBER
Apple Inc. 16 6 16 6 16 6
16 6 16 6
4
NC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L NC_PCIE_CLK100M_PEBN NC_PCIE_CLK100M_PEBP
NC_CLINK_CLK 6 16 TRUE MAKE_BASE=TRUE NC_CLINK_DATA 6 16 TRUE MAKE_BASE=TRUE NC_CLINK_RESET_L 6 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PEBN TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PEBP TRUE MAKE_BASE=TRUE
3
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
16
6 16
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
SIZE
D REVISION
R
6 16
B
91
PAGE TITLE 16 6
C
6 17
NC_GPU_BUFRST_L TP_GPU_GSTATE<0> NC_GPU_GSTATE<1> TP_GPU_MIOA_D<9..0> NC_GPU_MIOA_DE
6
I1513
D
NC_FW643_AVREG 6 38 TRUE MAKE_BASE=TRUE NC_FW643_TDI TRUE 6 38 MAKE_BASE=TRUE NC_DP_IG_C_HPD TRUE MAKE_BASE=TRUE NC_DP_IG_C_CTRL_CLK TRUE MAKE_BASE=TRUE NC_DP_IG_C_CTRL_DATA TRUE MAKE_BASE=TRUE NC_DP_IG_C_MLP<3..0> TRUE MAKE_BASE=TRUE NC_DP_IG_C_MLN<3..0> TRUE MAKE_BASE=TRUE NC_DP_IG_C_AUXP TRUE MAKE_BASE=TRUE NC_DP_IG_C_AUXN TRUE MAKE_BASE=TRUE NC_DP_IG_D_HPD TRUE MAKE_BASE=TRUE NC_DP_IG_D_CTRL_CLK TRUE MAKE_BASE=TRUE NC_DP_IG_D_CTRL_DATA TRUE MAKE_BASE=TRUE NC_DP_IG_D_MLP<3..0> TRUE MAKE_BASE=TRUE NC_DP_IG_D_MLN<3..0> TRUE MAKE_BASE=TRUE NC_DP_IG_D_AUXP TRUE MAKE_BASE=TRUE NC_DP_IG_D_AUXN TRUE MAKE_BASE=TRUE
78 95
DP_T29SNK1_ML_C_P<3..0> 33 78 95 DP_T29SNK1_ML_C_N<3..0> 33 78 95 DP_T29SNK1_ML_P<3..0> 33 95 18 DP_T29SNK1_ML_N<3..0> 33 95 6 TP_DP_T29SRC_AUXCH_CN 33 6 TP_DP_T29SRC_AUXCH_CP 33 16 6 TP_DP_T29SRC_ML_CP<3..0> 33 16 6 TP_DP_T29SRC_ML_CN<3..0> 33 19 6 DP_SDRVA_ML_C_P<0> 84 95 19 6 DP_SDRVA_ML_C_N<0> 84 95 19 6 DP_SDRVA_ML_C_P<2> 84 95 19 6 DP_SDRVA_ML_C_N<2> 84 95 52 6 DP_SDRVA_ML_P<0> 84 95 6 DP_SDRVA_ML_N<0> 84 95 6 DP_SDRVA_ML_P<2> 84 95 6 DP_SDRVA_ML_N<2> 84 95 6 TP_T29_PCIE_RESET0_L 33 16 6 TP_T29_PCIE_RESET1_L 33 16 6 TP_T29_PCIE_RESET2_L 33 16 6 TP_T29_PCIE_RESET3_L 33 16 6 T29DPA_D2R1_AUXCH_N 85 95 16 6 T29DPA_D2R1_AUXCH_P 85 95 16 6 T29_D2R1_BIAS 16 6
TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
I767
NC_DP_IG_D_HPD NC_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_DATA TP_DP_IG_D_MLP<3..0> TP_DP_IG_D_MLN<3..0> NC_DP_IG_D_AUXP NC_DP_IG_D_AUXN
17 6
6 18
NCNO_TEST NO_TESTs
95
16 6
38
NC_HDA_SDIN1 NC_HDA_SDIN2 NC_HDA_SDIN3
I765
6 17
17 6 46
I764
NC_DP_IG_C_HPD NC_DP_IG_C_CTRL_CLK NC_DP_IG_C_CTRL_DATA TP_DP_IG_C_MLP<3..0> TP_DP_IG_C_MLN<3..0> NC_DP_IG_C_AUXP NC_DP_IG_C_AUXN
17 6 6 17
NC_CRT_IG_DDC_CLK NC_CRT_IG_DDC_DATA
42 44 45 46 19 46 55
6 17
I763
NC_SMC_FAN_3_TACH 44 45 NC_SMC_FAN_3_CTL 44 45 NC_SMC_FAN_2_TACH 44 45 NC_SMC_FAN_2_CTL 44 45 NC_FW2_TPBP 38 40 NC_FW2_TPBN 38 40 NC_FW2_TPBIAS 38 40 NC_FW2_TPAP 38 40 NC_FW2_TPAN 38 40 NC_FW0_TPBP 38 40 94 NC_FW0_TPBN 38 40 94 NC_FW0_TPAP 38 40 94 NC_ESTARLDO_EN NC_ALS_GAIN
NC_FW643_AVREG NC_FW643_TDI
38 6
NO_TEST
42 44 45 46
16 6
I1592
A
TP_CPU_RSVD<58..45>
16 6
62 63
I762
TP_CPU_RSVD<65..62>
NC NO_TESTs
NO_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
I761
16 44 46
NC NO_TESTs
62
41 92
TRUE
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
1
I1297
NO_TEST
TP_CPU_RSVD<27..26>
NO_TEST
J6950 (MAIN BATT CONN) PPVBAT_G3H_CONN I1136 TRUE SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA TRUE I1135 I1137 TRUE NC_SMC_BS_ALRT_L
41 92
SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L SPI_ALT_MISO SPI_ALT_MOSI SYS_LED_ANODE_R
CPU NO_TESTs
17 44 46
GND
I1134 TRUE
41 92
I1485
17 29 44 TRUE PM_SLP_S3_L I1487 66 72 7 26 TRUE PP0V75_S0_DDRVTT 28 I602 I1489 29 TRUE PP18V5_S3 I603 I1491 44 67 69 17 20 22 TRUE PP1V05_S0 7 9 10 12 I1490 I604 13 14 16 23 35 39 PP1V05_S0GPU TRUE 72 101 I605 I1492 TRUE PP1V05_S5 I1563 I607 TRUE PP1V0_FW_FWPHY 7 38 39 I1562 I606 TRUE PP1V2_ENET 7 36 70 I1564 I610 PP1V2_S0 TRUE 7 70 87 I1566 I612 TRUE PP1V5_S3 7 26 28 29 I1565 I611 66 71 TRUE PP1V5_S3RS0 98 I1567 I613 TRUE PP1V8R1V55_S0GPU_ISNS I1569 I600 PP1V8R1V55_S0GPU_ISNS_R TRUE I625 I1568 TRUE PP1V8_GPUIFPX 7 71 100 I624 I1570 71 87 TRUE PP1V8_S0 7 14 17 20 I1571 I623 22 25 70 89 98 PP3V3_ENET TRUE I620 I1572 79 82 83 53 56 60 45 47 48 TRUE PP3V3_FW_FWPHY I621 I1573 32 35 36 20 22 23 TRUE PP3V3_S0 6 7 12 16 I1574 I618 17 18 19 25 26 28 PP3V3_S0GPU TRUE 39 40 41 I617 I1575 49 50 51 61 71 72 TRUE PP3V3_S3 I1576 I615 84 87 88 TRUE PP3V3_S5 I616 I1577 44 TRUE PP3V3_S5_AVREF_SMC I614 46 47 45 I1578 25 42 44 PP3V42_G3H TRUE 6 45 I627 72786 8852 I1579 53 64 6762 TRUE PP5V_S0 6 7 8 22 63 I626 41 46 5172 I1580 68 69 71 TRUE PP5V_S3 101 I639 I1581 TRUE PP5V_S5 7 53 65 71 I1583 I638 63 88 PPBUS_G3H TRUE 7 8 35 39 I637 I1582 48 49 62 TRUE PPDCIN_G3H 7 48 62 63 I1584 I636 TRUE PPVCORE_GPU 7 48 74 81 I1585 I709 7 12 14 48 I1587 I714 TRUE PPVCORE_S0_CPU 68 101 I1156 TRUE PPVCORE_S0_GFX I1588 7 39 40 I1160 TRUE PPVP_FW I1589 7 30 66 I1586 I1161 TRUE PPVTTDDR_S3
5 TPs
GND
TRUE
J5800 (IPD FLEX CONN) TRUE PP18V5_S4 53 TRUE Z2_HOST_INTN 52 53 Z2_MOSI TRUE 52 53 52 53 TRUE Z2_CS_L TRUE Z2_DEBUG3 52 53 TRUE Z2_MISO 52 53 53 TRUE Z2_BOOST_EN TRUE Z2_SCLK 52 53 TRUE Z2_CLKIN 52 53 TRUE Z2_KEY_ACT_L 52 53 52 53 TRUE Z2_RESET TRUE PSOC_F_CS_L 52 53 TRUE PICKB_L 52 53 PSOC_MISO TRUE 52 53 52 53 TRUE PSOC_MOSI 52 53 TRUE PSOC_SCLK TRUE SMBUS_SMC_A_S3_SCL 6 31 TRUE SMBUS_SMC_A_S3_SDA 6 31
J6900 (DC POWER CONN) I1131 TRUE ADAPTER_SENSE I1132 TRUE PP18V5_DCIN_FUSE
41
I1486
I1488
I1094
92
I1484
POWER RAILS
62
I640
I1093
3 TPs
SYS_DETECT_L
FUNC_TEST
I1092
J4500 (SATA ODD CONN) TRUE PP5V_SW_ODD 41 41 44 TRUE SMC_ODD_DETECT SATA_ODD_D2R_C_P TRUE 41 TRUE SATA_ODD_D2R_C_N 41 TRUE SATA_ODD_R2D_P 41 92 TRUE SATA_ODD_R2D_N 41 92 TRUE SATA_ODD_D2R_UF_P 41 92 TRUE SATA_ODD_D2R_UF_N 41
TRUE
SMC_TX_L
2
17 6
41
J6950 (BAT CONN) I1510
SMC_TCK SMC_TDI SMC_TDO SMC_TMS SMC_TRST_L
NO_TEST=TRUE
I1483
PP3V3_SW_LCD 82 84 87 88 89 98 48 49 50 51 53 56 60 61 71 72 PP3V3_S0 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 82 83 PPVOUT_S0_LCDBKLT 7982 8 2 TP needed 88 100 LVDS_DDC_CLK 82 83 LVDS_DDC_DATA 82 83 LVDS_CONN_A_DATA_P<0> 82 83 97 LVDS_CONN_A_DATA_N<0> 82 83 97 LVDS_CONN_A_DATA_P<1> 82 83 97 LVDS_CONN_A_DATA_N<1> 82 83 97 LVDS_CONN_A_DATA_P<2> 82 83 97 LVDS_CONN_A_DATA_N<2> 82 83 97 LVDS_CONN_A_CLK_F_P 82 97 LVDS_CONN_A_CLK_F_N 82 97 LVDS_CONN_B_DATA_P<0> 82 83 97 LVDS_CONN_B_DATA_N<0> 82 83 97 LVDS_CONN_B_DATA_P<1> 82 83 97 LVDS_CONN_B_DATA_N<1> 82 83 97 LVDS_CONN_B_DATA_P<2> 82 83 97 LVDS_CONN_B_DATA_N<2> 82 83 97 LVDS_CONN_B_CLK_F_P 82 97 LVDS_CONN_B_CLK_F_N 82 97 LED_RETURN_1 82 88 LED_RETURN_2 82 88 LED_RETURN_3 82 88 LED_RETURN_4 82 88 LED_RETURN_5 82 88 LED_RETURN_6 82 88 GND 4 TPs
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
LPC_PWRDWN_L LPC_SERIRQ PM_CLKRUN_L PM_SYSRST_L SMC_MD1 SMC_NMI SMC_ONOFF_L SMC_RESET_L SMC_RX_L
I730
I1482
I995
3
ICT Test Points
FUNC_TEST I720 TRUE BKLT_EN I722 TRUE TP_ISSP_SCLK_P1_1 8 52 I724 TRUE TP_ISSP_SDATA_P1_0 8 52 87 88 I723 TRUE LCD_BKLT_PWM 19 46 I725 TRUE LPCPLUS_GPIO I726 TRUE LPCPLUS_RESET_L 25 46 87 93 LPC_AD<0..3> 16 44 46 87 93 I727 TRUE LPC_CLK33M_LPCPLUS 25 46 93 I729 TRUE LPC_FRAME_L 16 44 46 87 93 I728 TRUE
PAGE
7 OF 132 SHEET
6 OF 101
1
A
8 63 62 49 8 7 6 48 39 35 88
PPBUS_G3H
G3H Rails
7
6
PPBUS_G3H
98 89 85 82 72 22 20 19 17 7 6 71 70 65 55 45 39 29 25 24 23
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE
PPBUS_G3H PPBUS_G3H PPBUS_G3H
PPVIN_S5_HS_COMPUTING_ISNS
6 7 8 35 39 48 49 62 63 88 6 7 8 35 39 48 49 62 63 88 6 7 8 35 39 48 49 62 63 88 6 7 8 35 39 48 49 62 63 88 6 7 8 35 39 48 49 62 63 88
PPVIN_S5_HS_COMPUTING_ISNS
7 49 64 66 67 68 69
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE
D
PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS 49 7 86 81
PPVIN_S5_HS_GPU_ISNS
PPVIN_S5_HS_GPU_ISNS MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm
49 7 65
63 48 6 7 62
63 52 46 44 25 6 7 42 45 47 62 72
PPVIN_S5_HS_OTHER_ISNS
7 49 64 66 67 68 69 7 49 64 66 67 68 69 7 49 64 66 67 68 69 7 49 64 66 67 68 69
7 49 81 86
7 49 81 86 7 49 81 86
PPVIN_S5_HS_OTHER_ISNS MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm
7 49 65
VOLTAGE=12.8V MAKE_BASE=TRUE
PPVIN_S5_HS_OTHER_ISNS 49 48 PPDCIN_G3H
PPDCIN_G3H
7 49 64 66 67 68 69
VOLTAGE=12.8V MAKE_BASE=TRUE
PPVIN_S5_HS_GPU_ISNS PPVIN_S5_HS_GPU_ISNS
87 72 71 54 53 7 49 65 18 8 7 6 47 32 31 30 29 25 24 19 6 7 48 62 63
PP3V3_S3
PP3V42_G3H
6 7 48 62 63
PP3V42_G3H MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM
C For PCH RTC Power 17 16 7 25 20
PPVRTC_G3H
PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H
6 7 25 42 44 45 46 47 52 62 63 72 6 7 25 42 44 45 46 47 52 62 63 72 6 7 25 42 44 45 46 47 52 62 63 72 6 7 25 42 44 45 46 47 52 62 63 72 6 7 25 42 44 45 46 47 52 62 63 72 6 7 25 42 44 45 46 47 52 62 63 72 6 7 25 42 44 72 6 7 25 42 44 72 6 7 25 42 44 72 6 7 25 42 44 72 98 89 88 87 84 83 51 50 49 48 23 22 20 19 18 17 16 12 7 45 41 40 39 36 35 32 28 26 79 72 71 61 60 56
PPVRTC_G3H
MIN_LINE_WIDTH=0.3 MM VOLTAGE=3.42V MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
5V Rails 65 53 7 6 71
VOLTAGE=3.42V MAKE_BASE=TRUE
PP5V_S5
PPVRTC_G3H
PP5V_SUS
PP5V_S0
71 53 52 45 7
PP3V3_S4
PP5V_SUS
7 22 71
VOLTAGE=5V MAKE_BASE=TRUE 7 22 71
PP5V_S3
6 7 29 31 41 42 43 45 65 66 71 81 100
VOLTAGE=5V MAKE_BASE=TRUE 6 7 29 31 41 42 43 45 65 66 71 81 100 6 7 29 31 41 42 43 45 65 66 71 81 100 6 7 29 31 41 42 43 45 65 66 71 81 100 6 7 29 31 41 42 43 45 65 66 71 81 100 6 7 29 31 41 42 43 45 65 66 71 81 100 6 7 29 31 41 42 43 45 65 66 71 81 100 6 7 29 31 41 42 43 45 65 66 71 81 100 6 7 29 31 41 42 43 45 65 66 71 81 100 6 7 29 31 41 42 43 45 65 66 71 81 100 6 7 29 31 41 42 43 45 65 66 71 81 100 6 7 29 31 41 42 43 45 65 66 71 81 100 6 7 29 31 41 42 43 45 65 66 71 81 100
PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0
6 7 8 22 41 46 51 53 64 67 68 69 71 72 86 88 101 6 7 8 22 41 46 51 53 64 67 68 69 71 72 86 88 101 6 7 8 22 41 46 51 53 64 67 68 69 71 72 86 88 101 6 7 8 22 41 46 51 53 64 67 68 69 71 72 86 88 101 6 7 8 22 41 46 51 53 64 67 68 69 71 72 86 88 101 6 7 8 22 41 46 51 53 64 67 68 69 71 72 86 88 101 6 7 8 22 41 46 51 53 64 67 68 69 71 72 86 88 101 6 7 8 22 41 46 51 53 64 67 68 69 71 72 86 88 101 6 7 8 22 41 46 51 53 64 67 68 69 71 72 86 88 101 6 7 8 22 41 46 51 53 64 67 68 69 71 72 86 88 101 6 7 8 22 41 46 51 53 64 67 68 69 71 72 86 88 101 6 7 8 22 41 46 51 53 64 67 68 69 71 72 86 88 101 6 7 8 22 41 46 51 53 64 67 68 69 71 72 86 88 101 6 7 8 22 41 46 51 53 64 67 68 69 71 72 86 88 101
PP3V3_S4
7 45 52 53 71
VOLTAGE=3.3V MAKE_BASE=TRUE
PP3V3_S4 PP3V3_S4 20 19 18 17 16 7 72 71 70 45 22
PP3V3_SUS
7 45 52 53 71 7 45 52 53 71
PP3V3_SUS MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
6 7 8 22 41 46 51 53 64 67 68 69 71 72 86 101
88 VOLTAGE=5V MAKE_BASE=TRUE
MAKE_BASE=TRUE VOLTAGE=3.3V
PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS
20 22 45 70 71 72 7 34 33 25 19 16 7 16 17 18 19 87 35
T29 Rails PP3V3_T29
6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98 6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98 6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98 6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98 6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98
7 16 17 18 19 20 22 45 70 71 72 72 7 16 17 18 19 20 22 45 70 71 35 34 7 7 16 17 18 19 20 22 45 70 71 72
PP1V05_T29
72 7 16 17 18 19 20 22 45 70 71 85 35 8 7
PP15V_T29
6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98
VOLTAGE=3.3V MAKE_BASE=TRUE
6
PP1V5_S3RS0_CPUDDR
6 7 14 17 20 22 25 70 71 87 6 7 14 17 20 22 25 70 71 87 6 7 14 17 20 22 25 70 71 87
6 7 8 18 19 24 25 29 30 31 32 47 48 49 53 54 71 72 87
PP1V8_S0_CPU_VCCPLL_R
7 12 14
100 71 7 6
VOLTAGE=1.8V MAKE_BASE=TRUE
18 49 18 49
19 53 19 53
24 54 24 54
25 71 25 71
29 72 29 72
6 7 26 28 29 66 71
PP1V5_S3RS0_CPUDDR
7 10 13 15 29 71 72
7 10 13 15 29 71 72 7 10 13 15 29 71 72
7 16 20 22 25 41 56 70
PP0V75_S0_DDRVTT
66 29 28 26 7 6 7 8 18 19 24 25 29 30 6 31 32 47 48 49 53 54 71 72 87
PP0V75_S0_DDRVTT PP0V75_S0_DDRVTT PP0V75_S0_DDRVTT PP1V2_S0
PP1V05_SUS
PP1V05_SUS
7 23 70
48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98 48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98 48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98 6 26 28 177 12 16 17 18 19 20 22 23 25 12 32 35 36 39 40 41 45 47 48 6 49 50 51 53 56 60 61 71 72 7 79 82 83 84 87 88 89 98 16 18 19 20 22 23 25 26 28 32 98 35 36 39 40 41 45 47 48 49 89 50 51 53 56 60 61 71 72 87 88 79 82 83 84 87 88 89 98 83 84 48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98 79 82 48 49 50 51 53 56 60 61 71 72 26 28 32 35 36 39 40 41 45 47 6 7 12 16 17 18 19 20 22 23 25 48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98 48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98 6 26 28 7 12 16 17 18 19 20 22 23 25 32 35 36 39 40 41 45 47 48 49 50 51 53 56 60 61 71 72 8279 82 83 84 87 88 89 98 48 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 49 50 51 53 56 60 61 71 72 79 836 84 87 88 89 98 7 47 48 49 50 1212 16 17 18 19 20 22 23 25 6 26 28 32 35 36 39 40 41 45 7 51 53 56 60 61 71 72 79 16 82 83 84 87 88 89 98 17 35 18 19 20 22 23 25 26 28 32 36 39 40 41 45 47 48 49 88 7 50 51 53 56 60 61 71 72 83 100 79 82 83 84 87 88 89 98 48 49 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 50 51 53 56 60 61 71 72 79 82 84 87 88 89 98
7 16 19 25 33 34 35 87
7 16 19 25 33 34 35 87
PP1V05_T29 PP15V_T29
5
PP1V2_ENET
7 8 35 85
VOLTAGE=15V MAKE_BASE=TRUE
10 23 10 72
7 74 78 80 100 7 86 100
7 86 100 7 74 75 76 77 100
7 74 75 76 77 100 7 74 75 76 77 100 7 74 75 76 77 100 7 74 75 76 77 100
C
7 86 100
7 86 100
7 73 74 78 80 100
7 73 74 78 80 100 7 73 74 78 80 100 7 73 74 78 80 100 7 73 74 78 80 100 7 73 74 78 80 100 7 73 74 78 80 100 7 73 74 78 80 100 6 7 48 74 81
VOLTAGE=1.0V MAKE_BASE=TRUE 6 7 48 74 81
6 7 9 23 35 6 7 9 20 22 6 7 9 67 69
10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101 39 44 67 69 72 101 10 12 13 14 16 17 68 48 15 13 12 7 10 12 13 14 16 17 20 22 23 35 39 44 72 101
PPVCORE_S0_CPU
12 13 14 16 17 35 39 44 67 69 72 101 12 13 14 16 17 20 22 23 35 39 44 101
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM
10 72 10 23 10 67 10 23 10 72
12 13 14 16 17 101 39 44 67 69 12 13 14 16 17 35 14 12 10 7 12 13 14 16 17 67 69 69 72 101 12 13 14 16 17 35 64 15 12 7 12 13 14 16 17 101
6 7 9 67 69 6 7 9 67 69 6 7 9 67 69
10 72 10 72 10 72
6 7 9 20 22 6 7 9 67 69 6 7 9 67 69
10 23 10 72 10 72
12 13 101 12 13 101 12 13 101 72 12 13 35 39 12 13 101 12 13 101
6 7 9 67 69 6 7 9 67 69 6 7 9 20 22
10 72 10 72 10 23
6 7 12 14 48 68 101
PPVCORE_S0_AXG MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
7 12 13 15 48 68
MAKE_BASE=TRUE VOLTAGE=1.05V
PPVCORE_S0_AXG
PP1V5_S3_CPU_VCCDQ
6 7 9 67 69 6 7 9 20 22 6 7 9 39 44 6 7 9 20 22 6 7 9 67 69
6 7 12 14 48 68 101
MAKE_BASE=TRUE VOLTAGE=1.25V
PPVCORE_S0_CPU
PPVCORE_S0_AXG
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
20 22 23 35 39 44 72 101
PP1V05_S0_CPU_VCCPQE
7 12 15
MAKE_BASE=TRUE VOLTAGE=1.5V
PP1V05_S0_CPU_VCCPQE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
20 22 23 35 39 44 72 101
7 10 12 14
VOLTAGE=1.05V MAKE_BASE=TRUE
PPVCCSA_S0_REG
PPVCCSA_S0_REG
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
20 22 23 35 39 44
14 16 17 20 22 23 35 39 44
B
7 12 13 15 48 68
PP1V5_S3_CPU_VCCDQ
6 7 9 10 12 13 15 12 7 14 16 17 20 22 23 35 39 44 67 69 72 101
7 12 15 64
VOLTAGE=0.9V MAKE_BASE=TRUE
PPVCCSA_S0_REG
7 12 15 64
14 16 17 20 22 23 35 39 44
FireWire Rails
14 16 17 20 22 23 35 39 44 101 14 16 17 44 67 69 14 16 17 20 22 23 35 39 44
PPVP_FW
PPVP_FW
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM
6 7 39 40
VOLTAGE=12.8V MAKE_BASE=TRUE
14 16 17 20 22 23 35 39 44
12 13 14 16 17 101 12 13 14 16 17 101 35 39 44 67 12 13 14 16 17 40 39 38 7 6 6 7 9 10 12 13 14 16 17 67 69 72 101 6 7 9 10 12 13 14 16 17 67 69 72 101
PPVP_FW PPVP_FW
20 22 23 35 39 44 20 22 23 35 39 44
6 7 39 40 6 7 39 40
69 72 101
PP3V3_FW_FWPHY
PP3V3_FW_FWPHY
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM
20 22 23 35 39 44 20 22 23 35 39 44
6 7 9 10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101 6 7 9 10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101 101 6 7 9 10 12 39 38 7 6 13 14 16 17 20 22 23 35 39 44 67 69 72
PP1V0_FW_FWPHY
6 7 38 39 40
VOLTAGE=3.3V MAKE_BASE=TRUE
PP3V3_FW_FWPHY
6 7 38 39 40
PP1V0_FW_FWPHY
6 7 38 39
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V MAKE_BASE=TRUE
PP1V0_FW_FWPHY
6 7 38 39
7 88 100
MAKE_BASE=TRUE VOLTAGE=12.8V
SYNC_MASTER=K18_MLB
SYNC_DATE=04/27/2010
PAGE TITLE
PP3V3_ENET
Power Aliases
6 7 25 36 70 72
DRAWING NUMBER
Apple Inc.
6 7 25 36 70 72 6 7 25 36 70 72 6 7 25 36 70 72
PP1V2_ENET
6 7 36 70
PP1V2_ENET
6 7 36 70
7 8 35 85
4
7 74 78 80 100
PPVCORE_GPU
6 7 9 10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101 6 7 9 10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.2V MAKE_BASE=TRUE
7 34 35
7 74 78 80 100
PPVCORE_GPU
PPVCORE_S0_CPU
6 7 9 20 22 6 7 9 67 69
7 34 35 70 36 7 6
7 74 78 80 100
Chipset "VCore" Rails
PP3V3_ENET PP3V3_ENET PP3V3_ENET
7 16 19 25 33 34 35 87
VOLTAGE=1.05V MAKE_BASE=TRUE
PPVCORE_GPU
6 7 9 10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE
7 16 19 25 33 34 35 87
7 74 78 80 100
PP1V0_S0GPU_ISNS PP1V0_S0GPU_ISNS PP1V0_S0GPU_ISNS PP1V0_S0GPU_ISNS PP1V0_S0GPU_ISNS PP1V0_S0GPU_ISNS PP1V0_S0GPU_ISNS
ENET Rails
PP3V3_ENET
7 74 78 80 100
VOLTAGE=1.0V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
PPBUS_SW_BKL MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm
7 74 78 80 100
PP1V0_S0GPU_ISNS
Backlight Rails PPBUS_SW_BKL
7 74 78 80 100
PP1V0_S0GPU PP1V0_S0GPU_ISNS
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
7 23 70
PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0
79 82 83 84 87 88 89 98 48 49 50 51 53 56 60 61 71 72 26 28 32 35 36 39 40 41 45 47 6 7 12 16 17 18 19 20 22 23 25 48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98
PP3V3_T29 PP3V3_T29 PP3V3_T29 PP1V05_T29
6 7 70 87
PP1V05_S0
7 74 78 80 100
6 7 26 28 29 66
81 74 48 7 6
48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98
36 25 7 6 72 70
6 7 26 28 29 66
PP1V2_S0
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE
7 74 78 80 100
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V MAKE_BASE=TRUE
6 7 70 87
PP1V05_SUS
PP1V05_S0
7 16 19 25 33 34 35 87
PP1V0_S0GPU
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE
48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98 6 26 28 177 12 16 17 18 19 20 22 23 25 12 32 35 36 39 40 41 45 47 48 6 49 50 51 53 56 60 61 71 72 7 79 82 83 84 87 88 89 98 16 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 48 49 50 51 53 56 60 61 71 72 79 82 83 84 87 88 89 98 48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98 6 26 28 7 12 16 17 18 19 20 22 23 25 32 35 36 39 40 41 45 47 48 49 50 51 53 56 60 61 71 72 79 82 83 84 87 88 89 98
VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
100 86 7
6 7 26 28 29 66
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.2V MAKE_BASE=TRUE
48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98
7 74 78 80 100
PP1V5_S0GPU_ISNS PP1V5_S0GPU_ISNS PP1V5_S0GPU_ISNS PP1V5_S0GPU_ISNS PP1V0_S0GPU
6 7 26 28 29 66
100 80 78 74 73 7
PP1V2_S0
PP3V3_T29
PP0V75_S0_DDRVTT
7 74 78 80 100
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE
6 7 30 66
MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V MAKE_BASE=TRUE
48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98 83 84 87 88 89 98 48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 79 82 83 84 87 88 89 98 48 49 50 51 53 56 60 61 71 72 26 28 32 35 36 39 40 41 45 47 6 7 12 16 17 18 19 20 22 23 25 47 48 49 50 51 53 56 60 61 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 71 72 79 82 83 84 87 88 89 98
70 23 7
PP1V5_S0GPU_ISNS
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE
6 7 8 18 19 24 25 29 30 31 32 47 48 49 53 54 71 72 87
6 7 71 100 7 74 78 80 100
PP1V5_GPU_REG PP1V5_S0GPU_ISNS
7 16 20 22 25 41 56 70
PPVTTDDR_S3
D
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE
7 16 20 22 25 41 56 70
100 77 76 75 74 7
6 7 8 18 19 24 25 29 30 31 32 47 48 49 53 54 71 72 87
PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0
PP1V5_GPU_REG
7 16 20 22 25 41 56 70
6 7 8 18 19 24 25 29 30 31 32 47 48 49 53 54 71 72 87
6 7 71 100
PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V5_GPU_REG
6 7 26 28 29 66 71
100 86 7
PPVTTDDR_S3
6 7 71 74 78 79 81 83
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.15 MM VOLTAGE=1.8V MAKE_BASE=TRUE
6 7 26 28 29 66 71
PP1V5_S0 PP1V5_S0 PP1V5_S0
6 7 8 18 19 24 25 29 30 31 32 47 48 49 53 54 71 72 87 66 30 7 6
6 7 71 74 78 79 81 83 6 7 71 74 78 79 81 83
PP1V8_GPUIFPX PP1V8_S0GPU_ISNS
PP1V8_S0GPU_ISNS
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE
30 31 32 87 30 31 32 87
6 7 71 74 78 79 81 83
PP1V8_GPUIFPX
6 7 26 28 29 66 71
PP1V5_S0
6 7 8 18 19 24 25 29 30 31 32 47 48 49 53 54 71 72 87
6 7 71 74 78 79 81 83
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.15 MM VOLTAGE=1.8V MAKE_BASE=TRUE
100 80 78 74 7
6 7 8 18 19 24 25 29 30 31 32 47 48 49 53 54 71 72 87
6 7 8 47 48 6 7 8 47 48
PP1V8_GPUIFPX
6 7 26 28 29 66 71
6 7 26 28 29 66 71
PP1V5_S3RS0_CPUDDR PP1V5_S3RS0_CPUDDR PP1V5_S0
6 7 71 74 78 79 81 83
6 7 14 17 20 22 25 70 71 87
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE
6 7 8 18 19 24 25 29 30 31 32 47 48 49 53 54 71 72 87 49 53 6 7 8 18 19 24 25 29 30 31 32 47 48 70 56 41 25 22 20 16 7 548 71 726 87 7 48 49 53 54 71 72 87 18 19 24 25 29 30 31 32 47
PP15V_T29
7
6 7 14 17 20 22 25 70 71 87
PP1V5_S3 PP1V5_S3 PP1V5_S3 PP1V5_S3 PP1V5_S3
6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98
6 7 71 74 78 79 81 83
PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU
6 7 14 17 20 22 25 70 71 87
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE
6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98
PP3V3_S0GPU MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V MAKE_BASE=TRUE
PP1V5_S3
6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98
"GPU" Rails
PP3V3_S0GPU
6 7 14 17 20 22 25 70 71 87
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM
8
PP1V5_S3
6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM
7 16 17 18 19 20 22 45 70 71 72
PP1V8_S0_CPU_VCCPLL_R
6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98 6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98
PP3V3_T29 7 16 17 18 19 20 22 45 70 71 72
6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98 6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98
6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98 6 45 55 65 70 71 72 82 85 89 7 17 19 20 22 23 24 25 29 39 98
1
6 7 14 17 20 22 25 70 71 87 83 81 79 78 74 71 7 6
PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0
6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98
6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98
2
PP1V8_S0 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE
6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98
MIN_LINE_WIDTH=0.4 MM
7 16 17 18 19 20 22 45 70 71 72
PP1V8_S0 2A max supply
6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98
MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V MIN_NECK_WIDTH=0.075 mmMAKE_BASE=TRUE
6 7 53 65 71
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
A
PP3V3_S0
6 7 53 65 71
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM
3.3V Rails
82 47 6 25 53
6 7 53 65 71
PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3
86 72 71 69 51 46 41 22 8 7 6 68 67 64 53 101 88
45 46 47 52 62 63
6 7 53 65 71
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm
B
45 46 47 52 62 63
VOLTAGE=5V MAKE_BASE=TRUE
PP5V_SUS
PP5V_S3
45 46 47 52 62 63
6 7 53 65 71
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
81 71 66 65 31 29 7 6 45 43 42 41 100
45 46 47 52 62 63
7 16 17 20 25
PP5V_S5 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 71 22 7
6 7 25 42 44 45 46 47 52 62 63 72
3 1.8V/1.5V/1.2V/1.05V Rails
6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98
PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S0
6 7 48 62 63
6
98 6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.6 MM VOLTAGE=18.5V MIN_NECK_WIDTH=0.25 MMMAKE_BASE=TRUE
PPDCIN_G3H PPDCIN_G3H
4 6 7 17 19 20 22 23 24 25 29 39 98
VOLTAGE=3.3V 45 55 65 70 71 72 82 85 89 MAKE_BASE=TRUE 87 71 70 25 22 20 17 14 7
PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S3
6 7 8 35 39 48 49 62 63 88
PPBUS_G3H PPBUS_G3H PPBUS_G3H
5 PP3V3_S5 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
6 7 8 35 39 48 49 62 63 88
PPBUS_G3H
69 64 49 7 68 67 66
PP3V3_S5
3
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
SIZE
D REVISION
BRANCH
PAGE
8 OF 132 SHEET
7 OF 101
1
A
8
7
6
ZT0984 Thermal Module Holes ZT0981 STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH 1
5
Fan Holes ZT0930
1
4
3 CPU signals CPU_VID<0..6>
90
1
ZT0985
ZT0988
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
T29 / GMUX JTAG Signals
1
1
ZT0980 STDOFF-4.5OD.98H-1.1-3.48-TH 1
ZT0986
ZT0989
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0991
33 8
T29_LSEO_LSOE3
33 8
T29_LSEO_LSOE2
Left Speaker Holes
T29_LSEO_LSOE3
T29_LSEO_LSOE3
9 8 33
T29_LSEO_LSOE2
9 8 33
93 33 9
PM_ALL_GPU_PGOOD
93 33 9 8 73 81 86 87 89 93 33 9
87 8
87 73 8
ZT0935
3R2P5
93 33 9
EG_RESET_L
EG_RESET_L
MAKE_BASE=TRUE
LVDS_IG_BKL_ON
87 18 8
LVDS_IG_BKL_ON
87 18 8
LVDS_IG_PANEL_PWR
100 88 82 8 6
PPVOUT_S0_LCDBKLT
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
PEX_CLKREQ_L
87 16 8
PEG_CLKREQ_L
PCIE_T29_R2D_C_N<3..0>
SH0900
SM
POGO-2.0OD-3.5H-K86-K87
1
FW_PLUG_DET_L
39 19 8
ZT0953
90 73
PEG_R2D_C_P<7..0>
90 73
PEG_R2D_C_N<7..0>
8
1
SH0903 POGO-2.0OD-3.5H-K86-K87
POGO-2.0OD-3.5H-K86-K87
1
16 8
SM
16 8
1
SH0904
R0921 85 8
T29_A_BIAS_R
51
1
T29_A_BIAS_R2D_P0
2
B
1.4DIA-SHORT-SILVER-K99
1
T29_A_BIAS_R
1
51
T29_A_BIAS_R2D_N0
5% 1/20W MF 201
1
1
84
8
NC_PCIECLKRQ4_L_GPIO26
TP_ISSP_SCLK_P1_1
52 8 6
TP_ISSP_SDATA_P1_0
NC_T29_R2D_CP<3..2>
95
T29_R2D_C_N<3..2>
NC_T29_R2D_CN<3..2>
1.4DIA-SHORT-SILVER-K99 SM
1.4DIA-SHORT-SILVER-K99
85 8
1
T29_A_BIAS_R
1
2
T29_A_BIAS_R2D_P1
5% 1/20W MF 201
SH0917 1.4DIA-SHORT-SILVER-K99
SH0901
51
1
16 8
NC_PCH_CLKOUT_DPP
DP_EG_AUXCH_P
SH0914
51
5% 1/20W MF 201
1.4DIA-SHORT-SILVER-K99 SM
GND_CHASSIS_AUDIO_JACK
60
2
1
8
NC_FSB_CLK133M_PCHP MAKE_BASE=TRUE
0.01UF
8
10% 10V 2 X5R 201
8
SH0923 STDOFF-4.0OD1.85H-SM
1
1
8
PP5V_S0
1
MAKE_BASE=TRUE
8
8
88 87
8
NC_DPB_EG_DDC_CLK
8
NC_DPB_EG_DDC_DATA
8
PP3V3_S3
R09151 10K
DPB_EG_ML_N<3..0>
NO_TEST=TRUE
NC_DPB_EG_MLP<3..0>
T29_A_BIAS_R
8
NC_SW_GAIN_TP
8
5% 1/16W MF-LF 2 402
USB_T29A_N USB_T29A_P
DPB_EG_ML_P<3..0>
1
51
2
1
85
85 8
T29_A_BIAS_R
1
51
2
5% 1/20W MF 201
C0906 0.01UF
10% 2 10V X5R 201
1
SH0922 STDOFF-4.0OD2.23H-SM
0.01UF
10% 2 10V X5R 201
DP_A_BIAS2
DP_A_BIAS0
8 16
1
8 16 17 8 16
92 83 17 8
LCD_BKLT_EN
4.7K
5% 1/16W MF-LF 2 402
NC_DP_IG_MLP<3..0>
17 8 83 79
83 79 17 8
83 17 8
1
TP_DP_IG_B_MLP<3..0>
NC_DP_IG_MLN<3..0> DP_IG_AUX_CH_P
DP_IG_AUX_CH_P
8 17 83 92
MAKE_BASE=TRUE
DP_IG_AUX_CH_N
DP_IG_AUX_CH_N
8 17 83 92
DP_IG_DDC_CLK
8 17 79 83
DP_IG_DDC_DATA
8 17 79 83
DP_IG_HPD
8 17 83
MAKE_BASE=TRUE
DP_IG_DDC_CLK MAKE_BASE=TRUE
DP_IG_DDC_DATA MAKE_BASE=TRUE
DP_IG_HPD MAKE_BASE=TRUE
10% 10V 2 X5R 201
10% 10V 2 X5R 201
TP_DP_IG_B_MLN<3..0>
MAKE_BASE=TRUE NO_TEST=TRUE
2
88 63 62 49 48 39 35 7 6 8 56
PP5V_S0_AUDIO_AMP_L
PPBUS_G3H
1
GND MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.095 mm VOLTAGE=0V
Digital Ground
SYNC_MASTER=K18_MLB
0
2
SYNC_DATE=04/27/2010
PAGE TITLE
Signal Aliases PP15V_T29
DRAWING NUMBER
7 35 85
5% 1/8W MF-LF 805
Apple Inc. R
8
2
7
6
5
PP5V_S0_AUDIO_AMP_R
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
59
4
3
2
SIZE
D REVISION
59
XW0903 SM
1
C0908 0.01UF
C0905 0.01UF
MAKE_BASE=TRUE NO_TEST=TRUE
R0950
8 56
MAKE_BASE=TRUE
1 1
85
C0907
NOTICE OF PROPRIETARY PROPERTY:
SH0921
24 92
B T29_A_BIAS_D2R_N1
8 16
T29BST:N PP5V_S0_AUDIO
PP5V_S0_AUDIO
STDOFF-4.0OD2.23H-SM
24 92
R0927 T29_A_BIAS_D2R_P1
84
R0901
8
10K
NO_TEST=TRUE
1
NC_RT_GAIN_TP
47 48 49 53 54 6 7 8 18 19 24 25 29 30 31 32 71 72 87
R0916
1
5% 1/16W MF-LF 402 2
NO_TEST=TRUE
92 83 17 8
NC_LT_GAIN_TP
8 24
NO_TEST=TRUE
2
1
8
NO_TEST=TRUE
NC_DPB_EG_DDC_DATA MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_DPB_EG_AUX_CHN NC_DPB_EG_AUX_CHP
84
NC_FSB_CLK133M_PCHN
8 24
USB_SDCARD_N
8 78 83 97
8 16
NC_FSB_CLK133M_PCHP
USB_SDCARD_P
USB_SDCARD_N
8 16
NC_PCH_GPIO64_CLKOUTFLEX0 TRUE MAKE_BASE=TRUE NC_PCH_GPIO65_CLKOUTFLEX1 TRUE MAKE_BASE=TRUE NC_PCH_GPIO66_CLKOUTFLEX2 TRUE MAKE_BASE=TRUE NC_PCH_GPIO67_CLKOUTFLEX3 TRUE MAKE_BASE=TRUE
XW0902 SM
Heat spreader mounting boss for PCH
USB_SDCARD_P
NO_TEST=TRUE
NC_DPB_EG_DDC_CLK
8
XW0901 SM 86 72 71 69 68 67 64 53 51 46 41 22 7 6 101 88
5% 1/16W MF-LF 2 402
NO_TEST=TRUE
NC_DPB_EG_AUX_CHP MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SW_GAIN_TP MAKE_BASE=TRUE
10K
MAKE_BASE=TRUE
DP_EG_AUXCH_P
NC_DPB_EG_AUX_CHN MAKE_BASE=TRUE
8
NO_TEST=TRUE
NC_RT_GAIN_TP MAKE_BASE=TRUE
Heat spreader mounting boss for T29 router SH0920
8 8 16 93
NO_TEST=TRUE
NC_LT_GAIN_TP MAKE_BASE=TRUE
STDOFF-4.0OD1.85H-SM
8 8 16 93
NO_TEST=TRUE
NC_FSB_CLK133M_PCHN MAKE_BASE=TRUE
NOSTUFF
R0914
8 78 83 97
MAKE_BASE=TRUE
84
C0904
C 6 7 8 18 19 24 25 29 30 31 32 47 48 49 53 54 71 72 87
8 16
17
T29_A_BIAS_R2D_N1
8
A
NC_PCH_CLKOUT_DPP TRUE MAKE_BASE=TRUE
24 92 24 92
1
24 8
NC_DPB_EG_MLN<3..0>
NC_PCH_CLKOUT_DPN TRUE MAKE_BASE=TRUE
NC_PCH_GPIO64_CLKOUTFLEX0 NC_PCH_GPIO65_CLKOUTFLEX1 NC_PCH_GPIO66_CLKOUTFLEX2 NC_PCH_GPIO67_CLKOUTFLEX3
16 8
16 8
R0924 1
6 8 52
USB_EXTC_N USB_EXTC_P
MAKE_BASE=TRUE
DP_EG_AUXCH_N
5% 1/20W MF 201
NC_PCH_CLKOUT_DPN
16 8
T29_A_BIAS_R
TP_ISSP_SDATA_P1_0
5% 1/16W MF-LF
2 402
PP3V3_S3
R0926
16 8
16 8
1
85 8
33
NO_TEST=TRUE
MAKE_BASE=TRUE
85 8
0.01UF
1
SM
6 8 52
84
C0903
10% 10V 2 X5R 201
SM
1.4DIA-SHORT-SILVER-K99
NC_PCIE_CLK100M_EXCARD_N TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_EXCARD_P TRUE MAKE_BASE=TRUE
TP_ISSP_SCLK_P1_1
10K
33
24 8
8 16
6 7 8 18 19 24 25 29 30 31 32 47 48 49 53 54 71 72 87
R0904
33
5% 1/16W MF-LF 402 2
DP_EG_AUXCH_N
8 24
PP3V3_S3 1 NOSTUFF
5% 1/16W MF-LF 402 2
R09131
8 16 97 83 78 8 8 16
8 24
NC_USB_HUB2_OCS4
NO_TEST=TRUE
MAKE_BASE=TRUE
GND
R0923
1
SM
R09031
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE
NC_USB_HUB1_OCS4
MAKE_BASE=TRUE
10K
NC_T29_D2RN<3..2>
GND GND GND GND
0.01UF
NC_USB_HUB2_OCS4
8
MAKE_BASE=TRUE
10% 10V 2 X5R 201
8 18
NC_USB_HUB1_OCS4
8 38 39
MAKE_BASE=TRUE
C0902
8 18
NC_LVDS_IG_B_DATAN<3>
MAKE_BASE=TRUE
33
T29_R2D_C_P<3..2>
NC_PEG_B_CLKRQ_L_GPIO56 TRUE MAKE_BASE=TRUE NC_PCIECLKRQ4_L_GPIO26 TRUE MAKE_BASE=TRUE
52 8 6
SH0913
SH0912
1
NC_PEG_B_CLKRQ_L_GPIO56
NC_LVDS_IG_B_DATAP<3>
NO_TEST=TRUE
NOSTUFF
T29_D2R_N<3..2>
8
8
MAKE_BASE=TRUE
10K
TP_SMC_EXCARD_PWR_EN
NC_PCIE_CLK100M_EXCARD_P
93 16 8
10% 2 10V X5R 201
2
9
95
0.01UF
1
SM
84
8 18 92
NO_TEST=TRUE
NC_LVDS_IG_B_DATAN<3>
NOSTUFF
FW643_WAKE_L
NC_PCIE_CLK100M_EXCARD_N
NC_LVDS_IG_B_DATAP<3>
MAKE_BASE=TRUE NO_TEST=TRUE
C0901
R0922
85 8
9
=PEG_R2D_C_N<7..0>
Unused T29 Ports T29_D2R_P<3..2> NC_T29_D2RP<3..2>
MAKE_BASE=TRUE
93 16 8
5% 1/20W MF 201
Short (IO Row) EMI pogo pins SH0911 1.4DIA-SHORT-SILVER-K99 SH0910 SM
=PEG_R2D_C_P<7..0>
MAKE_BASE=TRUE
8
1
9
MAKE_BASE=TRUE
POGO-2.0OD-3.5H-K86-K87 SM
=PEG_D2R_N<7..0>
MAKE_BASE=TRUE
NC_PCIE_EXCARD_D2R_N TRUE NC_PCIE_EXCARD_D2R_N MAKE_BASE=TRUE NC_PCIE_EXCARD_D2R_P TRUE NC_PCIE_EXCARD_D2R_P MAKE_BASE=TRUE NC_PCIE_EXCARD_R2D_C_NTRUE NC_PCIE_EXCARD_R2D_C_N MAKE_BASE=TRUE NC_PCIE_EXCARD_R2D_C_PTRUE NC_PCIE_EXCARD_R2D_C_P
16 8
8 18 92
NC_LVDS_IG_A_DATAN<3>
NO_TEST=TRUE
MAKE_BASE=TRUE
9
8 19 39
MAKE_BASE=TRUE
16 8
SH0916
SM
=PEG_R2D_C_N<11..8>
95 8
MAKE_BASE=TRUE
TP_SMC_EXCARD_PWR_EN
MAKE_BASE=TRUE
24 8
PEG_D2R_N<7..0>
95
FW_PLUG_DET_L
FW643_WAKE_L
39 38 8
1
SM
NC_LVDS_IG_A_DATAN<3>
18 8
MAKE_BASE=TRUE
4.0OD1.85H-M1.6X0.35
92 18 8
18 8
=PEG_D2R_P<7..0>
1
SH0902 POGO-2.0OD-3.5H-K86-K87
PEG_D2R_P<7..0>
90 73
4.0OD1.85H-M1.6X0.35
Tall EMI pogo pins
8
NC_LVDS_IG_A_DATAP<3>
MAKE_BASE=TRUE NO_TEST=TRUE
24 8
8 87 88
8 16 87
PM_ENET_EN
NC_GPU_XTALOUT
NC_LVDS_IG_A_DATAP<3>
=PEG_R2D_C_P<11..8>
MAKE_BASE=TRUE
6 8 82 88 100
8 79 87
MAKE_BASE=TRUE
ZT0952
C
PM_ENET_EN
NC_GPU_XTALOUT
D
6 8 18
MAKE_BASE=TRUE
92 18 8
MAKE_BASE=TRUE
MAKE_BASE=TRUE
Keyboard / IPD Conn Protect 8
TP_LVDS_IG_BKL_PWM
=PEG_D2R_N<11..8>
PCIE_T29_R2D_C_P<3..0>
8 18 87
PEG_CLKREQ_L
MAKE_BASE=TRUE
6 8 18
MAKE_BASE=TRUE
GPU signals
PEX_CLKREQ_L
MAKE_BASE=TRUE
TP_LVDS_IG_BKL_PWM
MAKE_BASE=TRUE
MAKE_BASE=TRUE 87 79 8
6 8 18
TP_LVDS_IG_B_CLKN
MAKE_BASE=TRUE NO_TEST=TRUE
=PEG_D2R_P<11..8>
PCIE_T29_D2R_N<3..0>
90 73
PPVOUT_S0_LCDBKLT GMUX_VSYNC
18 8 6
8
8 18 87
LVDS_IG_PANEL_PWR
GMUX_VSYNC
88 87 8
TP_LVDS_IG_B_CLKN
8 73 87
GND
1
18 8 6
=PEG_R2D_C_N<15..12>
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
3R2P5
=PEG_R2D_C_P<15..12>
PCIE_T29_D2R_P<3..0>
TP_LVDS_IG_B_CLKP
MAKE_BASE=TRUE
=PEG_D2R_N<15..12>
NC_PEG_R2D_C_N<15..12>
MAKE_BASE=TRUE
ZT0990
TP_LVDS_IG_B_CLKP
18 8 6
MAKE_BASE=TRUE NO_TEST=TRUE
NC_PEG_R2D_C_P<15..12>
MAKE_BASE=TRUE
1
GND
8 87
MAKE_BASE=TRUE NO_TEST=TRUE
1
STDOFF-4.0OD3.0H-TH
TP_LVDS_MUX_SEL_EG
TP_LVDS_MUX_SEL_EG
1
ZT0960
8 90
8 29 66
T29 Signals Through PEG
MAKE_BASE=TRUE
ZT0934 STDOFF-4.0OD3.0H-TH
GND SL-3.1X2.7-6CIR-NSP
MEMVTT_EN
NC_PEG_D2R_N<15..12>
NO_TEST=TRUE
T29_LSEO_LSOE2
PM_ALL_GPU_PGOOD
89 87 86 81 73 8
ZT0950 TH
MEMVTT_EN
MAKE_BASE=TRUE NO_TEST=TRUE
8 19 33 87
GMUX ALIASES
GND
TP_CPU_VTT_SELECT
MAKE_BASE=TRUE
MAKE_BASE=TRUE
Unused PEG signals =PEG_D2R_P<15..12> NC_PEG_D2R_P<15..12>
8 19 33 87 9
MAKE_BASE=TRUE NO_TEST=TRUE
GND
1
8 19 23 33 87
JTAG_ISP_TDO MAKE_BASE=TRUE
Frame Holes
1
JTAG_ISP_TCK
MAKE_BASE=TRUE
3R2P5
3R2P5
TP_CPU_VTT_SELECT
MAKE_BASE=TRUE
66 29 8 19 23 33 8 87
JTAG_ISP_TDI
JTAG_ISP_TDO
87 33 19 8
1
ZT0940
90 8
GFXIMVP_VID<0..6>
GFX_VID<0..6>
JTAG_ISP_TCK
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
1
CPUIMVP_VID<0..6>
MAKE_BASE=TRUE
90
MAKE_BASE=TRUE
JTAG_ISP_TDI
87 33 19 8
1
D
JTAG_ISP_TCK
87 33 23 19 8
STDOFF-4.5OD.98H-1.1-3.48-TH 1
ZT0915
1
1
ZT0987 STDOFF-4.5OD.98H-1.1-3.48-TH
2
BRANCH
PAGE
9 OF 132 SHEET
8 OF 101
1
A
8
7
6
5
4
PP1V05_S0
3
2
1
6 7 9 10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101
1
R1010 24.9
1% 1/16W MF-LF 2 402
IN
90 17
IN
90 17
IN
90 17 6
IN
90 17
IN
90 17
IN
90 17
OUT
90 17
OUT
90 17
OUT
90 17
OUT
90 17
OUT
90 17
OUT
90 17
OUT
90 17
OUT
90 17 6
OUT
90 17
OUT
90 17
OUT
90 17
OUT
90 17
OUT
90 17
OUT
90 17
C
OUT
90 17
OUT
90 17
OUT
90 17
OUT
90 17
OUT
90 17
OUT
90 17
OUT
90 17 6
IN
90 17 6
IN
90 17 6
90 17 6 90 17 6
B
DMI_TX_0* DMI_TX_1* DMI_TX_2* DMI_TX_3*
FDI_TX_0* FDI_TX_1* FDI_TX_2* FDI_TX_3* FDI_TX_4* FDI_TX_5* FDI_TX_6* FDI_TX_7* FDI_TX_0 FDI_TX_1 FDI_TX_2 FDI_TX_3 FDI_TX_4 FDI_TX_5 FDI_TX_6 FDI_TX_7 FDI0_FSYNC FDI1_FSYNC FDI_INT
IN
FDI_LSYNC<0> FDI_LSYNC<1>
AB7 AB3
FDI0_LSYNC FDI1_LSYNC
TP_EDP_TX_N<0> TP_EDP_TX_N<1> TP_EDP_TX_N<2> TP_EDP_TX_N<3>
AG2 AF1 AE6 AG6
1
R1030
EDP_TX_0* EDP_TX_1* EDP_TX_2* EDP_TX_3*
TP_EDP_TX_P<0> TP_EDP_TX_P<1> TP_EDP_TX_P<2> TP_EDP_TX_P<3>
AG4 AF3 AF7 AG8
EDP_TX_0 EDP_TX_1 EDP_TX_2 EDP_TX_3
TP_EDP_AUX_P TP_EDP_AUX_N
AE4 AE2
EDP_AUX EDP_AUX*
CPU_EDP_COMP
AB1 AC2
EDP_ICOMPO EDP_COMPIO
AE8
EDP_HPD
PLACE_NEAR=U1000.AB1:12.7mm
CPU_EDP_HPD 10K PU disables eDP HPD
CPU_CFG<4> should be pulled down to enable EDP
90 23 9 90 23 9 90 23 9 90 23 9 90 23 9
CPU_CFG<7> CPU_CFG<6> CPU_CFG<5> CPU_CFG<4> CPU_CFG<2>
90 23 9 90 23 9 90 23 9 90 23 9
NOSTUFF 1
A
EDP
1
NOSTUFF1
NOSTUFF1
NOSTUFF1
NOSTUFF1
NOSTUFF1
R1044
R1046
R1047
R1040
R1041
R1043
1K
1K
1K
1K
1K
1K
1K
1K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
2
2
2
90 23 9 90 23 9
CPU_PEG_COMP
90 23 9 90 23 9
PEG_RX_0* PEG_RX_1* PEG_RX_2* PEG_RX_3* PEG_RX_4* PEG_RX_5* PEG_RX_6* PEG_RX_7* PEG_RX_8* PEG_RX_9* PEG_RX_10* PEG_RX_11* PEG_RX_12* PEG_RX_13* PEG_RX_14* PEG_RX_15*
F23 H23 H21 H19 J20 G18 K17 F15 H15 H13 H11 J12 E8 G10 J8 F7
=PEG_D2R_N<0> =PEG_D2R_N<1> =PEG_D2R_N<2> =PEG_D2R_N<3> =PEG_D2R_N<4> =PEG_D2R_N<5> =PEG_D2R_N<6> =PEG_D2R_N<7> PCIE_T29_D2R_N<0> PCIE_T29_D2R_N<1> PCIE_T29_D2R_N<2> PCIE_T29_D2R_N<3> NC_PEG_D2R_N<12> NC_PEG_D2R_N<13> NC_PEG_D2R_N<14> NC_PEG_D2R_N<15>
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15
G22 K23 K21 F19 K19 H17 K15 G14 J16 K13 F11 K11 F9 H9 H7 G6
=PEG_D2R_P<0> =PEG_D2R_P<1> =PEG_D2R_P<2> =PEG_D2R_P<3> =PEG_D2R_P<4> =PEG_D2R_P<5> =PEG_D2R_P<6> =PEG_D2R_P<7> PCIE_T29_D2R_P<0> PCIE_T29_D2R_P<1> PCIE_T29_D2R_P<2> PCIE_T29_D2R_P<3> NC_PEG_D2R_P<12> NC_PEG_D2R_P<13> NC_PEG_D2R_P<14> NC_PEG_D2R_P<15>
PEG_TX_0* PEG_TX_1* PEG_TX_2* PEG_TX_3* PEG_TX_4* PEG_TX_5* PEG_TX_6* PEG_TX_7* PEG_TX_8* PEG_TX_9* PEG_TX_10* PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15*
A22 B23 C18 D21 B19 E20 A14 D17 B15 E16 D13 A10 B11 D9 B7 E12
=PEG_R2D_C_N<0> =PEG_R2D_C_N<1> =PEG_R2D_C_N<2> =PEG_R2D_C_N<3> =PEG_R2D_C_N<4> =PEG_R2D_C_N<5> =PEG_R2D_C_N<6> =PEG_R2D_C_N<7> PCIE_T29_R2D_C_N<0> PCIE_T29_R2D_C_N<1> PCIE_T29_R2D_C_N<2> PCIE_T29_R2D_C_N<3> NC_PEG_R2D_C_N<12> NC_PEG_R2D_C_N<13> NC_PEG_R2D_C_N<14> NC_PEG_R2D_C_N<15>
PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
C22 D23 A18 B21 D19 F21 C14 B17 D15 F17 B13 C10 D11 B9 D7 F13
=PEG_R2D_C_P<0> =PEG_R2D_C_P<1> =PEG_R2D_C_P<2> =PEG_R2D_C_P<3> =PEG_R2D_C_P<4> =PEG_R2D_C_P<5> =PEG_R2D_C_P<6> =PEG_R2D_C_P<7> PCIE_T29_R2D_C_P<0> PCIE_T29_R2D_C_P<1> PCIE_T29_R2D_C_P<2> PCIE_T29_R2D_C_P<3> NC_PEG_R2D_C_P<12> NC_PEG_R2D_C_P<13> NC_PEG_R2D_C_P<14> NC_PEG_R2D_C_P<15>
IN
8
90 23 9
IN
8
90 23 9
IN
8
90 23 9
IN
8
90 23
IN
8
90 23
IN
8
90 23
IN
8
90 23
IN
8
23
IN
8 33 93
23
IN
8 33 93
23
IN
8 33 93
23
IN
8 33 93
90 23 9
IN
8
IN
8
IN
8
IN
8
IN
8
IN
8
IN
8
IN
8
IN
8
IN
8
IN
8
IN
8
IN
8 33 93
IN
8 33 93
IN
8 33 93
IN
8 33 93
IN
8
IN
8
IN
8
IN
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8 33 93
OUT
8 33 93
90 23
2
2
B57 D57 B55 A54 A58 D55 C56 E54 J54 G56 F55 K55 F57 E58 H57 H55 D53 K57
CPU_CFG<0> CPU_CFG<1> CPU_CFG<2> CPU_CFG<3> CPU_CFG<4> CPU_CFG<5> CPU_CFG<6> CPU_CFG<7> CPU_CFG<8> CPU_CFG<9> CPU_CFG<10> CPU_CFG<11> CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15> CPU_CFG<16> CPU_CFG<17>
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
NOTE: Intel is investigating processor driven VREF_DQ generation. This connection is to support the same.
NOSTUFF
OUT
8 33 93
OUT
8 33 93
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8 33 93
OUT
8 33 93
OUT
8 33 93
OUT
8 33 93
OUT
8
OUT
8
OUT
8
OUT
8
R1021 30 26
PP0V75_S3_MEM_VREFDQ_A
1
0
1
R1020
2
1% 1/16W MF-LF 402
NOSTUFF
R1023 30 28
PP0V75_S3_MEM_VREFDQ_B
1
0 5% 1/16W MF-LF 402
2 1
R1022 1K
2
1% 1/16W MF-LF 402
AD5 RSVD_25 AH5 RSVD_26 AJ6 RSVD_27
NC NC
G52 RSVD_38 G64 RSVD_39
NC
AJ10 RSVD_40
BI
CPU_THERMD_P CPU_THERMD_N
BE6 AA4 AC4 AC6
RSVD_53 RSVD_54 RSVD_55 RSVD_56 RSVD_57 RSVD_58 RSVD_59 RSVD_60 RSVD_61 RSVD_62 RSVD_63 RSVD_64 RSVD_65 RSVD_66 RSVD_67 RSVD_68
F5 K9 H5 L10 G4 K7 K5 M9 L6 J2 L2 P7 M5 J4 L4 N6
RSVD_69 RSVD_70 RSVD_71 RSVD_72
G48 K49 H49 J50
RSVD_78 RSVD_79 RSVD_80 RSVD_81 RSVD_82 RSVD_83 RSVD_84 RSVD_85 RSVD_86 RSVD_87 RSVD_88 RSVD_89 RSVD_90 RSVD_91 RSVD_92 RSVD_93 RSVD_94 RSVD_95 RSVD_96 RSVD_97
AY13 BB13 BB15 AY15 AW14 BD13 BA16 BE16 BD15 BC14 BF19 BH19 BF21 BH21 BF23 BH23 BF25 BH25 BJ22 BG22
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
D
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
C
RSVD_28 (DDR_VREF0) RSVD_29 (DDR_VREF1) RSVD_30 RSVD_31 RSVD_32 RSVD_33 RSVD_34
D49 RSVD_35 B53 RSVD_36
NC NC NC NC NC BI
BF3 BG4 BD19 AY45 AY41 BG62 BB43
NC NC
NC
98 50
RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15 RSVD_16 RSVD_17 RSVD_18 RSVD_19 RSVD_20
NC NC NC
NC NC NC NC
98 50
CFG_5 (IPU) RESERVED CFG_6 (IPU) CFG_7 (IPU) OMIT CFG_8 (IPU) CFG_9 (IPU) CFG_10 (IPU) CFG_11 (IPU) CFG_12 (IPU) CFG_13 (IPU) CFG_14 (IPU) CFG_15 (IPU) CFG_16 (IPU) CFG_17 (IPU)
AW50 RSVD_22 BB57 RSVD_23 BF63 RSVD_24
NC NC NC NC NC
1K
BB17 AY17 BD29 BD33 BC30 BE32 AW42 BA48 BC42 AW46 BG26 BB25 BG34 BH35 BJ34 BF35 BF41 BH43 BJ42 BF43
CFG_0 (IPU) U1000 CFG_1 (IPU)SANDY-BRIDGE CFG_2 (IPU) MOBILE-REV1 CFG_3 (IPU) BGA CFG_4 (IPU) (5 OF 11)
NC NC NC
CPU_MEM_VREFDQ_A CPU_MEM_VREFDQ_B
2
5% 1/16W MF-LF 402
CPU_CFG<16> CPU_CFG<3> CPU_CFG<1> CPU_CFG<0>
R1042
2
R1045
1
90
90 23 9
DMI_TX_0 DMI_TX_1 DMI_TX_2 DMI_TX_3
AD9
IN
BGA (SYM 1 OF 11) OMIT
FDI_INT
1% 1/16W MF-LF 2 402
1% 1/16W MF-LF
2 402
AC8 AA2
PEG_ICOMPI G2 PEG_ICOMPO H1 PEG_RCOMPO F3
SANDY-BRIDGE MOBILE-REV1
DMI_RX_0 DMI_RX_1 DMI_RX_2 DMI_RX_3
IN
24.9
10K
W6 W10 Y9 AA10 U2 W4 V3 AA6
FDI_FSYNC<0> FDI_FSYNC<1>
PP1V05_S0
R1031
V7 W8 AA8 AC10 U4 W2 V1 Y5
FDI_DATA_P<0> FDI_DATA_P<1> FDI_DATA_P<2> FDI_DATA_P<3> FDI_DATA_P<4> FDI_DATA_P<5> FDI_DATA_P<6> FDI_DATA_P<7>
72 44 39 35 23 17 16 14 13 9 7 6 12 10 22 20 69 67 101
1
N2 R2 P3 T5
FDI_DATA_N<0> FDI_DATA_N<1> FDI_DATA_N<2> FDI_DATA_N<3> FDI_DATA_N<4> FDI_DATA_N<5> FDI_DATA_N<6> FDI_DATA_N<7>
OUT
90 17 6
N4 R4 P1 U6
DMI_N2S_P<0> DMI_N2S_P<1> DMI_N2S_P<2> DMI_N2S_P<3>
OUT
90 17
N8 T9 R6 U8
DMI_N2S_N<0> DMI_N2S_N<1> DMI_N2S_N<2> DMI_N2S_N<3>
OUT
90 17
DMI_S2N_P<0> DMI_S2N_P<1> DMI_S2N_P<2> DMI_S2N_P<3>
U1000
DMI_RX_0* DMI_RX_1* DMI_RX_2* DMI_RX_3*
PCI EXPRESS BASED INTERFACE SIGNALS
IN
90 17
N10 R10 R8 U10
DMI
90 17 6
DMI_S2N_N<0> DMI_S2N_N<1> DMI_S2N_N<2> DMI_S2N_N<3>
INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS
D
IN
EMBEDDED DISPLAY PORT
90 17
B
RSVD_41 RSVD_42 RSVD_43 RSVD_44
C52 RSVD_45 D3 C4 C24 D25 B25
RSVD_46 RSVD_47 RSVD_48 RSVD_49 RSVD_50
K47 RSVD_51 (THERMDA) H47 RSVD_52 (THERMDC)
NOSTUFF1
R1049 1K
2
5% 1/16W MF-LF 402
A
2
PAGE TITLE
CPU DMI/PEG/FDI/RSVD These can be Placed close to J2500 and Only for debug access
DRAWING NUMBER
Apple Inc.
FOR SANDYBRIDGE PROCESSOR
SIZE
D REVISION
R
CFG CFG CFG CFG CFG
8
[7] :PEG DEFER TRAINING [6:5] :PCIE BIFURCATION [4] :eDP ENABLE/DISABLE [3] :PCIE x4 LANE REVERSAL [2] :PCIE x16 LANE REVERSAL
1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4 1 = DISABLED 0 = ENABLED 1 = NORMAL OPERATION 0 = LANES REVERSED 1 = NORMAL OPERATION 0 = LANES REVERSED
7
6
5
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
4
3
2
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10 OF 132 SHEET
9 OF 101
1
8
7
6
5
4
3
2
1
D
D
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
PP1V05_S0 PP1V05_S0_CPU_VCCPQE
7 12 14
1
R1140
PP1V05_S0 1
R1100 1
NOSTUFF 1
R1104
1K
R1101
5% 1/20W MF 201 2
68 5%
1/16W MF-LF
R1102
BGA (2 OF 11) OMIT
5% 1/20W MF
5% 1/16W MF-LF 402
2 201
2 402
NC 90 17
AH9 PROC_SELECT*
CPU_PROC_SEL_L
OUT
R1103 CPU_PROCHOT_L
2
1
CPU_CATERR_L
H53 CATERR*
90 44 19
BI
CPU_PECI
F53 PECI
CPU_PROCHOT_R_L
H51 PROCHOT*
OUT
PM_THRMTRIP_L
F51 THERMTRIP*
R11261 75 1% 1/16W MF-LF 402 2 25 23
IN
90 19
2
43.2 1 1% 1/16W MF-LF 402
90 17
IN
PM_SYNC
K53 PM_SYNC
90 23 19
IN
CPU_PWRGD
C60 UNCOREPWRGOOD
PP1V5_S3RS0_CPUDDR
29
BE24 SM_DRAMRST*
PLACE_NEAR=R1121.2:1mm
BJ44 SM_VREF
CPU_DDR_VREF
1
R1120
1% 1/16W MF-LF 402 2
B
IN
R1121 2
PM_MEM_PWRGD
R1120 and R1121 are Intel recommended
130
BCLK D5 BCLK* C6
(IPD) (IPU)
ITPCPU_CLK100M_P ITPCPU_CLK100M_N
IN IN
16 90
DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N
IN
16 90
IN
16 90
16 90
J62 H65
XDP_CPU_PRDY_L XDP_CPU_PREQ_L
TCK J58 TMS H59 H63
XDP_CPU_TCK XDP_CPU_TMS XDP_CPU_TRST_L
TDI K61 TDO K59
XDP_CPU_TDI XDP_CPU_TDO XDP_DBRESET_L
OUT
23 25 90
DBR* H61 (IPU) BPM_0* (IPU) BPM_1* (IPU) BPM_2* (IPU) BPM_3* (IPU) BPM_4* (IPU) BPM_5* (IPU) BPM_6* (IPU) BPM_7*
C62 D61 E62 F63 D59 F61 F59 G60
XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>
OUT
23 90
IN
23 90
IN
23 90
IN
23 90
IN
23 90
IN
23 90
OUT
23 90
BI BI
C
23 90 23 90
BI
23 90
BI
23 90
BI
23 90
BI
23 90
BI
23 90
BI
23 90
1
R1141 1K
1 1
1% 1/16W values MF-LF 402 PLACE_NEAR=U1000.AY25:51.562mm
R1112
2 72 71 29 15 13 10 7
BJ46 SM_RCOMP_0 BG46 SM_RCOMP_1 BF45 SM_RCOMP_2
CPU_SM_RCOMP<0> CPU_SM_RCOMP<1> CPU_SM_RCOMP<2>
200
Unused eDP CLK
(IPU) TRST*
AY25 SM_DRAMPWROK
CPU_MEM_RESET_L
OUT
DPLL_REF_CLK DPLL_REF_CLK_L
BCLK_ITP K63 BCLK_ITP* K65
(IPU)
K51 RESET*
PLT_RESET_LS1V1_L
PM_MEM_PWRGD_R
90 29 17
DPLL_REF_CLK AJ4 DPLL_REF_CLK* AJ2
(IPU) PREQ*
R1125
PLT_RST_CPU_BUF_L
72 71 29 15 13 10 7
5% 1/16W MF-LF 2 402
(IPU) PRDY*
5% 1/16W MF-LF 402
PP1V05_S0
OUT
JTAG & BPM
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
BI
90
PWR MGMT
90 67 45
56
B59 PROC_DETECT*
THERMAL
C
1K
SANDY-BRIDGE MOBILE-REV1
1
1K
51
2
NOSTUFF
CLOCKS
NOSTUFF
U1000
DDR3 MISC
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
1
R1113
1
R1114
R1111
140
25.5
200
10K
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
1% PLACE_NEAR=U1000.BF45:12.7mm 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
2
5% 1/16W MF-LF 2 402
1
2
PLACE_NEAR=U1800.AY11:157mm
B
PP1V5_S3RS0_CPUDDR NOSTUFF 1
PLACE_NEAR=U1000.BG46:12.7mm
R1130 100
PLACE_NEAR=U1000.BJ44:2.54mm
1% 1/16W MF-LF 402
PLACE_NEAR=U1000.BJ46:12.7mm
2
NOSTUFF 1
R1131
PLACE_NEAR=U1000.BJ44:2.54mm 100 1% 1/16W MF-LF 402
NOSTUFF 1
C1130 0.1UF 10%
2 16V X5R 2
402
PLACE_NEAR=U1000.BJ44:2.54mm
A
A PAGE TITLE
CPU CLOCK/MISC/JTAG DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
11 OF 132 SHEET
10 OF 101
1
7
6
5
4
3
U1000
SANDY-BRIDGE MOBILE-REV1
BGA (SYM 3 OF 11) BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6 91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
C
B
BI
BI
91 27 6
BI
91 27 6
BI
91 27 26 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 26 6
OUT
91 26 6
OUT
91 26 6
OUT
91 26 6
OUT
91 26 6
OUT
91 26 6
OUT
AL6 AL8 AP7 AM5 AK7 AL10 AN10 AM9 AR10 AR8 AV7 AY5 AT5 AR6 AW6 AT9 BA6 BA8 BG6 AY9 AW8 BB7 BC8 BE4 AW12 AV11 BB11 BA12 BE8 BA10 BD11 BE12 BB49 AY49 BE52 BD51 BD49 BE48 BA52 AY51 BC54 AY53 AW54 AY55 BD53 BB53 BE56 BA56 BD57 BF61 BA60 BB61 BE60 BD63 BB59 BC58 AW58 AY59 AL60 AP61 AW60 AY57 AN60 AR60
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>
BA36 BC38 BB19
MEM_A_CAS_L MEM_A_RAS_L MEM_A_WE_L
BE44 BE36 BA44
OMIT
BGA (SYM 4 OF 11) SA_CK_0 BB31 SA_CK_0* BA32
MEM_A_CLK_P<0> MEM_A_CLK_N<0>
SA_CKE_0 BC18
MEM_A_CKE<0>
SA_CK_1 AW34 SA_CK_1* AY33
MEM_A_CLK_P<1> MEM_A_CLK_N<1>
SA_CKE_1 BD17
MEM_A_CKE<1>
SA_CS_0* BD41 SA_CS_1* BD45 SA_ODT_0 BB41 SA_ODT_1 BC46
MEMORY CHANNEL A
D
BI
91 27 6
MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>
1
U1000
SANDY-BRIDGE MOBILE-REV1
91 27 6
2
SA_DQS_0* SA_DQS_1* SA_DQS_2* SA_DQS_3* SA_DQS_4* SA_DQS_5* SA_DQS_6* SA_DQS_7*
AN8 AU6 BC6 BD9 BC50 BB55 BD59 AU60
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7
AN6 AU8 BD5 BC10 BB51 BD55 BD61 AV61
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15
BD27 BA28 BB27 AW26 BB23 BA24 AY21 BD21 BC22 BB21 AW38 AW22 BA20 BB45 BE20 AW18
MEM_A_CS_L<0> MEM_A_CS_L<1> MEM_A_ODT<0> MEM_A_ODT<1> MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7> MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7> MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>
OUT
6 26 91
91 27 6
BI
OUT
6 26 91
91 27 6
BI
91 27 6 6 26 91
BI
OUT OUT
91 27 6
BI
6 26 91
91 27 6
BI
OUT
6 26 91
91 27 6
BI
91 27 6
BI
OUT
6 26 91 91 27 6
BI
OUT
6 26 91
91 27 6
BI
OUT
6 26 91
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
OUT OUT
6 26 91 6 26 91
BI
6 27 91
91 27 6
BI
BI
6 27 91
91 27 6
BI
BI
6 27 91
91 27 6
BI
BI
6 27 91
91 27 6
BI
BI
6 27 91
91 27 6
BI
BI
6 27 91
91 27 6
BI
BI
6 26 27 91
91 27 6
BI
BI
6 27 91
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
BI BI
6 27 91 6 27 91
BI
6 27 91
BI
6 27 91
BI
6 27 91
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
6 27 91
BI
6 26 27 91
BI
6 27 91
OUT
6 26 91
91 27 6
BI
OUT OUT OUT
6 26 91
91 27 6
BI
6 26 91
91 28 27 6
BI
6 26 91
91 27 6
BI
OUT
6 26 91
91 27 6
BI
OUT
6 26 91
91 27 6
BI
OUT
6 26 91
91 27 6
BI
OUT
6 26 91
91 27 6
BI
OUT
6 26 91
91 27 6
BI
OUT
6 26 91
91 27 6
BI
OUT
6 26 91
91 27 6
BI
OUT
6 26 91
91 27 6
BI
OUT
6 26 91
91 27 6
BI
OUT
6 26 91
91 27 6
BI
OUT
6 26 91
91 27 6
BI
OUT
6 26 91
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
91 27 6
BI
SA_BS_0 SA_BS_1 SA_BS_2
91 28 6
OUT
91 28 6
OUT
91 28 6
OUT
SA_CAS* SA_RAS* SA_WE*
91 28 6
OUT
91 28 6
OUT
91 28 6
OUT
MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>
AL4 AK3 AP3 AR2 AL2 AK1 AP1 AR4 AV3 AU4 BA4 BB1 AV1 AU2 BA2 BB3 BC2 BF7 BF11 BJ10 BC4 BH7 BH11 BG10 BJ14 BG14 BF17 BJ18 BF13 BH13 BH17 BG18 BH49 BF47 BH53 BG50 BF49 BH47 BF53 BJ50 BF55 BH55 BJ58 BH59 BJ54 BG54 BG58 BF59 BA64 BC62 AU62 AW64 BA62 BC64 AU64 AW62 AR64 AT65 AL64 AM65 AR62 AT63 AL62 AM63
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>
BJ38 BD37 AY29
SB_BS_0 SB_BS_1 SB_BS_2
MEM_B_CAS_L MEM_B_RAS_L MEM_B_WE_L
BH39 BG38 BF39
SB_CAS* SB_RAS* SB_WE*
OMIT
MEMORY CHANNEL B
8
SB_CK_0 BF33 SB_CK_0* BH33
MEM_B_CLK_P<0> MEM_B_CLK_N<0>
OUT
6 28 91
OUT
6 28 91
SB_CKE_0 BD25
MEM_B_CKE<0>
OUT
6 28 91
SB_CK_1 BF37 SB_CK_1* BH37
MEM_B_CLK_P<1> MEM_B_CLK_N<1>
OUT
6 28 91
OUT
6 28 91
SB_CKE_1 BJ26
MEM_B_CKE<1>
OUT
6 28 91
SB_CS_0* BE40 SB_CS_1* BH41
MEM_B_CS_L<0> MEM_B_CS_L<1>
OUT
6 28 91
OUT
6 28 91
SB_ODT_0 BG42 SB_ODT_1 BH45
MEM_B_ODT<0> MEM_B_ODT<1>
OUT
6 28 91
OUT
6 28 91
SB_DQS_0* SB_DQS_1* SB_DQS_2* SB_DQS_3* SB_DQS_4* SB_DQS_5* SB_DQS_6* SB_DQS_7*
AN4 AW2 BH9 BF15 BF51 BH57 AY63 AN62
MEM_B_DQS_N<0> MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7>
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7
AN2 AW4 BF9 BH15 BH51 BF57 AY65 AN64
MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7>
SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15
BF31 BH31 BB37 BC34 BF27 BB33 BH27 BG30 BH29 BF29 AY37 BJ30 AW30 BA40 BB29 BE28
MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15>
BI
6 27 91
BI
6 27 91
BI
6 27 91
BI
6 27 91
BI
6 27 91
BI
6 27 91
BI
6 27 28 91
BI
6 27 91
BI
6 27 91
BI
6 27 91
BI
6 27 91
BI
6 27 91
BI
6 27 91
BI
6 27 91
BI
6 27 28 91
BI
D
6 27 91
OUT
6 28 91
OUT
6 28 91
OUT
6 28 91
OUT
6 28 91
OUT
6 28 91
OUT
6 28 91
OUT
6 28 91
OUT
6 28 91
OUT
6 28 91
OUT
6 28 91
OUT
6 28 91
OUT
6 28 91
OUT
6 28 91
OUT
6 28 91
OUT
6 28 91
OUT
6 28 91
C
B
A
SYNC_DATE=06/15/2010 PAGE TITLE
CPU DDR3 INTERFACES DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
12 OF 132 SHEET
11 OF 101
1
A
8
7
6
5
4
3
2
1
D
D 49 50 51 53 56 60 61 71 72 79 6 7 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 48 82 83 84 87 88 89 98 101 68 48 14 12 7 6
PP3V3_S0
PPVCORE_S0_CPU
For Future Compatibility
R1320
PPVCORE_S0_CPU
1
10K
64 15 12 7 6 7 9 10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101
PP1V05_S0
PLACE_NEAR=R1310.1:2.54mm 1
R1300
2 BI
W17 W15 W12 U17 U15 U12 T16 T14 T11 N18 N16 N14 M17 M15 M12 M11 L18 L14
R1302 130 PLACE_NEAR=U1000.A50:2.54mm
1% 1/16W MF-LF 402
CPU_VIDSOUT
6 7 9 10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101
1
75
90 67
PP1V05_S0
5% 1/16W MF-LF 402
PPVCCSA_S0_REG
R1312 402 1/16W
0 1
CPU_VIDSCLK
402 1/16W
0 1
CPU_VIDALERT_L
402 1/16W
1
2
1% 1/16W MF-LF 402
CPU_VIDSOUT_R
2 5% MF-LF
R1311 90 67
OUT
90 67
IN
CPU_VIDSCLK_R
2 5% MF-LF
R1310
PPVCORE_S0_CPU PP1V05_S0
C
6 7 9 10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101
1% 1/16W MF-LF 402 2
PLACE_SIDE=BOTTOM
1
R1362
100
PLACE_NEAR=U1000.B47:50.8mm
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM NOSTUFF
2
R13641
R1366 100
1% 1/16W MF-LF 402
1% NOSTUFF 1/16W MF-LF 402
2
6 7 12 14 48 68 101 7 12 13 15 48 68
PLACE_SIDE=BOTTOM PPVCCSA_S0_REG
49.9
1
R1370
OUT
90 67
OUT
90 67
OUT
90 67
OUT
90 69
OUT
90 69
OUT
A50 D51 B51
49.9
NOSTUFF
PLACE_SIDE=BOTTOM
1% 1/20W MF 201
2
2
1
R1368 100
1% 1/20W MF 201
1% 1/16W MF-LF
2 402
OUT 64
OUT
PLACE_NEAR=U1000.F49:50.8mm 90 67
7 12 15 64
NOSTUFF
1
100
PPVCORE_S0_CPU PPVCORE_S0_AXG
7 12 13 15 48 68
PLACE_NEAR=U1000.AW10:50.8mm
R13601
PLACE_NEAR=U1000.B51:38mm
6 7 12 14 48 68 101
PPVCORE_S0_AXG
NOSTUFF
CPU_VIDALERT_L_R
2 5% MF-LF
43
AE10 AG10
CPU_VCCSA_VID<0> CPU_VCCSA_VID<1> CPU_VCCSENSE_P CPU_VCCSENSE_N
B47 A46
CPU_AXG_SENSE_P CPU_AXG_SENSE_N
F49 E50 AW10 AU10
CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N
AY19 AW20
TP_CPU_VDDQSENSE_P TP_CPU_VDDQSENSE_N
PLACE_NEAR=U1000.E50:50.8mm 1 PLACE_SIDE=BOTTOM
R1367 100
2
64
1% 1/16W MF-LF 402
OUT
K3
CPU_VCCSASENSE
NOSTUFF
B
TP_CPU_DIE_SENSE
F47
CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N
D47 C48
CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N
B49 A48
R1314
1
1
10K 5% 1/16W MF-LF 402
PLACE_SIDE=BOTTOM PLACE_SIDE=BOTTOM
PLACE_NEAR=U1000.A46:50.8mm
PLACE_NEAR=U1000.AU10:50.8mm
PLACE_SIDE=BOTTOM
1
R1361
1
R1363
100 1% 1/16W MF-LF 402 2
49.9
100
NOSTUFF
2
1% 1/16W MF-LF 402
R13651 1% 1/20W MF 201
R1371 49.9
NOSTUFF
NOSTUFF
1
2 2
1% 1/20W MF 201
PLACE_SIDE=BOTTOM NOSTUFF
R1313 10K
2
2
5% 1/16W MF-LF 402
VCCSA_0 U1000 VCCIO_SEL VCCSA_1 SANDY-BRIDGE MOBILE-REV1 VCCDQ_0 VCCSA_2 BGA VCCDQ_1 VCCSA_3 (9 OF 11) VCCDQ_2 VCCSA_4 VCCDQ_3 VCCSA_5 OMIT VCCSA_6 VCCPLL_0 VCCSA_7 VCCPLL_1 VCCSA_8 VCCPLL_2 VCCSA_9 VCCPQE_0 VCCSA_10 VCCPQE_1 VCCSA_11 VCCPQE_2 VCCSA_12 VCCPQE_3 VCCSA_13 VCCSA_14 VSS_NCTF_0 VCCSA_15 VSS_NCTF_1 VCCSA_16 VSS_NCTF_2 VCCSA_17 VSS_NCTF_3 VSS_NCTF_4 VIDSOUT VSS_NCTF_5 VIDSCLK VSS_NCTF_6 VIDALERT* VSS_NCTF_7 VCCSA_VID_0 VSS_NCTF_8 VCCSA_VID_1 (IPU) VSS_NCTF_9 VSS_NCTF_10 VCC_SENSE VSS_NCTF_11 VSS_SENSE VSS_NCTF_12 VAXG_SENSE VSS_NCTF_13 VSSAXG_SENSE VSS_NCTF_14 VSS_NCTF_15 VCCIO_SENSE VSS_SENSE_VCCIO DC_TEST_A4 DC_TEST_A62 VDDQ_SENSE DC_TEST_A64 VSS_SENSE_VDDQ DC_TEST_B3 VCCSA_SENSE DC_TEST_B63 DC_TEST_B65 VCC_DIE_SENSE DC_TEST_BF1 VCC_VAL_SENSE DC_TEST_BF65 VSS_VAL_SENSE DC_TEST_BG2 DC_TEST_BG64 VAXG_VAL_SENSE DC_TEST_BH1 VSSAXG_VAL_SENSE DC_TEST_BH3 DC_TEST_BH63 DC_TEST_BH65 DC_TEST_BJ2 DC_TEST_BJ4 DC_TEST_BJ62 DC_TEST_BJ64 DC_TEST_C2 DC_TEST_C64 DC_TEST_D1 DC_TEST_D65
AJ8
R46 R42 R40 R36 R34 R29 R27 R23 R21 N45 N43 N39 N37 N33 N30 N26 N24 N20 M46 M42 M40 M36 M34 M29 M27 M23 M21 L44 L40 L38 L34 L32 L28 L26 L22 K45 K43 K41 K37 K35 K31 K29 K25 J44 J40 J38 J34 J32 J28 J26 H45 H43 H41 H37
2
CPU_VCCIO_SEL
AV23 AT23 AP23 AL23
PP1V5_S3_CPU_VCCDQ
AK65 AK63 AK61
PP1V8_S0_CPU_VCCPLL_R
AV21 AT21 AP21 AL21
PP1V05_S0_CPU_VCCPQE
7 15
7 14
7 10 14
BJ60 BJ6 BH61 BH5 BE64 BE2 BD65 BD1 F65 F1 E64 E2 B61 B5 A60 A6 A4 A62 A64 B3 B63 B65 BF1 BF65 BG2 BG64 BH1 BH3 BH63 BH65 BJ2 BJ4 BJ62 BJ64 C2 C64 D1 D65
TP_DC_TEST_A4 TP_DC_TEST_A62 DC_TEST_B63_A64 DC_TEST_B3_C2
6
DC_TEST_B65_C64 TP_DC_TEST_BF1 TP_DC_TEST_BF65 6 DC_TEST_BH1_BG2 DC_TEST_BG64_BH65 6
DC_TEST_BH3_BJ2 DC_TEST_BJ64_BH63
TP_DC_TEST_BJ4 TP_DC_TEST_BJ62
TP_DC_TEST_D1 TP_DC_TEST_D65
VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53
U1000 SANDY-BRIDGE MOBILE-REV1 BGA (6 OF 11)
CORE POWER OMIT
VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97 VCC_98 VCC_99 VCC_100 VCC_101 VCC_102 VCC_103 VCC_104 VCC_105 VCC_106 VCC_107
6 7 12 14 48 68 101
H35 H31 H29 H25 G44 G40 G38 G34 G32 G28 G26 F45 F43 F41 F37 F35 F31 F29 F25 E44 E40 E38 E34 E32 E28 E26 D45 D43 D41 D37 D35 D31 D29 C44 C40 C38 C34 C32 C28 C26 B45 B43 B41 B37 B35 B31 B29 A44 A40 A38 A34 A32 A28 A26
C
B
6
PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side. NOTE: Intel validation sense lines per doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.
A
SYNC_MASTER=K92_MLB
SYNC_DATE=08/03/2010
PAGE TITLE
CPU POWER DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
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13 OF 132 SHEET
12 OF 101
1
A
C
B
A
VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85
U1000 SANDY-BRIDGE MOBILE-REV1 BGA (10 OF 11)
OMIT
VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171
6
AG12 AF65 AF63 AF61 AF11 AF9 AF5 AE57 AD16 AD14 AD7 AD3 AD1 AC64 AC62 AC60 AC57 AB11 AB9 AB5 AA57 AA17 AA15 AA12 Y65 Y63 Y61 Y7 Y3 Y1 W57 V16 V14 V11 V9 V5 U64 U62 U60 U57 T7 T3 T1 R57 R50 R44 R38 R31 R25 R19 R17 R15 R12 P65 P63 P61 P11 P9 P5 N54 N47 N41 N35 N28 N22 M57 M50 M44 M38 M31 M25 M19 M7 M3 M1 L64 L62 L60 L58 L54 L50 L46 L42 L36 L30 L24
AW16 AV65 AV63 AV59 AV57 AV50 AV44 AV38 AV31 AV25 AV19 AV9 AV5 AU54 AU47 AU41 AU35 AU28 AU22 AU16 AU14 AT61 AT57 AT50 AT44 AT38 AT31 AT25 AT19 AT11 AT7 AT3 AT1 AR54 AR47 AR41 AR35 AR28 AR22 AP65 AP63 AP57 AP50 AP44 AP38 AP31 AP25 AP19 AP17 AP15 AP12 AP11 AP9 AP5 AN54 AN47 AN41 AN35 AN28 AN22 AM61 AM7 AM3 AM1 AL57 AL50 AL44 AL38 AL31 AL25 AL19 AK16 AK14 AK11 AK9 AK5 AJ64 AJ62 AJ60 AJ57 AH7 AH3 AH1 AG57 AG17 AG15
VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257
U1000 SANDY-BRIDGE MOBILE-REV1 BGA (11 Of 11)
OMIT
5
VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343
L20 L16 L12 L8 K39 K33 K27 K1 J64 J60 J56 J52 J48 J46 J42 J36 J30 J24 J22 J18 J14 J10 J6 H39 H33 H27 H3 G62 G58 G54 G50 G46 G42 G36 G30 G24 G20 G16 G12 G8 F39 F33 F27 E60 E56 E52 E48 E46 E42 E36 E30 E24 E22 E18 E14 E10 E6 E4 D63 D39 D33 D27 C58 C54 C50 C46 C42 C36 C30 C20 C16 C12 C8 B39 B33 B27 A56 A52 A42 A36 A30 A24 A20 A16 A12 A8
4
3
2
1
D 68 48 15 12 7
PPVCORE_S0_AXG
PP1V5_S3RS0_CPUDDR AH65 AH63 AH61 AH58 AH56 AG64 AG62 AG60 AF58 AF56 AE64 AE62 AE60 AD65 AD63 AD61 AD58 AD56 AB65 AB63 AB61 AB58 AB56 AA64 AA62 AA60 Y58 Y56 W64 W62 W60 V65 V63 V61 V58 V56 T65 T63 T61 T58 T56 R64 R62 R60 R55 R53 R48 N64 N62 N60 N58 N56 N52 N49 M65 M63 M61 M59 M55 M53 M48 L56 L52 L48
VAXG_0 VAXG_1 VAXG_2 VAXG_3 VAXG_4 VAXG_5 VAXG_6 VAXG_7 VAXG_8 VAXG_9 VAXG_10 VAXG_11 VAXG_12 VAXG_13 VAXG_14 VAXG_15 VAXG_16 VAXG_17 VAXG_18 VAXG_19 VAXG_20 VAXG_21 VAXG_22 VAXG_23 VAXG_24 VAXG_25 VAXG_26 VAXG_27 VAXG_28 VAXG_29 VAXG_30 VAXG_31 VAXG_32 VAXG_33 VAXG_34 VAXG_35 VAXG_36 VAXG_37 VAXG_38 VAXG_39 VAXG_40 VAXG_41 VAXG_42 VAXG_43 VAXG_44 VAXG_45 VAXG_46 VAXG_47 VAXG_48 VAXG_49 VAXG_50 VAXG_51 VAXG_52 VAXG_53 VAXG_54 VAXG_55 VAXG_56 VAXG_57 VAXG_58 VAXG_59 VAXG_60 VAXG_61 VAXG_62 VAXG_63
U1000 SANDY-BRIDGE MOBILE-REV1 BGA (8 OF 11)
OMIT
IO POWER DDR3
D
BJ56 BJ52 BJ48 BJ40 BJ32 BJ24 BJ20 BJ16 BJ12 BJ8 BG60 BG56 BG52 BG48 BG44 BG36 BG28 BG24 BG20 BG16 BG12 BG8 BF5 BE62 BE58 BE54 BE50 BE46 BE42 BE38 BE34 BE30 BE26 BE22 BE18 BE14 BE10 BD35 BD7 BD3 BC60 BC56 BC52 BC48 BC44 BC40 BC36 BC32 BC28 BC26 BC24 BC20 BC16 BC12 BB65 BB63 BB47 BB39 BB9 BB5 BA58 BA54 BA50 BA46 BA42 BA38 BA34 BA30 BA26 BA22 BA18 BA14 AY61 AY11 AY7 AY3 AY1 AW56 AW52 AW48 AW44 AW40 AW36 AW32 AW28 AW24
7
GRAPHIC CORE POWER
8
VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20 VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25 VDDQ_26 VDDQ_27 VDDQ_28 VDDQ_29 VDDQ_30 VDDQ_31 VDDQ_32 VDDQ_33 VDDQ_34 VDDQ_35 VDDQ_36 VDDQ_37 VDDQ_38 VDDQ_39 VDDQ_40 VDDQ_41 VDDQ_42 VDDQ_43 VDDQ_44 VDDQ_45 VDDQ_46 VDDQ_47 VDDQ_48 VDDQ_49 VDDQ_50 VDDQ_51 VDDQ_52 VDDQ_53 VDDQ_54 VDDQ_55 VDDQ_56 VDDQ_57 VDDQ_58 VDDQ_59 VDDQ_60 VDDQ_61 VDDQ_62 VDDQ_63 VDDQ_64 VDDQ_65 VDDQ_66 VDDQ_67 VDDQ_68
BJ36 BJ28 BG40 BG32 BD47 BD43 BD39 BD31 BD23 BB35 AY47 AY43 AY39 AY35 AY31 AY27 AY23 AV46 AV42 AV40 AV36 AV34 AV29 AV27 AU45 AU43 AU39 AU37 AU33 AU30 AU26 AU24 AT46 AT42 AT40 AT36 AT34 AT29 AT27 AR45 AR43 AR39 AR37 AR33 AR30 AR26 AR24 AP46 AP42 AP40 AP36 AP34 AP29 AP27 AN45 AN43 AN39 AN37 AN33 AN30 AN26 AN24 AL46 AL42 AL40 AL36 AL34 AL29 AL27
7 10 15 29 71 72
PP1V05_S0
PP1V05_S0
101 72 17 16 14 13 12 10 9 7 6 69 67 44 39 35 23 22 20
AV55 AV53 AV48 AV17 AV15 AV12 AU58 AU56 AU52 AU49 AU20 AU18 AT55 AT53 AT48 AT17 AT15 AT12 AR58 AR56 AR52 AR49 AR20 AR18 AR16 AR14 AP55 AP53 AP48 AN58 AN56 AN52 AN49
VCCIO_0 U1000 VCCIO_1 SANDY-BRIDGE VCCIO_2 MOBILE-REV1 VCCIO_3 BGA VCCIO_4 (7 OF 11) IO POWER VCCIO_5 VCCIO_6 VCCIO_7 OMIT VCCIO_8 VCCIO_9 VCCIO_10 VCCIO_11 VCCIO_12 VCCIO_13 VCCIO_14 VCCIO_15 VCCIO_16 VCCIO_17 VCCIO_18 VCCIO_19 VCCIO_20 VCCIO_21 VCCIO_22 VCCIO_23 VCCIO_24 VCCIO_25 VCCIO_26 VCCIO_27 VCCIO_28 VCCIO_29 VCCIO_30 VCCIO_31 VCCIO_32
VCCIO_33 VCCIO_34 VCCIO_35 VCCIO_36 VCCIO_37 VCCIO_38 VCCIO_39 VCCIO_40 VCCIO_41 VCCIO_42 VCCIO_43 VCCIO_44 VCCIO_45 VCCIO_46 VCCIO_47 VCCIO_48 VCCIO_49 VCCIO_50 VCCIO_51 VCCIO_52 VCCIO_53 VCCIO_54 VCCIO_55 VCCIO_56 VCCIO_57 VCCIO_58 VCCIO_59 VCCIO_60 VCCIO_61 VCCIO_62 VCCIO_63 VCCIO_64 VCCIO_65
67 69 72 101 6 7 9 10 12 13 14 16 17 20 22 23 35 39 44
AN20 AN18 AN16 AN14 AM11 AL55 AL53 AL48 AL17 AL15 AL12 AK58 AK56 AJ17 AJ15 AJ12 AH16 AH14 AH11 AF16 AF14 AE17 AE15 AE12 AD11 AC17 AC15 AC12 AB16 AB14 Y16 Y14 Y11
C
B
A PAGE TITLE
CPU POWER AND GND DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
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6
5
4
3
2
BRANCH
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14 OF 132 SHEET
13 OF 101
1
8
7
6
5
4
3
2
1
CPU VCORE DECOUPLING Intel recommendation: 4x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 16x 22uF 0805, 4x 10uF 0603, 20x 1uF 0402, 28x 1uF 0402 (NOSTUFF) Apple Implementation: 4x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 16x 22uF 0603, 4x 10uF 0402, 20x 1uF 0402, 28x 1uF 0201 (NOSTUFF), 4x 22uF 0603 (NOSTUFF) PLACEMENT_NOTE (C1600-C16C7): 101 68 48 12 7 6
PPVCORE_S0_CPU
Place on bottom side of U1000 U100. 1
C1600
1
1UF
D
1
1UF
1
1
1UF
1
1
1UF
20% 2 6.3V X5R 0201
NOSTUFF
C16C3
1
1UF
20% 2 6.3V X5R 0201
NOSTUFF
C16C4
20% 2 6.3V X5R 0201
1
1UF
20% 6.3V 2 X5R 0201
1
1
1UF
1
1
1
1
1
20% 6.3V 2 X5R 0201
1
1
C16B3 1UF
20% 2 6.3V X5R 0201
1
C16B4 1UF
20% 6.3V 2 X5R 0201
1
C16B5 1UF
20% 2 6.3V X5R 0201
1
1
1UF
C16B7 1UF
20% 2 6.3V X5R 0201
1
20% 6.3V 2 X5R 0201
D
10% 10V 2 X5R 402
NOSTUFF 1
C1619 1UF
10% 10V 2 X5R 402
NOSTUFF
C16B6
C1618 1UF
10% 2 10V X5R 402
NOSTUFF 1
C1617 1UF
10% 2 10V X5R 402
NOSTUFF 1
C1616 1UF
10% 2 10V X5R 402
NOSTUFF 1
C1615 1UF
10% 10V 2 X5R 402
NOSTUFF
C16B2
C1614 1UF
10% 2 10V X5R 402
1UF
20% 2 6.3V X5R 0201
C1613 1UF
NOSTUFF
C16B1 1UF
20% 2 6.3V X5R 0201
1
10% 10V 2 X5R 402
NOSTUFF
C16B0
C1612 1UF
10% 10V 2 X5R 402
1UF
20% 6.3V 2 X5R 0201
C1611 1UF
NOSTUFF
C16A9 1UF
20% 6.3V 2 X5R 0201
1
10% 2 10V X5R 402
NOSTUFF
C16A8
C1610 1UF
10% 2 10V X5R 402
NOSTUFF
C16B8
1
1UF
C16B9 1UF
20% 2 6.3V X5R 0201
20% 6.3V 2 X5R 0201
NOSTUFF
C16C6
C16C7
1
1UF
20% 2 6.3V X5R 0201
1
C1609 1UF
NOSTUFF
C16A7
20% 6.3V 2 X5R 0201
NOSTUFF
C16C5
1
1UF
1
10% 10V 2 X5R 402
1UF
20% 2 6.3V X5R 0201
C1608 1UF
NOSTUFF 1
1UF
20% 6.3V 2 X5R 0201
1
10% 2 10V X5R 402
C16A6
1
C1607 1UF
NOSTUFF
C16A5 1UF
20% 2 6.3V X5R 0201
NOSTUFF
C16C2
1
1
10% 2 10V X5R 402
NOSTUFF
C16A4
C1606 1UF
10% 10V 2 X5R 402
1UF
20% 6.3V 2 X5R 0201
NOSTUFF
C16C1
1
1
1UF
NOSTUFF
C16A3
C1605
1
10% 10V 2 X5R 402
1UF
20% 2 6.3V X5R 0201
1UF
20% 2 6.3V X5R 0201
1
C1604 1UF
NOSTUFF
C16A2
NOSTUFF
C16C0
1
10% 2 10V X5R 402
1UF
20% 2 6.3V X5R 0201
C1603 1UF
NOSTUFF
C16A1
NOSTUFF
1
10% 2 10V X5R 402
1UF
20% 6.3V 2 X5R 0201
C1602 1UF
NOSTUFF
C16A0
1
1
10% 10V 2 X5R 402
NOSTUFF 1
C1601 1UF
10% 2 10V X5R 402
1UF
20% 2 6.3V X5R 0201
20% 6.3V 2 X5R 0201
PLACEMENT_NOTE (C1620-C1623): Place near U1000 on bottom side CRITICAL CRITICAL CRITICAL CRITICAL 1
C1620
1
10UF
C
C1621
1
10UF
20% 2 6.3V CERM-X5R 0402-1
C1622
1
10UF
20% 2 6.3V CERM-X5R 0402-1
C1623 10UF
20% 2 6.3V CERM-X5R 0402-1
20% 2 6.3V CERM-X5R 0402-1
C
PLACEMENT_NOTE (C1624-C16D5): Place nearPlace inductors nearPlace inductors on bottom near inductors on side. bottom on side. bottom side. CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL 1
C1624
1
22UF
C1625
1
22UF
20% 6.3V 2 X5R-CERM1 0603
C1626
1
22UF
20% 6.3V 2 X5R-CERM1 0603
C1627 22UF
20% 2 6.3V X5R-CERM1 0603
C1628
1
1
22UF
20% 6.3V 2 X5R-CERM1 0603
C1629 22UF
20% 2 6.3V X5R-CERM1 0603
CRITICAL 1
C1630 22UF
20% 2 6.3V X5R-CERM1 0603
CRITICAL 1
C1631 22UF
20% 6.3V 2 X5R-CERM1 0603
CRITICAL 1
CRITICAL
C1632
1
22UF
20% 6.3V 2 X5R-CERM1 0603
C1633 22UF
20% 2 6.3V X5R-CERM1 0603
CRITICAL 1
C1634 22UF
20% 2 6.3V X5R-CERM1 0603
CRITICAL 1
CRITICAL
C1635
1
22UF
20% 2 6.3V X5R-CERM1 0603
C1636 22UF
20% 6.3V 2 X5R-CERM1 0603
20% 6.3V 2 X5R-CERM1 0603
CRITICAL 1
C1637 22UF
20% 6.3V 2 X5R-CERM1 0603
CRITICAL 1
C1638 22UF
20% 2 6.3V X5R-CERM1 0603
CRITICAL 1
NOSTUFF
C1639
1
22UF
NOSTUFF
C16D0
1
22UF
20% 2 6.3V X5R-CERM1 0603
NOSTUFF
C16D1
1
22UF
20% 2 6.3V X5R-CERM1 0603
NOSTUFF
C16D2
1
22UF
20% 6.3V 2 X5R-CERM1 0603
C16D3 22UF
20% 6.3V 2 X5R-CERM1 0603
20% 6.3V 2 X5R-CERM1 0603
NOSTUFF 1
C16D4 22UF
20% 6.3V 2 X5R-CERM1 0603
NOSTUFF 1
C16D5 22UF
20% 2 6.3V X5R-CERM1 0603
PLACEMENT_NOTE (C1640-C1645): Place near inductors on bottom side. CRITICAL CRITICAL CRITICAL 1
C1640
C1641
1
470UF-4MOHM
3
20% 2 2.0V POLY-TANT D2T-SM
1
470UF-4MOHM
20% 2 2.0V POLY-TANT D2T-SM
3
CRITICAL
C1642
1
470UF-4MOHM
20% 2 2.0V POLY-TANT D2T-SM
3
NOSTUFF
C1643
1
470UF-4MOHM
3
20% 2 2.0V POLY-TANT D2T-SM
C1644
470UF-4MOHM
3
20% 2 2.0V POLY-TANT D2T-SM
CPU VCCIO/VCCPQ DECOUPLING Intel recommendation: 2x 330uF, 10x 10uF 0603, 26x 1uF
0402 Apple Implementation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402
PLACEMENT_NOTE (C1646-C1671):
B
101 39 35 23 22 12 10 9 7 6 20 17 16 13 72 69 67 44
PP1V05_S0
CPU VCCPLL DECOUPLING
Place on bottom side of U1000 U100. 1
C1646 1UF
10% 2 10V X5R 402
1
C1647
1
1UF
C1648
1
1UF
10% 2 10V X5R 402
C1649
1
1UF
10% 2 10V X5R 402
C1650
1
1UF
10% 2 10V X5R 402
C1651
1
1UF
10% 2 10V X5R 402
C1652
1
1UF
C1653
1
1UF
10% 2 10V X5R 402
10% 2 10V X5R 402
C1654
1
1UF
10% 2 10V X5R 402
C1655
1
1UF
10% 2 10V X5R 402
C1656
1
1UF
10% 2 10V X5R 402
C1657
1
1UF
10% 2 10V X5R 402
C1658 1UF
10% 2 10V X5R 402
87 71 70 25 22 20 17 7 6
R1600 PP1V8_S0
10% 2 10V X5R 402
1
0
PP1V8_S0_CPU_VCCPLL_R
B
7 12
2
CRITICAL
5% 1/16W MF-LF 402
1
2 PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA
C1685
1
C1686
1UF
1UF
10% 10V X5R 402
10% 10V X5R 402
2
1
C1687
330UF-0.006OHM 20% 2V
2 POLY
CASE-D2-SM PLACE_NEAR=U1000.AK61:5 mm
PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA
1
C1659 1UF
10% 2 10V X5R 402
1
C1660
1
1UF
C1661 1UF
10% 2 10V X5R 402
1
C1662
1
1UF
10% 2 10V X5R 402
C1663
1
1UF
10% 2 10V X5R 402
C1664
1
1UF
10% 2 10V X5R 402
C1665
1
1UF
10% 2 10V X5R 402
C1666
1
1UF
10% 2 10V X5R 402
C1667
1
1UF
10% 2 10V X5R 402
C1668 1UF
10% 2 10V X5R 402
10% 2 10V X5R 402
1
C1669 1UF
10% 2 10V X5R 402
1
C1670 1UF
10% 2 10V X5R 402
1
C1671
CPU VCCPLL Low pass filter
1UF
10% 2 10V X5R 402
PLACEMENT_NOTE (C1672-C1681): Place near U1000 on bottom side CRITICAL CRITICAL CRITICAL CRITICAL 1
C1672
1
10UF
20% 2 6.3V X5R 603
C1673 10UF
20% 6.3V 2 X5R 603
1
C1674 10UF
20% 6.3V 2 X5R 603
1
C1675 10UF
20% 2 6.3V X5R 603
CRITICAL 1
C1676 10UF
20% 2 6.3V X5R 603
CRITICAL 1
C1677 10UF
20% 6.3V 2 X5R 603
CRITICAL 1
C1678 10UF
20% 6.3V 2 X5R 603
CRITICAL 1
C1679 10UF
20% 2 6.3V X5R 603
CRITICAL
1
C1680 10UF
20% 6.3V 2 X5R 603
CRITICAL 1
C1681 10UF
20% 6.3V 2 X5R 603
Place near inductors on bottom side CRITICAL 1
C1682
1
C1683
330UF-0.006OHM 330UF-0.006OHM
A
2
20% 2V POLY CASE-D2-SM
20% 2V
2 POLY
CASE-D2-SM
SYNC_MASTER=K92_MLB
CRITICAL
SYNC_DATE=08/19/2010
PAGE TITLE
CPU DECOUPLING-I Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
DRAWING NUMBER
R1601 0.0102 1
Apple Inc. PP1V05_S0_CPU_VCCPQE
1% 1/4W MF 0603
1
7 10 12
C1684
NOTICE OF PROPRIETARY PROPERTY:
1UF
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
10% 10V 402
7
D
R
2 X5R
8
SIZE
REVISION
6
5
4
3
2
BRANCH
PAGE
16 OF 132 SHEET
14 OF 101
1
A
8
7
6
5
4
3
2
1
VAXG DECOUPLING Intel recommendation: 2x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 6x 22uF 0805, 2x 22uF 0805 (NOSTUFF), 6x 10uF 0603, 2x 10uF 0603 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF) Apple Implementation: 2x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 6x 22uF 0603, 2x 22uF 0603 (NOSTUFF), 6x 10uF 0402, 2x 10uF 0402 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF) PLACEMENT_NOTE (C1700-C1708): 68 48 13 12 7
PPVCORE_S0_AXG
Place on bottom side of U1000 U100.
D
NOSTUFF 1
C1700
1
1UF
C1701
1
1UF
10% 2 10V X5R 402
C1702
1
1UF
10% 2 10V X5R 402
C1703
10% 2 10V X5R 402
C1704
1
1UF
10% 2 10V X5R 402
C1705
1
1UF
10% 2 10V X5R 402
C1706
1
1UF
10% 2 10V X5R 402
C1707
1
1UF
1
1UF
1UF
10% 2 10V X5R 402
10% 2 10V X5R 402
C1708
1
NOSTUFF
C1709 1UF
10% 2 10V X5R 402
1
1UF
10% 2 10V X5R 402
10% 2 10V X5R 402
NOSTUFF
C1710
1
C1711 1UF
10% 10V 2 X5R 402
NOSTUFF 1
C1712 1UF
10% 10V 2 X5R 402
NOSTUFF 1
C1713 1UF
NOSTUFF 1
C1714 1UF
10% 2 10V X5R 402
NOSTUFF 1
C1715 1UF
10% 2 10V X5R 402
NOSTUFF 1
C1716 1UF
10% 2 10V X5R 402
D
NOSTUFF 1
C1717 1UF
10% 2 10V X5R 402
10% 2 10V X5R 402
PLACEMENT_NOTE (C1718-C1723): Place close to U1000 on bottom side NOSTUFF 1
C1718
1
10UF
C1719
C1720
1
10UF
20% 6.3V 2 CERM-X5R 0402-1
C1721
1
10UF
20% 6.3V 2 CERM-X5R 0402-1
C1722
1
10UF
20% 6.3V 2 CERM-X5R 0402-1
C1723
1
10UF
20% 6.3V 2 CERM-X5R 0402-1
1
10UF
20% 6.3V 2 CERM-X5R 0402-1
NOSTUFF
C1724
1
10UF
20% 6.3V 2 CERM-X5R 0402-1
C1725 10UF
20% 6.3V 2 CERM-X5R 0402-1
20% 6.3V 2 CERM-X5R 0402-1
PLACEMENT_NOTE (C1726-C1731): Place near inductors on bottom side. 1
C1726
1
22UF
C1727
1
22UF
20% 2 6.3V X5R-CERM1 0603
C1728
1
22UF
20% 2 6.3V X5R-CERM1 0603
20% 6.3V 2 X5R-CERM1 0603
C1729
1
22UF
20% 6.3V 2 X5R-CERM1 0603
C1730
1
22UF
20% 2 6.3V X5R-CERM1 0603
NOSTUFF 1
C1731
NOSTUFF
C1732
22UF
20% 2 6.3V X5R-CERM1 0603
1
22UF
20% 6.3V 2 X5R-CERM1 0603
C1733 22UF
20% 2 6.3V X5R-CERM1 0603
PLACEMENT_NOTE (C1734-C1735): Place near inductors on bottom side.
C
C
NOSTUFF 1
C1734
1
470UF-4MOHM
20% 2 2.0V POLY-TANT D2T-SM
3
C1735
1
470UF-4MOHM
3
20% 2 2.0V POLY-TANT D2T-SM
C1737
470UF-4MOHM
20% 2 2.0V POLY-TANT D2T-SM
3
CPU VCCSA DECOUPLING
CPU VDDQ/VCCDQ DECOUPLING
Intel recommendation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402 Apple Implementation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402
Intel recommendation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402 Apple Implementation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402
PLACEMENT_NOTE (C1758-C1762):
PLACEMENT_NOTE (C1738-C1747): 72 71 29 13 10 7
PP1V5_S3RS0_CPUDDR
Place on bottom side of U1000 U100. 1
C1738 1UF
10% 2 10V X5R 402
1
C1739
1
1UF
64 12 7
C1740
1
1UF
C1741 1UF
10% 2 10V X5R 402
10% 2 10V X5R 402
10% 2 10V X5R 402
1
C1742 1UF
10% 2 10V X5R 402
1
C1743
1
1UF
C1744
1
1UF
10% 2 10V X5R 402
C1745 1UF
10% 2 10V X5R 402
10% 2 10V X5R 402
1
C1746 1UF
10% 10V 2 X5R 402
1
PPVCCSA_S0_REG
Place on bottom side of U1000 U100.
C1747
1
1UF
C1758 1UF
10% 2 10V X5R 402
10% 2 10V X5R 402
1
C1759
1
1UF
C1760
1
1UF
10% 2 10V X5R 402
C1761 1UF
10% 2 10V X5R 402
10% 2 10V X5R 402
1
C1762 1UF
10% 2 10V X5R 402
Place close to U1000 on bottom side 1
C1748 10UF
20% 6.3V 2 X5R 603
B
1
C1749
1
10UF
C1750 10UF
20% 6.3V 2 X5R 603
1
C1751 10UF
20% 2 6.3V X5R 603
20% 2 6.3V X5R 603
1
C1752 10UF
20% 6.3V 2 X5R 603
1
C1753 10UF
20% 6.3V 2 X5R 603
1
C1754 10UF
1
C1755 10UF
20% 2 6.3V X5R 603
20% 6.3V 2 X5R 603
1
10UF
20% 2 6.3V X5R 603
Place near inductors on bottom side 1
C1763
1
C1764 10UF
20% 2 6.3V X5R 603
1
C1765 10UF
20% 6.3V 2 X5R 603
1
C1766 10UF
20% 6.3V 2 X5R 603
1
C1767 10UF
B
20% 2 6.3V X5R 603
C1756 330UF-0.006OHM 20% 2V
1
2 POLY
C1768 270UF
CASE-D2-SM
20% 2 2V TANT CASE-B4-SM
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
R1700 0.0102
1
1% 1/4W MF 0603
PP1V5_S3_CPU_VCCDQ 1
7 12
C1757 1UF 10% 10V
2 X5R 402
A
SYNC_MASTER=K92_MLB
SYNC_DATE=08/19/2010
PAGE TITLE
CPU DECOUPLING-II DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
17 OF 132 SHEET
15 OF 101
1
A
7
6
K22
INTRUDER*
PCH_INTVRMEN_L
C17
INTVRMEN
93 16
HDA_BIT_CLK_R
N34
HDA_BCLK
93 16
HDA_SYNC_R
L34
HDA_SYNC
6 6
IN
23
23
23
C
23
93 46
93 46
K34 E34 G34 C34 A34 A36
HDA_SDOUT_R
93 16
OUT
HDA_RST_R_L HDA_SDIN0 NC_HDA_SDIN1 NC_HDA_SDIN2 NC_HDA_SDIN3
IN 6
25
T10
C36 N32
JTAG_T29_TMS ENET_MEDIA_SENSE_RDIV
IN
XDP_PCH_TCK
IN
XDP_PCH_TMS
J3 H7
HDA_RST* HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3
HDA_DOCK_EN*/GPIO33 HDA_DOCK_RST*/GPIO13
JTAG_TCK JTAG_TMS
XDP_PCH_TDI
K5
JTAG_TDI
OUT
XDP_PCH_TDO
H1
JTAG_TDO
T3
SPI_CLK_R SPI_CS0_R_L
OUT
TP_SPI_CS1_L
SPI_CLK
Y14
SPI_CS0*
T1
SPI_CS1*
93 46
OUT
SPI_MOSI_R
V4
SPI_MOSI
93 46
IN
SPI_MISO
U3
SPI_MISO
MF
1 5% 1/20W
MF
MF
1 5% 1/20W
MF
1 5% 1/20W
201
MF
6 44 46 87 93
BI
6 44 46 87 93
201
1
10K
BI
6 44 46 87 93
5% 1/20W MF 201
OUT
6 44 46 87 93
2
93 36
IN
93 36
IN
93 36
OUT
93 36
OUT
93 31 6 6 44 46
BI
AM3 AM1 AP7 AP5
SATA_HDD_D2R_N SATA_HDD_D2R_P SATA_HDD_R2D_C_N SATA_HDD_R2D_C_P
SATA1RXN SATA1RXP SATA1TXN SATA1TXP
AM10 AM8 AP11 AP10
SATA_ODD_D2R_N SATA_ODD_D2R_P SATA_ODD_R2D_C_N SATA_ODD_R2D_C_P
SATA2RXN SATA2RXP SATA2TXN SATA2TXP
AD7 AD5 AH5 AH4
TP_SATA_C_D2RN TP_SATA_C_D2RP TP_SATA_C_R2D_CN TP_SATA_C_R2D_CP
SATA3RXN SATA3RXP SATA3TXN SATA3TXP
AB8 AB10 AF3 AF1
NC_SATA_D_D2RN NC_SATA_D_D2RP NC_SATA_D_R2D_CN NC_SATA_D_R2D_CP
SATA4RXN SATA4RXP SATA4TXN SATA4TXP
Y7 Y5 AD3 AD1
NC_SATA_E_D2RN NC_SATA_E_D2RP NC_SATA_E_R2D_CN NC_SATA_E_R2D_CP
SATA5RXN SATA5RXP SATA5TXN SATA5TXP
Y3 Y1 AB3 AB1
NC_SATA_F_D2RN NC_SATA_F_D2RP NC_SATA_F_R2D_CN NC_SATA_F_R2D_CP 92
MF 1% 1/20W
OUT (IPU) 19
LPC_SERIRQ
SATAICOMPO Y11 SATAICOMPI Y10
1% 1/20W MF 201
R1820
6 44 46 87 93
IN
41 92
93 31
IN OUT
93 31
OUT
93 38
IN
IN
41 92
93 38
IN
41 92
93 38
OUT
OUT
41 92
93 38
OUT
IN
41 92
8
IN
41 92
8
IN
OUT
41 92
8
OUT
41 92
8
OUT
IN
SATALED* P3
PERN1 PERP1 PETN1 PETP1
PCIE_AP_D2R_N PCIE_AP_D2R_P PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P
BE34 BF34 BB32 AY32
PERN2 PERP2 PETN2 PETP2
PCIE_FW_D2R_N PCIE_FW_D2R_P PCIE_FW_R2D_C_N PCIE_FW_R2D_C_P
BG36 BJ36 AV34 AU34
PERN3 PERP3 PETN3 PETP3
NC_PCIE_EXCARD_D2R_N NC_PCIE_EXCARD_D2R_P NC_PCIE_EXCARD_R2D_C_N NC_PCIE_EXCARD_R2D_C_P
BF36 BE36 AY34 BB34
PERN4 PERP4 PETN4 PETP4
NC_PCIE_5_D2RN NC_PCIE_5_D2RP NC_PCIE_5_R2D_CN NC_PCIE_5_R2D_CP
BG37 BH37 AY36 BB36
PERN5 PERP5 PETN5 PETP5
NC_PCIE_6_D2RN NC_PCIE_6_D2RP NC_PCIE_6_R2D_CN NC_PCIE_6_R2D_CP
BJ38 BG38 AU36 AV36
PERN6 PERP6 PETN6 PETP6
6 6
6 6 6 6
6 6 6 6
PP1V05_S0 16
DP_AUXCH_ISOL
OUT
SATARDRVR_EN
OUT
(IPU)
92
BG34 BJ34 AV32 AU32
6
PCH_SATALED_L
SATA0GP/GPIO21 V14 SATA1GP/GPIO19 P1
PCIE_ENET_D2R_N PCIE_ENET_D2R_P PCIE_ENET_R2D_C_N PCIE_ENET_R2D_C_P
6
PCH_SATAICOMP
SATA3COMPI AB13 SATA3RCOMP0 AB12 SATA3RBIAS AH1
R18311
16 23 84 16 23 41
49.9 1% 1/20W MF 201
PLACE_NEAR=U1800.AB12:2.54mm PCH_SATA3COMP PCH_SATA3RBIAS
93 36
OUT
BG40 BJ40 AY40 BB40
PERN7 PERP7 PETN7 PETP7
NC_PCIE_8_D2RN NC_PCIE_8_D2RP NC_PCIE_8_R2D_CN NC_PCIE_8_R2D_CP
BE38 BC38 AW38 AY38
PERN8 PERP8 PETN8 PETP8
FCBGA (2 OF 10) OMIT
PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P
AB49 AB47
CLKOUT_PCIE1N CLKOUT_PCIE1P
AA48 AA47
CLKOUT_PCIE2N CLKOUT_PCIE2P
B
R1843 10K 25 20 17 7
5% 1/20W MF 201
PPVRTC_G3H
R1800 1
1
330K 5% 1/20W MF 201
R1802 1 R1801 20K 5% 1M
2
2
5% 1/20W MF 201
1/20W MF 201
1
10K
10K
5% 1/20W MF 201
5% 1/20W MF 201
2
2
2
R1877
10K
4.7K
10K
5% 1/20W MF 201
5% 1/20W MF 201
5% 1/20W MF 201
5% 1/20W MF 201
2
2
2
2
2
2
5% 1/20W MF 201
1
1
2
2
16
16 71 61 60 56 53 51 50 49 48 47 16 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
PP3V3_SUS
71 70 45 22 20 19 18 17 16 7 72
10K
10K
5% 1/20W MF 201
5% 1/20W MF 201
2
93 16 93 16 93 16
8
CLKIN_DMI_N BF18 CLKIN_DMI_P BE18
PCIE_CLK100M_PCH_N PCIE_CLK100M_PCH_P
IN
16 93
IN
16 93
PCH_CLK96M_DOT_N PCH_CLK96M_DOT_P
IN
16 93
IN
16 93
PCH_CLK100M_SATA_N PCH_CLK100M_SATA_P
IN
16 93
IN
16 93
PCH_CLK14P3M_REFCLK
IN
16 93
PCH_CLK33M_PCIIN
IN
25 93
CLKIN_DOT_96N G24 CLKIN_DOT_96P E24 CLKIN_SATA_N AK7 CLKIN_SATA_P AK5
PCIE_CLK100M_T29_N PCIE_CLK100M_T29_P
Y43 Y45
CLKOUT_PCIE4N CLKOUT_PCIE4P
XCLK_RCOMP Y47
PCH_XCLK_RCOMP
NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5P
V45 V46
CLKOUT_PCIE5N CLKOUT_PCIE5P
CLKOUTFLEX0/GPIO64 K43
NC_PCH_GPIO64_CLKOUTFLEX0
8
PCIECLKRQ5_L_GPIO44
L14
PCIECLKRQ5*/GPIO44
CLKOUTFLEX1/GPIO65 F47
NC_PCH_GPIO65_CLKOUTFLEX1
8
CLKOUTFLEX2/GPIO66 H47
NC_PCH_GPIO66_CLKOUTFLEX2
8
CLKOUTFLEX3/GPIO67 K49
NC_PCH_GPIO67_CLKOUTFLEX3
8
OUT
93 33
OUT
AB42 AB40
NC_PCIE_CLK100M_PEBN NC_PCIE_CLK100M_PEBP
DOES THIS NEED LENGTH MATCH???
CLKOUT_PEG_B_N CLKOUT_PEG_B_P
IN
T29_CLKREQ_L
PCIECLKRQ0*/GPIO73 PCIECLKRQ1*/GPIO18 PCIECLKRQ3*/GPIO25 PCIECLKRQ4*/GPIO26
IN
PEG_CLKREQ_L PEG_B_CLKRQ_L_GPIO56
M10 E6
PEG_A_CLKRQ*/GPIO47 PEG_B_CLKRQ*/GPIO56
IN
31 23 16
IN
16
IN
ENET_CLKREQ_L AP_CLKREQ_L EXCARD_CLKREQ_L
35 16
87 16 8
16
REFCLK14IN K45 CLKIN_PCILOOPBACK H45
J2 M1 A8 L12
36 16
CLKOUT_ITPXDP_N AK14 CLKOUT_ITPXDP_P AK13
PP1V5_S0
C
B
16 23 90 16 23 90
PCH_CLKIN_GNDN1 PCH_CLKIN_GNDP1
CL_CLK1 M7 70 56 41 25 22 20 7
47 93
16
ITPXDP_CLK100M_N ITPXDP_CLK100M_P
CLKIN_GND1_N BJ30 CLKIN_GND1_P BG30
R1840
90 23 16
ITPXDP_CLK100M_P
R1841
2
0
NOSTUFF
R18661 1 5% 1/20W
MF
ITPCPU_CLK100M_N
10 90
1 5% 1/20W
MF
ITPCPU_CLK100M_P
10 90
10K 5% 1/20W MF 201
201
2
0
NOSTUFF 1
NC_CLINK_CLK
6
CL_DATA1 T11
NC_CLINK_DATA
6
CL_RST1* P10
NC_CLINK_RESET_L
6
R1849 10K 5% 1/20W MF 201
2
HDA_SYNC_R HDA_SDOUT_R
2
DP_AUXCH_ISOL
16 23 84
SATARDRVR_EN
16 23 41
R1849 cannot be used w/ VCCSUSHDA on S0 16 93 16 93
PLACE_NEAR=U1800.N34:1.27mm HDA_BIT_CLK_R
1
33 5% 1/20W MF 201
16
93 16
R1811 33 1
R1812 93 16
HDA_RST_R_L
R1897
R1891 1R1892 1R1893 1R1894 1R1895 1R1896 10K
10K
10K
10K
10K
10K
5% 1/20W MF 2 201
5% 1/20W MF 2 201
5% 1/20W MF 2 201
5% 1/20W MF 2 201
5% 1/20W MF 2 201
5% 1/20W MF 2 201
5% 1/20W MF 2 201
93 16
HDA_SDOUT_R
IN
SYSCLK_CLK25M_SB
PP3V3_SUS
OUT
56 93
2
PLACE_NEAR=U1800.A36:1.27mm 33
2
1
R1855
10K
10K
5% 1/20W MF 201
5% 1/20W MF 201
2
2 201
16
1.8V -> 1.1V R1873
1
R1853 10K
2 201
SYNC_MASTER=K91_MLB
SYNC_DATE=10/19/2010
PAGE TITLE
PCH SATA/PCIE/CLK/LPC/SPI DRAWING NUMBER
5% 1/20W MF
Apple Inc.
2 201
SIZE
D REVISION
R
HDA_SDOUT
OUT
56 93
16 16
NOTICE OF PROPRIETARY PROPERTY:
SML_PCH_0_ALERT_L SML_PCH_1_ALERT_L
NOSTUFF 44 19
5% 1/20W MF
2
1
R1813 5% 1/20W MF 201
5
SYSCLK_CLK25M_SB_R
2
1% 1/20W MF
R1854
HDA_RST_L
1
10K
1K
OUT
IN
SMC_SCI_L
R1888
2
0
1 5% 1/20W
MF
16
PCH_GPIO11
UNUSED clock terminations for FCIM MODE
6
604
71 70 45 22 20 19 18 17 16 7 72 56 93
HDA_SYNC
201
7
1
1% 1/16W MF-LF 402
1
2 5% 1/20W MF 201
10K
2
33 1
56 93
5% 1/20W MF 201
PLACE_NEAR=U1800.K34:1.27mm
1
OUT
PLACE_NEAR=U1800.L34:1.27mm
HDA_SYNC_R
R1871
R1872 25
HDA_BIT_CLK
2
1
10K 5% 1/20W MF 201
R1810 93 16
R18701
2
201
1
8
8
OUT
SYSCLK_CLK25M_SB_R
NOSTUFF
PCH_CLK14P3M_REFCLK PCIE_CLK100M_PCH_N PCIE_CLK100M_PCH_P PCH_CLK100M_SATA_N PCH_CLK100M_SATA_P PCH_CLK96M_DOT_N PCH_CLK96M_DOT_P
Q1850 376S0859 376S0859 VGS 0.35~1V
ITPXDP_CLK100M_N
2
PCIECLKRQ5_L_GPIO44
93 16
90 23 16
R18331 R18341
10K
93 16
OUT
XTAL25_IN V47 XTAL25_OUT V49 NC
NOSTUFF NOSTUFF
5% 1/20W MF 201
93 16
NC_PCH_CLKOUT_DPN NC_PCH_CLKOUT_DPP
CLKOUT_PCIE3N CLKOUT_PCIE3P
6
PP3V3_S0
1UF
93 16
10 90
CLKOUT_DP_N AM12 CLKOUT_DP_P AM13
47 93
16
C1803 10% 10V X5R 402
10 90
OUT
Y37 Y36
2
2
OUT
NC_PCIE_CLK100M_EXCARD_N NC_PCIE_CLK100M_EXCARD_P
JTAG_T29_TMS 16 33 PCH_SPKR 16 FW_CLKREQ_L 16 23 39 AP_CLKREQ_L 16 23 31 PCH_SATALED_L 16 EXCARD_CLKREQ_L 16 T29_CLKREQ_L 16 35 PEG_CLKREQ_L 8 16 87 PEG_B_CLKRQ_L_GPIO56 16 ENET_CLKREQ_L 16 36
R18471
A
2
DMI_CLK100M_CPU_N DMI_CLK100M_CPU_P
OUT
R1876
20K
1UF 10% 10V X5R 402
10K 5% 1/20W MF 201
R1842
R1803
RTC_RESET_L PCH_SRTCRST_L PCH_INTRUDER_L PCH_INTVRMEN_L
C1802
10K 5% 1/20W MF 201
R1869
10K
5% 1/20W MF 201
73 93
CLKOUT_DMI_N AV22 CLKOUT_DMI_P AU22
OUT
1
4.7K
73 93
OUT
93 8
6
R1878
OUT
93 8
PP3V3_S0
R18481 R18461 R18451 R18441
PEG_CLK100M_N PEG_CLK100M_P
CLKOUT_PEG_A_N AB37 CLKOUT_PEG_A_P AB38
BI
PCIECLKRQ2*/GPIO20
6
1
OUT
V10
93 33
47 93
SML_PCH_1_CLK SML_PCH_1_DATA
FW_CLKREQ_L
2
47 93
16
IN
PLACE_NEAR=U1800.AH1:2.54mm
1
BI
SML_PCH_1_ALERT_L
OUT
39 23 16
23 26 28 30 41 47 61 88 93
D
OUT
PCIE_CLK100M_FW_N PCIE_CLK100M_FW_P
16
1
SML_PCH_0_CLK SML_PCH_0_DATA
SML1CLK/GPIO58 E14 SML1DATA/GPIO75 M16
2
23 26 28 30 41 47 61 88 93
16
OUT
6
1
BI
SML_PCH_0_ALERT_L
93 38
PP3V3_T29 PP3V3_S0 7 PP3V3_SUS
1
OUT
93 38
OUT
72 71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
SML0ALERT*/GPIO60 A12
SML1ALERT*/PCHHOT*/GPIO74 C13
CLKOUT_PCIE0N CLKOUT_PCIE0P
16
SMBUS_PCH_CLK SMBUS_PCH_DATA
SML0CLK C8 SML0DATA G12
Y40 Y39
PCIE_CLK100M_ENET_N PCIE_CLK100M_ENET_P
201
PCH_GPIO11
SMBCLK H14 SMBDATA C9
OUT
750 5% 1/20W MF 201
OUT
NC_PCIE_7_D2RN NC_PCIE_7_D2RP NC_PCIE_7_R2D_CN NC_PCIE_7_R2D_CP
SMBALERT*/GPIO11 E12
U1800 COUGAR-POINT MOBILE
6 7 9 10 12 13 14 16 17 20 22 23 35 93 31 39 44 67 69 72 101 93 31
R18321 2
93 36
98 89 88 87 84 83 82 79 72 71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 71 70 45 22 20 19 18 17 16
IN
OUT
OUT
1
90.9
37.4
93 31 6
SATA0RXN SATA0RXP SATA0TXN SATA0TXP
R1890
R1830 1
6
T29_PWR_EN_PCH
PP1V05_S0
PLACE_NEAR=U1800.Y47:2.54mm
PLACE_NEAR=U1800.Y11:2.54mm
2
33 LPC_FRAME_L
2
NC_LPC_DREQ0_L
BI
BI
201
33 LPC_AD<3>
2
LPC_FRAME_R_L R1864
201
33 LPC_AD<2>
2
LPC_R_AD<3> R1863
201
33 LPC_AD<1>
2
5% 1/20W
LPC_AD<0>
33
2
R1861
LPC_R_AD<2> R18621
SERIRQ V5
HDA_SDO
IN
OUT
LPC_R_AD<1>
LDRQ0* E36 LDRQ1*/GPIO23 K36
SPKR
1 5% 1/20W
SMBUS
PCH_INTRUDER_L
PCH_SPKR
C38 A38 B37 C37
FWH4/LFRAME* D36
16
93 16
33 16
SRTCRST*
16
16
93 56
RTCRST*
1
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
R1860
PEG
G22
FCBGA (1 OF 10) OMIT
RTC LPC
PCH_SRTCRST_L
COUGAR-POINT MOBILE
IHDA
RTC_RESET_L
16
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
SATA
D
16
D20
U1800
RTCX1 RTCX2
JTAG
NC
A20 C20
SPI
SYSCLK_CLK32K_RTC
IN
2
PP1V05_S0 PP3V3_S0 LPC_R_AD<0>
25
3
FROM CLK BUFFER
6 44 6 25 51 83
4
CLOCK FLEX
39 35 23 22 20 17 16 14 13 12 10 9 7 101 72 69 67 50 49 48 47 23 22 20 19 18 17 16 12 7 45 41 40 39 36 35 32 28 26 82 79 72 71 61 60 56 53 98 89 88 87 84
5
PCI-E*
8
4
3
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
18 OF 132 SHEET
16 OF 101
1
A
8
7 PP3V3_SUS PP1V05_S0
6
5
4
3
2
1
7 16 17 18 19 20 22 45 70 71 72 6 7 9 10 12 13 14 16 20 22 23 35 39 44 67 69 72 101
1
R1905
1
10K
R1900 49.9
PLACE_NEAR=U1800.BJ24:12.7mm
90 9
IN
90 9
IN
90 9
IN
90 9
IN
90 9
IN
90 9
IN
90 9
IN
90 9
IN
90 9
OUT
90 9 6
OUT
90 9
OUT
90 9
OUT
90 9
OUT
90 9 6
OUT
90 9
OUT
90 9
OUT
DMI_N2S_N<0> DMI_N2S_N<1> DMI_N2S_N<2> DMI_N2S_N<3>
BC24 BE20 BG18 BG20
DMI0RXN DMI1RXN DMI2RXN DMI3RXN
DMI_N2S_P<0> DMI_N2S_P<1> DMI_N2S_P<2> DMI_N2S_P<3>
BE24 BC20 BJ18 BJ20
DMI0RXP DMI1RXP DMI2RXP DMI3RXP
DMI_S2N_N<0> DMI_S2N_N<1> DMI_S2N_N<2> DMI_S2N_N<3>
AW24 AW20 BB18 AV18
DMI0TXN DMI1TXN DMI2TXN DMI3TXN
DMI_S2N_P<0> DMI_S2N_P<1> DMI_S2N_P<2> DMI_S2N_P<3>
AY24 AY20 AY18 AU18
DMI0TXP DMI1TXP DMI2TXP DMI3TXP
BH21
PCH_DMI2RBIAS
U1800 FCBGA (3 OF 10) OMIT
DMI2RBIAS
BJ24 BG25
PCH_DMI_COMP
750 1% 1/20W MF
2 201 44 25 6
C
K3
PM_SYSRST_L
IN
DMI_ZCOMP DMI_IRCOMP
SYSTEM POWER MANAGEMENT
R1920
FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7
SYS_RESET*
89 23
IN
PM_PCH_SYS_PWROK
P12
SYS_PWROK
89 19 17
IN
PM_PCH_PWROK
L22
PWROK
B13
DRAMPWROK
APWROK RSMRST*
OUT
SUSWARN_L
K16
SUSWARN*/SUSPWRDNACK/GPIO30
IN
PM_PWRBTN_L
E20
PWRBTN*
R1909
SUSCLK/GPIO62 N14 SLP_S5*/GPIO63 D10
9 90
OUT
6 9 90
IN BI
6 17 44 46
LPC_PWRDWN_L
OUT
6 44 46
PM_CLK32K_SUSCLK_R
OUT
45
OUT
17 44 72
PM_SLP_S4_L
OUT
17 29 42 44 65 72
SLP_S3* F4
PM_SLP_S3_L
OUT
6 17 29 44 72
25 20 16 7
TP_PM_SLP_A_L
TP23 AY16
PP1V8_S0
TP_PCH_TP23
PMSYNCH AP14
OUT
GPIO29_SLP_LAN_L
DF_TVS AY1
PCH_DF_TVS
R1980
17
1K
2
5% 1/20W MF 201
1 5% 1/20W
MF
390K 5% 1/20W MF 201 2
2
CPU_PROC_SEL_L
6 6 6
10 90 6
201 6
2
DSWVRMEN A18 G16 SLP_SUS*
PCH_DSWVRMEN PM_SLP_SUS_L
OUT
SUSACK* C12
PCH_SUSACK_L
IN
6 17 72
6
17
SDVO_TVCLKINN AP43 SDVO_TVCLKINP AP45
NC_SDVO_TVCLKINN NC_SDVO_TVCLKINP
SDVO_STALLN AM42 SDVO_STALLP AM40
NC_SDVO_STALLN NC_SDVO_STALLP
SDVO_INTN AP39 SDVO_INTP AP40
NC_SDVO_INTN NC_SDVO_INTP
SDVO_CTRLCLK P38 SDVO_CTRLDATA M39
DP_IG_DDC_CLK DP_IG_DDC_DATA
DDPB_AUXN AT49 DDPB_AUXP AT47 DDPB_HPD AT40 DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P
DP_IG_AUX_CH_N DP_IG_AUX_CH_P DP_IG_HPD
AV42 AV40 AV45 AV46 AU48 AU47
NC_DP_IG_MLN<0> NC_DP_IG_MLP<0> NC_DP_IG_MLN<1> NC_DP_IG_MLP<1> NC_DP_IG_MLN<2> NC_DP_IG_MLP<2> NC_DP_IG_MLN<3> NC_DP_IG_MLP<3>
AV47 AV49
DDPC_CTRLCLK P46 DDPC_CTRLDATA P42
NC_DP_IG_C_CTRL_CLK NC_DP_IG_C_CTRL_DATA
DDPC_AUXN AP47 DDPC_AUXP AP49 DDPC_HPD AT38 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P
NC_DP_IG_C_AUXN NC_DP_IG_C_AUXP NC_DP_IG_C_HPD
AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49
NC_DP_IG_C_MLN<0> NC_DP_IG_C_MLP<0> NC_DP_IG_C_MLN<1> NC_DP_IG_C_MLP<1> NC_DP_IG_C_MLN<2> NC_DP_IG_C_MLP<2> NC_DP_IG_C_MLN<3> NC_DP_IG_C_MLP<3>
DDPD_CTRLCLK M43 DDPD_CTRLDATA M36
1 R1915
2.2K 10 90
FCBGA (4 OF 10) OMIT
6 7 14 20 22 25 70 71 87
R1981
PM_SYNC
U1800 COUGAR-POINT MOBILE
PPVRTC_G3H
1
100K 5% 1/20W MF 201
6 17 25 31 84
PM_SLP_S5_L
SLP_LAN*/GPIO29 K14
1
9 90
SLP_S4* H4
SLP_A* G10
RI*
9 90
PM_CLKRUN_L
SUS_STAT*/GPIO61 G8
C21
A10
9 90 9 90
PCIE_WAKE_L
CLKRUN*/GPIO32 N3
L10
IN
9 90
FDI_INT
WAKE* B9
PM_RSMRST_L
BATLOW*/GPIO72
6 9 90
6 9 90
PM_PCH_PWROK
H20 ACPRESENT/GPIO31
9 90
OUT
IN
PCH_RI_L
FDI_DATA_P<0> FDI_DATA_P<1> FDI_DATA_P<2> FDI_DATA_P<3> FDI_DATA_P<4> FDI_DATA_P<5> FDI_DATA_P<6> FDI_DATA_P<7>
6 9 90
IN
E10
9 90
OUT
72 6
PM_BATLOW_L
9 90
FDI_LSYNC<0> FDI_LSYNC<1>
89 19 17
SMC_ADAPTER_EN
9 90
FDI_LSYNC0 AV14 FDI_LSYNC1 BB10
DPWROK
IN
9 90
6 9 90
E22
45
9 90
OUT
PM_DSW_PWRGD
72 45 44
9 90
OUT
IN
PD on SMC page
6 9 90
6 9 90
OUT
44 23 17
BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9
AT1 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
NC AT3 NC AT4 NC AT5 NC AT8 NC AT10 NC AT12 NC AU2 NC AU3 NC AV1 NC AV3 NC AV5 NC AV7 NC AV10 NC AY3 NC AY5 NC AY7 NC BA2 NC BA3 NC BB1 NC BB3 NC BB5 NC BB7 NC BC8 NC BD4 NC BE8 NC BF3 NC BF6 NC BG4 NC
9 90
FDI_FSYNC<0> FDI_FSYNC<1>
44
17
FDI_DATA_N<0> FDI_DATA_N<1> FDI_DATA_N<2> FDI_DATA_N<3> FDI_DATA_N<4> FDI_DATA_N<5> FDI_DATA_N<6> FDI_DATA_N<7>
FDI_FSYNC0 AV12 FDI_FSYNC1 BC10
PM_MEM_PWRGD
90 29 10
BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9
FDI_INT AW16
PLACE_NEAR=U1800.BH21:2.54mm 1
FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7
COUGAR-POINT MOBILE
DIGITAL DISPLAY INTERFACE
D
1% 1/20W MF 201
NC_CRT_IG_BLUE NC_CRT_IG_GREEN NC_CRT_IG_RED
N48 P49 T49
CRT_BLUE CRT_GREEN CRT_RED
NC_CRT_IG_DDC_CLK NC_CRT_IG_DDC_DATA
T39 M40
CRT_DDC_CLK CRT_DDC_DATA
NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC
M47 M49
CRT_HSYNC CRT_VSYNC
PCH_DAC_IREF
T43 T42
DAC_IREF CRT_IRTN
NC_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_DATA
DDPD_AUXN AT45 DDPD_AUXP AT43 DDPD_HPD BH41
CRT
2
DMI FDI
5% 1/20W MF
2 201
DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P
NC_DP_IG_D_AUXN NC_DP_IG_D_AUXP NC_DP_IG_D_HPD
BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42
NC_DP_IG_D_MLN<0> NC_DP_IG_D_MLP<0> NC_DP_IG_D_MLN<1> NC_DP_IG_D_MLP<1> NC_DP_IG_D_MLN<2> NC_DP_IG_D_MLP<2> NC_DP_IG_D_MLN<3> NC_DP_IG_D_MLP<3>
6 6
D
6 6
6 6
8 79 83 8 79 83
8 83 92 8 83 92 8 83
8 8 8 8 8 8 8 8
6 6
6 6 6
C
6 6 6 6 6 6 6 6
6 6
6 6 6
6 6 6 6 6 6 6 6
1
DF_TVS:DMI & FDI Term Voltage Set to Vss when Low Set to Vcc when High
R1951 1K
PLACE_NEAR=U1800.T43:2.54mm
B
5% 1/20W MF
B
2 201
84 31 25 17 6
PCIE_WAKE_L
PCIE_WAKE_L
IN
MAKE_BASE=TRUE
6 17 25 31 84
17
R1986
SUSWARN_L
2
0
1 5% 1/20W
MF
PCH_SUSACK_L
17
201
71 61 60 56 53 51 50 49 48 25 23 22 20 19 18 16 12 7 6 47 45 41 40 39 36 35 32 28 26 98 89 88 87 84 83 82 79 72
PP3V3_S0
R19911 8.2K 5% 1/20W MF 201
2
PM_CLKRUN_L
72 70 45 22 20 19 18 17 16 7 71 98 89 85 82 24 23 22 20 19 7 6 72 71 70 65 55 45 39 29 25
PP3V3_SUS PP3V3_S5
6 17 44 46
PP3V3_SUS
45 22 20 19 18 17 16 7 72 71 70
1
A
1
R1925 1K
R1985 1K
1% 1/20W MF 201
1% 1/20W MF 201
2
R19821
2
10K
5% 1/20W MF 201
5% 1/20W MF 201
2
72 44 29 17 6
R19831
10K
72 17
72 44 17 72 65 44 42 29 17
2
PM_SLP_S3_L PM_SLP_SUS_L PM_SLP_S5_L PM_SLP_S4_L
A PAGE TITLE
SUSWARN_L GPIO29_SLP_LAN_L PM_PWRBTN_L PCIE_WAKE_L
R1921
17 17 17 23 44
1
R1922
1
R1923
100K
100K
100K
5% 1/20W MF 201
5% 1/20W MF 201
5% 1/20W MF 201
2
2
1
R1924
PCH DMI/FDI/GRAPHICS
1
100K
2
5% 1/20W MF 201
DRAWING NUMBER
Apple Inc. 2
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
7
D
R 6 17 25 31 84
NOTICE OF PROPRIETARY PROPERTY:
8
SIZE
REVISION
6
5
4
3
2
BRANCH
PAGE
19 OF 132 SHEET
17 OF 101
1
8
5
10K 10K 10K
1
2
1
2
1
2
1
2
1
2
1
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
2
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
18 18
R2030 R2014 R2031
10K 10K 10K
1
2
1
2
1
2
5%
1/20W
MF
201 61
5%
1/20W
MF
201
5%
1/20W
MF
201
84 61
6
39 29 25
OUT
93 25
OUT
25
OUT
C
R2050
OUT
92 87
OUT
92 87
OUT
92 87
OUT
92 8
OUT
OUT
92 87
OUT
92 8
OUT
92 87
OUT
92 87
OUT
92 87
OUT
92 87
OUT
92 87
OUT
8
OUT
92 87
OUT
92 87
OUT
92 87
OUT
8
OUT
8 6
OUT
8 6
OUT
GNT1*/GPIO51 GNT2*/GPIO53 GNT3*/GPIO55
PCI_INTE_L AUD_IP_PERIPHERAL_DET T29_MCU_INT_L AUD_I2C_INT_L
G42 G40 C42 D44
PIRQE*/GPIO2 PIRQF*/GPIO3 PIRQG*/GPIO4 PIRQH*/GPIO5
NC_PCI_PME_L
K10
PME*
C6 H49 H43 J48 K42 H40 AN48 AM47 AK47 AJ48 AN47 AM49 AK49 AJ47
LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_P<2> NC_LVDS_IG_A_DATAP<3>
6
1
D47 E42 F46
LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_N<2> NC_LVDS_IG_A_DATAN<3>
OUT
92 87
PCH_PCI_GNT1_L PCH_PCI_GNT2_L PCH_PCI_GNT3_L
1% 1/20W MF 201
2
8 6
OUT
87 18 8
OUT
87 18 8
OUT
83
OUT
83
OUT
6 6
B
87 18 8
18 18 18
REQ1*/GPIO50 REQ2*/GPIO52 REQ3*/GPIO54
PLTRST* CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 LVDSA_DATA0* LVDSA_DATA1* LVDSA_DATA2* LVDSA_DATA3* LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3
LVDS_IG_A_CLK_N LVDS_IG_A_CLK_P
AK39 AK40
LVDSA_CLK* LVDSA_CLK
LVDS_IG_B_DATA_N<0> LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_N<2> NC_LVDS_IG_B_DATAN<3>
AH45 AH47 AF49 AF45
LVDSB_DATA0* LVDSB_DATA1* LVDSB_DATA2* LVDSB_DATA3*
LVDS_IG_B_DATA_P<0> LVDS_IG_B_DATA_P<1> LVDS_IG_B_DATA_P<2> NC_LVDS_IG_B_DATAP<3>
AH43 AH49 AF47 AF43
LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3
TP_LVDS_IG_B_CLKN TP_LVDS_IG_B_CLKP
AF40 AF39
LVDSB_CLK* LVDSB_CLK
PCH_LVDS_IBG NC_PCH_LVDS_VBG
AF37 AF36
LVD_IBG LVD_VBG
AE48 AE47
LVD_VREFH LVD_VREFL
2.37K
PLACE_NEAR=U1800.AF37:2.54mm
FCBGA (5 OF 10)
C46 C44 E40
LPC_CLK33M_SMC_R LPC_CLK33M_LPCPLUS_R LPC_CLK33M_GMUX_R NC_PCI_CLK33M_OUT3 PCH_CLK33M_PCIOUT
6
92 87
COUGAR-POINT MOBILE
JTAG_GMUX_TMS PCH_MLB_REVB_PD PCI_REQ3_L
PLT_RESET_L
25
25
U1800
PIRQA* PIRQB* PIRQC* PIRQD*
OMIT 87
5%
K40 K38 H38 G38
PCI_INTA_L PCI_INTB_L PCI_INTC_L PCI_INTD_L
2
1
P45 J47 M45 T45 P39 T40 K47
TP_LVDS_IG_BKL_PWM LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR NC_LVDS_IG_CTRL_CLK NC_LVDS_IG_CTRL_DATA LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA
USB
10K 10K 10K 10K
PCI
R2010 R2011 R2012 R2013
18
87 18 8
4
3
2
1
PP3V3_S0
R2016 R2017 R2018
D
6
USBP0N C24 USBP0P A24
USB_HUB1_UP_N USB_HUB1_UP_P
USBP1N C25 USBP1P B25
NC_USB_1N NC_USB_1P
Unused
USBP2N C26 USBP2P A26
NC_USB_2N NC_USB_2P
Unused
USBP3N K28 USBP3P H28
NC_USB_3N NC_USB_3P
Unused
USBP4N E28 USBP4P D28
NC_USB_4N NC_USB_4P
Unused
USBP5N C28 USBP5P A28
NC_USB_5N NC_USB_5P
Unused
USBP6N C29 USBP6P B29
NC_USB_6N NC_USB_6P
Unused
USBP7N N28 USBP7P M28
NC_USB_7N NC_USB_7P
Unused
USBP8N L30 USBP8P K30
USB_HUB2_UP_N USB_HUB2_UP_P
USBP9N G30 USBP9P E30
USB_CAMERA_N USB_CAMERA_P
USBP10N C30 USBP10P A30
NC_USB_10N NC_USB_10P
USBP11N L32 USBP11P K32
NC_USB_11N NC_USB_11P
USBP12N G32 USBP12P E32
NC_USB_12N NC_USB_12P
USBRBIAS* C33 USBRBIAS B33
OC0*/GPIO59 OC1*/GPIO40 OC2*/GPIO41 OC3*/GPIO42 OC4*/GPIO43 OC5*/GPIO9 OC6*/GPIO10 OC7*/GPIO14
BI
24 92
BI
24 92
BI
24 92
BI
24 92
USB HUB 1
D
USB HUB 2
31 31
Camera PP3V3_S3
6 7 8 19 24 25 29 30 31 32 47 48 49 53 54 71 72 87
PP3V3_SUS
7 16 17 19 20 22 45 70 71 72
Unused 1
R2065
Unused
5% 1/20W MF 201
1
R2061
R2068
10K 2 2
NC_USB_13N NC_USB_13P
R2067
PCH_USB_RBIAS
A14 K20 B17 C16 L16 A16 D14 C14
72 31
R20621
10K 5% 1/20W MF 201
R2064 10K
10K 5% 1/20W MF 201
2
5% 1/20W MF
10K 1
R2060
10K
1
5% 1/20W MF 201
1
Unused 92
1
10K
Unused
USBP13N C32 USBP13P A32
LVDS
72 71 61 60 56 53 51 50 49 48 25 23 22 20 19 17 16 12 7 6 47 45 41 40 39 36 35 32 28 26 98 89 88 87 84 83 82 79
7
2 2
5% 1/20W MF 201
2
5% 1/20W MF 201
2 201
C
1
R2069 10K 5% 1/20W MF 201
2
AP_PWR_EN USB_HUB_SOFT_RESET_L 23 24 SDCONN_STATE_RST_L 23 ENET_PWR_EN 23 PCH_GPIO43_OC4_L 23 SDCONN_STATE_CHANGE 23 32 PCH_GPIO10_OC6_L 23 PCH_GPIO14_OC7_L 23
R2070
1
22.6 1% 1/20W MF 201
PLACE_NEAR=U1800.B33:2.54mm 2
L_BKLTCTL L_BKLTEN L_VDD_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA
B
LVDS_IG_PANEL_PWR
1
R2015
LVDS_IG_BKL_ON
100K
PCH_PCI_GNT3_L PCH_PCI_GNT2_L PCH_PCI_GNT1_L
5% 1/16W MF-LF
2 402
NOSTUFF
R20521 10K 5% 1/20W MF 201
NOSTUFF
R20531
NOSTUFF
R20541
10K
10K
5% 1/20W MF 201
5% 1/20W MF 201
2
1
R2055 100K 5% 1/20W MF
2
2 201
2
A
SYNC_MASTER=K92_MLB
SYNC_DATE=07/06/2010
PAGE TITLE
PCH PCI/FLASHCACHE/USB DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
20 OF 132 SHEET
18 OF 101
1
A
6
23 19
D 87 33 23 19 8
41 19
87 19
T7
PCH_GPIO0
IN
FW_PLUG_DET_L
A42
TACH1/GPIO1
87 19
IN
GMUX_INT
H36
TACH2/GPIO6
IN
SMC_RUNTIME_SCI_L
98 89 88 87 84 51 50 49 48 47 45 41 20 19 18 17 16 12 7 6 40 39 36 35 32 28 26 25 23 22 83 82 79 72 71 61 60 56 53
PP3V3_S0
44 19
E38 (IPU)
GMUX_INT 1
R2190
19
100K
R21111
R21121
R21131
20K
10K
10K
5% 1/20W MF 201
5% 1/20W MF 201
5% 1/20W MF 201
2
5% 1/20W MF 201
2
46 6
C4
PCH_GPIO12
PCH_GPIO15 PD on audio page 23 19 OUT AUD_IPHS_SWITCH_EN_PCH 19
2
BI 41 19
OUT
44 19 16
R2180 35 19
T29_SW_RESET_L
0
1 1/20W
29 23
19
(IPU)
SATA4GP/GPIO16
T5 E8
PCH_GPIO24
E16
FCBGA (6 OF 10) OMIT
CLKOUT_PCIE7N V38 CLKOUT_PCIE7P V37
NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7P
MISC
TACH0/GPIO17
GPIO24/MEM_LED
OUT
GPIO28
T29_SW_RESET_L_R
K1
STP_PCI*/GPIO34
GPIO27
PP3V3_SUS
5% 1/20W MF 201
5% 1/20W MF 201 2
5% 1/20W MF 201
SATA2GP/GPIO36
TP5 BG16 NC
SATA3GP/GPIO37
N2
TP6 AH38 NC
IN
SLOAD/GPIO38
OUT
JTAG_ISP_TDI
M3
TP7 AH37 NC
87 33 19 8
SDATAOUT0/GPIO39
OUT
WOL_EN
T13
TP8 AK43 NC
72 19
PCIECLKRQ6*/GPIO45
K12
TP9 AK45 NC
PCH_GPIO46
PCIECLKRQ7*/GPIO46
V13
TP10 C18 NC
SDATAOUT1/GPIO48
TP11 N30 NC
SATA5GP/GPIO49
TP12 H3
OUT
FW_PWR_EN_PCH
OUT
ENET_LOW_PWR_PCH
BI
SPIROM_USE_MLB
55 46 19 6
GPIO57
TP13 AH12 NC
TACH4/GPIO68
19
PCH_GPIO69_TACH5
B41
TP14 AM4 NC
TACH5/GPIO69
PCH_GPIO70_TACH6
C41
TP15 AM5 NC
19
TACH6/GPIO70
19
PCH_GPIO71_TACH7
PP3V3_T29
25 19 16 7 87 35 34 33 51 50 49 40 39 36 25 23 22 16 12 7 6 20 19 18 17 35 32 28 26 48 47 45 41 61 60 56 53 82 79 72 71 88 87 84 83 98 89
PP3V3_S0
1
R2160
1
1
R2184
R2185
1
R2186
10K
10K
10K
10K
5% 1/20W MF 201
5% 1/20W MF 201
5% 1/20W MF 201
5% 1/20W MF 201
2
2
2
2
B JTAG_ISP_TDO FW_PLUG_DET_L FW_PWR_EN_PCH PCH_GPIO0
72 19
WOL_EN 71 70 45 22 20 19 18 17 16 7 72
8 19 33 87 8 19 39 19 19 23
PP3V3_SUS NOSTUFF
R21141
NOSTUFF
R21151
R21171
10K
10K
10K
5% 1/20W MF 201
5% 1/20W MF 201
5% 1/20W MF 201
2
2
2
PCH_GPIO15 PCH_GPIO46
89 88 87 84 83 71 61 60 56 53 48 47 45 41 40 32 28 26 25 23 18 17 16 12 7 6 22 20 19 39 36 35 51 50 49 82 79 72 98
39 29 25 24 23 22 20 17 7 6 98 89 85 82 72 71 70 65 55 45
19
19 23
PP3V3_S5
PP3V3_S0
R21911 R21751 R21741
A
R21731 R21721
10K
10K
10K
10K
5% 1/20W MF 201
5% 1/20W MF 201
5% 1/20W MF 201
5% 1/20W MF 201
2
2
2
D6 C40
19
A40
1
0
2
CPU_PWRGD
PM_THRMTRIP_L_R
1
390
10 23 90
PM_THRMTRIP_L
2
IN
JTAG_ISP_TDI PCH_GPIO36_SATA2GP
10 90
5% 1/20W MF 201
8 19 33 87 19 23
ENET_LOW_PWR_PCH
R2198
R21161
10K 5% 1/20W MF 201
19 23
NOSTUFF
1
10K 5% 1/20W MF 201
2
2
C GPIO ISOLATION CIRCUIT
32 31 30 29 25 24 19 18 8 7 6 87 72 71 54 53 49 48 47 32 31 30 29 25 24 19 18 8 7 6 87 72 71 54 53 49 48 47
TP17 K24 NC
A4 A44 A45 A46 A5 A6 B3 B47 BD1 BD49 BE1 BE49 BF1 BF49 BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49
VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF
TP18 L24 NC
AH8 AK11 AH10 AK10
TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4
U47
VSSADAC
PP3V3_S3
PP3V3_S3 1 1
2
TP19 AB46 NC
23 19
ENET_LOW_PWR_PCH
89 19 17
PM_PCH_PWROK
2
20% 10V CERM 402
CRITICAL 8 74LVC2G08GT SOT833 1
16
T29_PWR_EN_PCH
2 B
TP21 B21 NC
20% 10V CERM 402
CRITICAL 8 74LVC2G08GT SOT833 1 A
U2152Y 7
A
U2150Y 7
TP20 AB45 NC
C2152 0.1UF
C2150 0.1UF
ENET_LOW_PWR
OUT
32 36
89 19 17
2
PM_PCH_PWROK
B
08
T29_PWR_EN
OUT
35
AUD_IPHS_SWITCH_EN OUT
61
08 4
4
TP22 M20 NC TP24 BG46 NC TP25 BE28 NC TP26 BC30 NC
8 74LVC2G08GT 8 74LVC2G08GT
TP27 BE32 NC
19
FW_PWR_EN_PCH
TP28 BJ32 NC
5
U2150Y 89 19 17
TP29 BC28 NC
PM_PCH_PWROK
23 19
5
AUD_IPHS_SWITCH_EN_PCH
SOT833
6 B
SOT833
3
FW_PWR_EN
OUT
39
89 19 17
6
PM_PCH_PWROK
B
08
B
A
U2152Y 3
A
08 4
4
TP30 BE30 NC TP31 BF32 NC TP32 BG32 NC TP33 AV26 NC TP34 BB26 NC TP35 AU28 NC TP36 AY30 NC NC_1 P37 NC INIT3_3V* T14 TP38 TP37 TP39 TP40
PCH_INIT3V3_L
19
AY26 NC AU26 NC AV28 NC AW30
This has internal pull up and should not pulled low. THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
NC
SYNC_MASTER=K91_MLB
2
SYNC_DATE=10/20/2010
PAGE TITLE 2
SMC_SCI_L
16 19 44 19 71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
PCH_GPIO68_TACH4 PCH_GPIO69_TACH5 PCH_GPIO70_TACH6 PCH_GPIO71_TACH7
7
DRAWING NUMBER
R21961
19 19 19
6
5
PCH MISC
PCH_INIT3V3_L
PP3V3_S0
19
10K
10K 5% 1/20W MF 201
2
R2130
R2197
5% 1/20W MF 201
4
Apple Inc.
NOSTUFF1
NOSTUFF 1
5% 1/20W MF 201
2
3
19 35 19 44
SIZE
D REVISION
R
1K
T29_SW_RESET_L SMC_RUNTIME_SCI_L
8
OUT
R2156
MF 5% 201
TP16 Y13 NC
TACH7/GPIO71
10K 5% 1/20W MF 201
2
NC
PCH_GPIO68_TACH4
6 19 46 55
(PUs necessary?)
V3
10K 5% 1/20W MF 201
44 90
MF
TP4 BJ16 NC
M5
19
CPU_PECI 10
2
R21991 2
TP3 BH25 NC
JTAG_ISP_TDO
19 19
45
GPIO35
23 19
10K
1/20W
JTAG_ISP_TCK
23 19
R21551
2
5% 1/20W MF 201
PCH_PROCPWRGD
V8
2
PCH_GPIO12 PCH_GPIO24 SPIROM_USE_MLB
PROCPWRGD AY11
OUT
2
PP3V3_T29
TP2 BJ26 NC
RSVD
10K
10K
100K
6
87 35 34 33 25 19 16 7
R2140
K4
NCTF
R21921
R21931
C
R21941
D
10K 5% 1/20W MF 201
PCH_RCIN_L
87 33 19 8
87 33 23 19 8
1
48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98
5% 201
RCIN* P5
PCH_GPIO36_SATA2GP
(NC-ed per Intel chklist)
70 45 22 20 19 18 17 16 7 72 71
PCH_PECI
43
1
R21501
6
TP1 BG26 NC ALL RSVD TPs NC-ed per INTEL approval
MF
NC_GPIO35
6
R2170
THRMTRIP* AY10
P8
23 19
PP3V3_S0 6
SCLOCK/GPIO22
ISOLATE_CPU_MEM_L
2
PCH_A20GATE NOSTUFF
1/20W
SMC_SCI_L
5% 201
A20GATE P4 PECI AU16
IN
2
NC_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6P
LAN_PHY_PWR_CTRL/GPIO12
U2 D40
CLKOUT_PCIE6N V40 CLKOUT_PCIE6P V42
GPIO8
GPIO15
ODD_PWR_EN_L
3
COUGAR-POINT MOBILE
TACH3/GPIO7
G2
LPCPLUS_GPIO
2
(PU necessary?)
NC
C10
4
U1800
BMBUSY*/GPIO0
39 19 8
JTAG_ISP_TCK ODD_PWR_EN_L
IN
5
CPU
7
GPIO
8
NOTICE OF PROPRIETARY PROPERTY: 2
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
21 OF 132 SHEET
19 OF 101
1
A
8
7
6
5
4
3
2
1
D
D
1
MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.2 mm VOLTAGE=3.3V
C2210
87 71 70 25 22 20 17 14 7 6
N16 Y49
PP1V8_S0
0.1UF 20% 10V
PP1V05_S0_PCH_VCCADPLLB_F
22
402 39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
PLACE_NEAR=U1800.N16:2.54mm 35
AF17
PP1V05_S0
23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44 39
PLACE_NEAR=U1800.V16:2.54mm 35
BD47 BF47
PP1V05_S0_PCH_VCCADPLLA_F
22
2 CERM
AF33 AF34 AG34
PP1V05_S0 55mA Max, 5mA Idle
23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44 39
AG33
PP1V05_S0
V16
PPVOUT_S0_PCH_DCPSST
B
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
T17
1
C2222
NC-ed per DG
0.1UF 2
20% 10V CERM 402
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
25 17 16 7
NC V19 NC
BJ8 V_PROC_IO
PP1V05_S0
A22 VCCRTC
PPVRTC_G3H
1
PLACE_NEAR=U1800.A22:2.54mm
2
C2231
1
C2232
1UF
0.1UF
10% 6.3V CERM 402
20% 10V CERM 402
2
1
AA16 W16 T34 AJ2
48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98
PP3V3_S0
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31
PP1V05_S0 1.44 A Max, 474mA Idle
48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98
PP3V3_S0
AF13 AH13 AH14
PP1V05_S0
6 7 9 10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101
AF14 AK1
NC VCCAPLLSATA pin left as NC per DG
AF11
PP1V8_S0
AC16 AC17 AD17
PP1V05_S0
T21 V21 T19
6 7 9 10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101
PP1V05_S0
6 7 9 10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44 6
N26 P26 P28 T27 T29
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44 6 7 9 10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101
PP1V05_S0
T23 T24 V23 V24 P24
PP3V3_SUS
T26
PP1V05_S0
M26
NC-ed per DG
AN24
PP3V3_SUS
NC
TP_1V05_S0_PCH_VCCAPLLEXP
BJ22 VCCAPLLEXP
PP1V05_S0
AN16 VCCIO_17_FDI AN17 VCCIO_18_FDI AN21 AN26 AN27 AP21 AP23 AP24 AP26 AT24
VCCIO_19_PCIE VCCIO_20_PCIE VCCIO_21_PCIE VCCIO_22_PCIE VCCIO_23_PCIE VCCIO_24_PCIE VCCIO_25_PCIE VCCIO_26_PCIE
AN33 VCCIO_27_DP AN34 VCCIO_28_DP
6 7 9 10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101 71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
22
U1800 COUGAR-POINT MOBILE FCBGA (7 OF 10) OMIT
VCCALVDS AK36
PP3V3_S0
47 48 49 50 51 53 56 60 61 71 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98
VSSALVDS AK37 AM37 AM38 AP36 AP37
VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS
VCC3_3_6_HVCMOS V33 VCC3_3_7_HVCMOS V34
PP1V8_S0_PCH_VCCTX_LVDS_F
PP3V3_S0
VCCVRM_3_DMI AT16
PP1V8_S0
VCCDMI_1_DMI AT20
PP1V05_S0
VCCCLKDMI AB36
AN19 VCCIO_11_PLLPCIE
PP1V05_S0
7 16 17 18 19 20 22 45 70 71 72
PP5V_SUS_PCH_V5REFSUS
AN23
VCCSUSHDA P32
6 7 14 17 20 22 25 70 71 87
VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE
LVDS
7 16 17 18 19 20 22 45 70 71 72
VCC CORE
22
PP3V3_SUS
HVCMOS
PP5V_S0_PCH_V5REF
DMI
PCI/GPIO/ LPC SATA
P34 N20 N22 P20 P22
DFT/SPI
PCH output, for decoupling only PPVOUT_G3_PCH_DCPRTC
CLK/MISC
C
MISC
AA19 AA21 AA24 AA26 AA27 AA29 AA31 AC26 AC27 AC29 AC31 AD29 AD31 W21 W23 W24 W26 W29 W31 W33
PP1V05_S0
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
USB
AL24
NC
CPU
AL29
AL24 left as NC per DG
HDA
BH23
NC
PP1V05_S0
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
T38
PP3V3_S0_PCH_VCC3_3_CLK_F
RTC
22
V5REF FCBGA (8 OF 10) OMIT VCCSUS3_3_5_GPIO VCCSUS3_3_6_GPIO VCC3_3_4_CLK VCCSUS3_3_7_GPIO VCCAPLLDMI2 VCCSUS3_3_8_GPIO VCCIO_12_PLLCLK VCC3_3_2_GPIO DCPSUS_0_CLK VCC3_3_3_GPIO VCC3_3_1_GPIO VCCASW_3_CLK VCCASW_4_CLK VCC3_3_0_SATA VCCASW_5_CLK VCCIO_5_PLLSATA VCCASW_6_CLK VCCASW_7_CLK VCCIO_15_SATA3 VCCASW_8_CLK VCCIO_16_SATA3 VCCASW_9_CLK VCCASW_10_CLK VCCIO_9_PLLSATA3 VCCASW_11_CLK VCCAPLLSATA VCCASW_12_CLK VCCVRM_1_SATA VCCASW_13_CLK VCCASW_14_CLK VCCIO_6_SATA VCCASW_15_CLK VCCIO_7_SATA VCCASW_16_CLK VCCIO_8_SATA VCCASW_17_CLK VCCASW_18_CLK VCCASW_2_MISC VCCASW_19_CLK VCCASW_1_MISC VCCASW_20_CLK VCCASW_0_MISC VCCASW_21_CLK VCCASW_22_CLK VCCIO_0_USB DCPRTC VCCIO_1_USB VCCIO_2_USB VCCVRM_0_CLK VCCIO_3_USB VCCADPLLA VCCIO_4_USB VCCADPLLB VCCSUS3_3_1_USB VCCIO_13_CLK VCCSUS3_3_2_USB VCCSUS3_3_3_USB VCCDIFFCLKN_0 VCCSUS3_3_4_USB VCCDIFFCLKN_1 VCCSUS3_3_9_USB VCCDIFFCLKN_2 VCCIO_14_PLLUSB VCCSSC V5REF_SUS DCPSST DCPSUS_3_SUS DCPSUS_1_CLK DCPSUS_2_CLK VCCSUS3_3_0_SUS
V12 DCPSUSBYP
TP_PPVOUT_PCH_DCPSUSBYP
VCCAPLLDMI2 pin left as NC per DG
U1800 COUGAR-POINT MOBILE
VCCDFTERM VCCDFTERM VCCDFTERM VCCDFTERM
PP1V05_S0_PCH_VCCCLKDMI_F
AG16 AG17 AJ16 AJ17
VCCSPI V1 CRT
T16 VCCDSW3_3
VCCIO
AD49 VCCACLK
NC PP3V3_S5
VCCADAC U48 VCCVRM_2_FDI AP16
FDI
VCCACLK pin left as NC per DG 98 29 25 24 23 22 20 19 17 7 6 89 85 82 72 71 70 65 55 45 39
VCCAFDIPLL BG6 NC
22
47 48 49 50 51 53 56 60 61 71 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98
6 7 14 17 20 22 25 70 71 87
6 7 9 10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101 22
PP1V8_S0
6 7 14 17 20 22 25 70 71 87
PP3V3_S5
98 6 7 17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89
PP3V3_S0_PCH_VCCA_DAC_F
22
PP1V8_S0
C
6 7 14 17 20 22 25 70 71 87
VCCAFDIPLL pin left as NC per DG
VCCIO_10_PLLFDI AP17
PP1V05_S0
VCCDMI_0_FDI AU20
PP1V05_S0
6 7 9 10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101 6 7 9 10 12 13 14 16 17 20 22 23 35 39 44 67 69 72 101
BH29 VCC3_3_5_PCI
PP3V3_S0
B
7 16 17 18 19 20 22 45 70 71 72
PP1V5_S0
7 16 22 25 41 56 70
10 mA Max, 1mA Idle
C2233 0.1UF
2
20% 10V CERM 402
PLACE_NEAR=U1800.A22:2.54mm PLACE_NEAR=U1800.A22:2.54mm
A
A PAGE TITLE
PCH POWER DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
22 OF 132 SHEET
20 OF 101
1
8
7
6
AJ3 N24 BG29 H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD14 AD16 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD47 AD8 AE2 AE3 AF10 AF12 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3 AK38 AK4 AK42
D
C
B
A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
U1800 COUGAR-POINT MOBILE FCBGA (9 OF 10) VSS OMIT
5
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
4
AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP13 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV11 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AY12 AY22 AY28 AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31
3
B35 VSS B39 VSS B43 VSS B7 VSS BB12 VSS BB16 VSS BB20 VSS BB22 VSS BB24 VSS BB28 VSS BB30 VSS BB38 VSS BB4 VSS BB46 VSS BC14 VSS BC18 VSS BC2 VSS BC22 VSS BC26 VSS BC32 VSS BC34 VSS BC36 VSS BC40 VSS BC42 VSS BC48 VSS BD3 VSS BD46 VSS BD5 VSS BE10 VSS BE22 VSS BE26 VSS BE40 VSS BF10 VSS BF12 VSS BF16 VSS BF20 VSS BF22 VSS BF24 VSS BF26 VSS BF28 VSS BF30 VSS BF38 VSS BF40 VSS BF8 VSS BG17 VSS BG21 VSS BG22 VSS BG24 VSS BG33 VSS BG41 VSS BG44 VSS BG8 VSS BH11 VSS BH15 VSS BH17 VSS BH19 VSS BH27 VSS BH31 VSS BH33 VSS BH35 VSS BH39 VSS BH43 VSS BH7 VSS C22 VSS D12 VSS D16 VSS D18 VSS D22 VSS D24 VSS D26 VSS D3 VSS D30 VSS D32 VSS D34 VSS D38 VSS D42 VSS D8 VSS E18 VSS E26 VSS F3 VSS F45 VSS G14 VSS G18 VSS G20 VSS G26 VSS G28 VSS G36 VSS
U1800 COUGAR-POINT MOBILE FCBGA (10 OF 10) VSS OMIT
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
2
1
G48 H10 H12 H16
D
H18 H22 H24 H26 H30 H32 H34 H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 M14 M18 M22 M24 M30 M32
C
M34 M38 M4 M42 M46 M8 N18 N47 P11 P16 P18 P30 P40 P43 P47 P7 R2 R48 T12 T31 T33 T36 T37 T4 T46 T47 T8
B
V11 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W34 W48 Y12 Y38 Y4 Y42 Y46 Y8 V17 AP3 AP1 BE16 BC16 BG28 BJ28
SYNC_MASTER=K92_MLB
SYNC_DATE=04/30/2010
PAGE TITLE
PCH GROUNDS DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
23 OF 132 SHEET
21 OF 101
1
A
8
7
6
5
CRITICAL
87 71 70 25 22 20 17 14 7 6
1
PP1V05_S0
3
2
1
PCH VCCSUS3_3 BYPASS
L2406
10UH-0.45A 72 69 67 44 39 16 14 13 12 10 9 7 6 35 23 22 20 17 101
4
1
2 PP1V05_S0_PCH_VCCCLKDMI_R 1 MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V
1210-HF
PP1V8_S0
71 70 45 22 20 19 18 17 16 7 72 20
PP1V05_S0_PCH_VCCCLKDMI_F
2
1
1 1
C2411
2
1UF 10% 16V
1
C2484
C2413
0.1UF
0.1UF
10% 16V X5R 402
10% 16V X5R 402
2
1
0.1UF 2
402
35 23 22 20 17 16 14 13 12 101 72 69 67 44 39
C2440
PLACE_NEAR=U1800.AJ16:2.54mm
C2444
1
C2452
1UF
20% 10V CERM 402
2
1
1UF
10% 6.3V CERM 402
2
10% 6.3V CERM 402
C2446 1UF
PLACE_NEAR=U1800.P28:2.54mm 2
10% 6.3V CERM 402
PLACE_NEAR=U1800.AH13:2.54mm PLACE_NEAR=U1800.AC17:2.54mm
PLACE_NEAR=U1800.P24:2.54mm
2 X5R
PLACE_NEAR=U1800.AB36:2.54mm
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
PP3V3_SUS
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V MAKE_BASE=TRUE
5% 1/16W MF-LF 402
PCH VCCIO BYPASS (PCH USB 1.05V PWR) PP1V05_S0 10 9 7 6
PP1V05_S0
(PCH SUSPEND USB 3.3V PWR)
R2415
PCH VCCSUSHDA BYPASS
D
PLACE_NEAR=U1800.V24:2.54mm
D
70 56 41 25 20 16 7
PP1V5_S0
CRITICAL
L2407
1
0.1UH
1
87 22 20 17 14 7 6 71 70 25
PP1V8_S0
2
20
PP1V8_S0_PCH_VCCTX_LVDS_F MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.8V
0805
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
C2441 0.1UF
PLACE_NEAR=U1800.P32:2.54mm 2
PP1V05_S0
71 70 45 22 20 19 18 17 16 7 72
PP1V05_S0
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
20% 10V CERM 402
1 1
PLACE_NEAR=U1800.AG33:2.54mm
84 51 47 39 9828 72 71 6122 17 16 12 7 60 56 5319 89 88 8725 35 41 49 82
83 50 45 36 26 20 6 18 23 32 40 48 79
C2406
1
C2408
1
C2416
22UF
0.01UF
0.01UF
4.7UF
20% 6.3V CERM 805
10% 16V CERM 402
10% 16V CERM 402
20% 6.3V X5R 402
2
2
2
PLACE_NEAR=U1800.BJ8:2.54mm PLACE_NEAR=U1800.BJ8:2.54mm PLACE_NEAR=U1800.BJ8:2.54mm
1
1
C2417
1
0.1UF 2
2
1
2
PLACE_NEAR=U1800.P22:2.54mm
98 29 25 24 23 22 20 19 17 7 6 89 85 82 72 71 70 65 55 45 39
PP3V3_S5 1
C2442 1UF
2
PP3V3_S0_PCH_VCCA_DAC_F
20
10% 6.3V CERM 402
PP1V05_S0
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
20 17 16 14 13 12 10 9 7 6 101 72 69 67 44 39 35 23 22
PP1V05_S0
MAKE_BASE=TRUE 5% 1/20W MF 201
1
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
C
PP1V05_S0
C2455
0.1UF 10% 16V X5R 402
2
1 2
0.01UF 10% 16V CERM 402
2
10% 6.3V CERM 402
98 29 25 24 23 22 20 19 17 7 6 89 85 82 72 71 70 65 55 45 39
PP3V3_S5
2
C2499 20% 10V CERM 402
PP3V3_S0 PP5V_S0
100
PP3V3_S0
1
1
2
5% 1/16W MF-LF 402
SOT-363
PP3V3_S0_PCH_VCC3_3_CLK_R MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=3.3V
1
2 0603
1
20% 6.3V X5R 603
10% 10V X5R 402
PP5V_S0_PCH_V5REF
1
NC
C2438
5% 1/16W MF-LF 402
CRITICAL
C2491 1 220UF
PP1V05_S0_PCH_VCCADPLLA_F
1
C2426
1
1
C2456
C2496
C2428
1UF
1UF
1UF
22UF
22UF
10% 6.3V CERM 402
10% 6.3V CERM 402
10% 6.3V CERM 402
20% 6.3V CERM 805
20% 6.3V CERM 805
2
2
2
1
2
20
68 mA
NO STUFF
B
PLACE_NEAR=U1800.AC27:2.54mm PLACE_NEAR=U1800.AC27:2.54mm PLACE_NEAR=U1800.AC27:2.54mm PLACE_NEAR=U1800.AC27:2.54mm PLACE_NEAR=U1800.AC27:2.54mm
C2492 1UF
10% 2 6.3V CERM 402
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
L2491
0
10UH-0.12A-0.36OHM PP1V05_S0_PCH_VCCADPLLB_R
2
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.05V
5% 1/16W MF-LF 402
1
2 0603
CRITICAL
C2493 1 220UF
20% 2.5V 2 POLY-TANT CASE-B2-SM1
PP3V3_S0
PP1V05_S0
PCH VCCADPLLB Filter (PCH DPLLB PWR)
CRITICAL 20 22
R2491
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
2
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
<1 MA S0-S5
2
1
C2420
PP1V05_S0
20 22
PP5V_SUS_PCH_V5REFSUS
1
2
PLACE_NEAR=U1800.BD47:2.54MM PLACE_NEAR=U1800.BD47:2.54MM
NEED PWR CONSTRAINT
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V MAKE_BASE=TRUE
PP3V3_S0
2 0603
20% 2.5V 2 POLY-TANT CASE-B2-SM1
1
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
1
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.05V
BAT54DW-X-G
0.1UF 20% 10V CERM 402
PP1V05_S0_PCH_VCCADPLLA_R
2
SOT-363 3
1
1
0
D2400
PP5V_SUS_PCH_V5REFSUS
PLACE_NEAR=U1800.M26:2.54mm
PP1V05_S0
4
NC
5% 1/16W MF-LF 402
2
2
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
PCH VCCADPLLA Filter (PCH DPLLA PWR)
10UH-0.12A-0.36OHM
R2490
2
20% 6.3V CERM 805
2
1
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
10
1
10UF
10% 6.3V CERM 402
PLACE_NEAR=U1800.T38:2.54mm PLACE_NEAR=U1800.T38:2.54mm
PCH V5REF_SUS Filter & Follower (PCH Reference for 5V Tolerance on USB)
R2404 2
C2460
1UF
20 22
L2490
1 mA S0-S5
C2483
10% 6.3V CERM 402
<1 MA
CRITICAL
B
1
1UF
1UF 2
2
PP3V3_SUS PP5V_SUS
C2482
10% 6.3V CERM 402
C2454
10UF
NEED PWR CONSTRAINT PP5V_S0_PCH_V5REF 20 22 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE
1
1UF
PLACE_NEAR=U1800.AD21:2.54mm PLACE_NEAR=U1800.AG24:2.54mm PLACE_NEAR=U1800.AJ27:2.54mm PLACE_NEAR=U1800.AG26:2.54mm
20 PP3V3_S0_PCH_VCC3_3_CLK_F MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=3.3V 1
CRITICAL C2453 1
6
1UF 10% 10V X5R 402
87 47 6 25 56
BAT54DW-X-G
NC
NC
5% 1/16W MF-LF 402 1
C2439
D2400
5
C2481
L2451
10UH-0.12A-0.36OHM
R2451
98 89 88 53 51 50 49 48 23 22 20 19 18 17 16 12 7 45 41 40 39 36 35 32 28 26 84 83 82 79 72 71 61 60
1
R2405 2
PCH VCCCORE BYPASS (PCH 1.05V CORE PWR)
PP1V05_S0
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
2
1
PCH V5REF Filter & Follower (PCH Reference for 5V Tolerance on PCI)
1 mA
C
1
0.1UF
PLACE_NEAR=U1800.T16:2.54mm
PCH VCC3_3 BYPASS (PCH PCI 3.3V PWR)
2
71 7
10% 6.3V CERM 402
PLACE_NEAR=U1800.AF17:2.54mm
C2419
CRITICAL
71 70 45 22 20 19 18 17 16 7 72
C2469 1UF
2
1UF 1
PLACE_NEAR=U1800.AT20:2.54mm
PLACE_NEAR=U1800.P34:2.54mm
10% 6.3V CERM 402
PLACE_NEAR=U1800.AF34:2.54mm 2
PLACE_NEAR=U1800.U48:2.54mm PLACE_NEAR=U1800.U48:2.54mm PLACE_NEAR=U1800.U48:2.54mm
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72 101 88 6 86 72 71 69 68 67 64 53 51 46 41 8 7
C2434 1UF
1
C2451
10UF 20% 6.3V CERM 805
1
PCH VCCIO BYPASS 39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
CRITICAL C2450 1
10% 6.3V CERM 402
10% 16V X5R 402
PLACE_NEAR=U1800.V1:2.54mm
2
2
C2430
R2450 PP3V3_S0
C2476 1UF
10% 6.3V CERM 402
0.1UF
10% 16V X5R 402
PLACE_NEAR=U1800.AM37:2.54mm PLACE_NEAR=U1800.AM37:2.54mm PLACE_NEAR=U1800.AM37:2.54mm 0
C2475 1UF
2
CRITICAL C2400 1
PP3V3_SUS
1
PP1V05_S0_PCH_VCCADPLLB_F MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
20
69 mA 2
NO STUFF
1
C2494
C2429
1
1
0.1UF
1
C2407
1
C2463
C2401
1UF
1UF
1UF
10UF
10% 6.3V CERM 402
10% 6.3V CERM 402
10% 6.3V CERM 402
10% 6.3V CERM 402
10% 16V X5R-CERM 0805
2
2
2
1
2
1UF
10% 2 6.3V CERM 402
PLACE_NEAR=U1800.BF47:2.54MM PLACE_NEAR=U1800.BF47:2.54MM
C2421
C2414
1UF
PLACE_NEAR=U1800.AN27:2.54mm PLACE_NEAR=U1800.AN27:2.54mm PLACE_NEAR=U1800.AN27:2.54mm PLACE_NEAR=U1800.AN27:2.54mm PLACE_NEAR=U1800.AN27:2.54mm
C2423 0.1UF
10% 16V
2 X5R 402
2
PLACE_NEAR=U1800.AJ2:2.54mm
10% 16V X5R 402
PLACE_NEAR=U1800.BH29:2.54mm
A 98 89 56 53 51 50 49 48 47 45 22 20 19 18 17 16 12 7 40 39 36 35 32 28 26 25 87 84 83 82 79 72 71 61
88 41 6 23 60
SYNC_MASTER=K92_MLB
PCH DECOUPLING 1
C2424
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
0.1UF 10%
2 16V X5R
DRAWING NUMBER
PP3V3_S0
Apple Inc. 1
402
C2486
1
0.1UF
PLACE_NEAR=U1800.V33:2.54mm 2
10% 25V X5R 402
C2485
7
D
0.1UF 2
6
SIZE
REVISION
R
10% 25V X5R 402
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
PLACE_NEAR=U1800.T34:2.54mm PLACE_NEAR=U1800.AA16:2.54mm
8
SYNC_DATE=07/06/2010
PAGE TITLE
PP3V3_S0
5
4
3
2
BRANCH
PAGE
24 OF 132 SHEET
22 OF 101
1
A
8
7
6
5
4
3
2
PROCESSOR MINI XDP
1
DESIGN NOTE: ODT AVAILABLE ON JTAG
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
72 71 61 60 56 53 51 50 49 48 25 22 20 19 18 17 16 12 7 6 47 45 41 40 39 36 35 32 28 26 98 89 88 87 84 83 82 79
PP3V3_S0 CRITICAL XDP_CONN
1K 5% 1/16W MF-LF 402
90 10
90 10
IN
90 10
IN
90 10
IN
90 10
IN
XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>
0 0
R2560 5% 1 R2561 5%MF1 R2562 5%MF1 R2563 5%MF1
2 2
0
2
0
XDP_CPU_BPM XDP_CPU_BPM XDP_CPU_BPM XDP_CPU_BPM
1/20W 201 1/20W 201 1/20W 201 1/20W 201
2
MF
IN
90 10
IN
90 10
90 10 90 10
IN
90 9
IN
90 9
9
IN
9
IN
9
IN
9
IN
CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15>
R2564 5% 1 R2565 5%MF1 R2566 MF 5% 1 R2567 5%MF1
0
2
0
2
0 0
MF
PLACE_NEAR=U1000.C60:2.54mm
IN
IN
CPU_PWRGD
5%
XDP 1
1K
2
90
MF 201
93 88 28 26 23 16 61 47 41 30
XDP
PLACE_NEAR=U1000.B57:2.54mm
28 26 23 16 61 47 41 30 93 88
R2501 90 23 9
OUT
CPU_CFG<0>
5%
1
1K
2
1/20W
90 23 10
MF 201
IN
SMBUS_PCH_DATA SMBUS_PCH_CLK
OUT
XDP_CPU_TCK
BI
OUT
PM_PCH_SYS_PWROK
XDP 5%
330
1
12
13
14
OBSDATA_A2 OBSDATA_A3
15
16
17
18
19
20
OBSFN_B0 OBSFN_B1
21
22
SDA SCL TCK1 TCK0
NC
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
2
C2500
1/20W
10% 16V X5R 402
MF 201
OBSFN_C0 OBSFN_C1
CPU_CFG<16> CPU_CFG<17>
IN
9 90
IN
9 90
OBSDATA_C0 OBSDATA_C1
CPU_CFG<0> CPU_CFG<1>
IN
9 23 90
90 23 10
IN
9 90
90 23 10
OBSDATA_C2 OBSDATA_C3
CPU_CFG<2> CPU_CFG<3>
IN
9 90
IN
9 90
OBSFN_D0 OBSFN_D1
CPU_CFG<8> CPU_CFG<9>
IN
9 90
IN
9 90
OBSDATA_D0 OBSDATA_D1
CPU_CFG<4> CPU_CFG<5>
IN
9 90
IN
9 90
51
5% 1/20W MF 201
5% 1/20W MF 201
5% 1/20W MF 201
IN
9 90
IN
9 90
XDP
PLACE_NEAR=U1000.H63:2.54mm
CPU_CFG<6> CPU_CFG<7>
1
517S0774 2
D
2
PLACE_NEAR=U1000.J58:2.54mm
R25141
51
51
5% 1/20W MF 201
5% 1/20W MF 201
2
2
PLACEMENT NOTE: PLACE TCK/TDI/TMS/TRST* TERM NEAR CPU
R2515 5%
1
0
2
MF 201
1/20W
ITPXDP_CLK100M_P
IN
16 90
PLACE_NEAR=R1840.1:2.54mm
R2516 5%
1
0
2
1/20W
ITPXDP_CLK100M_N
IN
16 90
1/20W
PLT_RST_CPU_BUF_L
IN
10 25
MF 201
XDP OUT
R2505
10 23 25 90
5%
IN
10 23 90
OUT
10 23 90
OUT
10 23 90
OUT
10 23 90
1
1K
2
MF 201
PLACE_NEAR=U1000.G3:2.54mm
C PP1V05_SUS
XDP
PLACEMENT NOTE:
C2501
PLACE TDO TERM NEAR PCH XDP CONN
0.1uF
2
XDP
R25131
PLACE_NEAR=R1841.1:2.54mm
XDP
XDP 90 XDP_CPU_CLK100M_P ITPCLK/HOOK4 90 XDP_CPU_CLK100M_N ITPCLK#/HOOK5 VCC_OBS_CD 90 XDP_CPURST_L RESET#/HOOK6 XDP_DBRESET_L DBR#/HOOK7 NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28 XDP_CPU_TDO TDO XDP_CPU_TRST_L TRSTn XDP_CPU_TDI TDI XDP_CPU_TMS TMS XDP_PRESENT#
2
PLACE_NEAR=U1000.H59:2.54mm
90 23 10
OBSDATA_D2 OBSDATA_D3
XDP
R25121
51
XDP_CPU_TDO PLACE_NEAR=U1000.K61:2.54mm XDP_CPU_TDI XDP_CPU_TMS XDP_CPU_TCK XDP_CPU_TRST_L
90 23 10 90 23 10
1
0.1uF
XDP
R25111
51
PLACE_NEAR=J2500.52:2.54mm2
XDP
R2504 89 17
11
1/20W
MF 201
6 8
PWRGD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3
XDP_CPU_CFG<0> XDP_VR_READY
XDP R2502 PLACE_NEAR=U4900.P17:2.54mm 0 2 PM_PWRBTN_L 5% 1 OUT
44 23 17
C
XDP_CPU_PWRGD XDP_CPU_PWRBTN_L
4
5
10
OBSDATA_B2 OBSDATA_B3
1/20W
2
3
9
OBSDATA_B0 OBSDATA_B1
XDP_OBSDATA_B<2> XDP_OBSDATA_B<3>
1
7
OBSDATA_A0 OBSDATA_A1
XDP_OBSDATA_B<0> XDP_OBSDATA_B<1>
R2500 90 19 10
OBSFN_A0 OBSFN_A1
CPU_CFG<10> CPU_CFG<11>
XDP_CPU_CFG XDP_CPU_CFG XDP_CPU_CFG XDP_CPU_CFG
1/20W 201 1/20W 201 2 1/20W 201 2 1/20W 201
F-ST-SM-HF
XDP_BPM_L<2> XDP_BPM_L<3>
IN
XDP
R25101
DF40C-60DS-0.4V 2
XDP_BPM_L<0> XDP_BPM_L<1>
IN
PLACE TDO TERM NEAR SNB XDP CONN
J2500
XDP_CPU_PREQ_L XDP_CPU_PRDY_L
BI
90 10
72 101 20 22 23 35 6 7 9 10 12 13 14 16 17 39 44 67 69
PLACEMENT NOTE: NOSTUFF 1
R2540
D
PP1V05_S0
PP1V05_S0
PLACE_NEAR=U1800.K5:2.54mm
XDP1
10% 16V X5R 402
XDP
R25511
R2550 PLACE_NEAR=J2550.52:2.54mm
7 70
XDP
R25521
51
51
51
5% 1/20W MF 201
5% 1/20W MF 201
5% 1/20W MF 201
2
2
PLACE_NEAR=U1800.H7:2.54mm
2
XDP_PCH_TDO XDP_PCH_TDI XDP_PCH_TMS XDP_PCH_TCK
23 16 23 16 23 16 23 16
PCH MINI XDP
XDP
R25561 39 29 25 24 22 20 19 17 7 6 98 89 85 82 72 71 70 65 55 45
PP3V3_S5
51 5% 1/20W MF 201
CRITICAL XDP_CONN
J2550 DF40C-60DS-0.4V F-ST-SM-HF
PLACE_NEAR=U1800.K12:2.54mm
XDP
B 19
IN
PCH_GPIO46
PLACE_NEAR=U1800.A14:2.54mm 24 18
IN
USB_HUB_SOFT_RESET_L
PLACE_NEAR=U1800.K20:2.54mm 18
IN
SDCONN_STATE_RST_L
PLACE_NEAR=U1800.C16:2.54mm 18
IN
ENET_PWR_EN
PLACE_NEAR=U1800.A16:2.54mm 32 18
IN
SDCONN_STATE_CHANGE
PLACE_NEAR=J2550.39:2.54mm 89 87 72 44
IN
ALL_SYS_PWRGD
PLACE_NEAR=U4900.P17:2.54mm 44 23 17
OUT
A
PM_PWRBTN_L
5% 1 MF
0
TP_XDP_PCH_OBSFN_A<0> TP_XDP_PCH_OBSFN_A<1>
2 1/20W 201
OBSFN_A0 OBSFN_A1
XDP
R2580 5% 1 MF
0
XDP_PCH_GPIO46 XDP_PCH_USB_HUB_SOFT_RST_L
2 1/20W 201
XDP
XDP_PCH_SDCONN_STATE_RST_L XDP_PCH_ENET_PWR_EN
R2586 5% 1 MF
0
2 1/20W 201
5% 1 MF
18
2 1/20W 201
XDP
18
IN
18
IN
R2584 5% 1 MF
1K
OBSFN_B0 OBSFN_B1
PCH_GPIO43_OC4_L XDP_PCH_SDCONN_DET_L
IN
R2581 5% 1 MF
OBSDATA_B0 OBSDATA_B1
PCH_GPIO10_OC6_L PCH_GPIO14_OC7_L
OBSDATA_B2 OBSDATA_B3
XDP_PCH_S5_PWRGD XDP_PCH_PWRBTN_L
2 1/20W 201
PWRGD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3
XDP
R2585 5% 1 MF
0
R2578
3
4
0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2 1/20W 201
XDP
0
OBSDATA_A2 OBSDATA_A3
TP_XDP_PCH_OBSFN_B<0> TP_XDP_PCH_OBSFN_B<1>
XDP
R2587 0
OBSDATA_A0 OBSDATA_A1
6
2 1/20W 201
6
93 88 61 47 41 30 28 26 23 16
BI
93 88 61 47 41 30 28 26 23 16
IN
23 16
OUT
TP_XDPPCH_HOOK2 TP_XDPPCH_HOOK3 SMBUS_PCH_DATA SMBUS_PCH_CLK XDP_PCH_TCK
NC
OBSFN_C0 OBSFN_C1 OBSDATA_C0 OBSDATA_C1
2 1/20W 201
R2576
XDP_FW_CLKREQ_L XDP_AP_CLKREQ_L
5% 1 MF
0
DP_AUXCH_ISOL
IN
16 84
SATARDRVR_EN
IN
16 41
OBSFN_D0 OBSFN_D1
TP_XDP_PCH_OBSFN_D<0> TP_XDP_PCH_OBSFN_D<1>
OBSDATA_D0 OBSDATA_D1
PCH_GPIO36_SATA2GP JTAG_ISP_TCK
IN
19
IN
8 19 33 87
IN
B
19 29
5% 1 MF
0
PLACE_NEAR=U1800.V10:2.54mm FW_CLKREQ_L IN 16
2 1/20W 201
XDP
OBSDATA_C2 OBSDATA_C3
ISOLATE_CPU_MEM_L
XDP
19
PLACEMENT NOTE: PLACE TCK/TDI/TMS/TRST* TERM NEAR PCH 39
PLACE_NEAR=U1800.M1:2.54mm
2 1/20W 201
AP_CLKREQ_L
IN
16 31
26 28
29
30
31
32
R2579
33
34
0
35
36
37
38
39
40
41
42
43
44
OBSDATA_D2 OBSDATA_D3
TP_XDP_PCH_HOOK4 ITPCLK/HOOK4 TP_XDP_PCH_HOOK5 ITPCLK#/HOOK5 VCC_OBS_CD XDPPCH_PLTRST_L RESET#/HOOK6 XDP_DBRESET_L DBR#/HOOK7 NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28 XDP_PCH_TDO TDO TP_XDP_PCH_TRST_L TRSTn XDP_PCH_TDI TDI XDP_PCH_TMS TMS XDP_PRESENT#
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
XDP_PCH_AUD_IPHS_SWITCH_EN ENET_LOW_PWR_PCH
5% 1 MF IN
19
IN
25
OUT
PLACE_NEAR=U1800.U2:2.54mm
XDP
2 1/20W 201
AUD_IPHS_SWITCH_EN_PCH
IN
19
1K series R on PCH Support P. 28
10 23 25 90
IN
16 23
OUT
16 23
OUT
16 23
SYNC_MASTER=K91_MLB
SYNC_DATE=10/17/2010
PAGE TITLE
CPU & PCH XDP DRAWING NUMBER
XDP 1
0.1uF 10% 16V X5R 402
5% 1 MF IN
R2577
XDP
C2580
XDP_PCH_ISOLATE_CPU_MEM_L PCH_GPIO0
27
45
SDA SCL TCK1 TCK0
PLACE_NEAR=U1800.P8:2.54mm
XDP
2
1
R2582
2
PLACE_NEAR=U1800.J3:2.54mm
1
517S0774
C2581
Apple Inc.
0.1uF
2
2
10% 16V X5R 402
7
6
5
D
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
SIZE
REVISION
4
3
2
BRANCH
PAGE
25 OF 132 SHEET
23 OF 101
1
A
8
7
6
5
4
3
2
1 TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
HUB1_ALLREM
HUB1_NONREM1_0,HUB1_NONREM0_0
HUB1_1NONREM
HUB1_NONREM1_0,HUB1_NONREM0_1
HUB1_2NONREM
HUB1_NONREM1_1,HUB1_NONREM0_0
HUB1_3NONREM
HUB1_NONREM1_1,HUB1_NONREM0_1
HUB2_ALLREM
HUB2_NONREM1_0,HUB2_NONREM0_0
HUB2_1NONREM
HUB2_NONREM1_0,HUB2_NONREM0_1
HUB2_2NONREM
HUB2_NONREM1_1,HUB2_NONREM0_0
HUB2_3NONREM
HUB2_NONREM1_1,HUB2_NONREM0_1
TABLE_BOMGROUP_ITEM
BYPASS=U2600.5::2MM
PP3V3_S3
87 72 30 29 25 24 19 18 8 7 6 71 54 53 49 48 47 32 31
TABLE_BOMGROUP_ITEM
BYPASS=U2600.5::5MM
C2602
1
4.7UF
20% 6.3V 2 X5R 603
C2603
1
1
0.1UF
C2611 0.1UF
10% 16V X7R-CERM 2 402
10% 2 16V X7R-CERM 402
1
TABLE_BOMGROUP_ITEM
C2612 0.1UF
TABLE_BOMGROUP_ITEM
10% 16V 2 X7R-CERM 402
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BYPASS=U2600.15::2MM BYPASS=U2600.10::2MM BYPASS=U2600.23::5MM BYPASS=U2600.23::2MM
D
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
C2610
0.1UF
10% 16V X7R-CERM 2 402
PPUSB_HUB1_VDD1V8
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.8V
0.1UF
10% 16V X7R-CERM 2 402
10% 16V X7R-CERM 2 402
BYPASS=U2600.36::2MM BYPASS=U2600.29::2MM
Y2600 SM-2
VDD33
24.000MHZ-16PF 1
CRITICAL
C2619
5% 50V CERM 2 HUB1_NONREM0_1 402
HUB1_NONREM1_1
R26011
10K
1M
5% 50V 2 CERM 402
5% 1/16W MF-LF 402
1
100
5% 1/16W MF-LF 402
10K 5% 1/16W MF-LF 2 402
1
0.1UF
10% 16V 2 X7R-CERM 402
4.7UF
TEST
USB_HUB_RESET_L
26
RESET*
USB_HUB1_XTAL1 USB_HUB1_XTAL2
33 32
XTALIN/CLKIN XTALOUT
USB_HUB1_NONREM0
28
SUSP_IND/LOCAL_PWR/NON_REM0
USB_HUB1_NONREM1
22
SDA/SMBDATA/NON_REM1
USB_HUB1_CFG_SEL0
24
USB_HUB1_CFG_SEL1
25
10K
10K
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
C2653 1
1
USBDM_DN1/PRT_DIS_M1 1 USBDP_DN1/PRT_DIS_P1 2
OMIT
C2661
1
BI
8 92
BI
8 92
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
2
SMSC USB2514
U2600,U2650
CRITICAL
USBHUB_2514 USBHUB_2514B
10% 2 16V X7R-CERM 402
SMSC USB2514B
U2600,U2650
338S0721
2
SMSC USX2061
U2600,U2650
CRITICAL
USBHUB_2061
U2600,U2650
CRITICAL
USBHUB_2513B
TABLE_5_ITEM
43 92
BI
43 92
USBDM_DN3/PRT_DIS_M3 6 USBDP_DN3/PRT_DIS_P3 7
USB_EXTB_N USB_EXTB_P
BI
42 92
BI
42 92
NC 8 NC 9
USB_EXTC_N USB_EXTC_P
BI
8 92
BI
8 92
PRTPWR1/BC_EN1* PRTPWR2/BC_EN2* PRTPWR3/BC_EN3* NC
12 16 18 20
TP_USB_HUB1_PRTPWR1 NC_USB_HUB1_PRTPWR2 NC_USB_HUB1_PRTPWR3 NC_USB_HUB1_PRTPWR4
OCS1* OCS2* OSC3* NC
13 17 19 21
TP_USB_HUB1_OCS1 NC_USB_HUB1_OCS2 USB_EXTB_OC_L NC_USB_HUB1_OCS4
2
SMSC USX2513B
IR Receiver External B External C
6
PP3V3_S3
6
C
6 7 8 18 19 24 25 29 30 31 32 47 48 49 53 54 71 72 87
1
R2620 10K
IN
42
IN
8
5% 1/16W MF-LF 2 402
USB_HUB1_RBIAS
PP3V3_S3
32 31 30 29 25 24 19 18 8 7 6 87 72 71 54 53 49 48 47
R2640
VBUS_DET 27
USB_HUB1_VBUS_DET
USBDM_UP 30 USBDP_UP 31
USB_HUB1_UP_N USB_HUB1_UP_P
PP3V3_S5
18 92
BI
18 92
20K
1
39 29 25 23 22 20 19 17 7 6 98 89 85 82 72 71 70 65 55 45
CRITICAL
BI
2
5% 1/16W MF-LF 402
1
R2600 12K
1% 1/16W MF 2 402
THRM_PAD
C2662
2
338S0923 BI
HS_IND/CFG_SEL1
338S0824
CRITICAL
TABLE_5_ITEM
T29 - no longer used, pulled up to 3V3 S0
USB_IR_N USB_IR_P
SCL/SMBCLK/CFG_SEL0
0.1UF
10% 2 16V X7R-CERM 402
USB_T29A_N USB_T29A_P
USBDM_DN2/PRT_DIS_M2 3 USBDP_DN2/PRT_DIS_P2 4
IPU IPU IPU IPU
0.1UF
10% 16V X7R-CERM 2 402
QTY
TABLE_5_ITEM
BYPASS=U2650.5::2MM
0.1UF
20% 6.3V 2 X5R 603
BOM TABLE
37
1
10% 16V 2 X5R 402
338S0720
1
BYPASS=U2650.5::5MM
C2652
1UF
1UF
10% 16V 2 X5R 402
TABLE_5_HEAD
RBIAS 35
PP3V3_S3
10% 16V 2 X7R-CERM 402
C2616
NON_REM0 DESCRIPTION All ports are removable Port 1 is non removable Port 1 and 2 are non removable Port 1, 2, and 3 are non removable
PART#
R2606 R2607
87 72 71 29 25 24 19 18 8 7 6 54 53 49 48 47 32 31 30
1
0 1 0 1
1
R2641 10K
1
R2642 100K
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF
NOSTUFF 1
C2641
2402
100PF
5% 50V 2 CERM 402
USB_HUB_RESET
USB_HUB_RESET_L
6
BYPASS=U2650.15::2MM BYPASS=U2650.10::2MM BYPASS=U2650.23::5MM BYPASS=U2650.23::2MM
B
10% 16V X7R-CERM 2 402
CRITICAL
0.1UF
10% 16V X7R-CERM 2 402
VDD33
24.000MHZ-16PF 1
CRITICAL
C2669 18PF
HUB2_NONREM0_1 402
R26511
1
R2653
10K
10K
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
HUB2_NONREM1_0
CRITICAL
2 4
1
5% 50V CERM 2
HUB2_NONREM1_1
3 1
R2680 1
1M
18PF
5% 1/16W MF-LF 402
SYM VER 1
1
100
5% 1/16W MF-LF 402
CRITICAL
1
R2654
10K
10K
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
24
USB_HUB_RESET_L USB_HUB2_XTAL1 USB_HUB2_XTAL2
11 26 33 32
TEST
OMIT RESET*
1
C2665 0.1UF
5
G
1
C2666 1UF
10% 16V 2 X7R-CERM 402
1
Q2640
2N7002DW-X-G SOT-363
S
4
C2640 0.47UF
C2668
10% 6.3V 2 CERM-X5R 402
1UF
10% 16V 2 X5R 402
B
10% 2 16V X5R 402
D2600 SOD-523 23 18
IN
USB_HUB_SOFT_RESET_L
2
1
BAT54XV2T1
XTALIN/CLKIN XTALOUT
USBDM_DN1/PRT_DIS_M1 1 USBDP_DN1/PRT_DIS_P1 2
USB_BT_N USB_BT_P
USBDM_DN2/PRT_DIS_M2 3 USBDP_DN2/PRT_DIS_P2 4
USB_HUB2_NONREM0
28
USB_HUB2_NONREM1
22
USB_HUB2_CFG_SEL0
24
USBDM_DN3/PRT_DIS_M3 6 SUSP_IND/LOCAL_PWR/NON_REM0 USBDP_DN3/PRT_DIS_P3 7 SDA/SMBDATA/NON_REM1 NC 8 SCL/SMBCLK/CFG_SEL0 NC 9
USB_HUB2_CFG_SEL1
25
HS_IND/CFG_SEL1
R2656 1R2657 10K
10K
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
PRTPWR1/BC_EN1* PRTPWR2/BC_EN2* PRTPWR3/BC_EN3* NC
12 16 18 20
OCS1* OCS2* OSC3* NC
13 17 19 21
IPU IPU IPU IPU
37
THRM_PAD
7
0.1UF
10% 16V 2 X7R-CERM 402
RBIAS 35
8
SOT-363
QFN
USB_HUB2_TEST
2
1
A
C2667
CRITICAL
D
2N7002DW-X-G
USB2513B
R2655
HUB2_NONREM0_0
R26521
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.8V
Q2640
S
U2650
C2670
5% 50V 2 CERM 402
2
1
PPUSB_HUB2_VDD1V8PLL
BYPASS=U2650.36::2MM BYPASS=U2650.29::2MM
Y2650 SM-2
1
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.8V
10% 16V X7R-CERM 2 402
G
1
PPUSB_HUB2_VDD1V8
34
20% 6.3V 2 X5R 603
0.1UF
1
14
0.1UF
C2660
1
CRFILT
4.7UF
C2659
PLLFILT
C2658 1
1
2
P3V3S3_EN_RC
3
CRITICAL
D
5 10 15 23 29 36
C2657
D
TABLE_5_ITEM
11
24
R2604
10K 5% 1/16W MF-LF 402 2
C2615
NON_REM1 0 0 1 1
C2618
QFN
USB_HUB1_TEST
2
1
R2602
0.1UF
1
1
USB2513B
R2605
HUB1_NONREM0_0
1
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.8V
C2617
U2600
C2620 18PF
2
SYM VER 1
CRITICAL
5% 1/16W MF-LF 2 402
HUB1_NONREM1_0
C
1
R2603
10K
1
R2630
1
5% 1/16W MF-LF 402 2
CRITICAL
2 4
1
18PF
3
1
PPUSB_HUB1_VDD1V8PLL 34
C2609
0.1UF
14
CRITICAL
C2608
1
CRFILT
20% 6.3V 2 X5R 603
1
PLLFILT
4.7UF
1
5 10 15 23 29 36
C2607
1
6
5
BI
31 92
BI
31 92
USB_TPAD_N USB_TPAD_P
BI
52 92
BI
52 92
USB_EXTA_N USB_EXTA_P
BI
42 92
BI
42 92
BI
8
USB_SDCARD_N USB_SDCARD_P
TP_USB_HUB2_OCS1 6 NC_USB_HUB2_OCS2 USB_EXTA_OC_L NC_USB_HUB2_OCS4
Trackpad/Keyboard External A SD Card/Express Card
8
BI
TP_USB_HUB2_PRTPWR1 NC_USB_HUB2_PRTPWR2 NC_USB_HUB2_PRTPWR3 NC_USB_HUB2_PRTPWR4
Bluetooth
6
PP3V3_S3
1
R2670 10K
IN
42
IN
8
USB_HUB2_VBUS_DET
USBDM_UP 30 USBDP_UP 31
USB_HUB2_UP_N USB_HUB2_UP_P
SYNC_MASTER=K91_ERIC SYNC_DATE=10/08/2010
5% 1/16W MF-LF 2 402
USB_HUB2_RBIAS
VBUS_DET 27
6 7 8 18 19 24 25 29 30 31 32 47 48 49 53 54 71 72 87
PAGE TITLE
USB HUBS DRAWING NUMBER
Apple Inc.
CRITICAL
BI BI
18 92
1
R2650
SIZE
D REVISION
R
12K
18 92
1% 1/16W MF 2 402
4
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
3
2
BRANCH
PAGE
26 OF 132 SHEET
24 OF 101
1
A
8
7
6
5
4
3
2
1
Platform Reset Connections Unbuffered
Ethernet WAKE# Isolation
PCH Reset Button R2895
90 23 10
IN
XDP_DBRESET_L
0
1
5% 1/16W MF-LF 402
Q2830
5% 1/16W MF-LF 2 402
SOD-VESM-HF
PM_SYSRST_L
2
5% 1/16W MF-LF 402
6 17 44
BI
84 31 17 6
PCIE_WAKE_L
OUT
3
36 25
6 25 46 87 93
OUT
6 25 46 87 93
OUT
44
R2883 33
SMC_LRESET_L
2
D
R2871 1
5% 1/16W MF-LF 2 402
ENET_WAKE_L
ENET_WAKE_L
MAKE_BASE=TRUE
2
OUT
5% 1/16W MF-LF 402
10K
1
SSM3K15FV
LPCPLUS_RESET_L LPCPLUS_RESET_L MAKE_BASE=TRUE
6 7 25 36 70 72
R2830
G
XDP
2
1
4.7K
R2896
33
1
CRITICAL
1
S
D
R2881
PLT_RESET_L MAKE_BASE=TRUE
1
PP3V3_ENET
PP3V3_S0
D
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
IN
0
2
PCA9557D_RESET_L
OUT
30
XDPPCH_PLTRST_L
OUT
23
5% 1/16W MF-LF 402 IN
25 36
XDP
R2889
OMIT 1
1
R2897 0
1K
2
5% 1/16W MF-LF 402
5% 1/16W MF-LF 2 402
R2887
SILK_PART=SYS RESET
0
1
GMUX_RESET_L
2
25 87
MAKE_BASE=TRUE
5% 1/16W MF-LF 402
GMUX_RESET_L
ENET_MEDIA_SENSE ISOLATION CIRCUIT
PLT_RESET_L Series R is R4283
PLACE_NEAR=U1800.N32:5mm
OUT
25 87
OUT
18 25 29 39
R2810 36
IN
ENET_MEDIA_SENSE
1
12K
402 MF-LF
C 47 32 31 30 29 24 19 18 8 7 6 87 72 71 54 53 49 48
IN
PLACE_NEAR=U1800.N52
LPC_CLK33M_SMC_R
22
1
IN
18
IN
IN
LPC_CLK33M_GMUX_R
LPC_CLK33M_GMUX_R
25 18
22
1
MAKE_BASE=TRUE
22
2
LPC_CLK33M_LPCPLUS
OUT
5
G
S
CRITICAL
4
2 5 1
87
OUT
70 56 41 22 20 16 7
2
R2812
PCH_CLK33M_PCIIN
16 93
OUT
SOT563 D
35 32 25
PLT_RST_BUF_L
PLT_RST_BUF_L
PLT_RST_BUF_L OUT Series R on Pg38, R3803
100K
5% 1/16W MF-LF 2 402
20% 10V CERM 2 402
1
G
S
25 32 35
25 32 35
R2888
5% 1/16W MF-LF 2 402 2
OUT
MAKE_BASE=TRUE
R2880
3
0.1UF
6
0
5% 1/20W MF 201
SC70-HF
U2880 4
C2880 1
Q2810 1
MC74VHC1G08
1
SSM6N37FEAPE
PP1V5_S0
R2859 22
Note: Based on K91/K92 layout, ENET,AP and BKLT are moved to Buffered reset.
PP3V3_S0
41 40 39 36 35 32 28 26 25 88 87 84 83 82 79 72 71 61
2
LPC_CLK33M_GMUX
1
98 89 56 53 51 50 49 48 47 45 2 2360 22 20 19 18 17 16 12 7 6
ENET_MEDIA_SENSE_EN_L
2
PLACE_NEAR=U1800.P48
C Buffered
6 46 93
5% 1/20W MF 201
5% 1/20W MF 201
PCH_CLK33M_PCIOUT
1
R2857
PLACE_NEAR=U1800.P46 25 18
R2856
PLACE_NEAR=U1800.P53
LPC_CLK33M_LPCPLUS_R
5% 1/20W MF 201
100K 5% 1/20W MF 201
16
10K
R2811 1
44 93
OUT
OUT
R2819 1
Q2810 SOT563
LPC_CLK33M_SMC
2
5% 1/20W MF 201 18
ENET_MEDIA_SENSE_RDIV
2
CRITICAL SSM6N37FEAPE3 D
PP3V3_S3
R2855 93 18
5%
1/16W
0
2
AP_RESET_L
OUT
31
OUT
88
5% 1/16W MF-LF 402
1
ENET_MEDIA_SENSE_EN
R2893 1
System RTC Power Source & 32kHz / 25MHz Clock Generator B
VDDIO_25M_A: SB power rail for XTAL circuit. VDDIO_25M_B: Ethernet power rail for XTAL circuit. VDDIO_25M_C: T29 power rail for XTAL circuit. 63
98 39 29 24 23 22 20 19 17 7 6 89 85 82 72 71 70 65 55 45
GreenClk 25MHz Power 72
70 36 25 7 6
PP3V3_ENET
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
CRITICAL 5
PP3V3_S5 Coin-Cell & G3Hot: 3.42V G3Hot Coin-Cell & No G3Hot: 3.3V S5 No Coin-Cell: 3.3V S5 No bypass necessary
1
0.1UF
C2822
1
0.1UF
20%
C2820 1 0.1UF
20%
10V CERM 2
20%
10V CERM 2
402
10V CERM 2
402
402
1
C2802 1UF
+3.42V 13
C2824
U2800
10% 10V 2 X5R 402-1
SLG3NB148V TQFN
CRITICAL 11 6 14
R2805
C2806
1
CRITICAL 2
5% 50V CERM 402
4
A
SYSCLK_CLK25M_X2
1
3
2
NC NC
Y2805
25.000MHZ-12PF-20PPM
2
SYSCLK_CLK25M_X2_R NO STUFF
3 4
R2806 1M
X2 X1
GND
5% 1/16W MF-LF 2 402
PLT_RST_CPU_BUF_L
PLT_RST_CPU_BUF_L OUT
1 3 NC
+V3.3A should be first available ~3.3V power to reduce VBAT draw.
R2890 100K
5% 1/16W MF-LF 2 402
NOTE: This page is different for K92. ENET_RESET_L hooked up differently on both the projects.
32KHZ_A 12
SYSCLK_CLK32K_RTC
25MHZ_A 9 25MHZ_B 8 25MHZ_C 15
SYSCLK_CLK25M_SB OUT SYSCLK_CLK25M_ENET_R SYSCLK_CLK25M_T29 OUT PPVRTC_G3H 7 16 17 20 For SB RTC Power
THRM PAD
1
OUT
16
R2800 1 33
0
2
SYSCLK_CLK25M_ENET
OUT
36
5% 1/20W MF 201
SYNC_MASTER=K92_MLB
SYNC_DATE=07/06/2010
PAGE TITLE
Chipset Support
C2810
DRAWING NUMBER
1UF
10% 6.3V 2 CERM 402
SYSCLK_CLK25M_X1
Apple Inc. NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
6
5
SIZE
D REVISION
R
NOTE: 30 PPM crystal required
7
10 23 25
VTT voltage divider on CPU page
1
VBAT and +V3.3A are internally ORed to create VDD_RTC_OUT.
VDD_RTC_OUT 1
1
2
5% 50V CERM 402
8
5% 1/16W MF-LF 402
SM-3.2X2.5MM
12PF 1
1
0
7 10 16
12PF
VDDIO_25M_A VDDIO_25M_B VDDIO_25M_C
20% 10V CERM 2 402
17
C2805
25 23 10
MAKE_BASE=TRUE NC
+V3.3A 2
7
U2890 74LVC1G07 SC70 4
2
0.1UF
PP3V3_ENET PP1V8_S0 PP3V3_T29
VDD_25M 5
6
BKLT_PLT_RST_L
Buffered CPU reset
PP3V3_S0
C2890 1 6
2
B PP3V42_G3H Coin-Cell: VBAT (300-ohm & 10uF RC) No Coin-Cell: 3.42V G3Hot (no RC)
62 52 47 46 45 44 42 7 6 72
NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.
Ethernet XTAL Power 72 70 36 25 7 SB XTAL Power 87 71 70 22 20 17 14 7 T29 XTAL Power 87 35 34 33 19 16
0
5% 1/16W MF-LF 402
4
3
2
BRANCH
PAGE
28 OF 132 SHEET
25 OF 101
1
A
8
7
6
5
3
2
1
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
Page Notes 71 66 29 28 7 6
4
PP1V5_S3
Power aliases required by this page: - =PP1V5_S0_MEM_A
1
- =PP1V5_S3_MEM_A
Signal aliases required by this page:
1
C2900 10UF
- =I2C_SODIMMA_SCL - =I2C_SODIMMA_SDA
PLACE_NEAR=J2900.75:2.54mm BOM options provided by this page:
20% 6.3V 2 X5R 603
1
C2911
1
1
0.1UF
C2912 0.1UF
20% 10V 2 CERM 402
20% 2 10V CERM 402
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
D
C2910 0.1UF
- =PP0V75_S0_MEM_VTT_A
20% 10V 2 CERM 402
1
C2913 0.1UF
20% 10V 2 CERM 402
1
C2914 0.1UF
20% 10V 2 CERM 402
1
C2915 0.1UF
20% 2 10V CERM 402
1
C2916
1
0.1UF
C2917
1
0.1UF
20% 2 10V CERM 402
C2918 0.1UF
20% 2 10V CERM 402
20% 2 10V CERM 402
1
C2919 0.1UF
20% 10V 2 CERM 402
1
C2920 0.1UF
20% 2 10V CERM 402
1
C2921
1
0.1UF
C2922 0.1UF
20% 2 10V CERM 402
20% 10V 2 CERM 402
1
C2923 0.1UF
20% 10V 2 CERM 402
PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm
C2901 10UF
20% 6.3V 2 X5R 603
PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm 30 9
PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm
D
PP0V75_S3_MEM_VREFDQ_A
(NONE)
1
C2930
1
C2931
2.2UF
PLACE_NEAR=J2900.75:2.54mm 2
0.1UF
20% 6.3V CERM 402-LF
2
20% 10V CERM 402
OMIT_TABLE
NC 91 11 6
C
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6 91 11 6
IN IN
MEM_A_BA<2>
75 77 79 81 83
MEM_A_A<12> MEM_A_A<9>
85 87 89
MEM_A_A<8> MEM_A_A<5>
91 93 95
MEM_A_A<3> MEM_A_A<1>
97 99
MEM_A_CLK_P<0> MEM_A_CLK_N<0>
101
MEM_A_A<10> MEM_A_BA<0>
107
MEM_A_WE_L MEM_A_CAS_L
113
MEM_A_A<13> MEM_A_CS_L<1>
119 121
103 105 109 111 115 117
123
NC 27
BI
27
BI
27
BI
27
BI
27
BI
27
BI
125 127
=MEM_A_DQ<32> =MEM_A_DQ<33>
129
=MEM_A_DQS_N<4> =MEM_A_DQS_P<4>
135
=MEM_A_DQ<34> =MEM_A_DQ<35>
141 143
131 133 137 139
145 27
BI
27
BI
=MEM_A_DQ<40> =MEM_A_DQ<41>
147 149 151 153 155
B
27
BI
27
BI
27
BI
27
BI
=MEM_A_DQ<42> =MEM_A_DQ<43>
157
=MEM_A_DQ<48> =MEM_A_DQ<49>
163 165
159 161
167 91 27 11 6
BI
91 27 11 6
BI
27
BI
27
BI
MEM_A_DQS_N<6> MEM_A_DQS_P<6>
169 171 173
=MEM_A_DQ<50> =MEM_A_DQ<51>
175 177 179
27
BI
27
BI
=MEM_A_DQ<56> =MEM_A_DQ<57>
181 183 185 187 189
27
BI
27
BI
=MEM_A_DQ<58> =MEM_A_DQ<59>
191 193 195
82 79 72 71 61 45 41 40 39 36 18 17 16 12 7 6 35 32 28 25 23 22 20 19 60 56 53 51 50 49 48 47 98 89 88 87 84 83
6
MEM_A_SA<0>
197 199
6
MEM_A_SA<1>
201
PP3V3_S0
203 1 1
A
C2940 2.2UF
2
20% 6.3V CERM 402-LF
2
1
R2940
J2900
74
MEM_A_CKE<1>
76 78
IN
6 11 91
27 27
MEM_A_A<15> MEM_A_A<14>
80 82 84
MEM_A_A<11> MEM_A_A<7>
86 88 90
MEM_A_A<6> MEM_A_A<4>
92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122
IN
6 11 91
IN
6 11 91
BI BI
IN
6 11 91
27
BI
IN
6 11 91
27
BI
IN
6 11 91
27
BI
IN
6 11 91
27
BI
IN
6 11 91
27
BI
IN
6 11 91
27
BI
MEM_A_CLK_P<1> MEM_A_CLK_N<1>
IN
6 11 91
27
BI
IN
6 11 91
27
BI
MEM_A_BA<1> MEM_A_RAS_L
IN
6 11 91
27
BI
IN
6 11 91
27
BI
MEM_A_CS_L<0> MEM_A_ODT<0>
IN
6 11 91
27
BI
IN
6 11 91
27
BI
IN
7 9 11
MEM_A_A<2> MEM_A_A<0>
MEM_A_ODT<1>
=MEM_A_DQ<0> =MEM_A_DQ<1>
6 11 91
NC
27
BI
27
BI
13 15
=MEM_A_DQ<2> =MEM_A_DQ<3>
17 19 21
=MEM_A_DQ<8> =MEM_A_DQ<9>
23 25 27
=MEM_A_DQS_N<1> =MEM_A_DQS_P<1>
29 31 33
=MEM_A_DQ<10> =MEM_A_DQ<11>
35 37 39
=MEM_A_DQ<16> =MEM_A_DQ<17>
41 43 45
=MEM_A_DQS_N<2> =MEM_A_DQS_P<2>
47 49 51 53
=MEM_A_DQ<18> =MEM_A_DQ<19>
124
55
126 128 130 132 134
MEM_A_DQ<32> =MEM_A_DQ<37>
BI
6 11 27 91
BI
27
142 144 146 148 150 152 154 156 158 160 162 164 166
=MEM_A_DQ<38> =MEM_A_DQ<39>
BI
27
BI
27
=MEM_A_DQ<44> =MEM_A_DQ<45>
BI
27
BI
27
=MEM_A_DQS_N<5> =MEM_A_DQS_P<5>
BI
27
BI
27
=MEM_A_DQ<46> =MEM_A_DQ<47>
BI
27
BI
27
=MEM_A_DQ<52> =MEM_A_DQ<53>
BI
27
BI
27
=MEM_A_DQ<54> =MEM_A_DQ<55>
BI
27
BI
27
=MEM_A_DQ<60> =MEM_A_DQ<61>
BI
27
BI
27
BI
27
BI
57 59
=MEM_A_DQ<24> =MEM_A_DQ<25>
61 63 65
136 138 140
27
27
BI
27
BI
67
=MEM_A_DQ<26> =MEM_A_DQ<27>
69 71
J2900
2 4 6
=MEM_A_DQ<4> =MEM_A_DQ<5>
BI
27
BI
27
=MEM_A_DQS_N<0> =MEM_A_DQS_P<0>
BI
27
BI
27
=MEM_A_DQ<6> =MEM_A_DQ<7>
BI
27
BI
27
=MEM_A_DQ<12> =MEM_A_DQ<13>
BI
27
BI
27
30 32
MEM_RESET_L
IN
34
=MEM_A_DQ<14> =MEM_A_DQ<15>
BI
27
BI
27
=MEM_A_DQ<20> =MEM_A_DQ<21>
BI
27
BI
27
=MEM_A_DQ<22> =MEM_A_DQ<23>
BI
27
BI
27
=MEM_A_DQ<28> =MEM_A_DQ<29>
BI
27
BI
27
=MEM_A_DQS_N<3> =MEM_A_DQS_P<3>
BI
27
BI
27
=MEM_A_DQ<30> =MEM_A_DQ<31>
BI
27
BI
27
8 10 12 14 16 18 20 22 24 26 28
36 38 40 42 44
28 29
C
46 48 50 52 54 56 58 60 62 64 66 68 70 72
KEY
See CSA05 BOM table
B
168 170 172 174 176 178 180 182 184 186 188
PP0V75_S3_MEM_VREFCA_A
1
C2935
1
C2936
2.2UF
=MEM_A_DQS_N<7> =MEM_A_DQS_P<7>
BI
27
BI
27
=MEM_A_DQ<62> =MEM_A_DQ<63>
BI
27
BI
27
2
20% 6.3V CERM 402-LF
30
0.1UF 2
20% 10V CERM 402
190 192 194 196 198 200 202
MEM_EVENT_L SMBUS_PCH_DATA SMBUS_PCH_CLK
OUT
28 44
BI IN
"Factory" (top) slot
16 23 28 30 41 47 61 88 93 16 23 28 30 41 47 61 88 93
204
PP0V75_S0_DDRVTT
6 7 28 29 66
R2941
10K
10K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
CKE0 CKE1 VDD VDD NC A15 BA2 A14 F-RT-THB VDD VDD A12/BC* A11 A9 A7 VDD VDD A8 A6 A5 A4 VDD VDD A3 A2 A0 A1 VDD VDD CK0 CK1 CK0* CK1* VDD VDD A10/AP BA1 BA0 RAS* VDD VDD WE* S0* CAS* ODT0 VDD VDD A13 ODT1 S1* NC VDD VDD TEST VREFCA VSS VSS DQ32 DQ36 DQ33 DQ37 VSS VSS DQS4* DM4 DQS4 VSS VSS DQ38 DQ34 DQ39 DQ35 VSS VSS DQ44 DQ40 DQ45 DQ41 VSS VSS DQS5* DM5 DQS5 VSS VSS DQ42 DQ46 DQ43 DQ47 VSS VSS DQ48 DQ52 DQ49 DQ53 VSS VSS DQS6* DM6 DQS6 VSS VSS DQ54 DQ50 DQ55 DQ51 VSS VSS DQ60 DQ56 DQ61 DQ57 VSS VSS DQS7* DM7 DQS7 VSS VSS DQ58 DQ62 DQ59 DQ63 VSS VSS SA0 EVENT* VDDSPD SDA SA1 SCL VTT VTT
3 5
VREFDQ VSS VSS DQ4 DQ0 DQ5 CRITICAL DQ1 VSS VSS DQS0* DM0 DQS0 F-RT-THB VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ8 DQ12 DQ9 DQ13 VSS VSS DQS1* DM1 DQS1 RESET* VSS VSS DQ10 DQ14 DQ11 DQ15 VSS VSS DQ16 DQ20 DQ17 DQ21 VSS VSS DQS2* DM2 DQS2 VSS DQ22 VSS DQ18 DQ23 DQ19 VSS DQ28 VSS DQ24 DQ29 DQ25 VSS DQS3* VSS DM3 DQS3 VSS VSS DQ26 DQ30 DQ27 DQ31 VSS VSS (SYMBOL 1 OF 2)
73
MEM_A_CKE<0>
(SYMBOL 2 OF 2)
IN
DDR3-SODIMM-DUAL-K6
91 11 6
KEY
1
DDR3-SODIMM-DUAL-K6
OMIT_TABLE
1
516-0229
C2950 1UF
SPD ADDR=0xA0(WR)/0xA1(RD)
10% 2 10V X5R 402
1
C2951 1UF
10% 2 10V X5R 402
1
C2952 1UF
10% 2 10V X5R 402
1
C2953
SYNC_MASTER=K92_SUMA
1UF
10% 2 10V X5R 402
SYNC_DATE=06/23/2010
PAGE TITLE
DDR3 SO-DIMM Connector A DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
29 OF 132 SHEET
26 OF 101
1
A
8
7
6
CPU CHANNEL A DQS 0 -> DIMM A DQS 0 91 11 6 91 11 6
MEM_A_DQS_N<0> MEM_A_DQS_P<0>
MAKE_BASE=TRUE
5
4
3
2
1
CPU CHANNEL B DQS 0 -> DIMM B DQS 0
=MEM_A_DQS_N<0> =MEM_A_DQS_P<0>
26
91 11 6
26
91 11 6
MEM_B_DQS_N<0> MEM_B_DQS_P<0>
MAKE_BASE=TRUE
=MEM_B_DQS_N<0> =MEM_B_DQS_P<0>
28 28
MAKE_BASE=TRUE 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6
D
91 11 6
MEM_A_DQ<7> MEM_A_DQ<6> MEM_A_DQ<5> MEM_A_DQ<4> MEM_A_DQ<3> MEM_A_DQ<2> MEM_A_DQ<1> MEM_A_DQ<0>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DQ<3> =MEM_A_DQ<6> =MEM_A_DQ<5> =MEM_A_DQ<4> =MEM_A_DQ<7> =MEM_A_DQ<0> =MEM_A_DQ<1> =MEM_A_DQ<2>
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
MEM_B_DQ<7> MEM_B_DQ<6> MEM_B_DQ<5> MEM_B_DQ<4> MEM_B_DQ<3> MEM_B_DQ<2> MEM_B_DQ<1> MEM_B_DQ<0>
MAKE_BASE=TRUE
91 11 6
MEM_A_DQS_N<1> MEM_A_DQS_P<1>
MAKE_BASE=TRUE
91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DQS_N<1> =MEM_A_DQS_P<1>
26
91 11 6
26
91 11 6
MEM_B_DQS_N<1> MEM_B_DQS_P<1>
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
MEM_A_DQS_N<2> MEM_A_DQS_P<2>
MAKE_BASE=TRUE
MEM_B_DQ<15> MEM_B_DQ<14> MEM_B_DQ<13> MEM_B_DQ<12> MEM_B_DQ<11> MEM_B_DQ<10> MEM_B_DQ<9> MEM_B_DQ<8>
91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6
MEM_A_DQ<23> MEM_A_DQ<22> MEM_A_DQ<21> MEM_A_DQ<20> MEM_A_DQ<19> MEM_A_DQ<18> MEM_A_DQ<17> MEM_A_DQ<16>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DQS_N<2> =MEM_A_DQS_P<2>
26
91 11 6
26
91 11 6
MEM_B_DQS_N<2> MEM_B_DQS_P<2>
=MEM_A_DQ<23> =MEM_A_DQ<22> =MEM_A_DQ<17> =MEM_A_DQ<20> =MEM_A_DQ<19> =MEM_A_DQ<18> =MEM_A_DQ<16> =MEM_A_DQ<21>
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
91 11 6
MEM_A_DQS_N<3> MEM_A_DQS_P<3>
MAKE_BASE=TRUE
MEM_B_DQ<23> MEM_B_DQ<22> MEM_B_DQ<21> MEM_B_DQ<20> MEM_B_DQ<19> MEM_B_DQ<18> MEM_B_DQ<17> MEM_B_DQ<16>
91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6
MEM_A_DQ<31> MEM_A_DQ<30> MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DQ<27> MEM_A_DQ<26> MEM_A_DQ<25> MEM_A_DQ<24>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DQS_N<3> =MEM_A_DQS_P<3>
26
91 11 6
26
91 11 6
MEM_B_DQS_N<3> MEM_B_DQS_P<3>
=MEM_A_DQ<31> =MEM_A_DQ<30> =MEM_A_DQ<29> =MEM_A_DQ<28> =MEM_A_DQ<27> =MEM_A_DQ<26> =MEM_A_DQ<25> =MEM_A_DQ<24>
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26 26
91 11 6 91 11 6
MEM_A_DQS_N<4> MEM_A_DQS_P<4>
MAKE_BASE=TRUE
MEM_B_DQ<31> MEM_B_DQ<30> MEM_B_DQ<29> MEM_B_DQ<28> MEM_B_DQ<27> MEM_B_DQ<26> MEM_B_DQ<25> MEM_B_DQ<24>
91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 27 26 11 6
MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<37> MEM_A_DQ<36> MEM_A_DQ<35> MEM_A_DQ<34> MEM_A_DQ<33> MEM_A_DQ<32>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DQS_N<4> =MEM_A_DQS_P<4>
26
91 11 6
26
91 11 6
=MEM_A_DQ<38> =MEM_A_DQ<37> =MEM_A_DQ<39> =MEM_A_DQ<33> =MEM_A_DQ<35> =MEM_A_DQ<34> =MEM_A_DQ<32> MEM_A_DQ<32>
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
6 11 26 27 91
27 11 6 91 28
CPU CHANNEL A DQS 5 -> DIMM A DQS 5 91 11 6 91 11 6
MEM_A_DQS_N<5> MEM_A_DQS_P<5>
MAKE_BASE=TRUE
MEM_B_DQS_N<4> MEM_B_DQS_P<4> MEM_B_DQ<39> MEM_B_DQ<38> MEM_B_DQ<37> MEM_B_DQ<36> MEM_B_DQ<35> MEM_B_DQ<34> MEM_B_DQ<33> MEM_B_DQ<32>
91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
26
91 11 6
26
91 11 6
91 27 26 11 6
MAKE_BASE=TRUE
=MEM_A_DQ<47> =MEM_A_DQ<41> =MEM_A_DQ<43> =MEM_A_DQ<44> =MEM_A_DQ<40> =MEM_A_DQ<46> =MEM_A_DQ<42> =MEM_A_DQ<45>
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26 26
91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6
MEM_A_DQ<55> MEM_A_DQ<54> MEM_A_DQ<53> MEM_A_DQ<52> MEM_A_DQ<51> MEM_A_DQ<50> MEM_A_DQ<49> MEM_A_DQ<48>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
MEM_B_DQS_N<5> MEM_B_DQS_P<5>
91 11 6 91 11 6
MEM_B_DQ<47> MEM_B_DQ<46> MEM_B_DQ<45> MEM_B_DQ<44> MEM_B_DQ<43> MEM_B_DQ<42> MEM_B_DQ<41> MEM_B_DQ<40>
6 11 26 27 91 6 11 26 27 91
=MEM_A_DQ<49> =MEM_A_DQ<54> =MEM_A_DQ<55> =MEM_A_DQ<52> =MEM_A_DQ<51> =MEM_A_DQ<50> =MEM_A_DQ<53> =MEM_A_DQ<48>
27 11 6 91 28 27 11 6 91 28
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
91 11 6
MEM_A_DQS_N<7> MEM_A_DQS_P<7>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
28 28 28 28
MAKE_BASE=TRUE
=MEM_B_DQS_N<2> =MEM_B_DQS_P<2>
28
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_B_DQ<23> =MEM_B_DQ<22> =MEM_B_DQ<21> =MEM_B_DQ<20> =MEM_B_DQ<19> =MEM_B_DQ<18> =MEM_B_DQ<17> =MEM_B_DQ<16>
28
28 28 28 28 28 28 28 28
MAKE_BASE=TRUE
=MEM_B_DQS_N<3> =MEM_B_DQS_P<3>
C
28 28
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_B_DQ<31> =MEM_B_DQ<30> =MEM_B_DQ<29> =MEM_B_DQ<28> =MEM_B_DQ<27> =MEM_B_DQ<26> =MEM_B_DQ<25> =MEM_B_DQ<24>
28 28 28 28 28 28 28 28
MAKE_BASE=TRUE
=MEM_B_DQS_N<4> =MEM_B_DQS_P<4>
28
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_B_DQ<39> =MEM_B_DQ<38> =MEM_B_DQ<37> =MEM_B_DQ<36> =MEM_B_DQ<35> =MEM_B_DQ<34> =MEM_B_DQ<33> MEM_B_DQ<32>
28
28 28 28 28 28 28 28 6 11 27 28 91
MAKE_BASE=TRUE
=MEM_B_DQS_N<5> =MEM_B_DQS_P<5>
28
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_B_DQ<47> =MEM_B_DQ<46> =MEM_B_DQ<45> =MEM_B_DQ<44> =MEM_B_DQ<43> =MEM_B_DQ<42> =MEM_B_DQ<41> =MEM_B_DQ<40>
B
28
28 28 28 28 28 28 28 28
MEM_B_DQS_N<6> MEM_B_DQS_P<6>
MAKE_BASE=TRUE
MEM_B_DQS_N<6> MEM_B_DQS_P<6>
6 11 27 28 91 6 11 27 28 91
MAKE_BASE=TRUE
MEM_B_DQ<55> MEM_B_DQ<54> MEM_B_DQ<53> MEM_B_DQ<52> MEM_B_DQ<51> MEM_B_DQ<50> MEM_B_DQ<49> MEM_B_DQ<48>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_B_DQ<55> =MEM_B_DQ<54> =MEM_B_DQ<53> =MEM_B_DQ<52> =MEM_B_DQ<51> =MEM_B_DQ<50> =MEM_B_DQ<49> =MEM_B_DQ<48>
28 28 28 28 28 28 28 28
MAKE_BASE=TRUE
CPU CHANNEL A DQS 7 -> DIMM A DQS 7 91 11 6
MAKE_BASE=TRUE
CPU CHANNEL B DQS 6 -> DIMM B DQS 6
MEM_A_DQS_N<6> MEM_A_DQS_P<6>
MAKE_BASE=TRUE
A
MAKE_BASE=TRUE
28 28
MAKE_BASE=TRUE
MAKE_BASE=TRUE 91 11 6
MAKE_BASE=TRUE
28
MAKE_BASE=TRUE
CPU CHANNEL A DQS 6 -> DIMM A DQS 6 MEM_A_DQS_N<6> MEM_A_DQS_P<6>
MAKE_BASE=TRUE
28
CPU CHANNEL B DQS 5 -> DIMM B DQS 5
=MEM_A_DQS_N<5> =MEM_A_DQS_P<5>
MAKE_BASE=TRUE
91 27 26 11 6
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<47> MEM_A_DQ<46> MEM_A_DQ<45> MEM_A_DQ<44> MEM_A_DQ<43> MEM_A_DQ<42> MEM_A_DQ<41> MEM_A_DQ<40>
28
MAKE_BASE=TRUE
MAKE_BASE=TRUE
B
MAKE_BASE=TRUE
=MEM_B_DQ<15> =MEM_B_DQ<14> =MEM_B_DQ<13> =MEM_B_DQ<12> =MEM_B_DQ<11> =MEM_B_DQ<10> =MEM_B_DQ<9> =MEM_B_DQ<8>
CPU CHANNEL B DQS 4 -> DIMM B DQS 4
MAKE_BASE=TRUE 91 11 6
28
MAKE_BASE=TRUE
CPU CHANNEL A DQS 4 -> DIMM A DQS 4 91 11 6
MAKE_BASE=TRUE
=MEM_B_DQS_N<1> =MEM_B_DQS_P<1>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
91 11 6
D
28
CPU CHANNEL B DQS 3 -> DIMM B DQS 3
MAKE_BASE=TRUE 91 11 6
28
MAKE_BASE=TRUE
CPU CHANNEL A DQS 3 -> DIMM A DQS 3 91 11 6
MAKE_BASE=TRUE
28 28
MAKE_BASE=TRUE
MAKE_BASE=TRUE
C
MAKE_BASE=TRUE
28
CPU CHANNEL B DQS 2 -> DIMM B DQS 2
MAKE_BASE=TRUE 91 11 6
MAKE_BASE=TRUE
28
MAKE_BASE=TRUE
CPU CHANNEL A DQS 2 -> DIMM A DQS 2 91 11 6
MAKE_BASE=TRUE
28
MAKE_BASE=TRUE
=MEM_A_DQ<15> =MEM_A_DQ<14> =MEM_A_DQ<12> =MEM_A_DQ<13> =MEM_A_DQ<10> =MEM_A_DQ<11> =MEM_A_DQ<9> =MEM_A_DQ<8>
MAKE_BASE=TRUE
91 11 6
MAKE_BASE=TRUE
28
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<15> MEM_A_DQ<14> MEM_A_DQ<13> MEM_A_DQ<12> MEM_A_DQ<11> MEM_A_DQ<10> MEM_A_DQ<9> MEM_A_DQ<8>
MAKE_BASE=TRUE
CPU CHANNEL B DQS 1 -> DIMM B DQS 1
CPU CHANNEL A DQS 1 -> DIMM A DQS 1 91 11 6
MAKE_BASE=TRUE
=MEM_B_DQ<6> =MEM_B_DQ<3> =MEM_B_DQ<5> =MEM_B_DQ<4> =MEM_B_DQ<1> =MEM_B_DQ<7> =MEM_B_DQ<2> =MEM_B_DQ<0>
CPU CHANNEL B DQS 7 -> DIMM B DQS 7
=MEM_A_DQS_N<7> =MEM_A_DQS_P<7>
26
91 11 6
26
91 11 6
MEM_B_DQS_N<7> MEM_B_DQS_P<7>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<7> =MEM_B_DQS_P<7>
28 28
MAKE_BASE=TRUE
SYNC_MASTER=K92_SUMA 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6 91 11 6
MEM_A_DQ<63> MEM_A_DQ<62> MEM_A_DQ<61> MEM_A_DQ<60> MEM_A_DQ<59> MEM_A_DQ<58> MEM_A_DQ<57> MEM_A_DQ<56>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DQ<59> =MEM_A_DQ<58> =MEM_A_DQ<56> =MEM_A_DQ<61> =MEM_A_DQ<63> =MEM_A_DQ<62> =MEM_A_DQ<57> =MEM_A_DQ<60>
MAKE_BASE=TRUE
8
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
26
91 11 6
MEM_B_DQ<63> MEM_B_DQ<62> MEM_B_DQ<61> MEM_B_DQ<60> MEM_B_DQ<59> MEM_B_DQ<58> MEM_B_DQ<57> MEM_B_DQ<56>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_B_DQ<63> =MEM_B_DQ<62> =MEM_B_DQ<61> =MEM_B_DQ<60> =MEM_B_DQ<59> =MEM_B_DQ<58> =MEM_B_DQ<57> =MEM_B_DQ<56>
DDR3 Byte/Bit Swaps DRAWING NUMBER
28 28
Apple Inc.
28
6
SIZE
D REVISION
R 28
NOTICE OF PROPRIETARY PROPERTY:
28
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
28
MAKE_BASE=TRUE
7
SYNC_DATE=05/10/2010
PAGE TITLE
28 28
5
4
3
2
BRANCH
PAGE
30 OF 132 SHEET
27 OF 101
1
A
8
7
6
4
3
2
1
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
Page Notes 71 66 29 26 7 6
5
PP1V5_S3
Power aliases required by this page: - =PP1V5_S0_MEM_B
1
- =PP1V5_S3_MEM_B
Signal aliases required by this page:
1
C3100 10UF
- =I2C_SODIMMB_SCL - =I2C_SODIMMB_SDA
PLACE_NEAR=J3100.75:2.54mm
BOM options provided by this page:
20% 2 6.3V X5R 603
1
C3111
1
0.1UF
20% 2 10V CERM 402
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
D
C3110 0.1UF
- =PP0V75_S0_MEM_VTT_B
20% 2 10V CERM 402
1
C3112
1
0.1UF
C3113
1
0.1UF
20% 2 10V CERM 402
C3114 0.1UF
20% 10V 2 CERM 402
20% 10V 2 CERM 402
1
C3115 0.1UF
20% 10V 2 CERM 402
1
C3116
1
0.1UF
C3117
1
0.1UF
20% 2 10V CERM 402
C3118 0.1UF
20% 2 10V CERM 402
20% 10V 2 CERM 402
1
C3119 0.1UF
20% 10V 2 CERM 402
1
C3120 0.1UF
20% 2 10V CERM 402
1
C3121 0.1UF
20% 10V 2 CERM 402
1
C3122 0.1UF
20% 10V 2 CERM 402
1
C3123 0.1UF
20% 10V 2 CERM 402
PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm
C3101 10UF
PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm
20% 6.3V 2 X5R 603
30 9
PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm
D
PP0V75_S3_MEM_VREFDQ_B
(NONE)
1
C3130
1
C3131
2.2UF
PLACE_NEAR=J3100.75:2.54mm 2
0.1UF
20% 6.3V CERM 402-LF
2
20% 10V CERM 402
OMIT_TABLE
C
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6
IN
91 11 6 91 11 6
MEM_B_BA<2>
IN
81 83
MEM_B_A<12> MEM_B_A<9>
85 87 89
MEM_B_A<8> MEM_B_A<5>
91 93 95
MEM_B_A<3> MEM_B_A<1>
IN IN
79
97 99
MEM_B_CLK_P<0> MEM_B_CLK_N<0>
101
MEM_B_A<10> MEM_B_BA<0>
107
MEM_B_WE_L MEM_B_CAS_L
113
MEM_B_A<13> MEM_B_CS_L<1>
119 121
103 105 109 111 115 117
123
NC 91 27 11 6
BI
27
BI
27
BI
27
BI
27
BI
27
BI
125 127
MEM_B_DQ<32> =MEM_B_DQ<33>
129
=MEM_B_DQS_N<4> =MEM_B_DQS_P<4>
135
=MEM_B_DQ<34> =MEM_B_DQ<35>
141 143
131 133 137 139
145 27
BI
27
BI
=MEM_B_DQ<40> =MEM_B_DQ<41>
147 149 151 153 155
B
27
BI
27
BI
27
BI
27
BI
=MEM_B_DQ<42> =MEM_B_DQ<43>
157
=MEM_B_DQ<48> =MEM_B_DQ<49>
163 165
159 161
167 91 27 11 6
BI
91 27 11 6
BI
27
BI
27
BI
MEM_B_DQS_N<6> MEM_B_DQS_P<6>
169 171 173
=MEM_B_DQ<50> =MEM_B_DQ<51>
175 177 179
27
BI
27
BI
=MEM_B_DQ<56> =MEM_B_DQ<57>
181 183 185 187 189
27
BI
27
BI
=MEM_B_DQ<58> =MEM_B_DQ<59>
191 193 195
89 88 87 84 83 82 49 48 47 45 41 40 19 18 17 16 12 7 6 39 36 35 32 26 25 23 22 20 79 72 71 61 60 56 53 51 50 98
6
MEM_B_SA<0>
197 199
6
MEM_B_SA<1>
201
PP3V3_S0
203 1 1
A
C3140 2.2UF
2
20% 6.3V CERM 402-LF
2
1
R3140
R3141
10K
10K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
205 207 209 211
CKE0 CKE1 VDD VDD NC A15 BA2 A14 VDD F-RT-BGA6 VDD A12/BC* A11 A9 A7 VDD VDD A8 A6 A5 A4 VDD VDD A3 A2 A1 A0 VDD VDD CK0 CK1 CK0* CK1* VDD VDD A10/AP BA1 BA0 RAS* VDD VDD WE* S0* CAS* ODT0 VDD VDD A13 ODT1 S1* NC VDD VDD TEST VREFCA VSS VSS DQ32 DQ36 DQ33 DQ37 VSS VSS DQS4* DM4 DQS4 VSS VSS DQ38 DQ39 DQ34 DQ35 VSS DQ44 VSS DQ40 DQ45 DQ41 VSS VSS DQS5* DM5 DQS5 VSS VSS DQ42 DQ46 DQ43 DQ47 VSS VSS DQ48 DQ52 DQ49 DQ53 VSS VSS DQS6* DM6 DQS6 VSS VSS DQ54 DQ50 DQ55 DQ51 VSS VSS DQ60 DQ56 DQ61 DQ57 VSS DQS7* VSS DQS7 DM7 VSS VSS DQ58 DQ62 DQ59 DQ63 VSS VSS SA0 EVENT* VDDSPD SDA SA1 SCL VTT VTT
J3100
MTG PINS
MTG MTG MTG MTG
PIN PIN PIN PIN
MTG PIN MTG PIN
MTG PIN MTG PIN
74
MEM_B_CKE<1>
76 78
IN
6 11 91
27 27
MEM_B_A<15> MEM_B_A<14>
80 82 84
MEM_B_A<11> MEM_B_A<7>
86 88 90
MEM_B_A<6> MEM_B_A<4>
92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122
IN
6 11 91
IN
6 11 91
BI
IN
6 11 91
27
BI
IN
6 11 91
27
BI
IN
6 11 91
27
BI
IN
6 11 91
27
BI
IN
6 11 91
27
BI
IN
6 11 91
27
BI
MEM_B_CLK_P<1> MEM_B_CLK_N<1>
IN
6 11 91
27
BI
IN
6 11 91
27
BI
MEM_B_BA<1> MEM_B_RAS_L
IN
6 11 91
27
BI
IN
6 11 91
27
BI
MEM_B_CS_L<0> MEM_B_ODT<0>
IN
6 11 91
27
BI
IN
6 11 91
27
BI
IN
6 11 91
NC
27
BI
27
BI
=MEM_B_DQ<2> =MEM_B_DQ<3> =MEM_B_DQ<8> =MEM_B_DQ<9> =MEM_B_DQS_N<1> =MEM_B_DQS_P<1>
=MEM_B_DQ<36> =MEM_B_DQ<37>
BI
27
142 144 146 148 150 152 154 156 158 160 162 164 166
19 21 23 25 27 29 31 33
=MEM_B_DQ<16> =MEM_B_DQ<17>
39
=MEM_B_DQS_N<2> =MEM_B_DQS_P<2>
45
=MEM_B_DQ<18> =MEM_B_DQ<19>
51 53
35 37 41 43 47 49
BI
27
=MEM_B_DQ<38> =MEM_B_DQ<39>
BI
27
BI
27
=MEM_B_DQ<44> =MEM_B_DQ<45>
BI
27
BI
27
=MEM_B_DQS_N<5> =MEM_B_DQS_P<5>
BI
27
BI
27
=MEM_B_DQ<46> =MEM_B_DQ<47>
BI
27
BI
27
=MEM_B_DQ<52> =MEM_B_DQ<53>
BI
27
BI
27
=MEM_B_DQ<54> =MEM_B_DQ<55>
BI
27
BI
27
=MEM_B_DQ<60> =MEM_B_DQ<61>
BI
27
BI
27
27
BI
27
BI
=MEM_B_DQ<24> =MEM_B_DQ<25>
57 59 61 63 65
136 138 140
17
55
126 128 132 134
13 15
=MEM_B_DQ<10> =MEM_B_DQ<11>
124
130
7 9 11
MEM_B_A<2> MEM_B_A<0>
MEM_B_ODT<1>
=MEM_B_DQ<0> =MEM_B_DQ<1>
BI
3 5
27
BI
27
BI
=MEM_B_DQ<26> =MEM_B_DQ<27>
67 69 71
VREFDQ VSS VSS DQ4 DQ0 DQ5 CRITICAL DQ1 VSS VSS DQS0* DM0 DQS0 F-RT-BGA6 VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ8 DQ12 DQ9 DQ13 VSS VSS DQS1* DM1 DQS1 RESET* VSS VSS DQ14 DQ10 DQ15 DQ11 VSS VSS DQ20 DQ16 DQ17 DQ21 VSS VSS DQS2* DM2 DQS2 VSS DQ22 VSS DQ23 DQ18 DQ19 VSS DQ28 VSS DQ24 DQ29 DQ25 VSS DQS3* VSS DM3 DQS3 VSS VSS DQ26 DQ30 DQ27 DQ31 VSS VSS
J3100 (1 OF 2)
NC 91 11 6
75 77
(2 OF 2)
73
MEM_B_CKE<0>
IN
DDR3-SODIMM
91 11 6
KEY
1
DDR3-SODIMM
OMIT_TABLE
2 4 6
=MEM_B_DQ<4> =MEM_B_DQ<5>
BI
27
BI
27
=MEM_B_DQS_N<0> =MEM_B_DQS_P<0>
BI
27
BI
27
=MEM_B_DQ<6> =MEM_B_DQ<7>
BI
27
BI
27
=MEM_B_DQ<12> =MEM_B_DQ<13>
BI
27
BI
27
30 32
MEM_RESET_L
IN
34
=MEM_B_DQ<14> =MEM_B_DQ<15>
BI
27
BI
27
=MEM_B_DQ<20> =MEM_B_DQ<21>
BI
27
BI
27
=MEM_B_DQ<22> =MEM_B_DQ<23>
BI
27
BI
27
=MEM_B_DQ<28> =MEM_B_DQ<29>
BI
27
BI
27
=MEM_B_DQS_N<3> =MEM_B_DQS_P<3>
BI
27
BI
27
=MEM_B_DQ<30> =MEM_B_DQ<31>
BI
27
BI
27
8 10 12 14 16 18 20 22 24 26 28
36 38 40 42 44
26 29
C
46 48 50 52 54 56 58 60 62 64 66 68 70 72
KEY
516S0806
B
168 170 172 174 176 178 180 182 184 186 188
PP0V75_S3_MEM_VREFCA_B
1
C3135
1
C3136
2.2UF
=MEM_B_DQS_N<7> =MEM_B_DQS_P<7>
BI
27
BI
27
=MEM_B_DQ<62> =MEM_B_DQ<63>
BI
27
BI
27
2
30
0.1UF
20% 6.3V CERM 402-LF
2
20% 10V CERM 402
190 192 194 196 198 200 202
MEM_EVENT_L SMBUS_PCH_DATA SMBUS_PCH_CLK
OUT
26 44
BI IN
16 23 26 30 41 47 61 88 93
"Expansion" (bottom) slot
16 23 26 30 41 47 61 88 93
204 206 208 210 212
PP0V75_S0_DDRVTT
1
C3150 1UF
10% 2 10V X5R 402
1
C3151 1UF
10% 2 10V X5R 402
1
C3152 1UF
10% 2 10V X5R 402
1
6 7 26 29 66
C3153
SYNC_MASTER=K92_SUMA
1UF
10% 2 10V X5R 402
SYNC_DATE=06/23/2010
PAGE TITLE
DDR3 SO-DIMM Connector B DRAWING NUMBER
516S0806
Apple Inc.
SPD ADDR=0xA4(WR)/0xA5(RD)
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
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6
5
4
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31 OF 132 SHEET
28 OF 101
1
A
8
7
6
5
4
3
2
1
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary. ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals. WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated. WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
D
D
1V5 S0 "PGOOD" for CPU
P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L 72 65 44 42 17
PP3V3_S5
39 25 24 23 22 20 19 17 7 6 98 89 85 82 72 71 70 65 55 45
PM_SLP_S4_L
IN
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page CPUMEM_S0 1
R3205
72 71 15 13 10 7
PP1V5_S3RS0_CPUDDR
PM_MEM_PWRGD
10K
47 32 31 30 25 24 19 18 8 7 6 87 72 71 54 53 49 48
CPUMEM_S0
Q3205
R32011
SSM6N15FEAPE
5 IN
2
G
6 D
Q3220 SOT-563
PM_MEM_PWRGD_L
2 G
CRITICAL
Q3220
S
DMB53D0UV
1
SOT-563
CRITICAL CPUMEM_S0 3
D
4
S
C3220 1
33.2K
0.001UF
1% 1/16W MF-LF 402 2
SOT563
4
NO STUFF
R32211
Q3205 SSM6N15FEAPE
S 4
5
P1V5_S0_DIV
S 1
P1V5CPU_EN_L D 3
G
CRITICAL
DMB53D0UV
1% 1/16W MF-LF 402 2
D 6
SOT563
23 19
5% 1/16W MF-LF 2 402
R32201
71
27.4K
SSM6N15FEAPE
C
OUT
3
5% 1/16W MF-LF 402 2
Q3200
10K
SOT563
100K
CRITICAL CPUMEM_S0
10 17 90
R3222
P1V5CPU_EN
CRITICAL CPUMEM_S0
PP3V3_S3
OUT
1
5% 1/16W MF-LF 2 402
20% 50V CERM 2 402
C
G 5
ISOLATE_CPU_MEM_L
PM_SLP_S3_L CPUMEM_S0
IN
6 17 44 72
1
R3210 10K
5% 1/16W MF-LF 2 402 81 71 66 65 45 43 42 41 31 29 7 6 100
PP5V_S3
MEMVTT_EN
CRITICAL CPUMEM_S0 CPUMEM_S0
Q3210
CPUMEM_S0
1
R3202
100K
100K
5% 1/16W MF-LF 402 2
D 6
Q3200
3
D
10 5% 1/10W MF-LF 603 2
Q3210 SSM6N15FEAPE
G 2
SOT563
S 1
S
G 5
S
4
100 81 71 66 65 45 43 42 41 31 29 7 6
PLT_RESET_L
IN
PP5V_S3
CRITICAL CPUMEM_S0
CPUMEM_S0 CPUMEM_S0
Q3250
R32511
SSM6N15FEAPE
18 25 39
Q3215 5
MAKE_BASE=TRUE
CPUMEM_S0
C3216
Q3250
0.1UF
5% 1/16W MF-LF 2 402
D 3
SSM6N15FEAPE
10% 2 16V X5R 402
D
CPU_MEM_RESET_L
1
20K
MEM_RESET_L
OUT
5 66 29 8
IN
G
G
S 1
NO STUFF
C3251 1 20% 50V CERM 2 402
26 28
CPUMEM_S3
2
0.001UF
SOT563
3
CPU_MEM_RESET_L
4
IN
S
G
SOT563
R3216
B
VTTCLAMP_EN
CRITICAL
CPUMEM_S0
1
SSM6N15FEAPE MEMRESET_ISOL_LS5V_L
6 7 26 28 66 71
D 6
SOT563
5% 1/16W MF-LF 402 2
PP1V5_S3 CPUMEM_S0
75mA max load @ 0.75V 60mW max power
VTTCLAMP_L
CRITICAL G
100K
29 10
PP0V75_S0_DDRVTT CPUMEM_S0
R32501
1
6
66 28 26 7 6
CRITICAL CPUMEM_S0
SOT563
2
D
S 1
SSM6N15FEAPE
SSM6N15FEAPE
B
G
CPUMEM_S0
Q3215 SOT563
2
MEMVTT_EN_L
CRITICAL
CPUMEM_S0
MEMVTT Clamp Ensures CKE signals are held low in S3
SOT563
5% 1/16W MF-LF 402 2
CRITICAL
8 29 66
SSM6N15FEAPE
1
R3215
OUT
D 6
S 4
MEMVTT_EN
R3217 0
1
2
5% 1/16W MF-LF 402
Step
A
S0 to S3 to S0
PM_SLP_S3_L
PM_SLP_S4_L
CPU_MEM_RESET_L
0 1 2 3
ISOLATE_CPU_MEM_L 1 0 0 0
PLT_RESET_L 1 1 0 0
1 1 1 0
1 1 1 1
1 1 1 X
CPU_MEM_RESET_L 1 1 1
MEM_RESET_L
MEMVTT_EN 1 1 0 0
P1V5CPU_EN 1 1 1 0
4 5 6 7
0 0 0 1
0 1 1 1
1 1 1 1
1 1 1 1
X 0 (*) 1 1
1 1 1 CPU_MEM_RESET_L
0 1 1 1
1 1 1 1
SYNC_MASTER=K18_MLB
SYNC_DATE=04/27/2010
PAGE TITLE
CPU Memory S3 Support DRAWING NUMBER
Apple Inc. (*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.
NOTICE OF PROPRIETARY PROPERTY:
7
6
5
D
R
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0 transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.
8
SIZE
REVISION
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
4
3
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32 OF 132 SHEET
29 OF 101
1
A
8
47 32 31 29 25 24 19 18 8 7 6 87 72 71 54 53 49 48
7
6
5
4
3
2
NOTE: Must not enable more than two SO-DIMM margining buffers at once or VRef source may be overloaded.
PP3V3_S3
VREFMRGN
OMIT
R3318 SHORT2
1
NONE NONE NONE 402
66 7 6
PP3V3_S3_VREFMRGN_DAC MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VREFMRGN VOLTAGE=3.3V
C3300 1 2.2UF
20% 6.3V 2 CERM 402-LF
D
1
C3301
VREFMRGN
0.1UF
93 88 61 47 41 30 28 26 23 16
0.1UF
20% 10V CERM 2 402
U3300
IN
SMBUS_PCH_CLK
6 SCL
BI
SMBUS_PCH_DATA
7 SDA
10 A1
VOUTB 2
VREFMRGN_SODIMMB_DQ
VOUTC 4
VREFMRGN_SODIMMS_CA
B1
1
V+
VREFMRGN_DQ_SODIMMA_BUF
1
A4 V-
1
1
CRITICAL
R3301
C3
PP3V3_S3_VREFMRGN_CTRL
B1
C
Addr=0x30(WR)/0x31(RD)
93 88 61 47 41 30 28 26 23 16 93 88 61 47 41 30 28 26 23 16
IN BI
VREFMRGN_DQ_SODIMMB_BUF
1
SMBUS_PCH_CLK SMBUS_PCH_DATA
V-
100K NC
5% 1/16W MF-LF 2 402
VREFMRGN_DQ_SODIMMA_EN VREFMRGN_DQ_SODIMMB_EN VREFMRGN_CA_SODIMMA_EN VREFMRGN_CA_SODIMMB_EN VREFMRGN_MEMVREG_EN VREFMRGN_FRAMEBUF_EN
1
CRITICAL
16
GND
VREFMRGN
VREFMRGN
C3304 1 0.1UF
20% 10V CERM 2 402
A2
B1 V+
A3
UCSP A1
VREFMRGN_CA_SODIMMA_BUF
8
1
1
C
2 PLACE_NEAR=R3309.2:1mm
CRITICAL C2
V+
C3
CRITICAL
B1
QTY
DESCRIPTION
REFERENCE DES
116S0004
2
RES,MTL FILM,0,5%,0402,SM,LF
R3303,R3305
VREFMRGN_NOT
116S0004
2
RES,MTL FILM,0,5%,0402,SM,LF
R3309,R3311
VREFMRGN_NOT
PLACE_NEAR=J3100.126:2.54mm
R3312 VREFMRGN_CA_SODIMMB_BUF
1
133
V-
PP0V75_S3_MEM_VREFCA_B MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V
28
2
1% 1/16W MF-LF 402
C4 B4
PART NUMBER
2
VREFMRGN
U3303
MAX4253 UCSP C1
200
1% 1/16W MF-LF 402
VREFMRGN
5% 1/16W MF-LF 2 402
PCA9557D_RESET_L
PLACE_NEAR=R3311.2:1mm
VREFMRGN
Required zero ohm resistors when no VREF margining circuit stuffed
1
R3308
VREFMRGN
100K
BOM OPTION
CRITICAL VREFMRGN
C3305 1
5% 1/16W MF-LF 2 402
0.1UF
20% 10V CERM 2 402
C2
B1 V+
C3
VREFMRGN
U3304
MAX4253
R3314
UCSP C1
VREFMRGN_MEMVREG_BUF 133.2K2 1% 1/16W MF-LF 402
C4 V-
B4
Page Notes
DDRREG_FB
OUT
B
66
PLACE_NEAR=R7320.2:1mm
CRITICAL VREFMRGN
Power aliases required by this page: - =PP3V3_S3_VREFMRGN - =PPVTT_S3_DDR_BUF
R33161 0 5% 1/16W MF-LF 402 2
Signal aliases required by this page: - =I2C_VREFDACS_SCL - =I2C_VREFDACS_SDA - =I2C_PCA9557D_SCL - =I2C_PCA9557D_SDA
VREFMRGN
VREFMRGN_FRAMEBUF_BUF VREFMRGN
1
R3313 100K
5% 1/16W MF-LF 2 402
A2
B1 V+
A3
VREFMRGN_MEMVREG_FBVREF_R
BOM options provided by this page: VREFMRGN - Stuffs VREF Margining Circuitry. VREFMRGN_NOT - Bypasses VREF Margining Circuitry.
8
26
R3311
NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles.
A 1
133
PP0V75_S3_MEM_VREFCA_A MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V
VREFMRGN
RST* on ’platform reset’ so that system watchdog will disable margining.
DAC Channel: PCA9557D Pin: Nominal value Margined target: DAC range: VRef current: DAC step size:
PLACE_NEAR=J2900.126:2.54mm
NC
100K
MEM A VREF DQ
2
1% 1/16W MF-LF 402
A4 B4
R3307
B
200
R3310
V-
VREFMRGN
IN
PLACE_NEAR=R3305.2:1mm
VREFMRGN
U3303
MAX4253
1
25
2
1% 1/16W MF-LF 402
RESET* 15
PAD
9 28
R3309
R3302
QFN (OD) P0 6 P1 7 P2 9 P3 10 P4 11 P5 12 P6 13 P7 14
17
THRM
133
PP0V75_S3_MEM_VREFDQ_B MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V
VREFMRGN VREFMRGN
U3301
1 SCL 2 SDA
2 PLACE_NEAR=J3100.1:2.54mm
1% 1/16W MF-LF 402
C4
1
PCA9557 3 A0 4 A1 5 A2
200
R3306
UCSP C1
CRITICAL VREFMRGN
VCC
20% 10V CERM 2 402
D
PLACE_NEAR=R3303.2:1mm
VREFMRGN
U3302
MAX4253
B4
0.1UF
9 26
2
1% 1/16W MF-LF 402
VREFMRGN C2
OMIT
C3302 1
PP0V75_S3_MEM_VREFDQ_A MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V
R3305 VREFMRGN
V+
VREFMRGN
PLACE_NEAR=J2900.1:2.54mm
VREFMRGN
NOTE: MEMVREG and FRAMEBUF share a DAC output, cannot enable both at the same time!
R3319 NONE NONE NONE 402
133
1% 1/16W MF-LF 402
B4
5% 1/16W MF-LF 2 402
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
2
R3304
UCSP A1
100K
SHORT2 1
200
VREFMRGN
U3302
MAX4253
VREFMRGN_MEMVREG_FBVREF
VOUTD 5
GND 3
A2
A3
VREFMRGN_SODIMMA_DQ
MSOP VOUTA 1
9 A0
Addr=0x98(WR)/0x99(RD)
R3303 1% 1/16W MF-LF 402
VREFMRGN
C3303 1
CRITICAL VREFMRGN
20% 10V 2 CERM 402
DAC5574
93 88 61 47 41 30 28 26 23 16
PPVTTDDR_S3 10mA max load
CRITICAL
VREFMRGN
8 VDD
A
1
U3304
VREFMRGN 1
R3317
MAX4253
0
UCSP A1 A4
V-
VREFMRGN_FRAMEBUF_BUF_R
B4
5% 1/16W MF-LF 2 402
VREFMRGN 1
R3315 100K
5% 1/16W MF-LF 2 402
MEM B VREF DQ
MEM A VREF CA
B 2
C 3 0.75V (DAC: 0x3A) 0.300V - 1.200V (+/- 450mV) 0.000V - 1.501V (0x00 - 0x74) +3.4mA - -3.4mA (- = sourced) 7.69mV / step @ output
7
6
MEM B VREF CA C 4
MEM VREG
GPU Frame Buffer (1.8V, 70% VRef)
D 5 1.5V (DAC: 0x3A) 1.000V - 2.000V (+/- 500mV) 0.000V - 3.000V (0x00 - 0x74) +61uA - -61uA (- = sourced) 8.59mV / step @ output
5
4
D 6 1.267V (DAC: 0x8B) 1.056V - 1.442V (+/- 180mV) 0.000V - 3.300V (0x00 - 0xFF) +6.0mA - -5.0mA (- = sourced) 1.51mV / step @ output
3
SYNC_MASTER=K18_MLB
SYNC_DATE=04/27/2010
PAGE TITLE
FSB/DDR3/FRAMEBUF Vref Margining DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
33 OF 132 SHEET
30 OF 101
1
A
8
7
6
5
4
3
2
1
OMIT_TABLE
L3470
PLACE_NEAR=J3401.15:2.54mm
1
C3431
PCIE_AP_R2D_PI_P
2
1
10%
0.6NH+/-0.1NH-0.85A
2
PCIE_AP_R2D_C_P
0.1UF
16V
16 93
IN
X5R 402-1
0201
NOSTUFF
2
PART NUMBER
NOSTUFF
1 C3470 0.1UF
1 C3471
10% 16V X5R-CERM 0201
2
QTY
117S0002
0.1UF
4
DESCRIPTION
REFERENCE DES
RES, 0OHM, 0201
L3470,L3471,L3473,L3474
CRITICAL
BOM OPTION
10% 16V X5R-CERM 0201
L3471
D
1
2
PCIE_AP_R2D_PI_N
1 10%
0.6NH+/-0.1NH-0.85A NOSTUFF
NOSTUFF
OMIT_TABLE
1 C3472
SMBUS_SMC_0_S0_SCL
BI
IN
2
6 44 47 50 79 96
0.1UF
PCIE_AP_R2D_C_N
IN
10% 16V X5R-CERM 0201
2
6 44 47 50 79 96
D
3V S3 WLAN FET
16 93
16V X5R 402-1
MOSFET
TPCP8102
PLACE_NEAR=J3401.17:2.54mm
CHANNEL
P-TYPE
0.1UF
RDS(ON)
20-30 MOHM @2.5V
10% 16V X5R-CERM 0201
LOADING
1 A (EDP)
1 C3473
0.1UF
SMBUS_SMC_0_S0_SDA
2
C3430
0201
OMIT_TABLE
L3473
PCIE_AP_D2R_P
CRITICAL
6 16 93
Q3450 155S0367
0.1UF
10% NOSTUFF 16V X5R-CERM 0201
2
10% 16V X5R-CERM 0201
PCIE_AP_D2R_N
CRITICAL
2
J3401
PCIE_AP_D2R_PI_P
0.1UF 10% NOSTUFF 16V
OMIT_TABLE
2
X5R-CERM 0201
31
2
SM
PP3V3_WLAN_F 2
1
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm
0603
PP3V3_WLAN_R
6 16 93
C3422
10% 16V X5R-CERM 0201
1
C3421
PP3V3_S3
1
1
C3451
0.1uF
0.1uF
0.033UF
20% 10V CERM 402
20% 10V CERM 402
10% 16V X5R 402
2
PLACE_NEAR=J3401.29:2.54MM
2
C3450 0.1UF
PLACE_NEAR=J3401.29:2.54MM
1
AIRPORT
L3401
PCIE_AP_D2R_PI_N
OUT
0.1UF
CRITICAL
F-ST-SM 32 31
C
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.2 mm
1 C3477
0201
500913-0302
PP3V3_WLAN 1
NOSTUFF
0.6NH+/-0.1NH-0.85A
1 C3476
516S0582
XW3452
FERR-120-OHM-3A
45 6
2
23V1K-SM
MIN_NECK_WIDTH=0.4 mm MIN_LINE_WIDTH=1 mm
L3404
1A PEAK
L3474 1
TPCP8102
S
0.1UF
2
OUT
NOSTUFF
1 C3475
0201
1 2 3
2
0.6NH+/-0.1NH-0.85A
1 C3474
D
1
6 44 45
PCIE_AP_R2D_P PCIE_AP_R2D_N
4G
IN 93 6
5 6 7 8
WIFI_EVENT_L
1
R3450 33K
1
2
5% 1/16W MF-LF 402
2
PM_WLAN_EN_L
IN
72
5% 1/16W MF-LF 402
10% 16V X5R 402-1
90-OHM-100MA DLP11S
R3451 10K
2
P3V3WLAN_SS
2
49 53 54 71 72 87 6 7 8 18 19 24 25 29 30 31 32 47 48
C
SYM_VER-1
98 6 98 6
PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N
4
3
PCIE_CLK100M_AP_P
IN
16 93
1
2
PCIE_CLK100M_AP_N
IN
16 93
PLACE_NEAR=J3401.11:2.54mm
BLUETOOTH PP3V3_S3_BT_F
USB_BT_N BI
24 92
10% 16V CERM 402
PP3V3_WLAN_F 1
PP3V3_S3
6 7 8 18 19 24 25 29 30 31 32 47 48 49 53 54 71 72 87
FERR-120-OHM-1.5A
1
R3453
0402-LF
1% 1/16W MF-LF 402
R3454
VDD
232K
6
6
OUT
1
U3440
1% 1/16W MF-LF 2 402
C3440 0.1uF
SLG4AP016V
P3V3WLAN_VMON 2
B
6 7 8 18 19 24 25 29 30 31 32 47 48 49 53 54 71 72 87
CRITICAL
1
100K
PLACE_NEAR=J3401.27:2.54MM
2
PCIE_WAKE_L
PP3V3_S3 31
2
0.01UF
2
24 92
L3406
1 C3432
33
Delay = 60 ms +/- 20%
USB_BT_P BI
1
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm
Supervisor & CLKFREG # Isolation
TDFN
20% 2 10V CERM 402
SENSE + 0.7V -
B
DLY
AP_RESET_CONN_L
4 RESET*
AP_CLKREQ_Q_L 1
R3455
(OD)
THRM PAD
GND
IN
25
IN
18 72
OUT
16 23
AP_PWR_EN
EN 6 OUT 8
7 IN
6 17 25 84
AP_RESET_L
MR* 3
5
34
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
9
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
AP_CLKREQ_L
100K 1% 1/16W MF-LF
2 402
518S0816 CRITICAL
J3402
CCR20-6K710S F-RT-SM 8
6
6
5 4
A
3
92 6
2
92 6
PP5V_S3_ALSCAMERA_F SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA USB_CAMERA_CONN_P USB_CAMERA_CONN_N
IN BI
6 44 47 53 54 96
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm
275 mA peak 206 mA nominal max
6 44 47 53 54 96
ALS CAMERA
1
CRITICAL
7
L3407 90-OHM
PLACE_NEAR=J3402.6:2.54MM
L3408
FERR-120-OHM-1.5A 2
1
PP5V_S3
SYNC_MASTER=K91_MARY 6 7 29 41 42 43 45 65 66 71 81 100
1
C3452
DRAWING NUMBER
0.1uF
DLP0NS SYM_VER-1
4
3
USB_CAMERA_P
BI
18
1
2
USB_CAMERA_N
BI
18
SYNC_DATE=10/08/2010
PAGE TITLE
X19/ALS/CAMERA CONNECTOR
0402-LF
Apple Inc.
20% 10V 2 CERM 402
NOTICE OF PROPRIETARY PROPERTY:
7
6
5
D
R
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
PLACE_NEAR=J3402.3:2.54MM
8
SIZE
REVISION
4
3
2
BRANCH
PAGE
34 OF 132 SHEET
31 OF 101
1
A
8
7
6
5
4
3
2
1
SD CARD 3.3V OVERCURRENT PROTECTION CHIP WITH ACTIVE LOAD DISCHARGE TPS2065-1 (1.0A limit) has active load discharge so R4810 is NOSTUFF.
CRITICAL
U3500
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
36
PP3V3_S0
10UF 20%
6.3V 2 X5R 603
PP3V3_S0_SW_SD_PWR
C3501 0.1UF 10%
32
MAKE_BASE=TRUE
NOSTUFF
5
CRITICAL
C3502
1
THRM PAD
GND
1
C3500
1
OC*
32
D
7 8
353S3004 EN
CRITICAL 1
OUT1 OUT2
IN1
4
ENET_CR_PWREN
PP3V3_S0_SW_SD_PWR
TPS2065-1 IN0 DGNOUT0 6
1
10UF 20%
16V 2 X7R-CERM 402
C3503 0.1UF 10%
6.3V 2 X5R 603
9
D
2 3
2 16V X7R-CERM 402
SDCONN_OC_L_R
R3500 47K
1
5% 1/16W MF-LF 2402
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
PP3V3_S0
48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98
R3501 10K
1
5% 1/16W MF-LF 4022
R3502 0 1
2
SDCONN_OC_L
5% 1/16W MF-LF 402
SDCONN DETECT DEBOUNCE, INVERSION, AND DETECT-CHANGED PCH GPIO LATCH CIRCUIT 47 31 30 29 25 24 19 18 8 7 6 87 72 71 54 53 49 48
C
PP3V3_S3
C C3510
1
1UF
10% 10V 2 X5R 402-1
Must STUFF R3512 and NOSTUFF R3514 when R3511 is NOT STUFFED.
1
CRITICAL
VDD
R3511 and R3510 mutually exclusive to control effect of =ENET_RESET_L on DET_CHANGED# logic.
IN
PLT_RST_BUF_L
1
SLG_ENET_RESET_IN_L
2
5% 1/16W MF-LF 402
-> FROM PCH GPIO
SDCONN_DETECT FROM SD CONN -> 32
2
R3514 0
LOW_PWR RST LOGIC
3
RST_IN*
6
DET_IN (IPU)
DLY
4
RST_OUT*
(OD) DET_CHNGD* (OD)
NOSTUFF
SLG_ENET_RESET_OUT_L
1
8 7
TO PCH GPIO SDCONN_STATE_CHANGE -> OUT 18 23 -> TO ENET CHIP
SDCONN_DETECT_L
OUT
36
DET_OUT
R3510 10K
1
GND
OUT
36 94
NOSTUFF 1
R3512 0
5% 1/16W MF-LF 2 402
DLY block is 20ms nominal When ENET_LOW_PWR deasserts, RST_OUT# deasserts for >80ms, then asserts for 10ms regardless ofmove RST_IN# state. Otherwise RST_OUT# follows RST_IN#
THRM PAD
5
5% 1/16W MF-LF 402 2
ENET_RESET_L
2
5% 1/16W MF-LF 402
9
35 25
ENET_LOW_PWR
IN
R3514 and R3512 mutually exclusive to bypass reset logic
TDFN
XOR
36 19
R3511 0
U3511 SLG4AP014V
B
B
SD CARD CONNECTOR 516-0225 CRITICAL
J3500
SD-CARD-K19-K24 CRITICAL
F-RT-TH
L3500
3
47NH-1.3OHM 94 36
OUT
94 36
BI
94 36
A
IN
94 36
BI
94 36
BI
94 36
BI
94 36
BI
94 36
BI
94 36
BI
94 36
BI 32
SDCONN_CLK SDCONN_CMD SDCONN_DATA<0> SDCONN_DATA<1> SDCONN_DATA<2> SDCONN_DATA<3> SDCONN_DATA<4> SDCONN_DATA<5> SDCONN_DATA<6> SDCONN_DATA<7> SDCONN_DETECT
R3579 R3561 R3571 R3572 R3573 R3574 R3575 R3576 R3577 R3578 R3560
33 33 33 33 33 33 33 33 33 33 0
1
2
5%
1/16W MF-LF 402 1/16W MF-LF 402
1
2
5%
1
2
5% 1/16W MF-LF 402
1
2
5%
1/16W MF-LF 402
1
2
5%
1/16W MF-LF 402
1
2
5%
1/16W MF-LF 402
1
2
5%
1/16W MF-LF 402
1
2
5%
1/16W MF-LF 402
1
2
5%
1/16W MF-LF 402
1
2
5% 1/16W MF-LF 402
1
2
5% 1/16W MF-LF 402
94
6
SDCONN_CLK_R 1 SDCONN_CLK_R_L 94 2 0402 94 SDCONN_CMD_R SDCONN_R_DATA<0> SDCONN_R_DATA<1> SDCONN_R_DATA<2> SDCONN_R_DATA<3> SDCONN_R_DATA<4> SDCONN_R_DATA<5> SDCONN_R_DATA<6> SDCONN_R_DATA<7> SDCONN_DETECT_R
5 2 7 8 9 1 10 11 12 13 14 15
36
SDCONN_WP PP3V3_S0_SW_SD_PWR NOSTUFF
OUT
32
1
C3571
5% 2 50V CERM 402
7
6
4
1
22PF
8
16
NOSTUFF
17
C3570
18
15PF
19
5% 50V 2 CERM 402
5
20
VSS VSS CLK CMD DAT0 DAT1 DAT2
(CARD INSERTED = OPEN) CAESAR-IV CARD DETECT IS PROGRAMMABLE, BUT A SILICON BUG MAKES THE ACTIVE-HIGH CASE UNUSABLE.
CD/DAT3 DAT4 DAT5 DAT6 DAT7
SYNC_MASTER=K91_ERIC SYNC_DATE=10/08/2010
CARD_DETECT_SW CARD_DETECT_GND WRITE_PROTECT_SW VDD
PAGE TITLE
SD READER CONNECTOR DRAWING NUMBER
Apple Inc.
SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN
4
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
3
2
BRANCH
PAGE
35 OF 132 SHEET
32 OF 101
1
A
8
7
6
5
4
3
2
1
CRITICAL 93 9 8
IN
PCIE_T29_R2D_C_P<0>
C3600
1
93 9 8
IN
PCIE_T29_R2D_C_N<0>
C3601
OMIT_TABLE
2
10%
0.1uF 1
16V
X5R
402
93 93
2
10%
0.1uF
16V
X5R
V19 T19
PCIE_T29_R2D_P<0> PCIE_T29_R2D_N<0>
U3600
PER_0_P PER_0_N
PET_0_P PET_0_N
T29
V21 T21
93 93
C3640
PCIE_T29_D2R_C_P<0> PCIE_T29_D2R_C_N<0>
FCBGA
402
1
0.1uF
C3641
1
0.1uF
PCIE_T29_D2R_P<0>
2
10%
16V
2
PCIE_T29_D2R_N<0>
X5R
10%
16V
2
PCIE_T29_D2R_P<1>
X5R
402 402
OUT
8 9 93
OUT
8 9 93
OUT
8 9 93
OUT
8 9 93
OUT
8 9 93
OUT
8 9 93
OUT
8 9 93
OUT
8 9 93
1
2
10%
0.1uF
C3603
1
2
10%
0.1uF PCIE_T29_R2D_C_P<2>
C3604
1
93 9 8
IN
PCIE_T29_R2D_C_N<2>
C3605
1
IN
PCIE_T29_R2D_C_P<3>
C3606
IN
PCIE_T29_R2D_C_N<3>
C3607
X5R
402
1
16V
X5R
402
16V
X5R
402
93
10%
16V
X5R
1
5%
1
C3615
TP_T29_MONOBSP
3.3K
5% 1/16W MF-LF 402 2
R3691 3.3K
5% 1/16W MF-LF 2 402
C3690 1
C3616
8 VCC 5
CRITICAL OMIT_TABLE
U3690 M95160 2KX8-1.8V
6
C
(T29_SPI_CS_L)
1
S_L
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402 2
1
1
R3622 10K
16V
2
(T29_SPI_MISO)
16V
3
W_L
T29ROM_HOLD_L
7
HOLD_L
4
1
0.1uF
C3643
1
0.1uF PET_2_P PET_2_N
PET_3_P PET_3_N
K21 H21
93 93
C3644
PCIE_T29_D2R_C_P<2> PCIE_T29_D2R_C_N<2>
1
0.1uF
C3645
1
F21 D21
93 93
C3646
PCIE_T29_D2R_C_P<3> PCIE_T29_D2R_C_N<3>
1
0.1uF
C3647
1
1/16W MF-LF 402
X5R X5R
WAKE*
MONOBSP
M17
MONOBSN
402
16V
2
PCIE_T29_D2R_N<1>
10%
16V
X5R X5R
402 402
2
PCIE_T29_D2R_P<2>
10%
16V
2
PCIE_T29_D2R_N<2>
10%
16V
2
PCIE_T29_D2R_P<3>
X5R X5R
X5R
402 402
10%
16V
2
PCIE_T29_D2R_N<3>
10%
16V
F1
R3651
T29_PCIE_WAKE_L
2
X5R
402 402
PERST*
E6
T29_RESET_L
RSENSE
E14
T29_RSENSE
IN
D
7 16 19 25 33 34 35 87
1 5%
10K
K17
402
10%
PP3V3_T29 1/16W MF-LF 402
35
R36551 1.0K
E16
T29_RBIAS
PCIE_RST_0* PCIE_RST_1* PCIE_RST_2* PCIE_RST_3*
K1 J2 K3 J4
Not used in host mode. TP_T29_PCIE_RESET0_L TP_T29_PCIE_RESET1_L TP_T29_PCIE_RESET2_L TP_T29_PCIE_RESET3_L
TDI TMS TCK TDO
T3 R4 R2 T1
JTAG_ISP_TDI JTAG_T29_TMS JTAG_ISP_TCK JTAG_ISP_TDO
REFCLK_100_IN_P REFCLK_100_IN_N
H17 G16
PCIE_CLK100M_T29_P PCIE_CLK100M_T29_N
XTAL_25_IN XTAL_25_OUT
P17 R16
SYSCLK_CLK25M_T29_R TP_T29_XTAL25OUT
TMU_CLK_OUT TMU_CLK_IN
U2 E2
RBIAS
R3621 10K
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402 OUT
R3693 3.3K
95
95
VSS
C3642
PCIE_T29_D2R_C_P<1> PCIE_T29_D2R_C_N<1>
0.1uF
1
95
T29ROM_WP_L
PER_3_P PER_3_N
93
0.5% 1/16W MF-LF 603 2
5% 1/16W MF-LF 2 402
MLP
MONDC1
MF-LF 402
T29_MONOBSN
2
10%
1 Q
MONDC0
A20
1/16W
T29_MONOBSP
2
10%
35
D
(T29_SPI_CLK)
10K
1
0.1uF
PP3V3_T29
R36231
3.3K
10% 6.3V 2 CERM 402
(T29_SPI_MOSI)
C
R36921
1UF
T29_MONDC0
B21
T29_MONDC1
2
0.1uF
TP_T29_MONOBSN
1
F19 D19
93
0.1uF
2
0
R3611
DEBUG: For monitoring clock
R36901
PCIE_T29_R2D_P<3> PCIE_T29_R2D_N<3>
P21 M21
402
5% 0 NO STUFF
87 35 34 33 25 19 16 7
PER_2_P PER_2_N
PET_1_P PET_1_N
NO STUFF
R3610
TP_T29_MONDC1
93
2
0.1uF TP_T29_MONDC0
K19 H19
PCIE_T29_R2D_P<2> PCIE_T29_R2D_N<2>
2
10%
1
DEBUG: For monitoring current/voltage
93 93
10%
0.1uF 93 9 8
16V
2
0.1uF 93 9 8
402
2
10%
0.1uF
D
X5R
PER_1_P PER_1_N
95
THM PAD 9
50
T29_CLKREQ_ISOL_L T29_GPIO<1> T29_GPIO<2> T29_RSVD
P3 N4 M3 L4
PCIE_CLKREQ_0* PCIE_CLKREQ_1* PCIE_CLKREQ_2* PCIE_CLKREQ_3*
T29_SPI_MOSI T29_SPI_MISO T29_SPI_CS_L T29_SPI_CLK
P1 M1 N2 L2
EE_DI EE_DO EE_CS* EE_CLK
T29_THERMD_P
A2
THERM_DP
E4 P5 N6 M5 L6
TEST_EN TEST_POINT_0 TEST_POINT_1 TEST_POINT_2 TEST_POINT_3
Use B1 GND ball for THERM_DN
T29_TEST_EN TP_T29_TEST_POINT_0 TP_T29_TEST_POINT_1 TP_T29_TEST_POINT_2 T29_TEST_POINT_3
1
R3625 0
5% 1/16W MF-LF 2 402
JTAG
IN
16V
P19 M19
PCIE_T29_R2D_P<1> PCIE_T29_R2D_N<1>
POWER ON RESET
93 9 8
93 93
CLOCKS
PCIE_T29_R2D_C_N<1>
402
MISC
IN
X5R
CLK REQUEST
93 9 8
16V
TRANSMIT
C3602
TEST PORT
PCIE_T29_R2D_C_P<1>
RECEIVE
IN
EEPROM
93 9 8
PCIE GEN2
(SYM 1 OF 2)
6 6 6 6
IN
8 19 87
PP3V3_T29
IN
16
IN
8 19 23 87
OUT
R3698
8 19 87
IN
16 93
IN
16 93
C
7 16 19 25 33 34 35 87
1
10K
5% 1/16W MF-LF 2 402
R3695 1
R36961
T29_TMU_CLK_OUT T29_TMU_CLK_IN NO STUFF
1K
806
2
SYSCLK_CLK25M_T29
IN
25
1% 1/16W MF-LF 402
5% 1/16W MF-LF 402 2
R36991 10K
0.1uF 95 78 6
IN
DP_T29SNK0_ML_C_P<1>
C3622
1
0.1uF 95 78 6
IN
DP_T29SNK0_ML_C_N<1>
C3623
1
0.1uF
B
DP_T29SNK0_ML_N<0>
2
10% X5R
95 33 6 95 33 6
DP_T29SNK0_ML_P<1>
6 33 95
95 33 6
16V 402
95 33 6
DP_T29SNK0_ML_N<1>
2
10% X5R
6 33 95
16V 402
2
10% X5R
6 33 95
16V 402
95 33 6 95 33 6
95 78 6
IN
DP_T29SNK0_ML_C_P<2>
C3624
1
0.1uF 95 78 6
IN
DP_T29SNK0_ML_C_N<2>
C3625
1
0.1uF 95 78 6
IN
DP_T29SNK0_ML_C_P<3>
C3626
1
0.1uF 95 78 6
IN
DP_T29SNK0_ML_C_N<3>
C3627
1
0.1uF
DP_T29SNK0_ML_P<2>
2
10% X5R
DP_T29SNK0_ML_N<2>
6 33 95
OUT
R36301 100K
DP_T29SNK0_ML_P<3> DP_T29SNK0_ML_N<3>
95 33 6
5% 1/16W MF-LF 402 2
6 33 95
16V 402
2
10% X5R
83 79
16V 402
2
10% X5R
6 33 95
16V 402
2
10% X5R
95 33 6
95 33 6
6 33 95
16V 402
95 33 6
95 33 6 95 78 6
BI
DP_T29SNK0_AUXCH_C_P
C3628
1
0.1uF 95 78 6
BI
DP_T29SNK0_AUXCH_C_N
C3629
1
0.1uF
2
10% X5R
DP_T29SNK0_AUXCH_P
6 33 95
DP_T29SNK0_AUXCH_N
6 33 95
95 33 6
16V 402
2
10% X5R
95 33 6
16V 402
95 33 6
95 33 6
SNK1 AC Coupling DP_T29SNK1_ML_C_P<0> C3630 10% 16V 1
95 78 6
IN
95 78 6
IN
DP_T29SNK1_ML_C_N<0>
C3631
95 78 6
IN
DP_T29SNK1_ML_C_P<1>
C3632
IN
DP_T29SNK1_ML_C_N<1>
0.1uF 1
0.1uF 1
0.1uF 95 78 6
C3633
1
0.1uF
A
95 78 6
IN
DP_T29SNK1_ML_C_P<2>
C3634
1
0.1uF 95 78 6
IN
DP_T29SNK1_ML_C_N<2>
C3635
1
0.1uF 95 78 6
IN
DP_T29SNK1_ML_C_P<3>
C3636
1
0.1uF 95 78 6
IN
DP_T29SNK1_ML_C_N<3>
C3637
1
0.1uF 95 78 6
BI
DP_T29SNK1_AUXCH_C_P
C3638
BI
DP_T29SNK1_AUXCH_C_N
C3639
1
0.1uF 95 78 6
1
0.1uF
8
2
X5R
6 33 95
OUT
100K
DP_T29SNK1_ML_N<2>
5% 1/16W MF-LF 402 2
DP_T29SNK1_ML_P<3> DP_T29SNK1_ML_N<3>
95 84 6
IN
95 84 6
IN
84
OUT
84
IN
95 84 6
OUT
95 84 6
OUT
95 84 6
IN
6 33 95
95 84 6 6 33 95
DP_T29SNK0_ML_P<1> DP_T29SNK0_ML_N<1>
DPSNK0_ML_LANE_1P DPSNK0_ML_LANE_1N
DP_T29SNK0_ML_P<0> DP_T29SNK0_ML_N<0>
AA10 Y9
DPSNK0_ML_LANE_0P DPSNK0_ML_LANE_0N
DP_T29SNK0_AUXCH_P DP_T29SNK0_AUXCH_N
V1 W2
DPSNK0_AUX_CHP DPSNK0_AUX_CHN
DP_T29SNK0_HPD
V5
DPSNK0_HOT_PLUG_DET
DP_T29SNK1_ML_P<3> DP_T29SNK1_ML_N<3>
V9 U8
DPSNK1_ML_LANE_3P DPSNK1_ML_LANE_3N
DP_T29SNK1_ML_P<2> DP_T29SNK1_ML_N<2>
V11 U10
DPSNK1_ML_LANE_2P DPSNK1_ML_LANE_2N
DP_T29SNK1_ML_P<1> DP_T29SNK1_ML_N<1>
V13 U12
DPSNK1_ML_LANE_1P DPSNK1_ML_LANE_1N
DP_T29SNK1_ML_P<0> DP_T29SNK1_ML_N<0>
V15 U14
DPSNK1_ML_LANE_0P DPSNK1_ML_LANE_0N
DP_T29SNK1_AUXCH_P DP_T29SNK1_AUXCH_N
V7 U6
DPSNK1_AUX_CHP DPSNK1_AUX_CHN
DP_T29SNK1_HPD
U4
DPSNK1_HOT_PLUG_DET
T29_R2D_C_P<0> T29_R2D_C_N<0>
A6 A4
PRT0_T29T_P PRT0_T29T_N
T29_D2R_P<0> T29_D2R_N<0>
C4 C2
PRT0_T29R_P PRT0_T29R_N
T29_LSEO<0> T29_LSOE<0>
J6 K5
T29_0_LSEO T29_0_LSOE
DPSRC0_ML_LANE_3P DPSRC0_ML_LANE_3N
AA18 Y17
TP_DP_T29SRC_ML_CP<3> TP_DP_T29SRC_ML_CN<3>
DPSRC0_ML_LANE_2P DPSRC0_ML_LANE_2N
AA16 Y15
TP_DP_T29SRC_ML_CP<2> TP_DP_T29SRC_ML_CN<2>
DPSRC0_ML_LANE_1P DPSRC0_ML_LANE_1N
AA14 Y13
TP_DP_T29SRC_ML_CP<1> TP_DP_T29SRC_ML_CN<1>
DPSRC0_ML_LANE_0P DPSRC0_ML_LANE_0N
AA12 Y11
TP_DP_T29SRC_ML_CP<0> TP_DP_T29SRC_ML_CN<0>
W16 U16
TP_DP_T29SRC_AUXCH_CP TP_DP_T29SRC_AUXCH_CN
V3
DP_T29SRC_HPD
Y19 Y21 AA20
T29_DP_ATEST
DPSRC0_AUX_CHP DPSRC0_AUX_CHN DPSRC0_HOT_PLUG_DET DP_ATEST DP_RES_0 DP_RES_1
6 6
6 6
B
6 6
6 6
6 6
100pF SRF > 40MHz BYPASS=U3600.Y19::2mm BYPASS=U3600.Y19::5.08mm
C3685
T29_DP_RES
100PF 1
R3685 14.0K
1% 1/16W MF-LF 402 2
1
R3632 100K
1
5% 50V CERM 2 402
1
C3686 0.01UF
10% 16V 2 CERM 402
5% 1/16W MF-LF 2 402
IN
84
OUT
84
IN
95 84 47
BI
95 84 47
OUT
A10 A8
PRT1_T29T_P PRT1_T29T_N
T29_D2R_P<1> T29_D2R_N<1>
C8 C6
PRT1_T29R_P PRT1_T29R_N
T29_LSEO<1> T29_LSOE<1>
G6 H5
T29_1_LSEO T29_1_LSOE
I2C_T29_SDA I2C_T29_SCL
F3 F5
T29_SDA T29_SCL
T29_R2D_C_P<1> T29_R2D_C_N<1>
PRT2_T29T_P PRT2_T29T_N
A14 A12
NC_T29_R2D_CP<2> NC_T29_R2D_CN<2>
PRT2_T29R_P PRT2_T29R_N
C12 C10
OUT
8
OUT
8
NC_T29_D2RP<2> NC_T29_D2RN<2>
IN
8
IN
8
G4 H3
T29_LSEO_LSOE2 T29_LSEO_LSOE2
OUT
8 33
IN
8 33
PRT3_T29T_P PRT3_T29T_N
A18 A16
NC_T29_R2D_CP<3> NC_T29_R2D_CN<3>
OUT
8
OUT
8
PRT3_T29R_P PRT3_T29R_N
C16 C14
NC_T29_D2RP<3> NC_T29_D2RN<3>
IN
8
IN
8
G2 H1
T29_LSEO_LSOE3 T29_LSEO_LSOE3
OUT
8 33
IN
8 33
T29_2_LSEO T29_2_LSOE
6 33 95
6
5
SYNC_MASTER=T29_REF
SYNC_DATE=10/12/2010
PAGE TITLE
T29_3_LSEO T29_3_LSOE
6 33 95
16V 402
7
OUT
6 33 95
16V 402
DP_T29SNK1_AUXCH_N
OUT
95 84 6
6 33 95
16V 402
DP_T29SNK1_AUXCH_P
95 84 6
6 33 95
16V 402
2
10% X5R
DPSNK0_ML_LANE_2P DPSNK0_ML_LANE_2N
AA8 Y7
R36311
16V 402
2
10% X5R
DP_T29SNK1_ML_P<1>
DP_T29SNK1_ML_P<2>
2
10% X5R
6 33 95
16V 402
2
10% X5R
DP_T29SNK1_ML_N<0>
83 79
16V 402
2
10% X5R
6 33 95
DP_T29SNK1_ML_N<1>
2
10% X5R
DP_T29SNK1_ML_P<0>
16V 402
2
10% X5R
95 33 6
16V 402
2
10% X5R
AA6 Y5
402
2
10% X5R
DP_T29SNK0_ML_P<2> DP_T29SNK0_ML_N<2>
PORT2
C3621
95 33 6
PORT3
DP_T29SNK0_ML_C_N<0>
95 33 6
402
SOURCE PORT 0
IN
95 33 6
5% 1/16W MF-LF 402 2
6 33 95
SINK PORT 0
95 78 6
1
X5R
0
DP_T29SNK0_ML_P<0>
5% 1/16W MF-LF 402 2
DISPLAY
0.1uF
2
DPSNK0_ML_LANE_3P DPSNK0_ML_LANE_3N
PORTS
1
AA4 Y3
PORT0
IN
SNK0 AC Coupling C3620 10% 16V
DP_T29SNK0_ML_C_P<0>
DP_T29SNK0_ML_P<3> DP_T29SNK0_ML_N<3>
PORT1
95 78 6
95 33 6
SINK PORT 1
R36291
NOTE: All unused LSOE/EO pairs should be aliased together. Other signals okay to float (TP/NC).
4
3
T29 Host (1 of 2) DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
36 OF 132 SHEET
33 OF 101
1
A
8
7
6
5
4
D
3
2
1
PP3V3_T29 7 16 19 25 135 mA (Single-Port) 152 mA (Dual-Port) EDP: 200 mA
CRITICAL PP1V05_T29 2100 mA (Single Port) 2250 mA (Dual Port) EDP: 3000 mA
OMIT_TABLE
C3700
1
10UF
20% 6.3V 2 X5R 603
C3701 10UF
1
20% 6.3V 2 X5R 603
1
C3705 1UF
10% 6.3V 2 CERM 402
1
C3710 1UF
10% 6.3V 2 CERM 402
1
C3706 1UF
10% 6.3V 2 CERM 402
1
C3711 1UF
10% 6.3V 2 CERM 402
1
C3707 1UF
10% 6.3V 2 CERM 402
1
C3712 1UF
10% 6.3V 2 CERM 402
1
C3708 1UF
10% 6.3V 2 CERM 402
1
C3713 1UF
10% 6.3V 2 CERM 402
1
C3709 1UF
10% 6.3V 2 CERM 402
1
C3714 1UF
10% 6.3V 2 CERM 402
R3720 1
0
2
5% 1/16W MF-LF 402
PP1V05_T29_VDD_DP MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V
1
C3720 1UF
10% 2 6.3V CERM 402
C
1
C3721 1UF
10% 2 6.3V CERM 402
1
C3722
H9 H11 H13 K9 K11 K13 M9 M11 M13
VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0
U3600
VCC3P3 VCC3P3 VCC3P3
T29 FCBGA (SYM 2 OF 2)
H15 K15 M15 E8 E10 E12 G14
VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE
R8 R10 R12
VDD1P0_DP_RX1 VDD1P0_DP_TXRX VDD1P0_DP_TXRX
VCC3P3_T29 VCC3P3_T29
H7 M7 K7
C3744 1
C3743 1
C3745 1
10% 6.3V 2 CERM 402
10% 6.3V 2 CERM 402
10% 6.3V 2 CERM 402
1UF
G10 G12
1UF
1UF
1
C3746 10UF
20% 6.3V 2 X5R 603
P7 R6
C3747 10UF
20% 2 6.3V X5R 603
PP3V3_T29_DP
VCC3P3_DP_TXRX VCC3P3_DP_TXRX
P9 P11
VDD3P3DP_PLL
P13
C3753
1
1UF
10% 6.3V 2 CERM 402
C3752 1UF
1
C3751
10% 6.3V 2 CERM 402
1UF
1
10% 6.3V 2 CERM 402
C3750
1
1
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
0
2
5% 1/16W MF-LF 402
1UF
0-ohms are placeholders for now, replace with proper values after characterization.
10% 6.3V 2 CERM 402
R3760 PP3V3_T29_PLL
C3760
1UF
1
1
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
0
2
5% 1/16W MF-LF 402
2.2UF
10% 2 6.3V CERM 402
20% 6.3V 2 CERM 402-LF
L3730
C
L3770
FERR-120-OHM-1.5A 1 2 PP1V05_T29_VDD_DPPLL
FERR-120-OHM-1.5A R14
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V
1
VCC3P3_DP_TXRXBIAS
P15
C3730 2.2UF
20% 2 6.3V CERM 402-LF
B
VDD1P0_DP_PLL
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 C18 C20 D1 D3 D5 D7 D9 D11 D13 D15 D17 E18 E20 F7
VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE
VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP
T5 T7 T9 T11 T15 T17 V17 W4 W6 W8 W10 W12 W14 Y1 AA2
VSSDP_PLL
T13
VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE
F9 F11 F13 F15 F17 G18 G20 J16 J18 J20 L16 L18 L20 N16 N18 N20 R18 R20 U18 U20 W18 W20
1
PP3V3_T29_DPBIAS
C3770 1 G8 J8 J10 J12 J14 L8 L10 L12 L14 N8 N10 N12 N14
GND
0402
1
D
33 35 87
R3750 VCC3P3_DP_RX1 VCC3P3_DP_RX1
VCC
35 7
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
2 0402
2.2UF
20% 6.3V 2 CERM 402-LF
B
A
SYNC_MASTER=T29_REF
SYNC_DATE=10/12/2010
PAGE TITLE
T29 Host (2 of 2) DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
Current numbers from Vendor slide ( power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.
8
7
6
5
4
3
2
BRANCH
PAGE
37 OF 132 SHEET
34 OF 101
1
A
5
Page Notes Power aliases required by this page: - =PPVIN_SW_T29BST (8-13V Boost Input) - =PP18V_T29_REG (18V Boost Output) - =PP3V3_T29_P3V3T29FET (3.3V FET Input) - =PP3V3_T29_FET (3.3V FET Output) - =PP3V3_S0_T29PWRCTL - =PP1V05_T29_P1V05T29FET (1.05V FET Input) - =PP1V05_T29_FET (1.05V FET Output)
Q3880
SI8409DB
PPBUS_G3H 8-13V Input Changes required for 2S. T29BST:Y
C3880
D
2
G
1
470K
L3895
T29BST:Y
T29BST:Y
C3890
C3891
R3891
T29BST_SNS1 T29BST:Y
1% 1/16W MF-LF 402 2
T29BST_PWREN_DIV_L
VIN
T29BST_EN_UVLO
1
R3881
25 EN/UVLO
330K
5% 1/16W MF-LF 402 2
1
T29_A_HV_EN
1
1
4.7UF
G
C3887 47PF
10% 10V 2 X5R 805
SOD-VESM-HF
5% 2 50V CERM 402
T29BST:Y 1
R3892
1
C3893 3300PF
1% 1/16W MF-LF 2 402
10K 1% 1/16W MF-LF 402 2
LT3957
6
SNS2
3
30 VC
T29BST_RT
33 RT
10% 2 50V X7R-CERM 0402
1
41.2K
NC
1
5% 50V 2 CERM 402
C3889 100PF
GND
5% 2 50V CERM 402
GND_T29BST_SGND MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V
SGND shorted to GND inside package, no XW necessary.
2
1
PLACE_NEAR=C3895.1:2 mm
R38951 137K
1% 1/16W MF-LF 402 2
T29BST_FBX T29BST:Y NO STUFF 1
31
1
SGND
C3888 10PF
C3894
10% 2 6.3V CERM-X5R 402
DFLS230L
T29BST_VSNS T29BST:Y
34 SYNC
0.33UF
1% 1/16W MF-LF 402 2
D
D3895 POWERDI-123
XW3895 SM
32 SS
T29BST:Y
R3894
1 2 10 35 36
CRITICAL T29BST:Y
T29BST_SNS2
QFN
FBX
UVLO(falling) = 1.22 * (R1 + R2) / R2 UVLO(rising) = UVLO(falling) + (2uA * R1) UVLO = 4.55V (falling), 4.95 (rising)
Supervisor & CLKREQ# Isolation
T29BST_VC
T29BST_SS
R3896 15.8K
1% 1/16W MF-LF 402 2
PP15V_T29 T29BST:Y 1
T29BST:Y
C3895
1
4.7UF
C3897 4.7UF
10% 2 50V X7R-CERM 1206
10% 2 50V X7R-CERM 1206
T29BST:Y
T29BST:Y
C3896
C3898
1
4.7UF
4.7UF
10% 50V X7R-CERM 2 1206
1
10% 50V X7R-CERM 2 1206
7 8 85
Vout = 15V Max Current = 0.8A Freq = 300KHz T29BST:Y 1
C3899 0.001UF
10% 50V 2 X7R 402
Vout = 1.6V * (1 + Ra / Rb)
C
PP3V3_S0 PP3V3_T29
T29BST:Y
7 16 19 25 33 34 35 87
6 D
0.1UF PLT_RST_BUF_L
SLG4AP016V
PP1V05_T29
TDFN
R38032
1 S 7 34 35
G 2
R3887
IN
T29_SW_RESET_L
3 MR*
16
OUT
T29_CLKREQ_L
6 EN 8 OUT
5% 1/16W MF-LF 2 402
T29BST:Y 3 D
330K RESET* 4
IN 7
(OD)
Pull-up provided by SB page.
R3888
T29BST_SHDN_DIV T29BST:Y
DLY
19
T29BST:Y 1
330K
Max Vgs: 10V
1
5% 1/16W MF-LF 402 1
T29_RESET_L DLY = 60 ms +/- 20%
OUT
T29_CLKREQ_ISOL_L T29_CLKREQ_ISOL_L MAKE_BASE=TRUE
THRM PAD
GND
33
SOT563
4 S IN
Q3888 SSM6N37FEAPE
5% 1/16W MF-LF 2 402
33 35
G 5
SMC_DELAYED_PWRGD
33 35
IN
44 89
9
5
B
SOT563
2 + SENSE 0.7V
10K Open-Drain GPIO
R3807
5% 1/16W MF-LF 2 402
U3800
Q3888 SSM6N37FEAPE
1
100K
VDD
10% 25V 2 X5R 402
Platform (PCIe) Reset
CRITICAL
1
C3800 1 IN
0
SNS1
NC
R38931
T29BST_VC_RC T29BST:Y T29BST:Y 1
S 2
73.2K
32 25
U3890
4 23 24 37
C3892
SSM3K15FV
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
CRITICAL T29BST:Y
1
5% 1/16W MF-LF 402 2
SW
T29BST:Y
T29BST:Y D 3
Q3805
C
R38891
2
T29BST:Y
IN
28 INTVCC
T29BST_INTVCC T29BST_PWREN_L
85 84
T29BST_BOOST MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE
10% 25V X5R 2 805
200K
T29BST:Y
2
PCMB063T-100MS
1
10UF
10% 25V X5R 2 805
1
10% 25V 2 X5R 402
1
10UF
T29BST:Y
0.1UF
5% 1/16W MF-LF 402 2
BOM options provided by this page: T29BST:Y - Stuffs 18V boost circuitry.
S
4
T29BST:Y
R38801
Signal aliases required by this page: - =T29_CLKREQ_L - =T29_RESET_L
1
10UH-4A-68-MOHM 1
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm Voltage not specified here, add property on another page.
2
CRITICAL T29BST:Y
PPVIN_SW_T29BST
3
BGA
3
T29 15V Boost Regulator
-30V +/-12V -1.4V 46mOhm @ 4.5V Vgs 3.7A @ 70C
1
D
SI8409DB: Vds(max): Vgs(max): Vgs(th): Rds(on): Id(max):
CRITICAL T29BST:Y 88 63 62 49 48 39 8 7 6
4
8 9 20 21 38
6
12 13 14 15 16 17
7
27
8
B
3.3V T29 Switch 84 83 82 79 51 50 49 48 35 32 28 26 17 16 12 7 23 22 20 19 45 41 40 39 71 61 60 56 98 89 88
72 47 25 6 18 36 53 87
U3810
TPS22924
PP3V3_S0 A2 B2
CSP
VIN
VOUT
PP3V3_T29 7 16 19 25 33 34 Max Current = 1.7A (85C)
A1 B1
U3810 & U3815/U3816
CRITICAL C2 ON
1UF
GND
Part
TPS22924C
10% 6.3V 2 CERM 402
C1
C3810 1
35 87
Type
Load Switch
R(on)
18 mOhm Typ 50 mOhm Max
Max Output: 2A per IC
1.05V T29 Switch U3815
101 72 69 67 44 16 14 13 12 10 9 7 6 39 23 22 20 17
TPS22924
PP1V05_S0 A2 B2
C3815 1 10% 6.3V CERM 2 402
VOUT
A1 B1
PP1V05_T29 7 34 35 Max Current = 3.4A (85C)
CRITICAL C2 ON GND C1
1UF
CSP
VIN
A
SYNC_MASTER=T29_REF
SYNC_DATE=10/12/2010
PAGE TITLE
T29 Power Support
U3816
TPS22924 A2 B2
CSP
VIN
VOUT
DRAWING NUMBER
A1 B1
Apple Inc.
T29_PWR_EN
C2 ON
NOTICE OF PROPRIETARY PROPERTY:
U3816.A2: PLACE_NEAR=U3815.B2:3 mm GND
8
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
C1
IN
Pull-up provided by SB page.
7
D
R
CRITICAL 19
SIZE
REVISION
6
5
4
3
2
BRANCH
PAGE
38 OF 132 SHEET
35 OF 101
1
A
8
7
6
5
4
3
2
BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below. If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY. If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor. Special Star routing needed on these pins. Decoupling on Pg 37. 72 70 36 25
7 6 PP3V3_ENET 281mA (1000base-T max power, Caesar IV)
36
CRITICAL
ENET_SR_LX
70
L3900
PP1V2_ENET
6 7 36 70
Internal 1.2V Switching Regulator pins.
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
SM
C3900
CRITICAL
L3920
FERR-600-OHM-0.5A MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V
10% 16V X7R-CERM 2 402
CRITICAL
FERR-600-OHM-0.5A 1 2 PP3V3_S3_ENET_PHY_BIASVDDH SM
C3921 1
1
10% 16V X7R-CERM 2 402
10% 2 6.3V X5R-CERM 603
0.1UF
L3905
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
1
C3905
1
10% 16V 2 X7R-CERM 402
5% 1/16W MF-LF 402 2
0.1UF
C3931 1
C3950
1K
0.1uF
C3951
ENET_VMAIN_PRSNT
0.1uF 2
93
10% 16V X5R 402
93
93
93 16
IN
PCIE_ENET_R2D_C_P
1
2 10% 16V X5R 402
PCIE_ENET_R2D_C_N
C3956 0.1uF 1
R3943 25
OUT
ENET_WAKE_L (See note)
93
0
1
2
2 10% 16V X5R 402
33 PCIE_RXD_P 34 PCIE_RXD_N
IN IN
ENET_RESET_L
11 PERST*
OUT
ENET_CLKREQ_L
12 CLKREQ* (OD)
94 32
32 19
ENET_LOW_PWR
IN
35 61
29 32
39 45 51
TRD0_P TRD0_N TRD1_P TRD1_N TRD2_P TRD2_N TRD3_P TRD3_N
36 36 36 36
6 SMB_CLK 10 SMD_DATA (IPD)
BCM57765_SCLK BCM57765_MISO BCM57765_MOSI BCM57765_CS_L
66 64 65 63
TP_BCM57765_SPD100LED_L TP_BCM57765_TRAFFICLED_L 25
2 SPD100LED*/SERIAL_DO 67 TRAFFICLED*/SERIAL_DI
SYSCLK_CLK25M_ENET
IN
NC
BCM57765_RDAC
SCLK SI/LINKLED* SO CS*
(OD) (OD)
18 XTALI 19 XTALO 38 RDAC
10% 16V X7R-CERM 2 402
10% 2 6.3V X5R 805
LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for the card reader on-chip I/O. Connect only to U3900 pin 20.
10UF
ENET_MDI_P<0> ENET_MDI_N<0> ENET_MDI_P<1> ENET_MDI_N<1> ENET_MDI_P<2> ENET_MDI_N<2> ENET_MDI_P<3> ENET_MDI_N<3>
40 41 44 43 46 47 50 49 5 8 9
1
37 94
BI
37 94
BI
37 94
BI
37 94
BI
37 94
BI
37 94
BI
37 94
BI
37 94
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V
1
C3970 4.7UF
10% 2 6.3V X5R-CERM 603
1
C3971
1
0.1UF
10% 2 16V X7R-CERM 402
C3972 0.1UF 10%
16V 2 X7R-CERM 402
ENET_MEDIA_SENSE
o1
SDCONN_DETECT_L
OUT
25
IN
32
26
SDCONN_CMD
IN
32 94
CR_CLK/RY_BY*
21
SDCONN_CLK
OUT
32 94
CR_DATA0 CR_DATA1 CR_DATA2 CR_DATA3 CR_DATA4 CR_DATA5 CR_DATA6 CR_DATA7
25 24 23 22 52 53 54 55
SDCONN_DATA<0> SDCONN_DATA<1> SDCONN_DATA<2> SDCONN_DATA<3> SDCONN_DATA<4> SDCONN_DATA<5> SDCONN_DATA<6> SDCONN_DATA<7>
CE*/MS_INS* 59 CR_LED/ALE 60 CR_WP*/XD_WP* 57 XD_DETECT 68
TP_CE_L_MS_INS_L ENET_CR_PWREN
OUT
BDM57765_SR_DISABLE
32
R3980
BI
32 94
BI
32 94
BI
32 94
BI
32 94
BI
32 94
BI
32 94
BI
32 94
BI
32 94
B
No MS (Memory Stick) Insert feature needed. Control signal to light LED or control SD bus power. SDCONN_WP IN 32 1K 1 2 5%
1/16W
MF-LF 402
69
1
R3965 1.24K
ROM contains MAC address, PCIe config info as well as code for Bonjour proxy. Required for proper PHY operation. (Required ROM size TBD) PP3V3_ENET
6
72 70 36 25 7 6
BI
NC
THRM_PAD
PHY Non-Volatile Memory
C
36
PP3V3R1V8_ENET_LR_OUT_REG 36
BCM57765B0
(IPD)
CRITICAL
C3935
PP3V3R1V8_ENET_LR_OUT_REG
GPIO_0 GPIO_1/CR_BUS_PWR RE*/GPIO_2 NOTE: "IPx" == Programmable pull-up/down 3 WAKE* (OD) (IPx) SD_DETECT/WE* SD_DETECT can only be used active low due to errata. 4 LOW_PWR (IPD) (IPU) CR_CMD/CLE
BCM57765_SMB_CLK BCM57765_SMB_DATA
Must isolate from PCIe WAKE# if PHY is powered-down in S3/S5. Standard N-channel FET isolation suggested. If PHY is always powered then alias =ENET_WAKE_L to PCIE_WAKE_L.
B
PCIE_ENET_R2D_P PCIE_ENET_R2D_N
ENET_WAKE_R_L
5% 1/16W MF-LF 402
WAKE#
27 PCIE_TXD_N 28 PCIE_TXD_P
PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N
IN
93 16
16
PCIE_ENET_D2R_C_N PCIE_ENET_D2R_C_P
31 PCIE_REFCLK_P 30 PCIE_REFCLK_N
93 16
4.7UF
1
VDDC
QFN-8X8
0.1uF IN
58 VMAIN_PRSNT (IPD)
(IPU)
1
C3955 93 16
OMIT
U3900
SM
10% 2 6.3V X5R-CERM 603
C3936 1 0.1UF
(IPD)
10% 16V X5R 402
PCIE_ENET_D2R_P
5% Current 1/16W Limiting MF-LF Resistor 2 402
2
(IPU)
OUT
1
(IPU)
93 16
OUT
PCIE_ENET_D2R_N
AVDDL
GPHY_PLLVDDL 36
R3942
VDDO
PCIE_PLLVDDL
AVDDH
SR_LX 16
0.1UF
SR_VFB 13
10% 2 16V X7R-CERM 402
L3930
C3930
C3916 SR_VDD 14
1
10% 6.3V X5R-CERM 2 603
4.7UF
1
93 16
1
0.1UF
7 20 56 62
C3915 1
5% 1/16W MF-LF 2 402
CRITICAL
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V
0.1UF
10% 16V 2 X7R-CERM 402
SR_VDDP 15
PP3V3_S0
4.7UF
10% 16V X7R-CERM 2 402
4.7K
SM
C3925
10% 2 6.3V X5R-CERM 603
C3911
XTALVDDH 17
72 71 61 60 56 53 51 50 49 48 23 22 20 19 18 17 16 12 7 6 47 45 41 40 39 35 32 28 26 25 98 89 88 87 84 83 82 79
1
BIASVDDH 37
R3941
5% 1/16W MF-LF 402 2
L3925
FERR-600-OHM-0.5A 1 2 PP1V2_ENET_PHY_GPHYPLL
42 48
1
4.7K
C3910 0.1UF
4.7K
R39401
1
10% 16V X7R-CERM 2 402
L3910
R39101
CRITICAL
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V
C3926 1
FERR-600-OHM-0.5A 1 2 PP3V3_S3_ENET_PHY_AVDDH SM
C3920 4.7UF
0.1UF
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
D
2 SM
FERR-600-OHM-0.5A 1 2 PP1V2_ENET_PHY_PCIEPLL
10% 16V 2 X7R-CERM 402
CRITICAL
1
PP1V2_ENET_PHY_AVDDL
1
0.1UF
C
PP1V2_ENET 6 7 36 70 ???mA (1000base-T, Caesar V)
VDD for Card Reader I/O PP3V3R1V8_ENET_LR_OUT_REG
FERR-600-OHM-0.5A 1 2 PP3V3_S3_ENET_PHY_XTALVDDH
D
1
1% 1/16W MF-LF 2 402
BCM57765 supports both active-levels for WP.
SR_DISABLE must be pulled down to use internal SR. IPD has a race condition.
C3990 0.1UF
VCC
10% 16V 2 X7R-CERM 402
U3990 AT45DB011D SOIC-8S1 36
BCM57765_SCLK
2
SCK
36
BCM57765_CS_L
4
CS*
5
WP*
3
RESET*
OMIT
SI 1
BCM57765_MOSI
36
SO 8
BCM57765_MISO
36
SYNC_MASTER=K91_ERIC
R3990 4.7K
5% 1/16W MF-LF 2 402
DRAWING NUMBER
1
R3997
Apple Inc.
4.7K
5% 1/16W MF-LF 2 402
7
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
NOTE: Pull-down on SO plus internal pull-ups on other 3 SPI pins configures ENET for the Atmel AT45DB011D (1Mbit) ROM. If a different ROM is used then the straps must change. NOTE: ENETM requires SI pull-down instead of SO.
8
SYNC_DATE=10/11/2010
PAGE TITLE
6
A
ETHERNET PHY (CAESAR IV)
NOSTUFF 1
GND 7
A
5
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
4
3
2
BRANCH
PAGE
39 OF 132 SHEET
36 OF 101
1
8
7
6
5
4
3
2
1
Page Notes Power aliases required by this page: (NONE) Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE)
D
D
Place one of 0.1uf cap close to each centertap pin of transformer
ENETCONN_CTAP 1
1 C40021 C40041 C4006 C4000 0.1UF 0.1UF 0.1UF 0.1UF
10% 2 16V X5R 402-1
10% 2 16V X5R 402-1
10% 2 16V X5R 402-1
10% 2 16V X5R 402-1
CRITICAL 94 36
BI
ENET_MDI_P<0>
1
94 36
BI
ENET_MDI_N<0>
T4000 SM
ENETCONN_P<0>
12
98
2
11
98
3
10
ENET_CTAP0
9
ENET_CTAP1
ENETCONN_N<0>
CRITICAL J4000 RJ45-M97-3
TX
C
4
F-RT-TH
TLA-6T213HF
9
C
10
94 36
BI
ENET_MDI_N<1>
5
8
98
ENETCONN_N<1>
94 36
BI
ENET_MDI_P<1>
6
7
98
ENETCONN_P<1>
1 2 3
RX
4 5
CRITICAL 94 36
94 36
BI
ENET_MDI_N<2>
1
BI
ENET_MDI_P<2>
2
T4001 SM
6 7
12
98
ENETCONN_N<2>
8
11
98
ENETCONN_P<2>
11 12
3
10
ENET_CTAP2
9
ENET_CTAP3
TX
4 94 36
94 36
TLA-6T213HF
514-0636
BI
ENET_MDI_N<3>
5
8
98
ENETCONN_N<3>
BI
ENET_MDI_P<3>
6
7
98
ENETCONN_P<3>
RX
Transformers should be 1R40011 mirrored on opposite R4000 75 75 sides of the board 5% 5% 1/16W MF-LF 4022
B
1/16W MF-LF 4022
1R4003 R4002 75 75
1
5% 1/16W MF-LF 402 2
CRITICAL
5% 1/16W MF-LF 2402
ENET_BOB_SMITH_CAP MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm
PLACE_NEAR=T4001.1:5mm
SLP2510P8
B
2
10% 2KV CERM 1206
PLACE_NEAR=T4000.5:5mm
NC IO NC IO NC IO NC IO
6 5 7 4 9 2 10 1
1
D4000 RCLAMP0524P
GND
D4001 RCLAMP0524P
GND
NC IO NC IO NC IO NC IO
6 5 7 4 9 2 10 1
C4008 1000PF
SLP2510P8
CRITICAL
3
NOSTUFF
CRITICAL
3
NOSTUFF
A
SYNC_MASTER=K91_TRINHNI
SYNC_DATE=05/26/2010
PAGE TITLE
Ethernet Connector DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
40 OF 132 SHEET
37 OF 101
1
A
8
7
6
5
4
3
2
1
PP3V3_FW_FWPHY 7 mA I/O
C4120 1
C4121 1 C4122 1
1UF
1UF
10% 6.3V 2 CERM 402
1UF
10% 6.3V 2 CERM 402
6 7 38 39 40
138 mA
C4123 1
C4124 1
10% 6.3V 2 CERM 402
10% 6.3V 2 CERM 402
1UF
10% 6.3V 2 CERM 402
1UF
L4130
D
120-OHM-0.3A-EMI 1 2 PP3V3_FW_FWPHY_VDDA
114 mA FireWire PHY
C4130 1 C4131 1 1UF
PP1V0_FW_FWPHY
1
0
2
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V
5% 1/16W MF-LF 402
135 mA
10% 6.3V 2 CERM 402
L4135
120-OHM-0.3A-EMI 1 2 PP1V0_FW_FWPHY_AVDD
PP1V0_FW_R
25 mA PCIe SerDes
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V
0402-LF
1
C4110 1UF
10% 2 6.3V CERM 402
1
C4100 1UF
10% 2 6.3V CERM 402
1
120-OHM-0.3A-EMI 1 2 PP3V3_FW_FWPHY_VP25
17 mA PCIe SerDes
C4111 1UF
C4135 1
C4136 1
10% 6.3V 2 CERM 402
10% 6.3V 2 CERM 402
1UF
10% 2 6.3V CERM 402
110 mA Digital Core 1
D
0402-LF
1UF
10% 6.3V 2 CERM 402
L4110
R4100 39 7 6
C4132 1
1UF
10% 6.3V 2 CERM 402
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
0402-LF
1UF
0 mA VReg PWR
C4101 1UF
1
C4102 1UF
10% 2 6.3V CERM 402
10% 2 6.3V CERM 402
1
C4103 1UF
10% 2 6.3V CERM 402
1
C4104
1
1UF
C4105 1UF
10% 2 6.3V CERM 402
10% 2 6.3V CERM 402
1
C4106
C4141 1
1UF
0.1UF
10% 2 6.3V CERM 402
20% 10V CERM 2 402
1
C4140 1UF
10% 2 6.3V CERM 402
C VDD10
40
IN
40
IN
40
PPVP_FW_CPS
R41601
B
200K
1% 1/16W MF-LF 402 2
IN
94 40
BI
94 40 6
BI
94 40
BI
94 40
BI
40 6
BI
40 6
BI
94 40 6
BI
94 40 6
BI
94 40
BI
94 40
BI
40 6
BI
40 6
BI
40
BI
40 39
BI
40 6
BI
NC_FW0_TPBIAS FW_P1_TPBIAS NC_FW2_TPBIAS
PLACE_NEAR=U4100.B10:2mm
C4150 1
2
FW_CLK24P576M_XO CRITICAL 1
NC
22PF
1
Y4150 24.576MHZ
1
412
2
1% 1/16W MF-LF 402
SM-3.2X2.5MM
R41611 2.94K
1% 1/16W MF-LF 402 2
3
C4151 NC
2 4
5% 50V CERM 402
6
R4150
22PF
2
1
R4170 191
1% 1/16W MF-LF 2 402
5% 50V CERM 402
6 6
6 6 6 6 6
R41621 470K
5% 1/16W MF-LF 402 2
6
1
B8 A8 B5 A5 B3 A3 B9 A9 B6 A6 B4 A4
TPA0N TPA0P TPA1N TPA1P TPA2N TPA2P TPB0N TPB0P TPB1N TPB1P TPB2N TPB2P
K12
L5 L10
L6 L9
REFCLKN N9 REFCLKP N10
PCI EXPRESS PHY
93 93 93
0.1UF
PCIE_FW_R2D_N PCIE_FW_R2D_P PCIE_FW_D2R_C_N PCIE_FW_D2R_C_P
C4176 1 0.1UF
TP_FW643_TCK NC_FW643_TDI TP_FW643_TDO TP_FW643_TMS
NT-2 (IPU) TRST* N1
FW643_TRST_L
16 93
IN
16 93
FIXME!!! - TYPO IN SYMBOL REGCTL
POWER MANAGEMENT NT-12 (IPD) NT-13
WAKE* REGCLT VAUX_DETECT VAUX_DISABLE (OD) CLKREQN
C2 D13 E1 D2 L2
16 93
IN
16 93
10% 2 16V PCIE_FW_D2R_N OUT 16 93 X5R402-1PLACE_NEAR=U1800.BJ36:2.54mm 10% 2 16V PCIE_FW_D2R_P OUT 16 93 X5R402-1
0.1UF IN
IN
PLACE_NEAR=U1800.AU34:2.54mm
PCIE_FW_R2D_C_P
PLACE_NEAR=U1800.BG36:2.54mm
C4175 1
PCIE_CLK100M_FW_N PCIE_CLK100M_FW_P
M4 N2 M1 M3
NT-4 (IPU) TCK NT-3 (IPU) TDI (IPU) TDO NT-1 (IPU) TMS
NT-10 (IPD)
6 6
PP3V3_FW_FWPHY
6 7 38 39 40
6 6
FW643_LDO
R41651
FW643_WAKE_L FW643_REGCTL FW643_VAUX_DETECT TP_FW643_VAUX_ENABLE FW_CLKREQ_PHY_L
OUT
5% 1/16W MF-LF 402 2
8 39
1
R4166 10K
5% 1/16W MF-LF 2 402
6
OUT
39
B
1
R4164 10K
K1 L8 F13 G13
NAND_TREE REXT XO XI NT-9
TP_FW643_SE TP_FW643_SM TP_FW643_MODE_A TP_FW643_CE TP_FW643_FW620_L TP_FW643_JASI_EN NC_FW643_AVREG TP_FW643_VBUF FW643_PU_RST_L
M13 N13 J2 L13 D12 D1 A10 H13 K13
SE (IPD) SM (IPD) MODE_A (IPD) NT-18 CE (IPD) FW620* (IPU) JASI_EN (IPD) NT-11 AVREG VBUF FW_RESET* (IPU) NT-8
NT-16 (IPD) SCIFCLK NT-14 (IPD) SCIFDAIN NT-17 SCIFDOUT NT-15 (IPD) SCIFMC
SCIF
NT-OUT NOTE: NT-xx notes show NAND tree order.
SERIAL EEPROM CONTROLLER
NT-7 SCL NT-6 SDA
G2 G1 H1 F2
TP_FW643_SCIFCLK TP_FW643_SCIFDAIN TP_FW643_SCIFDOUT TP_FW643_SCIFMC
N12 M11
FW643_SCL TP_FW643_SDA
N4
FW_RESET_L
5% 1/16W MF-LF 2 402 6 6 6 6
6
MISCELLANEOUS CHIP RESET
NT-5 PERST*
IN
39
1
R4163 10K
J12 OCR_CTL_V10 J13 OCR_CTL_V12 (Reserved) VSS
10% 2 6.3V CERM-X5R 402
93
PCIE_FW_R2D_C_N
10K
TP_FW643_NAND_TREE FW643_REXT FW_CLK24P576M_XO_R FW_CLK24P576M_XI
NC
N8 N7 N5 N6
BGA
1394 PHY
B11 R0 B10 TPCPS
0.33UF
FW643
B7 TPBIAS0 C3 TPBIAS1 A2 TPBIAS2
TP_FW643_OCR10_CTL
0.1UF
PCIE_RXD0N PCIE_RXD0P PCIE_TXD0N PCIE_TXD0P
TEST CONTROLLER
10% 2 16V X5R402-1 2 16V 10% X5R402-1
C4171 1
VREG_PWR
U4100
FW643_R0 FW643_TPCPS
C4162
VP25
OMIT CRITICAL
B13 ATBUSB A13 ATBUSH A11 ATBUSN F12 DS0 (IPD) NT-19 E12 DS1 (IPD) NT-20 E13 DS2 (IPD) NT-21
NC_FW0_TPAN NC_FW0_TPAP FW_PORT1_TPA_N FW_PORT1_TPA_P NC_FW2_TPAN NC_FW2_TPAP NC_FW0_TPBN NC_FW0_TPBP FW_PORT1_TPB_N FW_PORT1_TPB_P NC_FW2_TPBN NC_FW2_TPBP
VP
5% 1/16W MF-LF 2 402
VREG_VSS
B2 D4 D7 D9 D10 E4 E5 E9 F4 F6 F7 F8 F10 G4 G6 G7 G8 G10 H4 H6 H7 H8 H10 J4 J5 J9 J10 K4 K5 K7 K8 K9 L7 K6 K10
40
FWPHY_DS0 FWPHY_DS1 FWPHY_DS2
VDDH
VDD33
PLACE_NEAR=U1800.AV34:2.54mm
C4170 1
L12
NC NC NC
A12 D5 D6 D8
C1 C12 F1 G12 J1 L3 L11 M2
A1 B1 B12 C13 E2 E10 H2 H12 K2 L1 M12 N3 N11
C
A
SYNC_MASTER=K18_MLB
SYNC_DATE=04/27/2010
PAGE TITLE
FireWire LLC/PHY (FW643) DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
41 OF 132 SHEET
38 OF 101
1
A
8
7
6
5
4
Page Notes
D
Power aliases required - =PPBUS_S5_FWPWRSW - =PPBUS_FW_FET - =PP3V3_FW_P3V3FWFET - =PP3V3_FW_FET - =PP3V3_FW_FWPHY - =PP3V3_S0_FWLATEVG - =PP3V3_S0_FWPWRCTL - =PP1V05_S0_FWPWRCTL - =PP1V05_FW_P1V0FWFET - =PP1V0_FW_FET_R - =PP1V0_FW_FWPHY
3
2
1
FireWire Port Power Switch
by this page: (FW VP FET Input) (FW VP FET Output) (3.3V FET Input) (3.3V FET Output) (PHY 3.3V Power)
CRITICAL
Q4260
CRITICAL
FDC638P_G Q4262 provides for fast-off of Q4260 in S0 (Late-VG detection)
5 4 2
(5KPD Bias Rail) (1.0V FET Input) (1.0V FET Output) (PHY 1.0V)
R4262
R4260
10K
FWPORT_FASTOFF_L_DIV
Signal aliases required by this page: - =FW_CLKREQ_L - =FW_PME_L
(SYM-VER2)
SOT-363
S
5
1
PPVP_FW
6 7 40
2
CRS08-1.5A-30V
10% 25V 2 X5R 402
D
3
Q4262
1
R4263
CRITICAL D
10
BOM options provided by this page: (NONE)
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm MINISMDC110H24 VOLTAGE=12.6V
FWPORT_PWREN_L_DIV
BSS8402DW
G
PPBUS_FW_FWPWRSW_D
2
0.1UF
5% 1/16W MF-LF 2 402
4
1
C4260 1
300K
5% 1/16W MF-LF 402 2
PPBUS_FW_FWPWRSW_F MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
1
1
1
D4260 SM
1.1A-24V 6
PPBUS_G3H
88 63 62 49 48 35 8 7 6
CRITICAL
F4260
SM
5% 1/16W MF-LF 402 2
3
FWPORT_FASTOFF_L 1
R4261
5% 1/16W MF-LF 2 402
BSS8402DW
G
2
FWPORT_PWREN_L
SOT-363
S
(SYM-VER1)
40 39 38 7 6
CRITICAL D 3
1
Q4261
40
0.1UF
0.1UF
SOD-VESM-HF 1
C4290 1
NO STUFF
C4261 1
SSM3K15FV G
S 2
10% 25V 2 X5R 402
29 25 18
IN
R4290
5% 1/16W MF-LF 2 402
SLG4AP016V
PP1V0_FW_FWPHY
TDFN
10K 5% 1/16W MF-LF 1 402
39 19
IN
23 16
OUT
6 7 38 39
2 + SENSE - 0.7V
R4283 DLY
FW_RESET_R_L
RESET* 4
3 MR*
FW_PWR_EN FW_CLKREQ_L
6 EN 8 OUT
FW_RESET_L OUT DLY = 60 ms +/- 20% FW_CLKREQ_PHY_L FW_CLKREQ_PHY_L
IN 7
(OD)
Pull-up provided by another page.
GND 5
PP1V05_S0
1
100K
U4290
2
C
101 72 69 16 14 13 12 10 9 7 6 67 44 39 35 23 22 20 17
CRITICAL
VDD
10% 25V 2 X5R 402
PLT_RESET_L
FWPORT_PWR_EN
IN
PP3V3_FW_FWPHY
PP3V3_S0
1
Q4262
PP3V3_S0
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
MAKE_BASE=TRUE
THRM PAD
IN
C
38
38 39
38 39
9
CRITICAL
D 71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
Supervisor & CLKREQ# Isolation
470K
6
FireWire Port 5K Pull-Down Detect R42751
All FireWire devices require 5K pull-down on TPB pair. Host can detect as load on TPBIAS signal. Current source only active when FW_PWR_EN is low.
1K
5% 1/16W MF-LF 402 2
3.3V FW Switch
FW_PWR_EN_L
U4201
330K
Q4275 DMB53D0UV
IN
FW_PWR_EN
2 G
CRITICAL
B
5% 1/16W MF-LF 402 2
Q4270
1
BC847CDXV6TXG SOT563
3
3
6
FWDET_MIRROR
5
CRITICAL
C4270
4
U4201 & U4202
10% 16V X5R 2 402
R42721
R42731
5% 1/16W MF-LF 402 2 PLACE_NEAR=C4360.1:2 mm
5% 1/16W MF-LF 402 2
1.0V FW Switch 39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44
TPS22924
PP1V05_S0 A2 B2
CSP
VIN
VOUT
TPS22924C
Type
Load Switch
R(on)
18 mOhm Typ 50 mOhm Max
1UF
40 39 38 7 6
10% 6.3V 2 CERM 402
C2 ON
1
R4202
GND
0.549
1% 1/16W MF 2 402
R4276
FW_PLUG_DET_L 8 19 OUT Pull-up provided on another page. 3 CRITICAL
100K
5% 1/16W MF-LF 2 402
FW_WAKE NO STUFF
A
6 D
FW643_WAKE_L
C4276
Q4276
5
DMB53D0UV SOT-563
1
4
SYNC_MASTER=T27_REF
0.1UF
10% 16V X5R 2 402
SYNC_DATE=06/10/2010
PAGE TITLE
FireWire Port & PHY Power DRAWING NUMBER
2 G
MAKE_BASE=TRUE
Apple Inc.
CRITICAL
Q4276 S
SIZE
D REVISION
R
DMB53D0UV
NOTICE OF PROPRIETARY PROPERTY:
SOT-563
1
6
6 7 38 39
1) 5K Pull-down Detect when FW_PWR_EN is low. 2) FW643 WAKE# (PME#) when PHY is powered.
1
10K
FW643_WAKE_L
LSI FireWire PHY requires 1.0V. To avoid an extra power supply, 1.05V is used with a series R to reduce voltage.
Dual-purpose output:
5% 1/16W MF-LF 402 2
IN
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V
PP1V0_FW_FWPHY
PP3V3_FW_FWPHY
R42771
39 38 8
B
Max Output: 2A
PP1V05_FW_FET A1 B1
CRITICAL
C4202 1
FW_P1_TPBIAS
FireWire PHY WAKE# Support
7
Part
U4202
12K
When PHY is powered, FW_5KPD_DET_L acts as legacy PME# signal.
8
PP3V3_FW_FWPHY 6 7 38 39 40 Max Current = 1.7A (85C)
A1 B1
GND
10% 6.3V CERM 2 402
SOT-563
0.1UF
BC847CDXV6TXG SOT563
VOUT
C2 ON
1UF
DMB53D0UV 1
CSP
VIN
CRITICAL
C4201 1
Q4275
5
FWDET_EMIT
1K
IN
A2 B2
1
FW_P1_TPBIAS_R
40 38
CRITICAL
Q4270
2
4
TPS22924
PP3V3_S5
MAKE_BASE=TRUE
FW_5KPD_DET_RC
S
29 25 24 23 22 20 19 17 7 6 98 89 85 82 72 71 70 65 55 45
FW_5KPD_DET_L
56K
5% 1/16W MF-LF 2 402
SOT-563 39 19
R42711
R4270
C1
D
1
CRITICAL
C1
6
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
5
4
3
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42 OF 132 SHEET
39 OF 101
1
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7
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Page Notes
4
FW643 TPCPS Leakage Protection
Power aliases required by this page: - =PPVP_FW_PORT1 - =PPVP_FW_PHY_CPS_FET (From Port) - =PPVP_FW_PHY_CPS (To PHY) - =PP3V3_FW_FWPHY - =PP3V3_S0_FWLATEVG
CRITICAL D
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V MAKE_BASE=TRUE
PPVP_FW_CPS To FW643
G
R4311
PPVP_FW_CPS 3
BSS8402DW
SOT-363
1
470K
5% 1/16W MF-LF 402 2
BOM options provided by this page: (NONE)
40 38
IN
NC_FW0_TPBIAS
94 40 38 6
BI
NC_FW0_TPAP
94 40 38
BI
NC_FW0_TPAN
94 40 38 6
BI
NC_FW0_TPBP
94 40 38 6
BI
NC_FW0_TPBN
40 38 6
IN
NC_FW2_TPBIAS
40 38 6
BI
NC_FW2_TPAP
40 38 6
BI
NC_FW2_TPAN
40 38 6
BI
NC_FW2_TPBP
40 38 6
BI
NC_FW2_TPBN
38 40
38 40
1
R4312 330K
5% 1/16W MF-LF 402 2
NC_FW0_TPBIAS MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW0_TPAP MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW0_TPAN MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW0_TPBP MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW0_TPBN MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW2_TPBIAS MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW2_TPAP MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW2_TPAN MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW2_TPBP MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW2_TPBN MAKE_BASE=TRUE
NO_TEST=TRUE
1
FireWire PHY Config Straps
Disabled per LSI instructions (All unused port signals TP/NC)
CPS_EN_L_DIV
1394b implementation based on Apple FireWire Design Guide (FWDG 0.6, 5/14/03)
2 Configures PHY for: - Port "1" Bilingual (1394B)
40 39 38 7 6
Q4300
(SYM-VER2)
PPVP_FW From Port
S
40 39 7 6
4
Signal aliases required by this page: - =FW_PHY_DS0 - =FW_PHY_DS1 - =FW_PHY_DS2 NOTE: This page is expected to contain the necessary aliases to map the FireWire TPA/TPB pairs to their appropriate connectors and/or to properly terminate unused signals.
3
Unused FireWire Ports
FW643 has internal leakage path from TPCPS pin to VDD33. FET blocks current to TPCPS until VDD33 is powered.
5
D
5
PP3V3_FW_FWPHY
38 40
R43821
1
R4380
10K
6 38 40 94
10K
1% 1/16W MF-LF 402 2
38 40 94
1% 1/16W MF-LF 2 402
6 38 40 94
FWPHY_DS0
38 40
FWPHY_DS0
MAKE_BASE=TRUE
6 38 40 94
FWPHY_DS1
40 38
FWPHY_DS1
MAKE_BASE=TRUE 40 38
6 38 40
FWPHY_DS2
FWPHY_DS2
MAKE_BASE=TRUE
6 38 40
D OUT
38 40
OUT
38 40
OUT
38 40
1
R4381 10K
6 38 40
1% 1/16W MF-LF 2 402
6 38 40
6 38 40
CPS_EN_L 6
CRITICAL
D 40 39 38 7 6
Q4300
PP3V3_FW_FWPHY 2
BSS8402DW
G S
SOT-363 (SYM-VER1)
1
C
C
39 38
IN
CRITICAL
Cable Power
Termination Place close to FireWire PHY
40 39 7 6
L4310
FERR-250-OHM Note: Trace PPVP_FW_PORT1 must handle up to 5A 1 2 PPVP_FW_PORT1_F
PPVP_FW
FW_P1_TPBIAS
SM 1
B
C4314
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V
B
0.01UF
1
10% 2 50V X7R 402
C4360 0.33UF
10% 2 6.3V CERM-X5R 402
(FW_PORT1_TPB_N) (FW_PORT1_TPB_P)
"Snapback" & "Late VG" Protection SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY 1 1 1% 1/16W MF-LF 2 402 94 40 38
94 40 38
BI BI
R4361 56.2
1% 1/16W MF-LF 402 2
C4350
10% 16V 2 X5R 402
FW_PORT1_TPA_P MAKE_BASE=TRUE
94 40 38
FW_PORT1_TPA_N
FW_PORT1_TPA_N
TP_FWLATEVG_VCLMP
MAKE_BASE=TRUE
94 40 38
BI
FW_PORT1_TPB_P
94 40 38
FW_PORT1_TPB_P
94 40 38
BI
FW_PORT1_TPB_N
94 40 38
FW_PORT1_TPB_N
39
MAKE_BASE=TRUE SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY 1 1
R4362 56.2
1% 1/16W MF-LF 2 402
CRITICAL
J4310
1
0.1UF 94 40 38
FW_PORT1_TPA_P
BILINGUAL
PLACE_NEAR=U4350.1:2 mm
OUT
FWPORT_PWR_EN
R43501 100K
R4363
F-RT-TH
VCC
U4350
(FW_PORT1_TPB_N) (FW_PORT1_BREF) (FW_PORT1_TPB_P)
TPD4S1394 3 VCLMP
LLP
4 FWPWR_EN
CRITICAL
MAKE_BASE=TRUE
1394B-M97
1
56.2
PORT 1
PP3V3_S0
GND
D1+ D1-
8
D2+
6
D2-
5
7
NC
(GND) (FW_PORT1_TPA_N) FW_PORT1_AREF (FW_PORT1_TPA_P)
2
R4360
72 71 61 60 56 53 51 50 49 48 23 22 20 19 18 17 16 12 7 6 47 45 41 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79
5% 1/16W MF-LF 402 2
56.2
1% 1/16W MF-LF 402 2
PLACE_NEAR=J4310.5:2 mm
C4319 1
FW_PORT1_TPB_C
0.1uF
A
1
C4364 220pF
5% 2 25V CERM 402
10% 50V 2 X7R 603-1
(FW_PORT1_TPA_N)
1
R4364 4.99K
(FW_PORT1_TPA_P)
1% 1/16W MF-LF 402 2
R4319 1M
PLACE_NOTE=J4310.5:2 mm
7
TPB(R)
TPBTPB
TPB+
VP
OUTPUT
TPB+ VP
SC/NC
NC
VG
TPA-
VG
TPA-
TPA
TPA+
10 11 12 13
INPUT
TPA(R) TPA+
CHASSIS GND
SYNC_MASTER=T27_REF
514S0605
FireWire Connector
6
5
4
AREF needs to be isolated from all local grounds per 1394b spec When a bilingual device is connected to a beta-only device, there is no DC path between them (to avoid ground offset issue) BREF should be hard-connected to logic ground for speed signaling and connection
3
SYNC_DATE=06/10/2010
PAGE TITLE
1
5% 1/16W MF-LF 2 402
8
TPB-
1 9 2 8 7 6 3 5 4
DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
43 OF 132 SHEET
40 OF 101
1
A
8
7
6
5
4
3
2
1
SATA ODD Connector ODD Power Control
CRITICAL
FL4520 90-OHM-100MA
CRITICAL
D
SYM_VER-1
CRITICAL
PP5V_S3
3
4
92 6
6
92 6
8
F-ST-SM 2
NOTE: 3.3V must be S0 if 5V is S3 or S5 to ensure the drive is unpowered in S3/S5.
ODD_PWR_EN_LS5V_L
1
D 6
Q4596
5
D
S 4
0.01UF
100K 2
1
ODD_PWR_SS
2
1
SATA_ODD_R2D_UF_N
C4520 1
7
8
9
10
92 6
11
12
92 6
13
14
15
16
IN
16 92
IN
16 92
OUT
16 92
OUT
16 92
10% 16V CERM 402
SATA_ODD_R2D_C_N
2
10% 16V CERM 402
CRITICAL
FL4525
SATA_ODD_D2R_UF_N SATA_ODD_D2R_UF_P
90-OHM-100MA DLP11S
PP3V3_S0
3
6
C4526 1
SATA_ODD_D2R_C_N
R45901
1
516S0616
2
6
C4525 1
SATA_ODD_D2R_C_P
SATA_ODD_D2R_N
2
10% 16V CERM 402
0.01UF
SATA_ODD_D2R_P
2
10% 16V CERM 402
0.01UF
33K
5% 1/16W MF-LF 402 2
100K
2 G
SATA_ODD_R2D_C_P
2
0.01UF
SATA_ODD_R2D_P SATA_ODD_R2D_N
4 71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
SOT563
5% 1/16W MF-LF 402 2
C4521 1
SYM_VER-1
2
10% 16V CERM 402
SSM6N15FEAPE
R45971
PP5V_SW_ODD
C4596
5% 1/16W MF-LF 402
CRITICAL
PP3V3_S0
5 41 6
R4595
SATA_ODD_R2D_UF_P
0.01UF
1
G
10% 10V CERM 2 402
5% 1/16W MF-LF 402 2
4
54722-0164
41
3
0.068UF
100K
98 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 89 88 87 84 83 82 79 72 71
1 2
C4595 1
R45961
3
J4500
PP5V_SW_ODD_R
7
23V1K-SM
6
100 81 71 66 65 45 43 42 41 31 29 7 6
D
DLP11S
Q4590 TPCP8102
S 1 44 6
ODD_PWR_EN
OUT
SMC_ODD_DETECT
Indicates disc presence
CRITICAL
Q4596
D 3
SSM6N15FEAPE SOT563
C
5 G 19
IN
XW4598
S 4
70 56 41 25 22 20 16 7
SM
ODD_PWR_EN_L
41
PP5V_SW_ODD_R
1
PP5V_SW_ODD
2
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
6 41
PP1V5_S0 NO STUFF
C
R45131 R45151
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
4.7K
4.7K
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402 2 SATARDRVR_I2C_ADDR0 41 SATARDRVR_I2C_ADDR1 41
CRITICAL
XW4599
L4500
SM
FERR-70-OHM-4A 1
2 0603
1
C4501
1
0.1UF
100 81 71 66 65 45 43 42 41 31 29 7 6
70 56 41 25 22 20 16 7
C4502
1
0
J4501
B
IR_RX_OUT
54722-0224
OUT
PP5V_S3_IR_R
MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm VOLTAGE=5V 1
NC
0.1UF
10% 16V 2 X7R-CERM 402
2 4
5
6
7
NC
C4532
1 3
6
10 12
13
14
15
16
17
18
19
20
21
22
2
C4531
8
9 11
SYS_LED_ANODE_R
NO STUFF
6 43
1
SYS_LED_ANODE
10% 50V CERM 2 402
SATA_HDD_D2R_RC_C_P
MF-LF 402
1 GND_VOID=TRUE
C4515
2
1
16V
2
CERM
16V
GND_VOID=TRUE
CERM
402
SATA_HDD_R2D_RDRVR_OUT_N SATA_HDD_R2D_RDRVR_OUT_P
1% 68.1 21/16W 1
0.01UF
PS8521A TQFN
1 2
A_INP A_INN
4 5
B_OUTN B_OUTP
CRITICAL
SATA_HDD_D2R_RDRVR_OUT_N
A_OUTP 15 A_OUTN 14 B_INN 12 B_INP 11 REXT 20
C4517 0.01UF
SATA_HDD_R2D_RDRVR_IN_N
C4513
10%
C4512
16V
CERM
SATA_HDD_D2R_P
OUT
16 92
SATA_HDD_D2R_N
OUT
16 92
SATA_HDD_R2D_C_N
IN
16 92
IN
16 92
16 23 26 28 30 47 61 88 93
402
GND_VOID=TRUE 1
2 10%
16V
CERM
402
GND_VOID=TRUE 1
2 10%
0.01UF SATA_HDD_R2D_RDRVR_IN_P
B
GND_VOID=TRUE C4518 1 2
1
16V
CERM
402
16V
CERM
402
2 10%
0.01UF
SATA_HDD_R2D_C_P
SATARDRVR_I2C_ADDR0
8
B_PRE0/I2C_ADDR0
A_PRE1/SCL_CTL 19
SMBUS_PCH_CLK
IN
41
SATARDRVR_I2C_ADDR1
9
APRE0/I2C_ADDR1
B_PRE1/SDA_CTL 17
SMBUS_PCH_DATA
BI
MF-LF 402
SATARDRVR_I2C_EN_L SATARDRVR_TEST
2
1
R4511 0
+/-0.25PFCERM 50V 402
5% 1/16W MF-LF
D2R values for 4.5dB de-emphasis
2 402
SATARDRVR_REXT
GND_VOID=TRUE 16 23 26 28 30 47 61 88 93
10 I2C_EN* 18
R45121
TEST
4.99K
GND THRM PAD
5PF
GND_VOID=TRUE
SATA_HDD_D2R_RDRVR_OUT_P
41
C4535 1
0x96/0x97 0x98/0x99 0xB6/0xB7 0xB8/0xB9
7 EN
2
R4535
Address (R/W)
L H L H
SATARDRVR_EN
IN
+/-0.25PFCERM 50V 402
0.01UF
U4510 402
SATA_HDD_D2R_RDRVR_IN_N 10%
C4519
ADD0
L L H H
20% 2 16V CERM 402
VDD
SATA_HDD_D2R_RDRVR_IN_P
10%
0.01UF
23 16
GND_VOID=TRUE
SATA_HDD_D2R_RC_C_N
1
C4536 5PF
516S0687
C4516 0.01UF
92 6 SATA_HDD_D2R_C_N
1% 68.1 21/16W 1
5% 1/16W MF-LF 402
6 45
GND_VOID=TRUE
92 6 SATA_HDD_D2R_C_P
R4536 GND_VOID=TRUE
4.7K
IN
1
ADDR1
PLACE_NEAR=U4510.16:2 mm PLACE_NEAR=U4510.6:2 mm
R4510
5% 1/16W MF-LF 402
1
0.001UF
NC
4.7
20% 10V 2 CERM 402
PP1V5_S0
R4531
F-ST-SM 6
C4514 0.1UF
70 56 41 25 22 20 16 7
CRITICAL
5% 1/16W MF-LF 402 1
PP1V5_S0
20% 10V 2 CERM 402
2
R4532
6 7 8 22 46 51 53 64 67 68 69 71 72 86 88 101
0.1UF
20% 10V 2 CERM 402
PP5V_S3
PP5V_S0
2
6 16
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
1
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
1% 1/16W MF-LF 402 2
21
PP5V_S0_HDD_FLT
PP5V_S0_HDD_R
3 13
SATA HDD / IR / SIL Connector 6
Internally PD ~150K Write:0xB6 Read:0xB7
PLACE_NEAR=J4501.9:3mm
338S0907
R2D values for 3dB de-emphasis
R4534
A
CRITICAL
FL4501 12-OHM-100MA-8.5GHZ
GND_VOID=TRUE
1
92 SATA_HDD_R2D_UF_N
1
SYM_VER-1
SATA_HDD_R2D_N
1
4
GND_VOID=TRUE
MF-LF 402
2
10%
GND_VOID=TRUE
1
92 SATA_HDD_R2D_UF_P
1% 41.2 21/16W
C4533
GND_VOID=TRUE
8
7
6
C4510 MF-LF 402 SATA_HDD_R2D_RC_UF_P
15PF 1
16V
DRAWING NUMBER
Apple Inc.
CERM 402
0.01UF
1
D
2 10%
16V
NOTICE OF PROPRIETARY PROPERTY:
CERM 402
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
GND_VOID=TRUE
2 5% 50V
SIZE
REVISION
R
R4533
3
SATA/IR/SIL Connectors
GND_VOID=TRUE C4511 1 2
CERM 402
0.01UF 92 6 SATA_HDD_R2D_P
SYNC_DATE=11/08/2010
PAGE TITLE
2 5% 50V
SYNC_MASTER=K91_ERIC
SATA_HDD_R2D_RC_UF_N
15PF
TCM0806-4SM 92 6
1% 41.2 21/16W
C4534
CERM 402
5
4
3
2
BRANCH
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45 OF 132 SHEET
41 OF 101
1
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8
7
6
5
4
3
2
1
D
D
USB Port Power Switch
Left USB Port A
CRITICAL
2 IN_0 3 IN_1
5.1K
5% 1/16W MF-LF 402 2
10% 10V 2 X5R 402
C4696
OUT
USB_EXTA_OC_L USB_EXTB_OC_L
NOSTUFF
1
220UF-35MOHM
20% 6.3V POLY-TANT CASE-B2-SM1
OUT
24
10 FAULT1* ILIM 7 6 FAULT2* 4 EN1 5 EN2 GND
USB_PWR_EN CRITICAL CRITICAL
CRITICAL 1
24
1
C4690 1
C4616
2
1
10UF
100UF
C4691 0.1UF
20% 6.3V 2 X5R 603
20% 2 6.3V POLY-TANT CASE-B2-SM
OUT1 9 OUT2 8
PP5V_S3_RTUSB_A_ILIM MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
USB_ILIM
PP5V_S3_RTUSB_B_ILIM
C
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
0603
C4605
1
CRITICAL
J4600
0.01uF
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
20% 16V CERM 2 402
USB
CRITICAL
F-RT-TH-M97-4 5
L4600 90-OHM-100MA
6
DLP11S
THRM PAD
SYM_VER-1
CRITICAL
R46001 C4695 1 23.2K 1% 1/16W MF-LF 402 2
20% 10V 2 CERM 402
10UF
20% 6.3V 2 X5R 603
CRITICAL
C4617
1
98
USB2_EXTA_MUXED_N
4
3
98
USB2_EXTA_MUXED_P
1
2
1
10UF
20% 6.3V X5R 603
2
USB2_LT1_N 6 USB2_LT1_P
98 6
2
98
3 4
2 5 3 4 6 VBUS
NC IO NC IO
R46901
0.47UF
FERR-120-OHM-3A 1 2 6 PP5V_S3_RTUSB_A_F
SON
PM_SLP_S4_L
C4692
L4605
TPS2561DR
1
C
72 65 44 29 17
CRITICAL
U4600
PP5V_S3
11
100 81 71 66 65 45 43 41 31 29 7 6
7 8
1 GND
Current limit per port (R4600): 2.18A min / 2.63A max
D4600 RCLAMP0502N SLP1210N6
CRITICAL CRITICAL L4615 We can add protection to 5V if we want, but leaving NC for now FERR-120-OHM-3A Place L4605 and L4615 at connector pin 1 2 6 PP5V_S3_RTUSB_B_F 0603
C4615
B
1
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
B
0.01uF
20% 16V CERM 2 402
USB/SMC Debug Mux
CRITICAL
J4610 USB
F-RT-TH-M97-4 5
CRITICAL 90-OHM-100MA DLP11S
SMC_DEBUG_YES
R4650
0.1UF 46 45 44 6
IN OUT
SMC_RX_L SMC_TX_L
20% 10V CERM 2 402
U4650
BI
USB_EXTB_N
4
3
98 6 98 6
5% 1/16W MF-LF 2 402
VCC 5 M+ 4 M-
92 24
10K
9
C4650 1
1
SYM_VER-1
1
SMC_DEBUG_YES
46 45 44 6
6
L4610
PP3V42_G3H
Y+ 1 Y- 2
92 24
BI
USB_EXTB_P
1
BI
92 24
BI
USB_EXTA_P USB_EXTA_N
7 D+ 6 D-
2 3 4
2
7
2 5 3 4
PI3USB102ZLE 92 24
USB_LT2_N USB_LT2_P
6 VBUS
TQFN
CRITICAL
8
NC IO NC IO
46 45 44 25 7 6 72 63 62 52 47
1 GND
SMC_DEBUG_YES 8
USB_DEBUGPRT_EN_L SEL=0 Choose SMC SEL=1 Choose USB
SEL 10
OE* 3
GND
IN
44
D4610 RCLAMP0502N SLP1210N6
CRITICAL
A
SMC_DEBUG_NO
SYNC_MASTER=K91_ERIC
R4651 1
0
5% 1/16W MF-LF 402
Left USB Port B
2
DRAWING NUMBER
R4652 0
Apple Inc.
2
SIZE
D REVISION
R
5% 1/16W MF-LF 402
7
External USB Connectors
SMC_DEBUG_NO 1
8
SYNC_DATE=10/08/2010
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
6
5
4
3
2
BRANCH
PAGE
46 OF 132 SHEET
42 OF 101
1
A
8
7
6
5
4
3
2
1
IR SUPPORT D
100 81 71 66 65 45 42 41 31 29 7 6
D
PP5V_S3
1
C4801 0.1UF
14
10% 16V 2 X7R-CERM 402 VCC
U4800 CY7C63803-LQXC
92 24
BI
92 24
BI
QFN 12 P1.0/D+ P0.0 13 P1.1/DP0.1 15 IR_VREF_FILTER P1.2/VREG INT0/P0.2 16 P1.3/SSEL INT1/P0.3 17 P1.4/SCLK INT2/P0.4 1 18 P1.5/SMOSI TIO0/P0.5 1UF 10% 19 P1.6/SMISO TIO1/P0.6 2 10V X5R 402-1 8 CRITICAL OMIT 9 10 P/N 338S0633 20 21 NC
USB_IR_P DIFFERENTIAL_PAIR=USB2_IR USB_IR_N DIFFERENTIAL_PAIR=USB2_IR
C4803
R4800 IR_RX_OUT_RC
100
1
2
IR_RX_OUT
IN
6 41
5% 1/16W MF-LF 402 1
C4804
0.001UF
10% 2 50V CERM 402
C 25
THRML PAD
VSS 11
22 23 24
C
7 6 5 4 3 2 1
B
B
A
SYNC_MASTER=K18_MLB
SYNC_DATE=04/27/2010
PAGE TITLE
Front Flex Support DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
48 OF 132 SHEET
43 OF 101
1
A
8
7
6
5
4
NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups. 45 6 63 62 52 47 46 45 42 25 7 6 72
3
0.1UF
20% 6.3V 2 CERM 805
D
C4903
1
22UF
20% 10V 2 CERM 402
1
C4905 0.1UF
20% 10V 2 CERM 402
1
C4906 0.1UF
20% 10V 2 CERM 402
SMC_VCL
89 87 72 23
IN
72 65
IN
17
PM_DSW_PWRGD SMC_DELAYED_PWRGD PM_PWRBTN_L
OUT
89 35
OUT
23 17
OUT
45
45 6
49 45
NC
TP_SMC_P20
TP_SMC_P24 SMC_BMON_MUX_SEL
NC NC NC NC NC
93 87 46 16 6
BI
93 87 46 16 6
BI
93 87 46 16 6
BI
93 87 46 16 6
BI
93 87 46 16 6
IN
25
IN
93 25 46 16 6
IN BI
TP_SMC_P41 SMBUS_SMC_MGMT_SDA TP_SMC_P43 45
NC
45 6 100 96 47
BI
79
OUT
53
OUT
46 45 44 42 6
OUT
46 45 44 42 6
IN
96 79 50 47 31 6
BI
SMC_GFX_THROTTLE_L SMC_SYS_KBDLED SMC_TX_L SMC_RX_L SMBUS_SMC_0_S0_SCL
(OC) NC NC
(OC)
SMC_PA0_PU (OC) TP_SPI_DESCRIPTOR_OVERRIDE_L (OC) PM_SYSRST_L (OC) USB_DEBUGPRT_EN_L (OC) MEM_EVENT_L (OC) WIFI_EVENT_L (OC) SYS_ONEWIRE (OC) SMC_BATLOW_L (OC)
45 6 25 17 6 42
OUT OUT
28 26
BI
45 31 6
BI
62
BI
72 45
OUT
19
OUT
41 6 85 72 45
IN OUT
45
IN
79
IN
51
OUT
51
OUT
45 6
OUT
45 6
OUT
51
IN
51
IN
45 6
IN
45 6
IN
48 45
IN
48 45
IN
49 45
IN
48 45
IN
49 45
IN
49 45
IN
49 45
IN
49 45
IN
SMC_RUNTIME_SCI_L SMC_ODD_DETECT SMC_S4_WAKESRC_EN SMC_PB4 45 SMC_DP_HPD_L SMC_GFX_OVERTEMP_L
P10 P11 P12 P13 P14 P15 P16 P17
D13 E11 D12 F11 E13 E12 F13 E10
P20 P21 P22 P23 P24 P25 P26 P27
A9 D9 C8 B7 A8 D8 D7 D6
LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L SMC_LRESET_L LPC_CLK33M_SMC LPC_SERIRQ
NC
NC
U4900
B12 A13 A12 B13 D11 C13 C12 D10
D4 A5 B4 A1 C2 B2 C1 C3
DF2117RVPLP20HV TLP-145V (1 OF 3)
OMIT
P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47
P60 P61 P62 P63 P64 P65 P66 P67
L13 K12 K11 J12 K13 J10 J11 H12
P70 P71 P72 P73 P74 P75 P76 P77
N10 M11 L10 N11 N12 M13 N13 L12
SMC_CPU_VSENSE SMC_CPU_ISENSE SMC_GPU_VSENSE SMC_GPU_ISENSE SMC_GFX_VSENSE SMC_GFX_ISENSE SMC_P1V5S3_ISENSE SMC_CPUVCCIO_ISENSE
P80 P81 P82 P83 P84 P85 P86
A7 B6 C7 D5 A6 B5 C6
SMC_SCI_L PM_CLKRUN_L LPC_PWRDWN_L SMC_TX_L SMC_RX_L (OC) SMBUS_SMC_MGMT_SCL
P90 P91 P92 P93 P94 P95 P96 P97
J4 G3 H2 G1 H4 G4 F4 F1
SMC_ONOFF_L SMC_BC_ACOK SMC_PME_S4_WAKE_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L SMC_CLK32K (OC) SMBUS_SMC_0_S0_SDA
SMC_PM_G2_EN NC NC NC NC
OUT
PP3V3_S5_SMC_AVCC
0.47UF
0.1UF
20% 10V CERM 2 402
65 72
AVCC
VCC
VCL AVREF
U4900 DF2117RVPLP20HV
NC E5
10% 6.3V CERM-X5R 2 402
R49091 10K
NC
5% 1/20W MF 201 2
TLP-145V (3 OF 3)
SMC_ADAPTER_EN
OUT
SMC_PROCHOT_3_3_L SMC_BIL_BUTTON_L
17 45 72
IN
45
IN
6 45 62
IN
45 48
IN
45 49
IN
45 48
IN
45 48
IN
45 48
IN
45 49
IN
45 48
IN
45 48
OUT
16 19
OUT
6 17 46
MD1 D1 MD2 H1
OMIT 63 46 45 6
IN 45 45
SMC_RESET_L
D3
RES*
SMC_XTAL SMC_EXTAL
A3 A2
XTAL EXTAL
NMI E3
AVSS L9
IN
6 42 44 45 46
IN
6 42 44 45 46
BI IN
10K
5% 1/20W MF 2 201
SMC_MD1
IN
6 46
SMC_NMI
IN
6 46
SMC_TRST_L
IN
6 46
R4902
R4998 10K
5% 1/20W MF 2 201
XW4900 SM
5% 1/20W MF 2 201
1
PLACE_NEAR=U4900.L3:4mm
C
GND_SMC_AVSS
45 48 49
47 96 100
6 45 52
IN
45 48 62 63
IN
45 52
IN
6 17 29 72
IN
17 29 42 65 72
IN
17 72
IN
45
BI
R4901
1
10K
6 17 46
OUT
1
VSS
2
1
SMC_KBC_MDE
ETRST* H3
NC
D
PLACE_NEAR=U4900.E1:3mm
C4907 1
L11
C4920 1
E1
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=3.3V
D2 L3 F10 B11 C5
TP_SMC_P10 TP_SMC_RSTGATE_L ALL_SYS_PWRGD S5_PWRGD
45 6
OUT
2
B1 M1 H10
4.7
5% 1/16W MF-LF 402
A
C4904
M12
1
B
1
0.1UF
20% 2 10V CERM 402
R4999 PLACE_NEAR=U4900.M12:3mm PLACE_NEAR=U4900.M12:3mm
45
1
PP3V3_S5_AVREF_SMC PP3V42_G3H
C4902 1
C
2
6 31 47 50 79 96
G2 P50 F3 P51 E4 P52
U4900
N3 N1 M3 M2 N2 L1 K3 L2
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
B8 C9 B9 A10 C10 B10 C11 A11
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
SMC_FAN_0_CTL SMC_FAN_1_CTL NC_SMC_FAN_2_CTL NC_SMC_FAN_3_CTL SMC_FAN_0_TACH SMC_FAN_1_TACH NC_SMC_FAN_2_TACH NC_SMC_FAN_3_TACH
G11 G13 F12 H13 G10 G12 H11 J13
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
SMC_SA_ISENSE SMC_DCIN_VSENSE SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BMON_ISENSE SMC_CPU_HI_ISENSE SMC_GPU_HI_ISENSE SMC_OTHER_HI_ISENSE
M10 N9 K10 L8 M9 N8 K9 L7
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
DF2117RVPLP20HV TLP-145V (2 OF 3)
OMIT
PE0 PE1 PE2 PE3 PE4 PF0
K1 J3 K2 J1 K4 K5
SMC_CASE_OPEN SMC_TCK SMC_TDI SMC_TDO SMC_TMS G3_POWERON_L
PF1 PF2 PF3 PF4 PF5 PF6 PF7
N5 M6 L5 M5 N4 L4 M4
SMC_SYS_LED SMC_LID
PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7
M8 N7 K8 K7 K6 N6 M7 L6
PH0 E2 PH1 F2 PH2 J2 PECI/PH3 A4 PEVREF/PH4 B3 PEVSTP/PH5 C4
NC NC
TP_SMC_PF5
IN
45
IN
6 45 46
IN
6 45 46
OUT
6 45 46
IN
6 45 46
IN
45
OUT
45
IN
45 52 62
IN
45 54
B
6 45
NC NC NC
(OC) (OC) (OC) (OC) (OC) (OC)
SMS_INT_L SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_B_S0_SCL SMC_PROCHOT SMC_THRMTRIP
NC
CPU_PECI_R PVCCIO_S0_SMC_R PM_PECI_PWRGD_R
BI
6 47 62 63 96
BI
6 47 62 63 96
BI
6 31 47 53 54 96
BI
6 31 47 53 54 96
BI
47 50 96
BI
NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.
47 50 96
OUT
45
OUT
45
R4910 1
43
CPU_PECI
2
10 19 90
5% 1/16W MF-LF 402
R4911 C4910 1
1
0.1UF
0
2
PP1V05_S0
6 7 9 10 12 13 14 16 17 20 22 23 35 39 67 69 72 101
SYNC_MASTER=K91_BEN
5% 1/16W MF-LF 402
20% 10V CERM 2 402
SMC
R4912 1
0
SYNC_DATE=07/12/2010
PAGE TITLE
2
DRAWING NUMBER
PM_PECI_PWRGD
72
Apple Inc.
5% 1/16W MF-LF 402
7
6
5
D
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
SIZE
REVISION
4
3
2
BRANCH
PAGE
49 OF 132 SHEET
44 OF 101
1
A
8
7
6
5
SMC Reset "Button", Supervisor & AVREF Supply
45 44 6
45 44 6
52 45 44 6
IN
6 MR1* (IPU) SN0903048 7 MR2* (IPU)
0
4 DELAY
NC_SMC_FAN_3_TACH
6 44 45 72 71 61 60 56 53 51 50 49 48 23 22 20 19 18 17 16 12 7 6 47 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79
6 44 45
NC_SMC_FAN_3_TACH
PP3V3_S0
6 44 45
C5025 10uF
10% 16V CERM 2 402
20% 6.3V 2 X5R 603
SILK_PART=SMC_RST
1
C5026
GND_SMC_AVSS
PLACEMENT_NOTE=Place R5001 on BOTTOM side MR1* and MR2* must both be low to cause manual reset. Used on mobiles to support SMC reset via keyboard.
54 45 44
SMS_INT_L
48 45 44
SMC_CPU_VSENSE
49 45 44
SMC_CPU_ISENSE
48 45 44
SMC_GPU_VSENSE
48 45 44
SMC_GPU_ISENSE
48 45 44
SMC_GFX_VSENSE
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=0V
SMC_CPU_VSENSE
SMC_GPU_VSENSE MAKE_BASE=TRUE
44 48 49
SMC_GPU_ISENSE MAKE_BASE=TRUE
SMC_CPUVCCIO_ISENSE
48 45 44
SMC_SA_ISENSE
48 45 44
SMC_DCIN_VSENSE
49 45 44
SMC_DCIN_ISENSE
48 45 44
SMC_PBUS_VSENSE
NOTE: Internal pull-ups are to VIN, not V+.
SMC_P1V5S3_ISENSE
TO CPU 90 67 10
44 45 48
SMC_SA_ISENSE
BI
R5062
CPU_PROCHOT_L
1
SMC_DCIN_VSENSE
6 D
44 45 48
MAKE_BASE=TRUE
SMC_DCIN_ISENSE
IN
44
IN
44
Q5060
2 G
SMC_PBUS_VSENSE
CRITICAL
Q5060
5
S
DMB53D0UV
1
SOT-563
CRITICAL
4
Q5059 SSM6N15FEAPE
44 45 49
MAKE_BASE=TRUE
3
3.3K 2 CPU_PROCHOT_L_R 5% 1/16W MF-LF 402
44 45 48
MAKE_BASE=TRUE
SOT563
44 45 48
MAKE_BASE=TRUE
SMC_BMON_ISENSE
SMC_BMON_ISENSE
1 S
44 45 49
MAKE_BASE=TRUE
SMC_CPU_HI_ISENSE
G 2
SMC_PROCHOT
44 45 49
MAKE_BASE=TRUE 49 45 44
SMC_GPU_HI_ISENSE
49 45 44
SMC_OTHER_HI_ISENSE
SMC_GPU_HI_ISENSE
44 45 49
MAKE_BASE=TRUE 19
SMC_OTHER_HI_ISENSE
44 45 49
OUT
PM_THRMTRIP_L_R CRITICAL
MAKE_BASE=TRUE 45 44 6
Debug Power "Buttons"
TP_SMC_P10
TP_SMC_P10
3 D
6 44 45
MAKE_BASE=TRUE 45 44
TP_SMC_P20
45 44 6
TP_SMC_P24
TP_SMC_P20
OMIT
C
R50161
OUT
6 44 45 52
SOT563
49 45 44
R5015
SMC_BMON_MUX_SEL
SMC_BMON_MUX_SEL
4 S
44 45 49
MAKE_BASE=TRUE
0
PLACE_SIDE=TOP 5% 1/10W MF-LF 2 603
SILK_PART=PWR_BTN
6 44 45
MAKE_BASE=TRUE
1
0 PLACE_SIDE=BOTTOM 5% 1/10W MF-LF 603 2
TP_SMC_P24
Q5059 SSM6N15FEAPE
44 45
MAKE_BASE=TRUE
SMC_ONOFF_L OMIT
SILK_PART=PWR_BTN
45 44 6
TP_SMC_P41
45 44
TP_SMC_P43
45 44 6
TP_SMC_PF5
45 44
TP_SMC_P41 TP_SMC_P43
SMC_THRMTRIP
44 45
MAKE_BASE=TRUE
TP_SMC_PF5
6 44 45
MAKE_BASE=TRUE
TP_SMC_RSTGATE_L
C
G 5
6 44 45
MAKE_BASE=TRUE
TP_SMC_RSTGATE_L
44 45
MAKE_BASE=TRUE
62 52 47 46 45 44 42 25 7 6 72 63
R5012 17
IN
PM_CLK32K_SUSCLK_R
22
1
SMC_CLK32K
2
OUT
44
52 45 44 6
5% 1/16W MF-LF 402
PLACE_NEAR=U1800.N14:5.1mm
44 62 52 44 46 44 42 6 46 44 42 6
PP3V3_S4
46 44 6
SMC Crystal Circuit 44
SMC_XTAL
0
1
2
5% 1/16W MF-LF 402
15pF
1
SMC_XTAL_R
Y5010 1
20.00MHZ
B
5X3.2-SM
46 44 6 46 44 6 62 44 6
SMC_DP_HPD_L OUT
Q5020
R5070 R5072 R5071 R5073 R5074
10K 10K 100K 10K 100K
1 1 1 1 1
2 2 2 2 2
SMC_TMS SMC_TDO SMC_TDI SMC_TCK SMC_BIL_BUTTON_L SMC_BC_ACOK SMS_INT_L
R5077 R5078 R5079 R5080 R5081 R5087 R5093
10K 10K 10K 10K 10K 470K 10K
1 1 1 1 1 1 1
2 2 2 2 2 2 2
63 62 48 45 44 44 54 45 44
SMC_PA0_PU
R5091
100K
1
PP3V42_G3H
5% 5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W 1/20W
MF MF MF MF MF
201 201 201 201 201
5% 5% 5% 5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W
MF MF MF MF MF MF MF
201 201 201 201 201 201 201
NOSTUFF
5%
1/20W
MF
201
5% 5%
1/20W 1/20W
MF MF
201 201
5% 5%
1/20W 1/20W
MF MF
201 201
D 3
SSM3K15FV SOD-VESM-HF
44
2
C5011
2 44
46 44 6
100K
CRITICAL
2
5% 50V CERM 402
CRITICAL
R5020
5% 1/20W MF 2 201
C5010
SMC_ONOFF_L G3_POWERON_L SMC_LID SMC_TX_L SMC_RX_L
7 45 52 53 71
1
R5010
D
CRITICAL SOT-563
44 45 48
SMC_CPUVCCIO_ISENSE MAKE_BASE=TRUE
SMC_CPU_HI_ISENSE
44
44 45 49
MAKE_BASE=TRUE
49 45 44
D
CPU_PROCHOT_BUF
MAKE_BASE=TRUE
49 45 44
6
44 45 48
44 45 48
SMC_GFX_ISENSE
SMC_P1V5S3_ISENSE
44 45 48
OUT
DMB53D0UV
SMC_GFX_VSENSE MAKE_BASE=TRUE
48 45 44
TO SMC
44 45 49
MAKE_BASE=TRUE
48 45 44
5% 1/16W MF-LF 2 402
SMC_PROCHOT_3_3_L
SMC_CPU_ISENSE
49 45 44
10K
5% 1/16W MF-LF 2 402
44 45 48
MAKE_BASE=TRUE
R5060
100K
44 45 54
MAKE_BASE=TRUE
1
R5061
44 45 48 62 63
SMS_INT_L
SMC_GFX_ISENSE
0.01UF
10% 2 16V CERM 402
1
SMC_BC_ACOK MAKE_BASE=TRUE
6 44
PAD
1
SMC_BC_ACOK
1
SMC FSB to 3.3V Level Shifting
6 44 45
NC_SMC_FAN_3_CTL
6 44 46 63
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=3.3V
8
THRM
0.01UF
5% 1/10W MF-LF 2 603
OUT
PP3V3_S5_AVREF_SMC
CRITICAL REFOUT
GND
1
SMC_RESET_L
RESET* 5
2
C5001
5% 1/16W MF-LF 2 402
VREF-3.3V-VDET-3.0V
SMC_MANUAL_RST_L OMIT
R5001
1K
U5010
SMC_TPAD_RST_L SMC_ONOFF_L
1
R5000
VIN
DFN
63 62 48 45 44
1
3 V+
10% 6.3V CERM-X5R 2 402
D
NC_SMC_FAN_3_CTL
2
MAKE_BASE=TRUE
0.47UF
IN
NC_SMC_FAN_2_CTL NC_SMC_FAN_2_TACH MAKE_BASE=TRUE
C5020 1
52
NC_SMC_FAN_2_TACH
MAKE_BASE=TRUE
9
52 47 46 45 44
NC_SMC_FAN_2_CTL
45 44 6
3
MAKE_BASE=TRUE
PP3V42_G3H 42 25 7 6 72 63 62 PP3V42_G3H 42 25 7 6 72 63 62 Desktops: 5V Mobiles: 3.42V 1
52 47 46 45 44
45 44 6
4
B
15pF
1
SMC_EXTAL
2
1 G
5% 50V CERM 402
84 83
IN
S 2
DP_A_EXT_HPD 72 44 17 44
PP3V3_S4
System (Sleep) LED Circuit
44 7 45 52 53 71 85 72 44
SMC_ADAPTER_EN SMC_CASE_OPEN
R5085 R5086
10K 10K
1 1
2 2
SMC_PB4 SMC_S4_WAKESRC_EN
R5088 R5090
10K 100K
1 1
2 2
WIFI_EVENT_L
R5089
10K
1
1
R5076 100K
PP5V_S3
5% 1/20W MF 2 201
R50311
1
R5030
523
52 45 44
IN
SMC_PME_S4_WAKE_L
1% 1/16W MF-LF 402 2
MAKE_BASE=TRUE
PP3V3_S5
4
D
B
E
Q5030
PP3V3_SUS
R50401 100K
SOT-563
5% 1/20W MF 201 2
SYS_LED_L Q2
Q1
72 44
201
S
G
C
1
2
3
SMC_SYS_LED
IN
SYNC_MASTER=K91_BEN
SMC Support
1
SOD-VESM-HF
SMC_BATLOW_L
OUT
3
Internal 20K pull-up on PM_BATLOW_L in PCH. PM_BATLOW_L
DRAWING NUMBER
Apple Inc. OUT
17
0
6
5
SIZE
D REVISION
R
2
5% 1/16W MF-LF 402
6 41
SYNC_DATE=07/12/2010
PAGE TITLE
Q5040 SSM3K15FV
NOTICE OF PROPRIETARY PROPERTY:
R5041 SYS_LED_ANODE
7
7 16 17 18 19 20 22 70 71 72
CRITICAL
1
8
MF
CRITICAL
G
5
S
6
DMB54D0UV
IN
1/20W
BATLOW# Isolation 29 25 24 23 22 20 19 17 7 6 98 89 85 82 72 71 70 65 55 39
1% 1/16W MF-LF 402 2
2 5%
R50321 1.47K
PP3V3_WLAN
44 45 52
44 31 6
SYS_LED_L_VDIV
44
31 6
OUT
1% 1/16W MF-LF 2 402
SYS_LED_ILIM
A
SMC_PME_S4_WAKE_L
20
D
100 71 66 65 43 7 6 42 41 31 29 81
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
NOSTUFF
4
3
2
BRANCH
PAGE
50 OF 132 SHEET
45 OF 101
1
A
8
7
6
5
D
4
3
2
1
D
LPC+SPI Connector CRITICAL LPCPLUS_CONN:YES
J5100
55909-0374 63 62 52 47 45 44 42 25 7 6 72 86 72 71 69 68 67 64 53 51 41 22 8 7 6 101 88
93 87 44 16 6 93 87 44 16 6
LPC_AD<0> LPC_AD<1>
BI BI
46 6
IN
46 6
OUT
93 87 44 16 6
SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS LPCPLUS_RESET_L SMC_TDO SMC_TRST_L SMC_MD1 SMC_TX_L
IN
44 17 6
OUT
45 44 6
OUT
93 87 25 6
IN
45 44 6
OUT
44 6
IN
44 6
OUT
45 44 42 6
M-ST-SM 31 32
PP3V42_G3H PP5V_S0
IN
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
LPC_CLK33M_LPCPLUS LPC_AD<2> LPC_AD<3> SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO
IN
6 25 93
BI
6 16 44 87 93
BI
6 16 44 87 93
OUT
6 19 55
IN
6 46
IN
6 46 6 16 44
BI IN
6 17 44
OUT
6 44 45
OUT
6 44 45
OUT
6 44 45 63
OUT
6 44
OUT
6 42 44 45
OUT
6 19
C
516S0573
SPI Bus Series Termination SPI_ALT_MISO SPI_ALT_MOSI SPI_ALT_CLK SPI_ALT_CS_L LPCPLUS_R:YES 1
R5128 0
PLACE_NEAR=U1800.AV3:5mm IN
B
SPI_CS0_R_L
93 16
IN
SPI_CLK_R
PLACE_NEAR=U1800.AY1:5mm 93 16
IN
SPI_MOSI_R
R5111 1
R5112 1
15
15
15
OUT
R5126
R5125
47
47
5% 1/16W MF-LF 2 402
2
2
5% 1/16W MF-LF 2 402
SPI_CS0_L
1
R5121 93
SPI_CLK
1
5% 1/16W MF-LF 402 93
SPI_MOSI
1
R5123
SPI_MISO
6 46
PLACE_NEAR=J5100.14:5mm PLACE_NEAR=J5100.12:5mm PLACE_NEAR=J5100.9:5mm PLACE_NEAR=J5100.11:5mm
1
15
47
47
47
2
SPI_MLB_CS_L
OUT
55
5% PLACE_NEAR=R5125.2:5mm 1/16W MF-LF 402
2
SPI_MLB_CLK
B
OUT
55
SPI_MLB_MOSI
OUT
55
SPI_MLB_MISO
IN
55
5% PLACE_NEAR=R5126.2:5mm 1/16W MF-LF 402
R5122
2
6 46
R5120 93
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402 93 16
5% 1/16W MF-LF 2 402
6 46
LPCPLUS_R:YES LPCPLUS_R:YES 1 1
R5110 1
PLACE_NEAR=U1800.BA2:5mm
R5127 47
5% 1/16W MF-LF 2 402
93 16
LPCPLUS_R:YES 1
6 46
2
5% PLACE_NEAR=R5127.2:5mm 1/16W MF-LF 402
2 5% PLACE_NEAR=U6100.2:5mm 1/16W MF-LF 402
A
SYNC_MASTER=K18_MLB
SYNC_DATE=04/27/2010
PAGE TITLE
LPC+SPI Debug Connector DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
51 OF 132 SHEET
46 OF 101
1
A
8
7
6
5
PCH SMBus "0" Connections 98 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 89 88 87 84 83 82 79 72 71
R52001 1K
5% 1/16W MF-LF 402 2
U1800 (MASTER)
D
93 88 28 26 23 16 61 47 41 30
SMBUS_PCH_CLK
93 88 28 26 23 16 61 47 41 30
SMBUS_PCH_DATA
1
R5201 1K
5% 1/16W MF-LF 2 402
SO-DIMM "A" SMBUS_PCH_CLK
88 61 47 26 23 16 41 30 28 93 88 61 47 26 23 16 41 30 28 93
47 16 28 93 47 16 28 93
MAKE_BASE=TRUE
SMBUS_PCH_DATA
MAKE_BASE=TRUE
63 62 52 46 45 44 42 25 7 6 72
R52501 4.7K
5% 1/16W MF-LF 402 2
U4900 (MASTER)
61 88 23 26 30 41
47 44 31 6 96 79 50
61 88 23 26 30 41
47 44 31 6 96 79 50
SMBUS_SMC_0_S0_SCL
1
R5251
GPU Temp (Ext)
4.7K
5% 1/16W MF-LF 2 402
SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA
SMBUS_PCH_CLK
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_DATA
79 96 6 31 44 47 50
62 47 44 6 96 63
SMBUS_SMC_0_S0_SDA
79 96 6 31 44 47 50
62 47 44 6 96 63
47 16 28 93 47 16 28 93
61 88 23 26 30 41
SMBUS_SMC_0_S0_SCL
61 88 23 26 30 41
SMBUS_SMC_0_S0_SDA
50 44 6 31 47 79
X19 (Write: 0x90 Read: 0x91)
SMBUS_SMC_BSA_SCL
SMBUS_SMC_0_S0_SCL
SMBUS_PCH_DATA
SMBUS_SMC_0_S0_SDA
SATA Redriver
LED BACKLIGHT
U4510
U9701 (WRITE: 0x58 READ: 0x59)
(Write: 0xB6 Read: 0xB7)
SMBUS_SMC_BSA_SCL
47 16 28 93 47 16 28 93
SMBUS_PCH_CLK
SMBUS_PCH_CLK
96 50 6 31 44 47 79 5096 6 31 44 47 79
SMBUS_PCH_DATA
SMBUS_PCH_DATA
32 31 30 29 25 24 19 18 8 7 6 87 72 71 54 53 49 48 47
U6880 (Write: 0x72 Read: 0x73) 47 16 28 93 47 16 28 93
SMBUS_PCH_DATA
SDRVI2C:SB 1
R5237 0
5% 1/16W MF-LF 402 2
R52701
61 88 23 26 30 41 61 88 23 26 30 41
1K
5% 1/16W MF-LF 402 2
U4900 (MASTER) 47 44 31 6 96 54 53 47 44 31 6 96 54 53
SMBUS_SMC_A_S3_SCL
1
R5271
MAKE_BASE=TRUE
5% 1/16W MF-LF 2 402
Battery Manager - (Write: 0x16 Read: 0x17) Battery LED Driver - (Write: 0x36 Read: 0x37) Battery Temp - (Write: 0x92 Read: 0x93)
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SCL
54 96 6 31 44 47 53
SMBUS_SMC_A_S3_SDA
54 96 6 31 44 47 53
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SDA MAKE_BASE=TRUE
R5236
DP SDRV "A"
J3401
U9310 (Write: 0x94 Read: 0x95)
(Write: 0x72 Read: 0x73)
0
5% 1/16W MF-LF 2 402 84 47
I2C_DPSDRVA_SCL
84 47
I2C_DPSDRVA_SDA
ALS
R52901
8.2K
5% 1/16W MF-LF 402 2
U1800 (MASTER)
SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
100 96 47 44
SMBUS_SMC_A_S3_SCL
I2C_DPSDRVA_SDA
54 96 6 31 44 47 53
47 84
SMBUS_SMC_A_S3_SDA
54 96 6 31 44 47 53
1
R5211
SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
SMBUS_SMC_MGMT_SDA
44 47 96 100
C
44 47 96 100
PP3V3_S0
T29 IC
R52301
U3600 (MASTER)
5% 1/16W MF-LF 402 2
4.7K
1
R5231 4.7K
5% 1/16W MF-LF 2 402
T29 Port A MCU J9330 (Write: 0x26 Read: 0x27)
I2C_T29_SCL
I2C_T29_SCL
33 47 84 95
MAKE_BASE=TRUE
I2C_T29_SDA
I2C_T29_SDA
33 47 84 95
R5234
5% 1/16W MF-LF 402 2
SMBUS_SMC_A_S3_SCL
54 96 6 31 44 47 53
SMBUS_SMC_A_S3_SDA
54 96 6 31 44 47 53
SDRVI2C:MCU 1
R5235
DP SDRV "A"
0
5% 1/16W MF-LF 2 402 84 47
U9310 (Write: 0x94 Read: 0x95)
I2C_DPSDRVA_SCL
I2C_DPSDRVA_SCL
47 84
I2C_DPSDRVA_SDA
47 84
B
MAKE_BASE=TRUE 84 47
I2C_DPSDRVA_SDA MAKE_BASE=TRUE
5% 1/16W MF-LF 2 402
U1800 (Write: 0x88 Read: 0x89)
PP3V3_S0
R52601
SMC
4.7K
5% 1/16W MF-LF 402 2
U4900 (MASTER)
PP3V3_S0
Cougar Point
96 50 47 44
SMBUS_SMC_B_S0_SCL
96 50 47 44
96 50 47 44
SMBUS_SMC_B_S0_SDA
96 50 47 44
1
R5261
CPU Temp
4.7K
5% 1/16W MF-LF 2 402
EMC1414-A: U5570 (Write: 0x98 Read: 0x99)
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SCL
MAKE_BASE=TRUE
R52201 8.2K
5% 1/16W MF-LF 402 2
NO STUFF
R5221 8.2K
5% 1/16W MF-LF 2 402
SMBUS_SMC_B_S0_SDA
44 47 50 96
0
5% 1/16W MF-LF 402
1
SYNC_MASTER=K18_MLB
T29 Temp 2 2
SMBUS_SMC_B_S0_SCL
0 5%
SMBUS_SMC_B_S0_SDA
1/16W MF-LF 402
SYNC_DATE=04/27/2010
PAGE TITLE
SMBus Connections
EMC1412-A: U5520 (Write: 0x90 Read: 0x91)
R5222
SMLink 1 is slave port to access PCH & CPU via PECI.
44 47 50 96
R5223 1
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
1
MAKE_BASE=TRUE
8
SMBUS_SMC_MGMT_SCL
U5930 (Write: 0x10 Read: 0x11)
SMC "B" SMBus Connections
NO STUFF
SML_PCH_1_DATA
5% 1/16W MF-LF 2 402
8.2K
98 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 89 88 87 84 83 82 79 72 71
93 16
Sensor ADC A
4.7K
MAKE_BASE=TRUE
SDRVI2C:MCU 1
Digital SMS
MAKE_BASE=TRUE
SML_PCH_1_CLK
6 44 47 62 63 96
MAKE_BASE=TRUE
98 89 88 87 84 83 82 79 72 47 45 41 40 39 18 17 16 12 7 6 36 35 32 28 26 25 23 22 20 19 71 61 60 56 53 51 50 49 48
(Write: 0x32 Read: 0x33)
MAKE_BASE=TRUE
93 16
6 44 47 62 63 96
MAKE_BASE=TRUE
47 84
PCH "SMLink 1" Connections
A
R5291
5% 1/16W MF-LF 402 2
100 96 47 44
LIS331DLH: U5920 (Write: 0x30 Read: 0x31)
R52101
1
4.7K
100 96 47 44
95 84 47 33
I2C_DPSDRVA_SCL
PP3V3_S0
Cougar Point
98 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 89 88 87 84 83 82 79 72 71
SMBUS_SMC_BSA_SDA
PP3V3_S3
100 96 47 44
84 47 33 95
Lid Angle Detect
PCH "SMLink 0" Connections
SML_PCH_0_DATA
SMBUS_SMC_BSA_SCL
The bus formerly known as "Battery B" 32 31 30 29 25 24 19 18 8 7 6 87 72 71 54 53 49 48 47
0
SML_PCH_0_CLK
D
6 44 47 62 63 96
T29 SMBus Connections
J5800 (Write: 0x90 Read: 0x91)
MAKE_BASE=TRUE
93 16
6 44 47 62 63 96
J6955 (See Table)
Trackpad
1K
MAKE_BASE=TRUE
93 16
SMBUS_SMC_BSA_SDA
Battery
SDRVI2C:SB 1
98 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 89 88 87 84 83 82 79 72 71
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
PP3V3_S3
SMC
SMBUS_PCH_CLK
SMBUS_PCH_DATA
B
ISL6258 - U7000 (Write: 0x12 Read: 0x13)
NOTE: SMC RMT bus remains powered and may be active in S3 state
61 88 23 26 30 41
Mikey
SMBUS_PCH_CLK
SMC "A" SMBus Connections
61 88 23 26 30 41
J2500 & J2550 (MASTER) 93 88 28 26 23 16 61 47 41 30
Battery Charger
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDA
U4900 (MASTER)
XDP Connectors
93 88 28 26 23 16 61 47 41 30
5% 1/16W MF-LF 2 402
SMC "Management" SMBus Connections
SMBUS_PCH_CLK
93 88 28 26 23 16 61 47 41 30
2.0K
Battery
Whistler: U8000 (Write: 0x82 Read: 0x83) 96
U3301 (Write: 0x30 Read: 0x31)
93 88 28 26 23 16 61 47 41 30
R5281
5% 1/16W MF-LF 402 2
SMC
C
1
2.0K
GPU Temp (Int)
Margin Control 88 61 47 26 23 16 41 30 28 93 88 61 47 26 23 16 41 30 28 93
R52801
U4900 (MASTER)
SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE
SO-DIMM "B"
1
PP3V42_G3H
SMC
EMC1414-A: U5550 (Write: 0x98 Read: 0x99)
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
J3100 (Write: 0xA4 Read: 0xA5)
U3300 (Write: 0x98 Read: 0x99)
2
SMC "Battery A" SMBus Connections
PP3V3_S0
SMC
J2900 (Write: 0xA0 Read: 0xA1)
VRef DACs
3
SMC "0" SMBus Connections 98 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 89 88 87 84 83 82 79 72 71
PP3V3_S0
Cougar Point
4
DRAWING NUMBER
Apple Inc.
44 47 50 96
NOTICE OF PROPRIETARY PROPERTY:
6
5
4
D
R 44 47 50 96
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
7
SIZE
REVISION
3
2
BRANCH
PAGE
52 OF 132 SHEET
47 OF 101
1
A
8
7
6
5
4
3
PBUS Voltage Sense Enable & Filter
2
GPU VCore Load Side Current Sense / Filter
CRITICAL Q5300
72 71 61 60 56 53 51 50 49 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79
NTUD3169CZ
PP3V3_S0
ISNS_ON:YES 1
SOT-963
N-CHANNEL
Enables PBUS VSense divider when in S0. 72 71
IN
PM_SLP_S3_R_L
6
2
R53021
D
1 3
5 39 35 8 7 6 88 63 62 49
81
PBUS_S0_VSENSE
D
GFXIMVP6_IMON
IN
S
4
PLACE_NEAR=U4900.L8:5MM
SMC_PBUS_VSENSE
R5304
1
5.49K
44 45
IN
SMC_BC_ACOK
2
98 69
5
6.49K2
CPUVCCIOS0_CS_P
1
1% 1/16W MF-LF 402 2
98 69
IN
CPUVCCIOS0_CS_N
6.49K2 1% 1/16W MF-LF 402
ISNS_ON:YES
R53131 1% 1/16W MF-LF 402 2
4
V+
SMC_DCIN_VSENSE
OUT
4
R5314
1
5.49K
9
R5325
1
1M
1M
32 31 30 29 25 24 19 18 8 7 6 87 72 71 54 53 49 47
20% 2 6.3V X5R 402
2
1% 1/16W MF-LF 402
PLACE_NEAR=R7510.2:5 MM
B
SMC_CPU_VSENSE
ISNS_ON:YES 44 45 48 49
IN
PLACE_NEAR=U4900.N10:5MM
OUT
1
8
VCCSAISNS_R_P
98
1% 1/16W MF-LF 402
VCCSAS0_CS_N
44 45
1.82K2
1
ISNS_ON:YES
C5320
GND_SMC_AVSS
1
4.53K2
1 ISENSE_SA_IOUT
1% 1/16W MF-LF 402
4
9
VCCSAISNS_R_N
ISNS_ON:YES
R5365
ISNS_ON:YES
1% 1/16W MF-LF 2 402
1
1M
SMC_SA_ISENSE 1
OUT
44 45
C5367 PLACE_NEAR=U4900.M10:5mm 0.22UF
ISNS_ON:YES GND_SMC_AVSS 44 45 48 49
R5366
1M
SMC Key IC2C SMC_ADC8
20% 6.3V 2 X5R 402
GAIN:549X
1
0.22UF
20% 2 6.3V X5R 402
R5367
VTHRM
1% 1/16W MF-LF 402
PLACE_NEAR=U4900.M10:5mm
OPA2333
V+
2
R5364 IN
0.1UF
DFN
3
C5360
20% 10V 2 CERM 402
CRITICAL U5360
ISNS_ON:YES 1.82K2
VCCSAS0_CS_P
PLACE_NEAR=U4900.N10:5MM 1
44 45 48 49
PP3V3_S3 1
98 64
4.53K2
1
GND_SMC_AVSS
ISNS_ON:YES
Key VC0C SMC_ADC0
R5320 CPUVSENSE_IN
C
ISNS_ON:YES
SIGNAL_MODEL=EMPTY ISNS_ON:YES
EDP:6A
CPU Vcore Voltage Sense / Filter SMC 2
20% 6.3V 2 X5R 402
ISNS_ON:YES
1% 1/16W MF-LF 402
R5363
1
C5327 PLACE_NEAR=U4900.L12:5mm 0.22UF
Gain: 154x
1
44 45
OUT
CPU SA Current Sense / Filter
C5314 0.22UF
1% 1/16W MF-LF 402 2
98 64
XW5320 SM
1
44 45
Vi=Voltage across R7140=0.006V
PPVCORE_S0_CPU
SMC_CPUVCCIO_ISENSE
1% 1/16W MF-LF 402
R5326
1% 1/16W MF-LF 2 402
PLACE_NEAR=U4900.N9:5MM
1
GND_SMC_AVSS
68 14 12 7 6 101
4.53K2
RTHEVENIN = 4573 Ohms
PLACE_NEAR=U4900.N9:5MM
PDCINVSENS_EN_L_DIV
R5327
ISENSE_CPUVCCIO_IOUT 1
V-
CPUVCCIOISNS_R_N ISNS_ON:YES
7
ISNS_ON:YES
PLACE_NEAR=U4900.N9:5MM
P-CHANNEL
1% 1/16W MF-LF 402 2
DFN
6
SMC Key VD0R SMC_ADC9
27.4K S
100K
CPUVCCIOISNS_R_P5
THRM
1
DCIN_S5_VSENSE
R53111
98
SMC Key IC1C SMC_ADC7
PLACE_NEAR=U4900.L12:5mm
OPA2333
8
R5324
G
PPDCIN_G3H
CRITICAL U5310
ISNS_ON:YES
1% 1/16W MF-LF 402
100K
3
63 62 7 6
IN
R53121
D
ISNS_ON:YES GND_SMC_AVSS 44 45 48 49
CPU 1.05V VCCIO Current Sense / Filter
DCINVSENS_EN_L
1
0.22UF
20% 6.3V 2 X5R 402
4.02K2
R5323
S
C5308 PLACE_NEAR=U4900.N11:5mm
1
SIGNAL_MODEL=EMPTY ISNS_ON:YES
Vi=Voltage across R7640=0.02139V
G
44 45
R5307
44 45 48 49
SOT-963
62 45 44 63
OUT
1% 1/16W MF-LF 402
NTUD3169CZ
C
4
Gain: 3.75x
20% 6.3V 2 X5R 402
EDP:21.329A
D
SMC_GPU_ISENSE
1
CRITICAL Q5310 6
4.53K2
1
1% 1/16W MF-LF 402
GPUISENS_N
SIGNAL_MODEL=EMPTY
DC-In Voltage Sense Enable & Filter
Enables DC-In VSense divider when AC present.
98
C5304
GND_SMC_AVSS
N-CHANNEL
2
D
R5308
GPUVCORE_IOUT
V-
0.22UF
1% 1/16W MF-LF 402 2
PBUSVSENS_EN_L_DIV
OUT
1
9
PLACE_NEAR=U4900.L8:5MM
1
1% 1/16W MF-LF 402 2
V+
2
1% 1/16W MF-LF 402
RTHEVENIN = 4573 Ohms
PLACE_NEAR=U4900.L8:5MM
100K
ISNS_ON:YES
10K
ISNS_ON:YES
DFN
3
THRM
1
P-CHANNEL
R53011
GPUISENS_P
R5306
27.4K
1% 1/16W MF-LF 402 2
98
SMC Key IG0C SMC_ADC3
PLACE_NEAR=U4900.N11:5mm
OPA2333
8
2.87K2
1
1% 1/16W MF-LF 402
SMC Key VP0R SMC_ADC11
R53031
G
PPBUS_G3H
CRITICAL U5310
R5305
1% 1/16W MF-LF 402 2
S
20% 10V 2 CERM 402
ISNS_ON:YES
ISNS_ON:YES SIGNAL_MODEL=EMPTY
EDP:28A Vimon=31xVoltage across R8940=0.868V
100K
G
C5310 0.1UF
PBUSVSENS_EN_L
D
1
B
2
1% 1/16W MF-LF 402
44 45 48 49
SIGNAL_MODEL=EMPTY ISNS_ON:YES
AXG Vcore Voltage Sense / Filter 15 13 12 7 68
PPVCORE_S0_AXG
XW5330 SM 1
GFXVSENSE_IN
2
4.53K2 1 1% 1/16W MF-LF 402
PLACE_NEAR=U4900.N12:5MM
SMC_GFX_VSENSE
OUT
2
R5335 GPUVSENSE_IN
44 45 48 49
SMC_ADC2 SMC_GPU_VSENSE OUT 44
4.53K2 1 1% 1/16W MF-LF 402
PLACE_NEAR=R8940.1:5 MM
PLACE_NEAR=U4900.L10:5MM
DDR3 1.5V S3 Current Sense / Filter
IN
5.49K2
ISNS_1V5_S3_P
1
8 98
ISNS_1V5_S3_R_P
1% 1/16W MF-LF 402
45
V+
98 66
0.22UF
IN
ISNS_1V5_S3_N
5.49K2
1
THRM
20% 2 6.3V X5R 402
ISNS_ON:YES
R5375 1M
1% 1/16W MF-LF 2 402
44 45 48 49
6
5
4
1
1M
4.53K2
1
1% 1/16W MF-LF 402
ISNS_ON:YES
R5376 1
R5377
ISENSE_P1V5S3_IOUT
9
ISNS_1V5_S3_R_N
1% 1/16W MF-LF 402
7
2
SMC Key IM0C SMC_ADC6
PLACE_NEAR=U4900.N13:5mm
ISNS_ON:YES
V-
R5374
C5335
OPA2333 DFN
5
6
ISNS_ON:YES
7
CRITICAL U5360
ISNS_ON:YES
R5373 98 66
PLACE_NEAR=U4900.L10:5MM 1
GND_SMC_AVSS
8
ISNS_ON:NO
0.22UF
SMC Key VG0C 1
BOM OPTION
C5330
GPU Vcore Voltage Sense / Filter XW5335 SM
CRITICAL
20% 6.3V 2 X5R 402
EDP:18A
PPVCORE_GPU
REFERENCE DES C5308,C5327,C5367,C5377
RES, 0OHM, 0402
44 45
Vi=Voltage across R7350=0.006V=0.018V
81 74 7 6
DESCRIPTION
4
PLACE_NEAR=U4900.N12:5MM 1
GND_SMC_AVSS
A
QTY
116S0090
SMC_ADC4
R5330
PLACE_NEAR=R7550.2:5 MM
PART NUMBER SMC Key VN0R
SMC_P1V5S3_ISENSE OUT
SYNC_MASTER=K91_DINESH
SYNC_DATE=08/16/2010
PAGE TITLE 1
C5377 PLACE_NEAR=U4900.N13:5mm
Voltage & Load Side Current Sensing DRAWING NUMBER
0.22UF
20% 6.3V 2 X5R 402 ISNS_ON:YES
GND_SMC_AVSS
1% 1/16W MF-LF 402
44 45 48 49
Apple Inc.
ISNS_ON:YES SIGNAL_MODEL=EMPTY
3
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
Gain: 182x
4
44 45
2
BRANCH
PAGE
53 OF 132 SHEET
48 OF 101
1
A
8
7
6
5
4
3
2
1
COMPUTING High Side Current Sense / Filter SIGNAL_MODEL=EMPTY IMVPISNS_ENG
PP3V3_S0
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
1
C5401
2
20% 10V CERM 402
0.1UF
3
EDP Current:20.1A
69 68 67 66 64 7
PPVIN_S5_HS_COMPUTING_ISNS
OUT
D
4
0612 MF 1W 1%
Power Drop across R5400 at EDP becomes 1.21W
V+
SC70
IN-
HS_COMPUTING_IOUT 14.53K2
6
OUT
CRITICAL ISNS_HS_COMPUTING_P 4
98
0.003 1 CRITICAL
IN+
3
68 67
IN
5.23K2
1
C5403 0.22UF
PLACE_NEAR=R7530.3:5MM
2
2 X5R 402
68 67
GND_SMC_AVSS
IN
R5458 5.23K2
CPUIMVP_ISNS3_P 1
PLACE_NEAR=R7510.4:5MM
3
2
20% 10V CERM 402
V+
SMC Key IG0R SMC_ADC14
4 98
5
ISNS_HS_GPU_N
SC70
IN-
R5470
R5453
1
1
OUT
6
HS_GPU_IOUT
4
ISNS_HS_GPU_P
IN+
REF
SMC_GPU_HI_ISENSE
1% 1/16W MF-LF 402
1
3
PPBUS_G3H
Gain:200x
C
OUT
IN
PLACE_NEAR=U4900.M11:5MM
R5451 4.53K2
SMC_CPU_ISENSE
1
CPUIMVP_ISUM_IOUT
1% 1/16W MF-LF 402
V-
-
2
44 45
C5451
1
0.22UF
1
732K
OUT
PLACE_NEAR=U4900.M11:5MM
ISNS_ON:YES
20% 6.3V 2 X5R 402
GND_SMC_AVSS
R5455
R5454
D
IMVPISNS_ENG
OPA333DCKG4 SC70-5 4
IMVPISNS_ENG 1
44 45 48 49
732K 2 1% 1/16W MF-LF 402
1% 1/16W MF-LF 2 402
MF 402
Gain:140x
SIGNAL_MODEL=EMPTY
Scale: 28.55A / V Max VOut: 3.3V at 94.2A
R5472 5.23K2
CPUIMVP_ISNS3_N
1
0.5% SIGNAL_MODEL=EMPTY1/16W
44 45
SIGNAL_MODEL=EMPTY
MF 402
PLACE_NEAR=U4900.K9:5MM 1 C5413
Sense R is R7510, R7520 & R7530 Individual Sense R is 0.75mOhm
0.22UF 20% 6.3V
GND
CPUIMVP_ISNS2_N
PLACE_NEAR=R7530.4:5MM 68
14.53K2
IN
SMC Key IC0C SMC_ADC1
CPUIMVP_ISUM_R_N
IMVPISNS_ENG
5.23K2 1
5
+
3
1% 1/16W MF-LF 402
R5471
1
V+
3.48K2
0.5% SIGNAL_MODEL=EMPTY1/16W
R5413
CRITICAL 98
68
PLACE_NEAR=U4900.K9:5MM
INA210
2 X5R 402
2
0.003 1 CRITICAL
0.1UF
U5410
0612 MF 1W 1%
IN
1
C5411
CPUIMVP_ISUM_R_P
1% 1/16W MF-LF 402
IMVPISNS_ENG
MF 402
PPVIN_S5_HS_GPU_ISNS
R54102
39 35 8 7 6 88 63 62 49 48
CPUIMVP_ISNS1_N
PLACE_NEAR=R7520.4:5MM
EDP Current:4.9A OUT
3.48K2
CPUIMVP_ISNS_P 1
5.23K2 CPUIMVP_ISNS_N 0.5% SIGNAL_MODEL=EMPTY1/16W
IN
PP3V3_S0
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
86 81 7
68
U5450
R5452 98
MF 402
GRAPHICS High Side Current Sense / Filter
C5450
20% 2 10V CERM 402
IMVPISNS_ENG CRITICAL
IMVPISNS_ENG
0.5% SIGNAL_MODEL=EMPTY1/16W
44 45 48 49
PLACE_NEAR=U5450.5:3MM 1
0.1UF
0.5% 1/16W MF IMVPISNS_ENG 402
20% 6.3V
GND
IMVPISNS_ENG
PP3V3_S0
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 25 72
CPUIMVP_ISNS2_P 1
PLACE_NEAR=U4900.N8:5MM
PPBUS_G3H
IN
44 45
OUT
CPU VCore Load Side Current Sense / Filter
45 41 40 39 36 35 32 28 26 IMVPISNS_ENG 98 89 88 87 84 83 82 79 SIGNAL_MODEL=EMPTY
R5457
SMC_CPU_HI_ISENSE
1% 1/16W MF-LF 402
1
REF
Gain:50x 62 49 48 39 35 8 7 6 88 63
R5403
INA213
ISNS_HS_COMPUTING_N 5
R5456
PLACE_NEAR=R7510.3:5MM 5.23K2 68 67 IN CPUIMVP_ISNS1_P 1 0.5% 1/16W MF 402 PLACE_NEAR=R7520.3:5MM
PLACE_NEAR=U4900.N8:5MM
U5400
R5400 2 98
SMC Key IC0R SMC_ADC13
EDP: 94A
GND_SMC_AVSS 44
TDP :45A
(Effective Sense R is 0.25mOhm due to summing of the 3 phases)
C
45 48 49
OTHER High Side Current Sense / Filter 71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
PP3V3_S0
65 7
OUT
3
EDP Current:12.546A
PPVIN_S5_HS_OTHER_ISNS
1
C5431
2
20% 10V CERM 402
V+
R5430 0612 2
4 98
MF 1W 1%
SMC Key IO0R SMC_ADC15
0.1UF
SC70
1 3
ISNS_HS_OTHER_P 4
OUT
IN+
6
HS_OTHER_IOUT
REF
SMC_OTHER_HI_ISENSE
1% 1/16W MF-LF 402
1
CRITICAL
1
PPBUS_G3H
Gain:50x
IMVPISNS_ENG
C5433
PLACE_NEAR=R7550.3:5MM
0.22UF 98 68
R5466
CHARGER BMON High Side (BATTERY DISCHARGE) Current Sense, MUX & Filter
3
CRITICAL
98 63
98 63
IN
IN
CHGR_CSO_R_P
5 IN-
CHGR_CSO_R_N
4 IN+
Battery side
C5420
OUT
BMON:ENG REF (100V/V)
20% 10V CERM 2 402
U5421
NC7SB3157P6XG
1
VCC 5
IN
2
ISNS_ON:YES IMVPISNS_ENG
732K 2 1% 1/16W MF-LF 402
SMC_GFX_ISENSE
OUT
44 45
PLACE_NEAR=U4900.M13:5MM 1
C5461 0.22UF
20% 6.3V 2 X5R 402
GND_SMC_AVSS
R5465 1
IMVPISNS_ENG
1% 1/16W MF-LF 402
B
44 45 48 49
Gain:133.33x
SIGNAL_MODEL=EMPTY
Scale: 10A / V Max VOut: 3.3V at 33A
1
R5464 732K
1% 1/16W MF-LF 2 402
SIGNAL_MODEL=EMPTY
44 45
PLACE_NEAR=U4900.M9:5MM
R5422
2
3
4 B0
145.3K2
BMON_AMUX_OUT
A
VER 1
1% 1/16W MF-LF 402
BMON:ENG 1
BMON:PROD
R5420 2
0
1
5% PLACE_NEAR=U5421.1:5MM
For engineering, Bmon=6.6A*100*R7050=3.3V
SMC_BMON_MUX_SEL
0
Gain:100x IN
SEL 6
2 GND
CHGR_BMON
From charger
MF-LF 402
PLACE_NEAR=U4900.M13:5MM
R5461
4CPUIMVP_ISUMG_IOUT 14.53K2
1
GND
Sense R is R7050, 5mOhm NOTE: Monitoring current from battery to PBUS (battery discharge)
63
SC70
1 B1
BMON_INA_OUT
6
MF-LF 402
SMC Key IB0R SMC_ADC12 ISL6259 Gain: 36x
BMON:ENG
0.1uF
R5463
Sense R is R7550, 0.75mOhm EDP: 33A TDP: 21.5A
CRITICAL
C5421 1
20% 10V 2 CERM 402
INA214 SC70
1
0.1uF
U5420
EDP Current:6.6A
BMON:ENG BMON:ENG
R5467
IMVPISNS_ENG
OPA333DCKG4 SC70-5
V-
3 -
IMVPISNS_ENG
CPUIMVP_ISNS1G_N 1 0 2 CPUIMVP_ISNS1G_R_N 15.49K2 CPUIMVP_ISUMG_R_N 5% 1% SIGNAL_MODEL=EMPTY1/16W 1/16W
PP3V3_S3
V+
Charger/Load side
IN
5
+
V+
MF-LF 402
IMVPISNS_ENG 98 68
CPUIMVP_ISUMG_R_P 1
SMC Key IN0R SMC_ADC5
20% 10V CERM 402
U5460
R5462
MF-LF 402
PLACE_NEAR=R7550.4:5MM
32 31 30 29 25 24 19 18 8 7 6 87 72 71 54 53 48 47
IMVPISNS_ENG
CPUIMVP_ISNS1G_P 1 0 2 CPUIMVP_ISNS1G_R_P 15.49K2 5% 1% SIGNAL_MODEL=EMPTY1/16W 1/16W
IN
GND_SMC_AVSS
B
IMVPISNS_ENG 2 CRITICAL
44 45
20% 6.3V 2 X5R 402
2
IN
PLACE_NEAR=U5460.5:3MM
C5460 0.1UF
OUT
PLACE_NEAR=U4900.L7:5MM
GND 48 39 35 8 7 6 88 63 62 49
IMVPISNS_ENG 1
4.53K2 1
CRITICAL
0.005
PP3V3_S0
R5433
INA213 IN-
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
PLACE_NEAR=U4900.L7:5MM
U5430 ISNS_HS_OTHER_N 5
GFX/IG VCore Load Side Current Sense / Filter
R5423 100K
5% 1/16W MF-LF 2402
OUT
44 45
QTY 2
116S0090
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
C5451,C5461
RES, 0OHM, 0402
ISNS_ON:NO
1 C5422
0.022UF
10% PLACE_NEAR=U4900.M9:5MM 16V 2 CERM-X5R 402
GND_SMC_AVSS
1/16W MF-LF 402
For engineering, stuff BMON_ENG For production, stuff BMON_PROD
PART NUMBER SMC_BMON_ISENSE
44 45 48 49
RC values chosen per K17 Radar 7337775
For Production, Bmon=36*18.33A*R7050=3.3V
A
SYNC_MASTER=K91_DINESH
EDP Current:4.6A 63
IN
PLACE_NEAR=U4900.K10:5MM
CHGR_AMON
R5441 4.53K2 1 1% 1/16W MF-LF 402
High Side and CPU/AXG Current Sensing
SMC Key ID0R SMC_ADC10
SMC_DCIN_ISENSE
OUT
DRAWING NUMBER
Apple Inc.
44 45
NOTICE OF PROPRIETARY PROPERTY:
C5441
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
0.22UF
20% 2 6.3V X5R 402
GND_SMC_AVSS
8
7
SIZE
D REVISION
R
PLACE_NEAR=U4900.K10:5MM 1
SYNC_DATE=10/29/2010
PAGE TITLE
DC-IN (AMON) Current Sense Filter
44 45 48 49
6
5
4
3
2
BRANCH
PAGE
54 OF 132 SHEET
49 OF 101
1
A
8
7
6
5
4
3
2
1
GPU Proximity/GPU Die/Left Heat Pipe/Right Fin Stack R5550 71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
PP3V3_S0
PP3V3_S0_GPUTHMSNS_R
2
MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
5% 1/16W MF-LF 402 98 78
D
47
1
GPU_TDIODE_P
BI
Detect GPU Die Temperature
C5550 0.1uF 20% 10V R55511 2 CERM 1
PLACE_NEAR=U5550.2:5mm PLACE_NEAR=U5550.3:5mm
C5551
1
U5550
0.0022uF
98 78
Q5501
BC846BMXXH
98
CRITICAL 3
1
Placement note:
GPUTHMSNS_D_P
2
SOT732-3
SIGNAL_MODEL=EMPTY
Q5503
C5552
1
2 98
D
THERM*/ADDR
7
GPUTHMSNS_THM_L
3 DN1
ALERT*
8
GPUTHMSNS_ALERT_L
CRITICAL 4 DP2/DN3 SMDATA
9
SMBUS_SMC_0_S0_SDA
BI
6 31 44 47 79 96
5 DN2/DP3
10
SMBUS_SMC_0_S0_SCL
BI
6 31 44 47 79 96
SMCLK GND 6
1
10% 50V CERM 2 402
SOT732-3
3
5% 1/16W MF-LF
2 402
2 DP1
0.0022uF
BC846BMXXH
Place Q5501 on bottom side close to the right fin stack
10K
MSOP
GPU_TDIODE_N
BI
R5552
EMC1414-A
10% 50V CERM 2 402
Detect Right Fin Stack Temperature CRITICAL
5% 1/16W MF-LF 402 2
1 VDD
SIGNAL_MODEL=EMPTY
1
10K
402
Placement note:
GPUTHMSNS_D_N
Place U5550 on bottom side under GPU PLACE_NEAR=U5550.4:5mm PLACE_NEAR=U5550.5:5mm
Detect Left Heat Pipe Temperature
Placement note: Write Address: 0x98 Read Address: 0x99
Place Q5503 on top side under left heat pipe near GPU
CPU Proximity/CPU Die/PCH Proximity/LVDS Connector Proximity R5570
C
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
PP3V3_S0
47
1
2
5% 1/16W MF-LF 402
C
PP3V3_S0_CPUTHMSNS_R MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
1 1 VDD
2 CERM 402
U5570 98 9
C5571 CPU_THERMD_N
BI
Detect LVDS Connector Proximity Temperature CRITICAL 2
CRITICAL
SOT732-3
CPUTHMSNS_THM_L
3 DN1
CPUTHMSNS_ALERT_L
R5572 10K
5% 1/16W MF-LF
2 402
Note: EMC1414 can perform Beta Compensation for External Diode 1 only
ALERT*
8 9
SMBUS_SMC_B_S0_SDA
BI
44 47 50 96
5 DN2/DP3
10
SMBUS_SMC_B_S0_SCL
BI
44 47 50 96
SMCLK
Placement note: Place U5570 under CPU
0.0022uF
1
10% 50V CERM 2 402
2 98
Write Address: 0x98 Read Address: 0x99
CPUTHMSNS_D2_N
Detect PCH Proximity Temperature
B
7
1
C5590 1
SOT732-3
3
THERM*/ADDR
SIGNAL_MODEL=EMPTY
BC846BMXXH
Place Q5502 on bottom side close to the LVDS Connector
2 DP1
CPUTHMSNS_D2_P
3
Q5504
1
Placement note:
5% 1/16W MF-LF 402 2
GND 6
98
Q5502
10K
CRITICAL 4 DP2/DN3 SMDATA
1
0.0022uF
10% 50V CERM 2 402
BC846BMXXH
MSOP
SIGNAL_MODEL=EMPTY
Detect CPU Die Temperature
98 9
EMC1414-A
PLACE_NEAR=U5570.2:5mm PLACE_NEAR=U5570.3:5mm
CPU_THERMD_P
BI
C5570 0.1uF R55711 20% 10V
PLACE_NEAR=U5570.4:5mm PLACE_NEAR=U5570.5:5mm
B
Placement note: Place Q5504 under PCH
T29 Proximity 71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
PP3V3_S0 1
PLACE_NEAR=U3600 PLACE_SIDE=BOTTOM
V+
T29 Die
C5520 0.1uF
C1 2
U5520
20% 10V CERM 402
TMP105 WCSP-6
50 33
BI
T29_THERMD_P
50 33
T29_THERMD_P
96 50 47 44
MAKE_BASE=TRUE
BI
NOSTUFF 96 50 47 44
BI
SMBUS_SMC_B_S0_SDA SMBUS_SMC_B_S0_SCL
A1 B1
SDA
A0
CRITICAL SCL
ALERT
C2 B2
NC
1
R5520
PLACE_SIDE=BOTTOM
A
2
GNDS
5% 1/16W MF-LF
A2
2 402
PLACE_NEAR=U3600.B1:2mm
1
10K
SYNC_MASTER=K91_DINESH
SYNC_DATE=09/22/2010
PAGE TITLE
T29_THERMD_N
XW5520
Thermal Sensors
Placement note:
SM
DRAWING NUMBER
Place U5520 close to T29 router on BOTTOM side
Apple Inc.
Use GND pin B1 on U3600 for N leg
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
7
6
5
4
D
R
Write Address: 0x90 Read Address: 0x91
8
SIZE
REVISION
3
2
BRANCH
PAGE
55 OF 132 SHEET
50 OF 101
1
A
8
7
6
5
4
3
2
1
D
D
C
Left Fan 72 71 69 68 67 64 53 51 46 41 22 8 7 6 101 88 86 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 84 83 82 79 72 71 61 60 56 98 89 88 87
PP5V_S0 PP3V3_S0 CRITICAL 1
R5650 47K
5% 1/16W MF-LF 402 2
R5655 44
OUT
SMC_FAN_0_TACH
1
47K
2
6
FAN_LT_TACH
5% 1/16W MF-LF 402
R56511 5% 1/16W MF-LF 402 2
44
IN
SMC_FAN_0_CTL
72 71 69 68 67 64 53 51 46 41 22 8 7 6 101 88 86 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 84 83 82 79 72 71 61 60 56 98 89 88 87
PP5V_S0 PP3V3_S0
5
1
R5660
78171-0004 M-RT-SM 5
47K
2N7002DW-X-G D
SOT-363 3 6 FAN_LT_PWM
5% 1/16W MF-LF 402 2
R5665
1 2 3 4
44
OUT
SMC_FAN_1_TACH
1
47K
2
6
FAN_RT_TACH
5% 1/16W MF-LF 402
R56611 5% 1/16W MF-LF 402 2
518S0369 44
IN
SMC_FAN_1_CTL
J5660 78171-0004 M-RT-SM 5 1 2 3 4 6
100K
Q5660
G
4 S
CRITICAL
J5650
6
100K
C
Right Fan
2
Q5660 2N7002DW-X-G
G
SOT-363 1 S
D 6
6
518S0369
FAN_RT_PWM
B
B
A
SYNC_MASTER=K18_MLB
SYNC_DATE=04/27/2010
PAGE TITLE
Fan Connectors DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
56 OF 132 SHEET
51 OF 101
1
A
8
7
6
5
PSOC USB CONTROLLER -
R5704
D
0
2
BYPASS=U5701.49:50:11 mm BYPASS=U5701.49:50:8 mm BYPASS=U5701.49:50:5 mm
PP3V3_S4_PSOC
1
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V
5% 1/16W MF-LF 402
1
R5703
53 6 53 6 53 6 53 6
6 6 8 6
337S2983
TP_PSOC_SCL TP_PSOC_SDA NC_PSOC_P1_3 TP_ISSP_SCLK_P1_1 ISSP SCLK/I2C SCL 1
24
98
P2_2 P2_0 P4_6 P4_4 P4_2 P4_0 P3_6 P3_4 P3_2 P3_0 P5_6 P5_4 P5_2 P5_0 THRML PAD
42 41 40 39 38 37 36 35 34 33 32 31 30 29
1
24
36E-3 W 0.72E-3 W
PSOC
VDD
8MA (TYP) 1.5 OHM 14MA (MAX)
0.012 0.021
V V
96E-6 W 294E-6 W
18V BOOSTER
VIN
4MA (MAX) 4.7 OHM
0.0188 V
75.2E-6 W
71 53 52 45 7 62 52 47 46 45 44 42 25 7 6 72 63
USB_TPAD_R_N
5% 1/16W MF-LF 402
PP3V3_S4 PP3V42_G3H
NC
C5702
30
D
29
WS_KBD1 WS_KBD2 6 WS_KBD3 6 WS_KBD4 6 WS_KBD5 6 WS_KBD6 6 WS_KBD7 6 WS_KBD8 6 WS_KBD9 6 WS_KBD10 6 WS_KBD11 6 WS_KBD12 6 WS_KBD13 6 WS_KBD14 6 6 WS_KBD15_CAP 6 WS_KBD16_NUM WS_KBD17 6 WS_KBD18 6 WS_KBD19 6 WS_KBD20 6 WS_KBD21 6 WS_KBD22 6 WS_KBD23 6 6 WS_KBD_ONOFF_L
28
52 6
52 52 52
52 6 52 52 6 52 52 6 52
R5714
6 52 6 52
52
WS_KBD15_C
1
470
2
6 52
52
WS_KBD16N
1
10K
52
2
52
52 52 52
1% 1/16W MF-LF 402
52
52 52
1% 1/16W MF-LF 402
6 52
52
52 52
6 52
R5710
6 52 6 52 45 44 6
OUT
6 52
SMC_ONOFF_L
C5710
6 52
1
0.1UF
6 52
1K
1
2
6 52 6 52
52
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4
5% 1/16W MF-LF 402
52 6 52 6
20% 10V CERM 2 402
6 52
52
27
52 6
WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD
3
1
PLACEMENT_NOTE=NEAR J5713
NC
6 52
C
2
31 F-RT-SM
6 52
J5713 CRITICAL
1
100PF
5% 2 50V CERM 402
32
FF14-30A-R11B-B-3H
Z2_CLKIN TP_P7_7
1 98
V V
52
518S0637
6 52 6 52 6 52 6 8
SMC Manual Reset & Isolation
6 53 6
Left shift, option & control keys combined with power button cause SMC RESET# assertion.
(PP3V3_S4_PSOC)
2
0.6 0.012
57
USB_TPAD_R_P
R5702 USB_TPAD_N
10 OHM 60MA (MAX) 60MA (MAX) 0.2 OHM
4.7UF
WS_KBD17 WS_KBD16N WS_KBD15_C WS_KBD14 WS_KBD13 WS_KBD12 WS_KBD11 WS_KBD10 WS_KBD9 WS_KBD8 WS_KBD7 WS_KBD1 WS_KBD2 WS_KBD3
5% 1/16W MF-LF 402
92 24
VDD VOUT
20% 2 6.3V X5R 603
WS_KBD4 WS_KBD5 WS_KBD6 TP_ISSP_SDATA_P1_0 ISSP SDATA/I2C SDA 2
3V3 LDO
Keyboard Connector
0.255E-6 W 16.32E-6 W
R5715
R5701 USB_TPAD_P
92 24
2.55 KOHM 0.0255 V 0.204 V
43
44
45
47
49
50
48
51
52
53
55
(SYM-VER2)
P7_7 24 P7_0 25 P1_0 26 P1_2 27 P1_4 28 P1_6
53 6
POWER
10UA 80UA
1
23
53 6
MLF
22 VDD
53 6
CY8C24794
21 D-
53 6
U5701
19 VSS
53 6
CRITICAL OMIT
20 D+
53 6
6
NC
TPAD_VBUS_EN Z2_DEBUG3 Z2_RESET PSOC_MISO PSOC_F_CS_L PSOC_MOSI PSOC_SCLK Z2_MISO Z2_CS_L Z2_MOSI Z2_SCLK
IN
P2_3 2 P2_1 3 P4_7 4 P4_5 5 P4_3 6 P4_1 7 P3_7 8 P3_5 9 P3_3 10 P3_1 11 P5_7 12 P5_5 13 P5_3 14 P5_1
18 P1_1
53 6
1
15 P1_7
WS_CONTROL_KEY Z2_KEY_ACT_L
52
P2_5 P2_7 P0_1 P0_3 P0_5 P0_7 VSS VDD P0_6 P0_4 P0_2 P0_0 P2_6 P2_4
56
52
V_SNS
V+
C5706
WS_KBD23 WS_KBD22 WS_KBD21 WS_KBD20 WS_KBD19 WS_KBD18 54
52
R_SNS
TMP102
52
17 P1_3
53 6
CURRENT
2
52
16 P1_5
52
1
10% 16V 2 X7R-CERM 402
SMC_PME_S4_WAKE_L PICKB_L BUTTON_DISABLE Z2_HOST_INTN WS_LEFT_SHIFT_KEY WS_LEFT_OPTION_KEY
OUT 53 6
C
C5705 0.1UF
5% 2 50V CERM 402
5% 1/16W MF-LF 2 402
72
1
100PF
1
220K
45 44
C5704
PIN NAME
3
C5703 0.1UF
10% 16V 2 X7R-CERM 402
1
Keys ANDed with PSOC power to isolate when PSOC is not powered.
C5701 4.7UF
62 52 47 46 45 44 42 25 7 6 72 63
20% 2 6.3V X5R 603
71 53 52 45 7
BYPASS=U5701.22:19:5 mm BYPASS=U5701.22:19:8 mm BYPASS=U5701.22:19:11
PP3V42_G3H
PP3V3_S4
CRITICAL
mm
1
VDD
10% 16V 2 X7R-CERM 402
0.1UF
U5750
B
C5750
1
PP3V3_S4
IC
USB INTERFACES TO MLB SPI HOST TO Z2 TRACKPAD PICK BUTTONS KEYBOARD SCANNER
46
71 53 52 45 7
4
B
SLG4AP006 52 6
WS_LEFT_SHIFT_KBD
2 IN_A1
TDFN
(IPD)
3 IN_A2
OUT_A 4
WS_LEFT_SHIFT_KEY
52
OUT_B 8
WS_LEFT_OPTION_KEY
52
(IPD)
TPAD Buttons Disable
7 IN_A3_B2 (IPD)
52 6
BUTTON_DISABLE
(IPD)
D 6
PLACE THESE COMPONENTS CLOSE TO J5800 THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
THRM PAD
GND
9
CRITICAL
Q5701
6 IN_B1
5
52
WS_LEFT_OPTION_KBD
SSM6N15FEAPE SOT563
62 45 44
IN
SMC_LID
S 1
THE TPAD BUTTONS WILL BE DISABLE WHEN THE LID IS CLOSED LID OPEN => SMC_LID_LC ~ 3.42V LID CLOSE => SMC_LID_LC < 0.50V
Pull-up in U5010. SMC_TPAD_RST_L CRITICAL
C5755
1
2 G
1
VDD
10% 16V 2 X7R-CERM 402
0.1UF
U5755
OUT
45
CRITICAL
Q5701
D 3
SSM6N15FEAPE SOT563
SLG4AP006 2 IN_A1
TDFN 5 G
(IPD)
3 IN_A2
OUT_A 4
SMC_TPAD_RST
OUT_B 8
WS_CONTROL_KEY
S 4
(IPD)
A
52 6
WS_CONTROL_KBD
7 IN_A3_B2 (IPD)
6 IN_B1
SYNC_MASTER=K91_ERIC 52
WELLSPRING 1
THRM PAD
DRAWING NUMBER
9
5
GND
SYNC_DATE=10/08/2010
PAGE TITLE
(IPD)
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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52 OF 101
1
A
8
7
6
5
4
3
2
1
BOOSTER +18.5VDC FOR SENSORS
D
D
BOOSTER DESIGN CONSIDERATION: - POWER CONSUMPTION - DROOP LINE REGULATION - RIPPLE TO MEET ERS - 100-300 KHZ CLEAN SPECTRUM - STARTUP TIME LESS THAN 2MS - R5812,R5813,C5818 MODIFIED CRITICAL
CRITICAL
L5801
D5802 SOD-323
3.3UH-870MA PP5V_S4_P18V5S5 PP5V_S5
R5805 2
0
P18V5S4_SW
2
1
PP18V5_S4_R
2
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM SWITCH_NODE=TRUE B0520WSXG
VLF3010AT-SM-HF
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=5V
C5818
1
R5812
FB
52 6
C5819
2.2UF
C
402
10%
THRML
16V 2 X5R
PAD 9
603
25V 2 X5R
1
R5813
6 53
603-1
1
C5815
52 6
1000PF
52 6
5% 2 25V NP0-C0G 402
53 6
VOLTAGE=3.3V 52 6 MIN_NECK_WIDT=0.20MM MIN_LINE_WIDTH=0.50MM
71.5K
SW
1% 1/16W MF-LF 2 402
1
R5811
8
100K
GND
10%
16V X7R-CERM 2
Z2_BOOST_EN
5
CRITICAL
C5817
PGND
0.1UF
1
CTRL
1% 1/16W MF-LF 2 402
6
1
1
1UF 10%
QFN DO
7
C5816
3
J5800 PP3V3_S4
71 52 45 7
52 6
TPS61045 NC
CRITICAL
52 6
1% 1/16W MF-LF 2 402
P18V5S4_FB
4
2
1M
5% 50V CERM 2 402
U5805
L
0
IPD Flex Connector
PP18V5_S4 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=18.5V
5% 1/16W MF-LF 402
1 1
39PF
VIN
1
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=18.5V
PP5V_S5_P18V5S5_VIN
1
5% 1/16W MF-LF 402
2
71 65 7 6
1
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=5V
R5806
R5800 32 31 30 29 25 24 19 18 8 7 6 87 72 71 54 49 48 47
PP3V3_S3
1
0
52 6
55560-0228
PP18V5_S4
M-ST-SM
Z2_CS_L Z2_DEBUG3 Z2_MOSI Z2_MISO Z2_SCLK Z2_BOOST_EN Z2_HOST_INTN PP3V3_S3_TPAD Z2_CLKIN
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
6 53
Z2_KEY_ACT_L 6 52 Z2_RESET 6 52 PSOC_F_CS_L 6 52 PICKB_L 6 52 PSOC_MISO 6 52 PSOC_MOSI 6 52 PSOC_SCLK 6 52 SMBUS_SMC_A_S3_SDA 6 SMBUS_SMC_A_S3_SCL 6
31 44 47 54 96 31 44 47 54 96
C
2
5% 1/16W MF-LF 402
NO STUFF
516S0689
Keyboard Backlight Driver & Detection 86 72 71 69 68 67 64 51 46 41 22 8 7 6 101 88
PP5V_S0
CRITICAL KB_BL
Keyboard Backlight Connector
L5850
B PP3V3_S0
470K
1UF
5% 1/16W MF-LF 402 2 BI
SMC_SYS_KBDLED 1
If LOW, keyboard backlight present If HIGH, keyboard backlight not present
5% 1/16W MF-LF 2 402
R5853 always stuffed, R5854 only grounded when KB BL flex connected.
R5854 4.7K
LED 5
6
KB_BL
KB_BL
5% 1/16W MF-LF 402 2
KBDLED_ANODE
4
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
R5855
U5850
NO STUFF
10
518S0691
1% 1/16W MF-LF 2 402
KBDLED_CAP
CAP 4
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
THRML GND
PAD
J5815 pin 1 is grounded on keyboard backlight flex
1
DFN
10K
1
3
CRITICAL
LT3491
R58521
SMC_KDBLED_PRESENT_L
2
SW 3
6 CTRL
KB_BL
To detect Keyboard backlight, SMC will tristate and read SMC_SYS_KBDLED:
F-RT-SM 6
10V 2 X5R 402-1
FF18-4A-R11AD-B-3H
VIN
10%
7
44
1
J5815
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.25 MM SWITCH_NODE=TRUE
1098AS-SM
KB_BL
C5850
B
CRITICAL KB_BL
1
R58531
2
72 71 61 60 56 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79
10UH-0.58A-0.35OHM 1 2 KBDLED_SW
KB_BL 1
C5855 1UF
10% 35V 2 X5R 603
(SMC_KBDLED_PRESENT_L)
A
SYNC_MASTER=K91_ERIC
SYNC_DATE=07/14/2010
PAGE TITLE
WELLSPRING 2 DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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8
7
6
5
4
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1
D
D
PP3V3_S3
BYPASS=U5920.14:13:8 mm 1
10UF
C
20% 6.3V X5R 2 603
1
C5922 0.1UF
VDD
10% 6.3V 2 X5R 201
BYPASS=U5920.14:13:8 mm
R59241
NC NC
10K
OUT
2 3 NC
SMS_INT_L TP_SMS_INT2
R59201 R59251
VDD_IO
U5920 LIS331DLH
LGA 10 15 RESERVED
5% 1/20W MF 201 2 45 44
CRITICAL 1
C5926
14
32 31 30 29 25 24 19 18 8 7 6 87 72 71 53 49 48 47
11 INT1 9 INT2
CS 8
SDO 7 SDA/SDI/SDO 6 SCL/SPC 4
10K
10K
5% 1/20W MF 201 2
5% 1/20W MF 201 2
SMS_I2C_SEL
R59211
PLACEMENT_NOTE=See schematic for orientation.
Desired orientation when placed on board bottom-side (view thru top):
10K 5% 1/20W MF 201 2
0
2
SMBUS_SMC_A_S3_SDABI
6 31 44 47 53 96
5% 1/20W MF 201
SMS_ADDR_SELECT I2C_SMC_SMS_SDA_R I2C_SMC_SMS_SCL_R
338S0687
C
R5923 1
GND 5 12 13 16
NOSTUFF
R5922 1
0
2
SMBUS_SMC_A_S3_SCLIN
6 31 44 47 53 96
5% 1/20W MF 201
SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd) SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd) NOTE: SDA and SCL have internal pull-ups to VDD_IO.
+Y Front of system
+X +Z (dn)
B
B
Circle indicates pin 1 location when placed in correct orientation
A
SYNC_MASTER=K91_DINESH
SYNC_DATE=08/06/2010
PAGE TITLE
Digital Accelerometer DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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8
7
6
5
4
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1
D
D
C
C PP3V3_S5
1
R6101 3.3K
5% 1/16W MF-LF 2 402 46
IN
CRITICAL VDD 8
29 25 24 23 22 20 19 17 7 6 98 89 85 82 72 71 70 65 45 39
C6100 1 0.1UF
20% 10V CERM 2 402
U6100 64MBIT
SPI_MLB_CLK
6
SCK
SOIC
SI
5
SPI_MLB_MOSI
IN
46
SO
2
SPI_MLB_MISO
OUT
46
SST25VF064C
46 19 6
IN
IN
SPI_MLB_CS_L SPI_WP_L SPIROM_USE_MLB
NOTE: If HOLD* is asserted ROM will ignore SPI cycles.
1 3 7
CE* WP* HOLD*
OMIT
VSS 4
46
B
B
A
SYNC_MASTER=K91_BEN
SYNC_DATE=06/08/2010
PAGE TITLE
SPI ROM DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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8
7
6
5
4
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1
AUDIO CODEC APPLE P/N 353S3199
CRITICAL
L6201
FERR-220-OHM 70 41 25 22 20 16 7
1
PP1V5_S0
IN
PP5V_S0_AUDIO 8
2 0402
VOLTAGE=1.5V MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM
CRITICAL
C6210
1
1
4.7UF 20% 4V X5R-1 402
C6211
PP3V3_S0
0.1UF
10% 16V 2 X5R 402-1
2
C6216
1
1
1
C6220
MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM
59
OUT
AUD_GPIO_3
14 15
VD VA_REF VA_HP VA VBIAS_DAC CRITICAL HPOUT_L VHP_FILT+ HPOUT_R VHP_FILTCS4206B HPREF QFN GPIO0/DMIC_SDA1 LINEOUT_L1+ GPIO1/DMIC_SDA2 LINEOUT_L1/SPDIF_OUT2 GPIO2 LINEOUT_R1+ GPIO3 LINEOUT_R1-
61
IN
AUD_SENSE_A
13
SENSE_A
45 43 42
FLYP FLYC FLYN
10UF
1
R6210
10UF
20% 6.3V X5R 603
2.67K
2
1% 1/16W MF-LF MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM 2 402
2
VBIAS_DAC CS4206_FP CS4206_FN
29 44 41
MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM
AUD_DMIC_SDA1
2 12
MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM
CS4206_FLYP CS4206_FLYC CRITICAL
CRITICAL
C6222
1
1
2
2
C6223
2.2UF 20% 6.3V CERM 402-LF
2.2UF 20% 6.3V CERM 402-LF
CS4206_FLYN MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM
IN
HDA_BIT_CLK
93 16
IN
HDA_SYNC
93 16
OUT
HDA_SDIN0
R6211
93 16
IN
93 16
IN
60
IN
1
HDA_SDOUT HDA_RST_L AUD_SPDIF_IN
39
2
AUD_SDI_R
1
VL_IF
6
BITCLK
1
0.1UF
C6213
20% 6.3V 2 X5R 603
GND_AUDIO_HPAMP 56 58 60 GND_AUDIO_CODEC 56 57 61
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
AUD_HP_PORT_L AUD_HP_PORT_R AUD_HP_PORT_REF
28
LINEIN_L+ LINEIN_CLINEIN_R+
22
MICIN_L+ MICIN_LMICIN_R+ MICIN_R-
18 17 19 20
VREF+_ADC
27
OUT
58
OUT
58
IN
60
TP_AUD_LO1_L_P NC 6 TP_AUD_LO1_L_N NC 6 AUD_LO1_R_P OUT 59 AUD_LO1_R_N OUT 59
35 34 36 37
VCOM
D
10UF
10% 16V 2 X5R 402-1
39
16
SPDIF_IN SPDIF_OUT
2
DMIC_SCL
5% 1/16W MF-LF 402
AUD_LO2_L_P AUD_LO2_L_N AUD_LO2_R_P AUD_LO2_R_N AUD_CODEC_MICBIAS
98 98
OUT
59 98
OUT
59 98
OUT
59 98
OUT
59 98
OUT
61
CS4206_VCOM MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM
AUD_LI_P_L AUD_LI_REF AUD_LI_P_R
21 23
AUD_MIC_INP_L AUD_MIC_INN_L AUD_MIC_INP_R AUD_MIC_INN_R
IN
57
IN
57
IN
57
IN
61
IN
61
IN
61
IN
61
C
CS4206_VREF_ADC NC MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM
AUD_DMIC_CLK
4
60
7
DGND THRM_PAD AGND
CRITICAL
CRITICAL
C6224 1
1
1UF
C6225 10UF
10% 20V TANT 2 CASE-P3-HF
61 57 56
10% 16V 2 X5R 402-1
MIN_NECK_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM
MICBIAS
RESET*
47 48
AUD_SPDIF_OUT_CHIP
2
MIN_LINE_WIDTH=0.30MM MIN_LINE_WIDTH=0.30MM
31 30 32 33
SDI SDO
11
39
C6217
1
SYNC
8 5
5% 1/16W MF-LF 402
AUD_SPDIF_OUT
OUT
VL_HD
10 93
R6212 60
3
10% 1CRITICAL10V X5R 402-1 10UF 20% 2 16V TANT-POLY 2012-LLP
56
CRITICAL
C6215 1 C6214 1 0.1UF
38 40
LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+ LINEOUT_R2-
26
93 16
U6201
49
6
20% 6.3V X5R 603
NC TP_AUD_GPIO_1 NC TP_AUD_GPIO_2
60 6
C
10% 16V 2 X5R 402-1
25
CRITICAL
C6221
46
CRITICAL
0.1UF
24
IN
C6218 1
20% 16V TANT-POLY 2 2012-LLP 9
56
GND_AUDIO_HPAMP PP4V5_AUDIO_ANALOG
1
1UF
10UF
60 58 56
48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98
PP4V5_AUDIO_ANALOG IN
CRITICAL
CRITICAL
C6219
D
56
PP1V5_S0_AUDIO_DIG
20% 2 16V POLY-TANT CASE-B2-SM
1
R6213 100K
5% 1/16W MF-LF 2 402
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V
GND_AUDIO_CODEC
B
B GND_AUDIO_HPAMP
60 58 56
4.5V POWER SUPPLY FOR CODEC APPLE P/N 353S2234 CRITICAL
L6200
56 8
IN
PP5V_S0_AUDIO
CRITICAL
U6200
MIN_LINE_WIDTH=0.40MM
FERR-220-OHM MIN_NECK_WIDTH=0.20MM VOLTAGE=5V 1 2 4V5_REG_IN
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM VOLTAGE=4.5V
NOTES ON CODEC I/O
MAX8840-4.5V 1 IN
UDFN
PP4V5_AUDIO_ANALOG
OUT 6
DIFF FSINPUT= 2.45VRMS SE FSINPUT= 1.22VRMS DAC1 FSOUTPUT= 1.34VRMS DAC2/3 FSOUTPUTDIFF= 2.67VRMS DAC2/3 FSOUTPUTSE= 1.34VRMS
56
OUT
0402
R6200 IN
PP3V3_S0
4V5_REG_EN
2.21K2
1
1% 1/16W MF-LF 402
BP 4 4V5_NR
3 SHDN* GND
1
C6200
CRITICAL
1UF
10% 10V 2 X5R 402-1
1
C6201 1UF
XW6200 SM 1
NC 5
2
98 89 60 56 53 51 50 49 48 47 45 23 22 20 19 18 17 16 12 7 6 41 40 39 36 35 32 28 26 25 88 87 84 83 82 79 72 71 61
CRITICAL
C6202
1
0.1UF 1
10% 2 10V X5R 402-1
MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM 10% 16V X7R-CERM 402
10% 2 10V X5R 402-1
C6203 1UF
2
GND_AUDIO_CODEC
2
56 57 61
VOLTAGE=0V
NOSTUFF
R6201
A
1
0
2
SYNC_MASTER=K91_AUDIO
5% 1/16W MF-LF 402
AUDIO: CODEC/REGULATOR
XW6201 SM 1
SYNC_DATE=09/30/2010
PAGE TITLE
2
DRAWING NUMBER
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=0V
GND_AUDIO_HPAMP
Apple Inc. 56 58 60
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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1
D
D LINE INPUT VOLTAGE DIVIDER CODEC RIN = 20K OHMS NET RIN = 18K OHMS FC = 8 HZ VIN = 2VRMS, CODEC VIN = 1.14 VRMS
CRITICAL
C6300
R6300 60
AUD_LI_L
IN
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
7.87K2
1
1% 1/16W MF-LF 402
3.3UF AUD_LI_L_DIV
2
1
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
AUD_LI_P_L MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
OUT
56
10% 16V TANT SMA-HF1
C R63011 21.5K
1% 1/16W MF-LF 402 2
C
NOSTUFF 1
C6301 820PF
10% 50V 2 CERM 402
CRITICAL
C6302 3.3UF
60
IN
AUD_LI_GND
2
R6303 10
1% 1/16W MF-LF 2 402
IN
AUD_LI_REF OUT
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
56
10% 16V TANT SMA-HF1
1
61 56
1
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
GND_AUDIO_CODEC
R63051 21.5K
B
1% 1/16W MF-LF 402 2
NOSTUFF 1
C6304 820PF
B
10% 50V 2 CERM 402
CRITICAL
C6303
R6306 60
IN
AUD_LI_R MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
3.3UF
7.87K2
AUD_LI_R_DIV
1
2
1
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
1% 1/16W MF-LF 402
AUD_LI_P_R MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
OUT
56
10% 16V TANT SMA-HF1
A
SYNC_MASTER=K91_AUDIO
SYNC_DATE=07/12/2010
PAGE TITLE
AUDIO: LINE INPUT FILTER DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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1
D
D
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER R6501
C
56
IN
AUD_HP_PORT_L
1
0
C6500 1 0.1UF
NC
10% 16V X7R-CERM 2 402
MIN_LINE_WIDTH=0.30MM OUT MIN_NECK_WIDTH=0.20MM
C
60
1
R6502 3.32K
1% 1/16W MF-LF 2 402
AUD_HP_ZOBEL_L
MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM
AUD_HP_L
2
5% 1/10W MF-LF 603
CRITICAL
1
R6500 39
5% 1/16W MF-LF 402 2 60 56
IN
GND_AUDIO_HPAMP
R65101 39
5% 1/16W MF-LF 402 2
AUD_HP_ZOBEL_R NC MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM
1
R6512 3.32K
1% 1/16W MF-LF 2 402
CRITICAL
C6510
1
0.1UF
10% 16V X7R-CERM 2 402 56
IN
AUD_HP_PORT_R
R6511 1
0
5% 1/10W MF-LF 603
B
2
AUD_HP_R
MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM
OUT
60
B
A
SYNC_MASTER=K91_AUDIO
SYNC_DATE=07/12/2010
PAGE TITLE
AUDIO: HEADPHONE FILTER DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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8
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1
3X MONO SPEAKER AMPLIFIERS (SSM2375) APN: 353S2958 GAIN = +3 DB 1ST ORDER FC (L&R) = ~737 HZ 1ST ORDER FC (SUB) = ~90 HZ
D
D
PLACE C6611 CLOSE TO VDD PIN 8
PP5V_S0_AUDIO_AMP_L CRITICAL 20% 6.3V 2 TANT-POLY CASE-A4
C6613 FERR-1000-OHM 0.0027UF 1 2 AUD_SPKRAMP_LIN_P 1 2 98 0402 NO_TEST=TRUE 10%
AUD_LO2_L_P
IN
1
47UF
L6610
98 56
CRITICAL
C6612 1
CRITICAL
0.1UF
CRITICAL
CRITICAL
98
IN
OUT+ C3 OUT- B3
A2 SD*
GAIN A3
OUT
6 60 98
MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM
TP_LT_GAIN NC
SPKRCONN_L_OUT_N
EDGE B2
GND
5% 1/16W MF-LF 402 2
FERR-1000-OHM 1
B1 IN+ A1 IN-
100K
L6601
AUD_GPIO_3
SSM2375L_P SSM2375L_N
R66001
CRITICAL
56
98
50V CERM 402
AUD_SPKRAMP_SHUTDOWN_L
6 60 98
C1
59
OUT
WLCSP
C6614 FERR-1000-OHM 0.0027UF 1 2 AUD_SPKRAMP_LIN_N 1 2 98 0402 NO_TEST=TRUE 10%
AUD_LO2_L_N
IN
SPKRCONN_L_OUT_P
U6610
SSM2375
L6611
98 56
MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM
VDD
50V CERM 402
CRITICAL
C6611
10% 2 16V X5R 402-1
C2
CRITICAL
2 0402
C
C PLACE C6621 CLOSE TO VDD PIN 59 8
PP5V_S0_AUDIO_AMP_R CRITICAL
CRITICAL
C6622 1 CRITICAL
L6620
C6623
FERR-1000-OHM IN
AUD_LO2_R_P
98
2
0402
0.0027UF AUD_SPKRAMP_RIN_P NO_TEST=TRUE
CRITICAL
L6621
IN
AUD_LO2_R_N
1
98
2
0402
59
OUT
6 60 98
OUT
6 60 98
WLCSP
98 98
SSM2375R_P SSM2375R_N
C6624
AUD_SPKRAMP_SHUTDOWN_L
SPKRCONN_R_OUT_P
U6620
SSM2375
10% 50V CERM 402
1
MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM
VDD
0.0027UF AUD_SPKRAMP_RIN_N NO_TEST=TRUE
CRITICAL
2
CRITICAL
FERR-1000-OHM 98 56
1
10% 2 16V X5R 402-1
B1 IN+ A1 IN-
OUT+ C3 OUT- B3
A2 SD*
GAIN A3
MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM
TP_RT_GAIN NC
SPKRCONN_R_OUT_N
EDGE B2
2
GND
10% 50V CERM 402
C1
98 56
1
20% 6.3V TANT-POLY 2 CASE-A4
C6621 0.1UF
47UF
C2
CRITICAL
1
R66011 100K
B
B
5% 1/16W MF-LF 402 2
PLACE C6631 CLOSE TO VDD PIN 59 8
PP5V_S0_AUDIO_AMP_R CRITICAL
L6630
98 56
IN
98 56
IN
59
20% 6.3V 2 TANT CASE-AL1
C6631 0.1UF
10% 2 16V X5R 402-1
CRITICAL
VDD
MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM
SPKRCONN_S_OUT_P
U6630
OUT
6 60 98
OUT
6 60 98
SSM2375 WLCSP
CRITICAL
CRITICAL
L6631
C6634
FERR-1000-OHM 0.022UF 1 2 AUD_SPKRAMP_SUBIN_N 1 2 AUD_LO1_R_N 98 0402 NO_TEST=TRUE 10%
98 98
SSM2375S_P SSM2375S_N
B1 IN+ A1 IN-
OUT+ C3 OUT- B3
A2 SD*
GAIN A3
MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM
TP_SW_GAIN NC
SPKRCONN_S_OUT_N
EDGE B2
GND C1
25V X7R 0402
A
1
100UF
C6633 FERR-1000-OHM 0.022UF 1 2 AUD_SPKRAMP_SUBIN_P 1 2 AUD_LO1_R_P 98 0402 NO_TEST=TRUE 10% 25V X7R 0402
CRITICAL
C6632 1
CRITICAL
C2
CRITICAL
AUD_SPKRAMP_SHUTDOWN_L SYNC_MASTER=K91_AUDIO
SYNC_DATE=07/12/2010
PAGE TITLE
AUDIO: SPEAKER AMP DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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1
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1
MIC CONNECTOR Dual DMIC removed.Added single analog mic like K18. Sept 21st 2010
AUDIO JACK 1 LO/HP JACK, SPDIF TX
Place this in place of DMIC connector J6780 CRITICAL AUD_SPDIF_OUT
D
J6780
56
IN
L6703
M-RT-SM 4
FERR-1000-OHM CRITICAL 1
2
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM 98 89 88 79 72 71 61 49 48 47 45 32 28 26 25 17 16 12 7 6 23 22 20 19 18 41 40 39 36 35 60 56 53 51 50 87 84 83 82
HS_MIC_P
61
OUT
0402
61 6
OUT
L6702
61 6
OUT
61 6
OUT
FERR-1000-OHM CRITICAL PP3V3_S0
1
2
HS_MIC_N
0402
APN: 514-0671
1
J6700
1 2 3
61
OUT
5
2
AUD_HP_PORT_REF
56
BI
0402
CRITICAL
L6701
F-RT-TH
FERR-220-OHM-2.5A 1
AUD_CONNJ1_SLEEVE2 AUD_CONNJ1_SLEEVEDET AUD_CONNJ1_TIPDET AUD_CONNJ1_TIP AUD_CONNJ1_RING AUD_CONNJ1_SLEEVE
6 5
MIC DETECT SWITCH LEFT RIGHT GND
2 1 3 4
2
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM
L6704
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM
FERR-220-OHM 1
2
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM
56
OUT
1
DIGI_MIC L6784 600-OHM-300MA AUD_DMIC_SDA1 1 CON_DMIC_SDA 2
2
10K
1
CRITICAL 1
C6700 0.1UF
10% 2 16V X5R 402-1
1
C6701
CRITICAL
2.2UF
DZ6703
20% 2 6.3V CERM 402-LF
DZ6704
2
2
CRITICAL
6.8V-100PF
2
DZ6706
4
AUD_J1_SLEEVEDET_R
2
OUT
61
98 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 89 88 87 84 83 82 79 72 71
PP3V3_S0
DIGI_MIC L6785 600-OHM-300MA CON_DMIC_PWR 1 2
6
6.8V-100PF
402
402
C
0402
SPEAKER CONNECTOR OUT
61
CRITICAL
1
J6781
DZ6701
6.8V-100PF 1
3
0402
0402
CRITICAL
1
CRITICAL
2
1
2
CRITICAL
FERR-1000-OHM CRITICAL 1 2 AUD_J1_TIPDET_R
402
402
1
OUT
L6705
2
6.8V-100PF
402
BI
5% 1/16W MF-LF 402
DZ6700
6.8V-100PF
56 58
R6700
10
13
AUD_HP_L
0402
POF
M-RT-SM 5
0402
CRITICAL
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM
J6783 78171-0004
CRITICAL
L6706
11 12
CRITICAL DIGI_MIC L6783 600-OHM-300MA 2 CON_DMIC_CLK AUD_DMIC_CLK 1
0402
OPERATING VOLTAGE 3.3
SHIELD PINS
58
BI
FERR-220-OHM
9
SHELL
AUD_HP_R
DIGI_MIC CRITICAL
56 58
OUT
CRITICAL
7 8
A - VIN B - VCC C - GND
GND_AUDIO_HPAMP
0603
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM
AUDIO
C
BI_MIC_N BI_MIC_SHIELD BI_MIC_P
L6707 CRITICAL FERR-220-OHM
CRITICAL
SPDIF-TXRX-K24
D
78171-0003
1
APN: 518S0519
C6705 100PF
5% 50V 2 CERM 402
1
78171-0002
MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V
GND_CHASSIS_AUDIO_JACK
8 60
98 59 6
IN
98 59 6
IN
M-RT-SM 3
SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N
1 2 4
XW6701 SM 1
1
B
J6782
2
78171-0004
XW6702 SM
GND PATCH 79 72 71 61 60 41 40 39 36 35 18 17 16 12 7 6 32 28 26 25 23 22 20 19 56 53 51 50 49 48 47 45 98 89 88 87 84 83 82
CRITICAL
2
R6701
PP3V3_S0 60 8
GND_CHASSIS_AUDIO_JACK
CRITICAL
AUD_J2_OPT_OUT
J6750
LEFT RIGHT GROUND
5 2 1 3 4
1
4.7
2
AUD_SPDIF_IN
OUT
98 59 6
IN
98 59 6
IN
SPKRCONN_S_OUT_P SPKRCONN_S_OUT_N SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N
1 2 3 4
C6781 1
1
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM
2
AUD_LI_R
BI
57
AUD_LI_L
BI
57
1
NOSTUFF CRITICAL 1
B
6
C6784 33PF
2
5% 50V 2 CERM 402
C6782 33PF
5% 50V CERM 2 402
FERR-1000-OHM
AUD_CONNJ2_RING
1
33PF
L6754
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM
33PF 5% 50V NOSTUFF CERM CRITICAL 402
NOSTUFF CRITICAL
56
CRITICAL
AUD_CONNJ2_TIPDET
5% 2 50V CERM 402
0402
CRITICAL
L6756
FERR-1000-OHM
6 7 8
1
AUD_CONNJ2_TIP
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM
2 0402
CRITICAL
L6758
600-OHM-300MA
POF
SHIELD PINS
IN
C6783
OPERATING VOLTAGE 3.3
SHELL
IN
98 59 6
R6749
AUDIO A - VDD B - GND C - VOUT
98 59 6
NOSTUFF CRITICAL
5% 1/16W MF-LF 402
F-RT-TH5 SWITCH
2
5% 1/16W MF-LF 402
AUDIO-RCVR-M97 DETECT FOR PLUG TYPE
0
1
APN: 514-0635
M-RT-SM 5
APN: 518S0521
9 10 11 12
1
AUD_CONNJ2_SLEEVE
2
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM
CRITICAL 1
C6750
CRITICAL
1UF
DZ6758
10% 2 10V X5R 402-1
DZ6754
2
57
2
DZ6757
L6752
FERR-1000-OHM 1
402
SOD882
CRITICAL
CRITICAL 2
6.8V-100PF
ESDALC5-1BM2
A
AUD_LI_GND
0402
2 1
2
AUD_J2_TIPDET_R
OUT
61
0402
CRITICAL
1
DZ6756 6.8V-100PF 402
ESDALC5-1BM2
1
SOD882
SYNC_MASTER=K91_AUDIO
C6756
AUDIO: JACKS
5% 2 50V CERM 402
1
SYNC_DATE=09/30/2010
PAGE TITLE
100PF
1
DRAWING NUMBER
GND_CHASSIS_AUDIO_JACK
Apple Inc.
8 60
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
AUDIO JACK 2 LINE IN JACK, SPDIF RX
8
7
6
5
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
4
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2 PORT B LEFT(HEADSET MIC) HP=80HZ, LP=8.82KHZ
CODEC OUTPUT SIGNAL PATHS FUNCTION HP/LINE OUT SATELLITES SUB SPDIF OUT
VOLUME 0X02 (2) 0X04 (4) 0X03 (3) N/A
CONVERTER 0X02 (2) 0X04 (4) 0X03 (03) 0X08 (8)
PIN COMPLEX 0X09 (9,A) 0X0B (11) 0X0A (10) 0X10 (16)
MUTE CONTROL N/A GPIO_3 GPIO_3 N/A
CRITICAL
DET ASSIGNMENT 0X09 (A) N/A N/A 0X0C (B)
L6880
MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V
FERR-1000-OHM 71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
1
PP3V3_S0
2
PP3V3_S0_HS_RX
VREF N/A N/A N/A MIKEY
DET ASSIGNMENT 93 88 0X0C (12,C) N/A N/A MIKEY 93 88
47 41 30 28 26 23 16
SMBUS_PCH_CLK
IN
1
SMBUS_PCH_DATA
BI
1
18
GPIO SATA4GP/GPIO 16 GPIO 5 GPIO 3
INT PIRQ H PIRQ F
1
R6885 19
AUD_IPHS_SWITCH_EN
IN
1
0
0
A2
1
10UF
C6887 0.1UF
20% 6.3V X5R 2 603
CRITICAL
D
AVDD
10% 25V 2 X5R 402
U6880 CD3282A1
MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM
WCSP
R6884
AUD_I2C_INT_L
OUT
2
CRITICAL
C6880 1
2
5% 1/16W MF-LF 402
SYSTEM INT AND GPIO LINES FUNCTION MIKEY ENABLE MIKEY INTERRUPT PERIPHERAL DETECT
0
CRITICAL
5% 1/16W MF-LF 402
R6883 47 41 30 28 26 23 16
0
2
5% 1/16W MF-LF 402
R6887
C3
SCL
MICBIAS
C1
HS_MIC_BIAS
HS_SDA
B3
SDA
DETECT
B1
HS_SW_DET
HS_INT_L
D3
INT*
BYPASS
D1
HS_RX_BP
HS_ENABLE
A3
ENABLE
A1 TIPDET_UNFILT
61
1
HS_SCL
HDET
B2
100K
2
CS
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 402
1
CRITICAL 1
2.2UF
C6881 0.01UF
GND_AUDIO_CODEC
R68801 61 57 56
C6882
20% 6.3V 2 TANT 402
10% 16V 2 CERM 402
D2 AGND
PIN COMPLEX 0X0C (12,C) 0X0F (15) 0X0D (13) 0X0D (13,V22,B,LEFT)
5% 1/16W MF-LF 402 2
R6882
PULLUPS ON MCP PAGE
CONVERTER 0X05 (5) 0X07 (7) 0X06 (6) 0X06 (6)
C2 DGND
D
APN:353S2640
10K
CODEC INPUT SIGNAL PATHS
CSP MIKEY
0402
R68861 FUNCTION LINE IN SPDIF IN BUILT-IN MIC HEADSET MIC
1
1
R6881
1K
GND_AUDIO_CODEC
56 57 61
2.2K
1% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
CRITICAL
PORT A DETECT (HEADPHONES)
C6883
PORT B DETECT(SPDIF DELEGATE)
61 56
OUT 61
PP3V3_S0_AUDIO_F
1
220K
5% 1/16W MF-LF 2 402
SSM6N15FEAPE
Q6801
47K
D 3
SSM6N15FEAPE
Q6801
AUD_MIC_INN_L
AUD_PORTB_DET_L NC
1
5 G
C6801
220K 2 1
PP3V3_S0_AUDIO_F
S 4
2 G
220K
5% 1/16W MF-LF 2 402
R6850 56
IN
AUD_CODEC_MICBIAS
1
61 57 56
D 6
Q6800
61 60
2
HS_MIC_N
C6802
2 G
OUT
AUD_MIC_INP_R
1
1
C6852
MF 402-1
2.2UF
L6850
FERR-1000-OHM
2
10% 16V 2 CERM 402
AUD_MIC_INN_R
R6852 100K
5% 1/16W MF-LF 2 402
C6853
L6862
1
PP3V3_S0
2
PP3V3_S0_AUDIO_F MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V
0402
C6861
1
0.1UF
61 57 56
10% 402 CERM 2
BI_MIC_LO_F
1
1
0
5% 1/16W MF-LF 402
2
100K 2
R6867 AUD_PERPH_DET_R
5% 1/16W MF-LF 402
R6864 R6866
1
0
2
61 56
AUD_IP_PERIPHERAL_DET
OUT
10% 25V X5R 2.4K 402 1 2 1% 1/16W MF 402-1
61
1
2
Q6803 SSM6N15FEAPE SOT563
6 60
BI_MIC_SHIELD
Place this next to the connector
2 G
S 1
5 G
NC
Q6802 SSM3K15FV
D 3
SOD-VESM-HF
R6812 S 4
60
IN
AUD_J2_TIPDET_R
1
47K
2
5% 1/16W MF-LF 402
C6860 0.1UF
10V 2 20% CERM 402 61 57 56
AUD_INJACK_INSERT_L
5% 1/16W MF-LF 2 402
D 3
TIPDET_FILT 1
2
HP=80HZ
10K
R6860 5% 1/16W MF-LF 402
IN
XW6851 SM
1% 1/16W MF-LF 402 2
270K
D 6
SOT563
AUD_J1_TIPDET_R1
6 60
B BI_MIC_N
R68131
PP3V3_S0_AUDIO_F
R6811
Q6803 SSM6N15FEAPE
15K
2 0402
AUD_SENSE_A
OUT
1
5% 1/16W 402 61
1
18
5% 1/16W MF-LF 402
220K 2 AUD_J1_TIPDET_INV
TIPDET_UNFILT MF-LF
IN
L6851
FERR-1000-OHM
PORT C DETECT (LINE-IN)
R6865
GND_AUDIO_CODEC
1
6 60
61
10V 20% 2 402 CERM
61 60
2
FERR-1000-OHM IN
IN
1
0.001UF 50V
R6853
GND_AUDIO_CODEC
BI_MIC_P
CRITICAL
1
C6851
OUT
2 0402
CRITICAL 1
1
BI_MIC_HI_F
10% 25V X5R 402
CRITICAL 89 53 32 7 6 20 45 79
60
20% 2 6.3V TANT 402
S 1
61 57 56
98 56 35 12 22 47 82
IN
R6851
0.1UF
EXTRACTION NOTIFICATION
60 36 16 23 48 83
CRITICAL
CRITICAL
C6850
56
61 39 17 25 49 84
C
50V 2 5% CERM 402
2
0.1UF
71 40 18 26 50 87
C6885 27PF
0.0082UF
10% 25V 2 X7R 402
CRITICAL
SOT563
B
72 41 19 28 51 88
1
C6884
60
MIC_BIAS_FILT 1 2.4K 2 1% CRITICAL 1/16W
GND_AUDIO_CODEC
AUD_J1_SLEEVEDET_R
SSM6N15FEAPE
0.01UF
A
100
AUD_J1_SLEEVEDET_INV
56
GND_AUDIO_CODEC
1
IN
PORT B RIGHT(BUILT-IN MIC)
S 1
1% 1/16W MF-LF 402
5% 1/16W MF-LF 402
R6804
61 57 56
HS_MIC_P
5% 1/16W MF-LF 402
SOT563
0.1UF 10V
1
XW6880 SM 1
S 4
GND_AUDIO_CODEC
AUD_J1_SLEEVEDET_R
5% 1/16W MF-LF 2 402
2.2K 2
SSM6N15FEAPE
SOT563
5 G
1
IN
R6888 100K
GND_AUDIO_CODEC
R6803
61 60
1
2
1
D 6
2 20% CERM 402
61
1
HS_MIC_HI_RC
AUD_J1_DET_RC
2
5% 1/16W MF-LF 402
61 57 56
OUT
10% 25V X5R 402 61 57 56
R6802 1
56
1% 1/16W MF-LF 2 402
D 3
SOT563
AUD_J1_TIPDET_R
20.0K
1% 1/16W MF-LF 2 402
AUD_PORTA_DET_L NC
Q6800
0.1UF
R6805
39.2K
2 10% 25V X5R 402
C6886
1
R6806
APN:376S0613 AUD_OUTJACK_INSERT_L
R6801
IN
1
AUD_MIC_INP_L CRITICAL
1
61 60
OUT
AUD_SENSE_A
C
R6890
0.1UF
56
APN:376S0612 AUD_J2_DET_RC 1
C6811
SYNC_MASTER=K91_AUDIO
AUDIO: JACK TRANSLATORS
S 2
DRAWING NUMBER
0.1UF
10V 2 20% CERM 402
GND_AUDIO_CODEC 61 57 56
SYNC_DATE=09/21/2010
PAGE TITLE
1 G
Apple Inc.
GND_AUDIO_CODEC
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
7
6
5
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NOTICE OF PROPRIETARY PROPERTY:
8
SIZE
REVISION
4
3
2
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PAGE
68 OF 132 SHEET
61 OF 101
1
A
8
7
6
5
4
3
2
1
MagSafe DC Power Jack CRITICAL
CRITICAL
F6905
J6900 6
M-RT-SM PWR PWR GND GND SIG
PPDCIN_G3H
6AMP-24V
78048-0573
1
PP18V5_DCIN_FUSE
MIN_LINE_WIDTH=1mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V
1 2 3 4 5
1
C6905
1206-2
PP3V42_G3H
0.01UF
20% 50V 2 CERM 603
1
C6908 0.1UF
R6929 2.0K
5
U6900
4
SC70-5 4 INT
EXT 5
NC
2
3
SMC_BC_ACOK
2
U6901
IN
44 45 48 63
1
B
CRITICAL GND
Y
402
TC7SZ08AFEAPE SOT665 A
MAX9940
SYS_ONEWIRE
20% PLACEMENT_NOTE=PLACE NEAR U6900 and U6901 2 10V CERM
CRITICAL
VCC
5% 1/16W MF-LF 2 402 BI
6 7 25 42 44 45 46 47 52 62 63 72
SMC_BC_ACOK_VCC 1
44
D
6 7 48 62 63
2
1
D
3
NC
BIL CONNECTOR PP3V42_G3H
62 52 47 46 45 44 42 25 7 6 72 63
C6951
1-Wire OverVoltage Protection 6
516S0523
1
CRITICAL
0.1UF 10% 25V X5R 402
ADAPTER_SENSE
J6955
CPB6312-0101F
2
F-ST-SM 14
The chassis ground will otherwise float and can send transients onto ADAPTER_SENSE when AC is connected.
C
R6961 52 45 44
2
SMC_LID
OUT
100
NC
1
402
SMC_LID_R SMBUS_SMC_BSA_SDA BI SMBUS_SMC_BSA_SCL BI 6
1/16W
96 47 44 6 63 62
5% MF-LF
47 44 6 63 62 96
C6955
1
C6953
10% 50V CERM 402
1
47PF
0.001UF
5% 50V CERM 402
2
C6952 5% 50V CERM 402
2
1
4
3
6
5
8
7
10
9
12
11
16
15
C
NC
TO SMC SMC_BIL_BUTTON_L
C6954
1
47PF 2
13
OUT
6 44 45
1
0.001UF 10% 50V CERM 402
2
2
3.425V "G3Hot" Supply CRITICAL
Supply needs to guarantee 3.31V delivered to SMC VRef generator
D6990
P3V42G3H_REF3
BAT30CWFILM SOT-323 1
47
1
1% 1/3W MF 805
B
2
PPDCIN_S5_P3V42G3H 2 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V
4.7UF
10% 35V X5R-CERM 2 0805
R6995
5% 1/16W MF-LF 2 402
P3V42G3H_TON
3 TON 4 EN
P3V42G3H_FB
C6991 1
NC
353S2776
CRITICAL 33UH-20%-0.44A-0.455OHM
THRM GND PAD
L6995
SW 6
P3V42G3H_SW MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE
1
PP3V42_G3H
2
DIDT=TRUE
300mA max output f = 470 kHz
10% 16V 2 X5R 402-1
1
1
22UF
3
7
SMBUS_SMC_BSA_SCL
6 44 47 62 63 96
6 SYS_DETECT_L
SMBUS_SMC_BSA_SDA CRITICAL
63 6 PPVBAT_G3H_CONN
D6950 1
8 9
C6950
C6960
1
11
10% 25V X5R 402
1
RCLAMP2402B
10% 25V X5R 603-1
2
R6950
1
10K
SC-75
5% 1/16W MF-LF 402
1UF
0.1UF 10
6 44 47 62 63 96
2
6
2
2
3
5
C6999
20% 6.3V 2 X5R-CERM-1 603
2
4
6 7 25 42 44 45 46 47 52 62 63 72
Vout = 3.425
D52LC-SM
0.1UF
M-RT-TH
A
DFN CRITICAL
C6994 1
BAT-K90-K91-K92
SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN
B
BYP 9
PM6640
5
10% 25V 2 X5R 402
BATTERY CONNECTOR
CRITICAL
P1 P2 P3 P4 P5 P6 P7 P8 P9
1 REF
1UF
J6950
U6990
8 VCC 2 FB
518-0375
20% 10V CERM 2 402
1
1M
C6990 1
REF3 10
PPDCIN_G3H
1
0.1UF
VIN 7
63 62 48 7 6
C6995 PPVIN_G3H_P3V42G3H MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V
3
R6990
11
88 63 49 48 39 35 8 7 6
PPBUS_G3H
12 13
SYNC_MASTER=K91_ERIC
SYNC_DATE=10/08/2010
PAGE TITLE
DC-In & Battery Connectors DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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62 OF 101
1
A
8
7
6
5
4
3
2
1
CRITICAL
Q7080
IRF9395TRPBF DIRECTFET-MC
2 1
9 8
5 4
NC
Reverse-Current Protection
10% 25V 402
1% 1/16W MF-LF 402
2
D
100K
5% 1/16W MF-LF 2 402
CHGR_AGATE_DIV
CHGR_SGATE_DIV
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm 1
R7081
1
R7086
62K
332K
5% 1/16W MF-LF 2 402
1% 1/16W MF-LF 402 2
CRITICAL
D7005
(CHGR_AGATE)
BAT30CWFILM SOT-323 1
(CHGR_SGATE)
R7005 CHGR_DCIN_D_R
20
1
R7021
(CHGR_DCIN)
2
1
Divider sets ACIN threshold at 13.55V
BI IN
CHGR_ACIN
R7011 9.31K
1
R7015
96
330K
96
5% 1/16W MF-LF 2 402
1
CHGR_VCOMP_R
C7015 1
CHGR_ICOMP CHGR_VCOMP CHGR_VNEG CHGR_CSO_P CHGR_CSO_N
C7050 1UF
10% 16V 2 X5R 402
20% 2 25V POLY-TANT CASE-D2-SM
10% 2 25V X5R 402
CHGR_DCIN
26 1 28 27
CHGR_SGATE CHGR_AGATE CHGR_CSI_P CHGR_CSI_N
96 96
CRITICAL
D 1
4
C7025
RJK0332DPB-01 LFPAK-SM
0.22UF
25 24 23
CHGR_BOOT CHGR_UGATE CHGR_PHASE
21
CHGR_LGATE
GATE_NODE=TRUE DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
CHGR_BGATE CHGR_AMON CHGR_BMON SMC_BC_ACOK
OUT
49
OUT
49
OUT
44 45 48 62
DIDT=TRUE
PLACE_NEAR=U7000.25:2mm
3
1 2 3 GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 mm
1
C7037 0.001UF
10% 50V 2 X7R 402
10% 25V 2 X5R 603-1
C
1
NO STUFF
F7041 8AMP-24V PPVBAT_G3H_CHGR_REG MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V
CRITICAL 1
RJK0305DPB
NO STUFF 1
C7039
10% 2 50V CERM 402
1 2 3
(GND)
R7051 R7052
(CHGR_CSO_P) (CHGR_CSO_N) (PPVBAT_G3H_CHGR_R)
2.2
1
2
98 49
0
1
2
98 49
CRITICAL
Q7055 SI7137DP SO-8
1% 1W MF 0612
2 4
1 3
PPVBAT_G3H_CHGR_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V
C7055 1
C7056 1
C7057 1
10% 25V X5R 2 603-1
10% 16V 2 X5R 402-1
10% 16V CERM 2 402
1UF
470PF
0.001UF
0.005
CHGR_VNEG_R
C7016
10% 2 50V X7R 402
2 1206
R7050
PLACE_NEAR=U7000.29:1mm PLACE_NEAR=U7000.22:1mm
10% 2 50V CERM 402
20% POLY-TANT CASE-D2-SM
22UF
CRITICAL
C7045
C7040
1
2 25V
DIDT=TRUE
470PF
XW7000 SM
1
CHGR_PHASE_RC
Q7035
6 7 8 35 39 48 49 62 88
CRITICAL
180
CRITICAL
PPBUS_G3H
2 1206
5
2
1
FDA1254F-SM
5% 1/10W MF-LF 603 2
353S2392
TO SYSTEM
F7040 8AMP-24V
R70391
LFPAK-HF
1
CRITICAL
4.7UH-10.2A 2
B
1
C7036
L7030
MIN_NECK_WIDTH=0.2 mm
4
1% 1/16W MF-LF 402 2
1
1UF
10% 25V 2 X5R 603-1
20% 25V 2 POLY-TANT CASE-D2-SM
CRITICAL
S
220PF
3.01K
C7035 1UF
22UF
Max Current = 8A (L7030 limit) f = 400 kHz
Q7030
G
10% 10V 2 CERM 402
10% 50V X7R-CERM 2 402
R70161
1
C7031
5 2
16 9 36V/V BMON 15 (OD) ACOK 14
29
1% 1/16W MF-LF 2 402
U7000
(AGND) THRM_PAD
1
C7021
CRITICAL 1
B
TO/FROM BATTERY
0.1UF
D
44 6 62 72
22UF
PPVBAT_G3H_CONN 5
IN
C7030
S
1% 1/16W MF-LF 2 402
44 6 62
CRITICAL 1
0.01uF
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V
6 62
G
5% 47 1/16W96 MF-LF47 402 96
PPDCIN_G3H_CHGR MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V
4
30.1K
CHGR_RST_L SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA CHGR_VFRQ CHGR_CELL
2
3 1 0612
2
VDDP
VHST CRITICAL DCIN SMB_RST_N SGATE SCL AGATE TQFN SDA CSIP VFRQ CSIN CELL BOOT 3 ACIN UGATE 5 ICOMP PHASE 7 VCOMP LGATE 8 VNEG 18 CSOP BGATE 17 CSON 20V/V AMON
ISL6259
1
0.5% 1W MF-LF
CHGR_CSI_R_N
0.1UF
10% 25V 2 X5R 402
PGND
SMC_RESET_L
0.020
2 3
VDD 12 13 11 10 4 6
R7020
20
5% 1/16W MF-LF 2 402
1
0.1UF
10% 10V X5R 2 402
100K
63
C7022 1
1UF
R7002
GND_CHGR_AGND
IN
C7001 1
22
R7010
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V
5% 1/16W MF-LF 402
R7000 0
98
10
4 2
CHGR_CSI_R_P
5% 1/16W MF-LF 402
PP5V1_CHGR_VDDP
2
19
1% 1/16W MF-LF 402 2
4.7
1
10% 10V 2 X5R 402
1K
1
NO STUFF
1
1UF
R70121
1
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=5.1V
PP3V42_G3H
C7002
C
R7022 1
R7001
PP5V1_CHGR_VDD 62 52 47 46 45 44 42 25 7 6 72
CRITICAL 98
C7020
10% 10V 2 CERM 402
30mA max load
2
5% 1/16W MF-LF 402
0.047UF
Input impedance of ~40K meets sparkitecture requirements
10
1
5% 1/16W MF-LF 402
2
1
3
ACIN pin threshold is 3.2V, +/- 50mV
D
R7080
G
R7085 470K
0.1UF
2 X5R
3
C7085
G
1
PPDCIN_G3H_INRUSH MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V
1
6
D
1
S
S
PPDCIN_G3H
D
Inrush Limiter
FROM ADAPTER 62 48 7 6
NC 10 7
NC
NC
CHGR_CSO_R_P
5% 1/16W MF-LF 402
CHGR_CSO_R_N
5% 1/16W MF-LF 402
(PPVBAT_G3H_CHGR_R) (CHGR_BGATE)
1
C7042
C7011 1
0.068UF
0.01UF
10% 2 10V CERM 402
10% 16V CERM 2 402
1
C7000 1UF
10% 10V 2 X5R 402-1
C7005 1
C7026 1
0.22UF
0.001UF
20% 25V 2 X5R 603 63
10% 50V CERM 2 402
GND_CHGR_AGND MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
A
SYNC_MASTER=K91_CHANG
SYNC_DATE=07/20/2010
PAGE TITLE
PBus Supply & Battery Charger DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
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63 OF 101
1
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8
7
6
5
4
3
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1
D
D
69 68 67 66 49 7 86 72 71 69 68 67 53 51 46 41 22 8 7 6 101 88
PPVIN_S5_HS_COMPUTING_ISNS PP5V_S0 PLACE_NEAR=Q7100.2:1.5mm
VCCSAS0_BOOT_RC CRITICAL
R71011
1
C7101
20% 2 10V X5R 603
5% 1/16W MF-LF 402 2
1
R7130
19
20
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE
ISL95870A 72
CRITICAL UGATE OMIT_TABLE
10 FB
CPU_VCCSASENSE
7
VCCSAS0_SREF
1
R7147 113K
1% 1/16W MF-LF 2 402
72
OUT
VCCSAS0_VO
12 VO 11 OCSET 14
VCCSAS0_RTN
4
VCCSAS0_FSEL 13
C7103 1 0.022UF
10% 16V CERM-X5R 2 402
C7105 1000PF
5% 25V 2 NP0-C0G 402
LGATE 1
3
7
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE
1
C7122 1000PF
5% 2 25V NP0-C0G 402
CRITICAL
CRITICAL
Q7100 SIZ700DT
0.001
L7100
1
1% 1W MF-1 0612
1.0UH-7.7A
VCCSAS0_LL
8
1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE
C
R7140
CRITICAL
POWERPAIR-6X3.7
2
PPVCCSA_S0_REG_R
1 MIN_LINE_WIDTH=0.6 mm 3 MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V
FDV0630H-SM
PPVCCSA_S0_REG 2 4
7 12 15
6A Max Output f = 300 kHz
6
PGOOD
VCCSAS0_DRVL
RTN
VCCSAS0_SET0
8 SET0
VCCSAS0_SET1
9 SET1
4
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE
FSEL
5
R7148
6 VID0
XW7101 SM
1% 1/16W MF-LF 2 402
1
1
C7102 2.2UF
10% 2 16V X5R 603
R71031
5 VID1
0 5% 1/16W MF-LF 402 2
GND
1
PGND
R7141
12
IN
98 48
VCCSAS0_CS_P
98 48
VCCSAS0_CS_N
1K
PLACE_NEAR=C1763.2:3mm
1% 1/16W MF-LF 402 2
C7140 1000PF 2
B
10% 16V X7R-CERM 2 402
2 1
140K 1
17
PHASE 16
SREF
VCCSAS0_OCSET PVCCSA_PGOOD
BOOT 18
2
VCCSAS0_DRVH
2
IN
IN
15 EN
3
12
PVCCSA_EN
0.1UF
10% 16V X5R-CERM 2 0805
VCCSAS0_VBST
U7100 UTQFN
C7121 1
1
10UF
10% 10V 2 CERM 402
5% 1/10W MF-LF 603 2
PVCC
C7130
C7120
1
10% 16V X5R-CERM 2 0805
0.22UF
0
VCC
CRITICAL
10UF
1
PP5V_S0_VCCSAS0_VCC
C
C7119
10UF
2.2
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V
CRITICAL
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE
CPU_VCCSA_VID<1>
1
5% 25V NP0-C0G 402
1
R7149 47.5K
1% 1/16W MF-LF 2 402
B
1
R7142 1K
OCP = R7141 x 8.5uA / R7140 OCP = 8.5A
1% 1/16W MF-LF 2 402
(VCCSAS0_OCSET) (VCCSAS0_VO)
XW7100 SM VCCSAS0_AGND
1
2
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V PLACE_NEAR=U7100.3:1mm
PART NUMBER 353S3074
VID1
VID0
QTY 1
DESCRIPTION IC,ISL95870A,PWM,2BIT-VID,RMOT-SNSE,20P
REFERENCE DES
CRITICAL
U7100
CRITICAL
BOM OPTION
Voltage
0
0
0.9V
1
0
0.8V
A
SYNC_MASTER=K91_ERIC
SYNC_DATE=10/08/2010
PAGE TITLE
System Agent Supply DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
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BRANCH
PAGE
71 OF 132 SHEET
64 OF 101
1
A
8
7
6
5
4
3
2
1
D
D
CRITICAL
C7240 1
C7242 1
68UF
1
1
C7200
10% 2 50V X7R 402
1UF
10% 25V X5R 2 603-1
2.2UH-14A-7.0M-OHM
1
C
1 VIN
10% 2 50V X7R 402
2
PLACE_NEAR=L7220.1:3mm
20% 10V X5R 2 805
20% 6.3V 2 POLY-TANT CASE-D3L-SM1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE
2
1
P5VS3_VFB1_R 2
XW7220 SM
PGND
1% 1/16W MF-LF 2 402
B
1
mm mm mm mm mm mm
GATE_NODE=TRUE
DIDT=TRUE
P5VS3_LL SWITCH_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
P5VS3_CSP1 P5VS3_CSN1
0.1UF
P5VS3_SNUBR
1
10% 16V X5R 402-1
NO STUFF
C7299 1 10% 50V CERM 2 402
R7249
5% 1/16W MF-LF 2 402
5.11K2
9.09K
44 42 29 17 72
0
1
R72561
XW7221 SM
1
R7247
0.0033UF
2
P5VS3_MODE P5VS3_VFB1 P5VS3_COMP1
2
OUT
PM_SLP_S4_L P5VS3_PGOOD
1% 1/16W MF-LF 402
NO STUFF 1
R7237 20.0K
1% 1/16W MF-LF 2 402
P5VS3_CSP1_R
R72361
13
QFN
1 DRVH1
30 DRVL1
DRVH2 24 SW2 25 DRVL2 27
7 CSP1 8 CSN1
CSP2 18 CSN2 17
11 MODE 9 VFB1 10 COMP1
RF 3 VFB2 16 COMP2 15
4 EN1 5 PGOOD1
EN2 21 PGOOD2 20
47PF
1
5% 50V CERM 2 402
1
R7221 10K
1
IN
44 72
Q7260
10% 50V X7R 2 603-1
R7263 0
2
2 WPAK2
OUT
1
7.5K
1% 1/16W MF-LF 402 2
C7238
4700PF
4700PF
1
10% 100V 2 CERM 402
P3V3S5_SNUBR MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE
NO STUFF
511
C7298 0.001UF
10% 50V 2 X7R 402
2 1
R7216
2
3.16K
XW7260 SM
1% 1/16W MF-LF 2 402
P3V3S5_COMP2_R NO STUFF
(P5VP3V3_VREF2)
10 5% 1/10W MF-LF 603 2
3 4 5
2
1% 1/16W MF-LF 402
R72391
C7236
R72981
R7246
1% 1/16W MF-LF 402 2
NO STUFF
10% 2 100V CERM 402
NO STUFF 6
1
249K
44 72
THRM_PAD
1% 1/16W MF-LF 2 402
7
10% 10V CERM 402
R72061
72
1
1
CRITICAL 1
CRITICAL
C7290
1
10UF
C7292 330UF
20% 6.3V 2 X5R 603
20% 2 6.3V POLY-TANT CASE-D3L-SM1
2
XW7262 SM 1
P3V3S5_VFB2_R 2
XW7261 SM R72601
1
23.2K 1% 1/16W MF-LF 402 2
P3V3S5_CSP2_R 1
C
10% 50V 2 X7R 402
1
0.22UF 1
C7272
0.001UF 1
C7288
IN
98 39 45 55 70 71 6 7 17 19 20 22 23 24 25 29 72 82 85 89
2.2UH-14A IHLP2525CZ-SM1
5% 1/16W MF-LF 402
P3V3S5_RF P3V3S5_VFB2 P3V3S5_COMP2 P3V3S5_EN S5_PWRGD
L7260
P3V3S5_TG
P3V3S5_CSP2 P3V3S5_CSN2
10K
0.001UF
10% 2 50V X7R 402
Vout = 3.3V 10A MAX OUTPUT f = 400 kHZ
CRITICAL
RJK0214DPA
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE GATE_NODE=TRUE P3V3S5_DRVH DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm P3V3S5_LL DIDT=TRUE SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm P3V3S5_DRVL DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
R7238
10% 2 25V X5R 603-1
2
CRITICAL
C7264 1 0.1UF
P3V3S5_VBST
P5VS3_COMP1_R
C7237
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
1
C7283
1
1UF
PP3V3_S5
2.2UF
1
VBST2 26
C7281
C7203
20% 10V 2 X5R-CERM 402
SMC_PM_G2_EN
10K
1% 1/16W MF-LF 402 2
1
10% 10V CERM 2 402
EN 12
1
10UF
0.22UF
VREF2
22 VREG3
29 VREG5
31 VBST1
GND
1% 1/16W MF-LF 402 2
1
IN
72
U7201
20% 16V 2 POLY-TANT CASE-D2E-SM
68UF
C7205
CRITICAL
32 SW1
P5VS3_DRVL
C7218
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE
1
40.2K
P5VS3_VBST DIDT=TRUE
P5VS3_DRVH MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.2 MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.2 MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.2
BG 5
R7299 1
5% 1/16W MF-LF 402 2
TGR 4
NO STUFF 5% 1/10W MF-LF 2 603
5% 1/16W MF-LF 2 402
4.7
P5VS3_TG
6 SKIPSEL1 19 SKIPSEL2 14 OCSEL
0
R72441
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
6 VSW 7 8
1
XW7222 SM
R7220
TG 3
9
10UF
330UF
PLACE_NEAR=L7220.2:3mm
CRITICAL
C7250 1
C7252 1
P5VS3_VSW
PLACE_NEAR=L7220.1:3mm
CRITICAL
SON5X6
R7248
0.1UF
CSD58864Q5D
0.001UF
1
10% 50V 2 X7R 603-1
Q7220
PIMB104E2R2MS-SM
C7271
C7224
C7282 1
20% 16V 2 POLY-TANT CASE-D2E-SM
20% 6.3V 2 X5R 603
C7201 1
33
CRITICAL
TPS51980
L7220
NO STUFF
28
1
VIN
2 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
CRITICAL
V5SW
1
23
PP5V_S3
CRITICAL
C7280 1 68UF
CRITICAL 1
P5VP3V3_VREF2
Vout = 5.0V 14.4A MAX OUTPUT f = 400 kHZ
6 7 53 71
Vout = 5V 100mA MAX OUTPUT
1
P5VP3V3_VREG3 100 42 41 31 29 7 6 81 71 66 65 45 43
CRITICAL
PP5V_S5
C7270
0.001UF
10% 2 25V X5R 603-1
20% 16V 2 POLY-TANT CASE-D2E-SM
20% 16V 2 POLY-TANT CASE-D2E-SM
C7241 1UF
68UF
PLACE_NEAR=L7260.2:3mm
CRITICAL
PP5V_S3
PLACE_NEAR=L7260.2:3mm
100 81 71 66 65 45 43 42 41 31 29 7 6
PPVIN_S5_HS_OTHER_ISNS
PLACE_NEAR=L7260.1:3mm
49 7
C7239 330PF
10% 50V 2 CERM 402
B
R72611 10K
(P5VP3V3_VREF2)
1% 1/16W MF-LF 2 402
1% 1/16W MF-LF 402 2
A
SYNC_MASTER=K91_ERIC
SYNC_DATE=10/08/2010
PAGE TITLE
5V / 3.3V Power Supply DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
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65 OF 101
1
A
8
7
6
5
4
3
2
1
D
D
69 68 67 64 49 7
PPVIN_S5_HS_COMPUTING_ISNS CRITICAL
CRITICAL
C7330 1
C7331 1
68UF
71 66 29 28 26 7 6
100 81 71 65 45 43 42 41 31 29 7 6
1
PP1V5_S3
C7332 1UF
68UF
10% 2 25V X5R 603-1
20% 20% 16V 16V POLY-TANT 2 POLY-TANT 2 CASE-D2E-SM CASE-D2E-SM
1
C7333
1
0.001UF
10% 2 50V X7R 402
C7334 1UF
10% 25V 603-1
2 X5R
CRITICAL
PP5V_S3
C7301
1
10UF
20% 10V X5R 2 603
CRITICAL
C7300 1 10UF
R7330 1
(DDRREG_DRVH)
20% 10V 2 X5R 603
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm
2
C
4.7
2
DDRREG_DRVH_R
5% 1/16W MF-LF 402
C7325
VLDOIN VBST 15 DRVH 14 SW 13
IN
MEMVTT_EN DDRREG_EN
DDRREG_1V8_VREF
C7315 0.1UF
1 1
10% 16V 2 X5R 402
U7300
(VTT Enable) 17 S3 (VDDQ/VTTREF Enable) 16 S5
R7315
30
20.0K
DDRREG_FB
TPS51916
6 VREF
DRVL PGOOD VDDQSNS VTT VTTSNS
CRITICAL
8 REFIN
1% 1/16W MF-LF 2 402
0.01UF
10% 16V 2 CERM 402
1
R7317 1R7318 200K
1% 1/16W MF-LF 2 402
7
10
C7316
DIDT=TRUE
10% 50V X7R 603-1
DDRREG_DRVL GATE_NODE=TRUE
3 TG
OUT
PP0V75_S0_DDRVTT
XW7360 SM 1
DDRREG_VTTSNS 6
PPVTTDDR_S3 10mA max load
CRITICAL 1
20% 6.3V 2 X5R 603
1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm
1
270UF
270UF
20% 2V 2 TANT CASE-B4-SM
20%
PP1V5_S3 2
C7340
20% 2 2V TANT CASE-B4-SM
C7341 1
C7361
3
PPDDR_S3_REG_R
CRITICAL
CRITICAL
2 6.3V X5R
C7360, C7361 close 1
PGND
4
2
DIDT=TRUE
10UF
PLACE_NEAR=C3101.1:1mm
48 98
VOLTAGE=1.5V MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.8 MM
FDU1040D-SM
CRITICAL 1
10UF
C7350
1
SWITCH_NODE=TRUE
5 BG
(DDRREG_DRVL) MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm
2
C7360
XW7300 SM
1.0UH-21A
DDRREG_VSW
VTT THRM GND PAD
2
CRITICAL
VSW 6 7 8
L7330
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm
89
OUT
C VIN 1
DDRREG_VDDQSNS
47.5K 1% 1/16W MF-LF 2 402
SON5X6
4 TGR
(DDRREG_LL) DIDT=TRUE
TP_DDRREG_PGOOD
30
1
DIDT=TRUE
ISNS_1V5_S3_N
CSD58864Q5D
PLACE_NEAR=C7361.1:3mm
PGND GND
100K
GATE_NODE=TRUE
SWITCH_NODE=TRUE
DDRREG_LL
11 20 9 3 1
VTTREF 5 7
1
R7316
DDRREG_DRVH
48 98
Q7330
2
QFN
DDRREG_MODE 19 MODE DDRREG_TRIP 18 TRIP
1% 1/16W MF-LF 2 402
1
9
IN
MIN_NECK_WIDTH=0.17 mm MIN_LINE_WIDTH=0.6 mm
21
72
4
29 8
DDRREG_VBST
OUT
CRITICAL
0.1UF 12 V5IN
ISNS_1V5_S3_P
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm
1
0612 MF-1 1W 1%
1
0.001
C7346 R7350 0.001UF
10% CRITICAL 2 50V X7R 402 1
C7345 10UF
6 7 26 28 29 66 71
Vout = 1.5V 18A max output (Q7335 limit) f = 400 kHz
CRITICAL 2
XW7301 SM
20% 2 6.3V X5R 603
1
603
PLACE_NEAR=C3101.1:3mm
to memory (DDRREG_VDDQSNS)
0.22UF
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm
10% 10V CERM 2 402
PLACE_NEAR=U7300.7:1mm
GND_DDRREG_SGND MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0V
B
B
A
SYNC_MASTER=K91_ERIC
SYNC_DATE=10/08/2010
PAGE TITLE
1.5V DDR3 Supply DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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8
7
6
5
4
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2
PART NUMBER
QTY
353S3259
D
PP5V_S0
DESCRIPTION
1
1 REFERENCE DES
CRITICAL
U7400
CRITICAL
IC,MAX15092,3+1PH CPU REG,IMVP7,5X5QFN40
BOM OPTION
D
6 7 8 22 41 46 51 53 64 68 69 71 72 86 88 101
R7401 PP5V_S0_CPUIMVP_VCC
10
1
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V
2
5% 1/16W MF-LF 402
PP1V05_S0
PPVIN_S5_HS_COMPUTING_ISNS
39 35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 44
1
1
R7480
20% 10V X5R-CERM 2 402
20% 2 10V X5R-CERM 402
130 1% 1/16W MF-LF 2 402 24
15
VDDB
PLACE_NEAR=U7400.24:2mm PLACE_NEAR=U7400.15:2mm
PLACE_NEAR=U7400.16:2mm
VCC 40
PLACE_NEAR=U7400.18:2mm
VDDA
1% 1/16W MF-LF 402 2
R7406 1
U7400
R7402
MAX17511 68
OUT
68 67 90 45 10
C
B
2
IN
R7466 5.76K
1% 1/16W MF-LF 2 402
1
R7464
NONE NONE NONE 2 402
33 34
THERMA THERMB
CPUIMVP_SLEW
32
SR
R7462 215K
1% 1/16W MF-LF 2 402
29 30
CRITICAL
R7469
R7467
100KOHM
100KOHM
0402
0402 2
CSPA2 BSTA2 DHA2 LXA2 DLA2 BSTB DHB LXB DLB
IMAXA IMAXB
1
R7460 215K
1% 1/16W MF-LF 2 402
1
R7465 200K
1% 1/16W MF-LF 2 402
1
R7463 137K
1% 1/16W MF-LF 2 402
CPUIMVP_ISUM CPUIMVP_ISUM_N CPUIMVP_FBA
38 28 26 27 25
CPUIMVP_ISUM2_P CPUIMVP_BOOT2 CPUIMVP_UGATE2 CPUIMVP_PHASE2 CPUIMVP_LGATE2
11
CPUIMVP_BOOT1G CPUIMVP_UGATE1G CPUIMVP_PHASE1G CPUIMVP_LGATE1G
13 12 14
CSPB1 8 CSNB 9 FBB 6
1
CRITICAL
CPUIMVP_BOOT1 CPUIMVP_UGATE1 CPUIMVP_PHASE1 CPUIMVP_LGATE1 CPUIMVP_ISUM1_P
CSPAAVE 35 37 68 CSNA FBA 4
VDIO CLK ALERT*
CPUIMVP_NTC CPUIMVP_NTCG
CPUIMVP_IMAXA CPUIMVP_IMAXB
NOSTUFF
EN
16 18 17
CPU_VIDSOUT CPU_VIDSCLK CPU_VIDALERT_L
1
POKA POKB
1
CPUIMVP_VR_ON
OMIT
1
19 10
1
R7461
3
1
90 12
CPUIMVP_PGOOD CPUIMVP_AXG_PGOOD
CSPA3 VRHOT*
CPUIMVP_ISUMG_P CPUIMVP_ISUMG_N CPUIMVP_FBB
OUT
6 68
OUT
68
OUT
68
OUT
68
1
SIGNAL_MODEL=EMPTY
150PF
68
OUT
1
1
C7404 2200PF
1
C7409 1
SIGNAL_MODEL=EMPTY
2
OUT
OUT
68
OUT
68
OUT
68
OUT
68
1
C7405 2200PF
1
5% 10V 2 CERM 0402
SIGNAL_MODEL=EMPTY OUT
C7406 2200PF
5% 10V 2 CERM 0402
10% 50V CERM 402
68
137K
2
CPUIMVP_ISNS2_P
IN
49 68
300
2
CPUIMVP_ISNS3_P
IN
49 68
C
1
NO STUFF
1
2
5% 1/16W MF-LF 402
R7409 40.2K2
1
1% 1/16W MF-LF 67 402
CPUIMVP_ISUM3_P
68
SIGNAL_MODEL=EMPTY
67
1
OUT
68
OUT
68
C7407
0.001UF
10% 2 50V CERM 402
NO STUFF
1
XW7400 SM
1% 1/16W MF-LF 2 402
300
R7410
470PF
OUT
68
49 68
5% 1/16W MF-LF 402
NO STUFF
SIGNAL_MODEL=EMPTY
68
IN
R7408
CPUIMVP_ISUM_R
2
5% 50V CERM 402
5% 10V 2 CERM 0402
67
OUT
CPUIMVP_ISNS1_P
5% 1/16W MF-LF 402
C7408
OUT
2
R7407
1% 1/16W MF-LF 402
THRM PAD
1% 1/16W MF-LF 2 402
IN
OUT
BSTA1 20 DHA1 22 LXA1 21 DLA1 23 CSPA1 36
300
5% 1/16W MF-LF 402
90.9K2 1
CPUIMVP_TON
CRITICAL
41
5.76K
IN
90 12
OUT
89
CPUIMVP_ISUM3_P CPU_PROCHOT_L
TON 2
OMIT_TABLE
GNDSA
R7468
90 12
89
31 39 5
7
1
IN
OUT
CPUIMVP_PWM3
QFN DRVPWMA
GNDSB
72
7 49 64 66 68 69
C7403 2.2UF
20% 2 10V X5R-CERM 402
2.2UF
54.9
1
2.2UF
C7401 1 R74791
C7402
2
C7418 100PF
5% 50V 2 CERM 402
1
NO STUFF
1
C7419 100PF
5% 50V 2 CERM 402
NO STUFF
NO STUFF
1
C7414 100PF
5% 50V 2 CERM 402
1
C7415 100PF
5% 50V 2 CERM 402
NO STUFF
NO STUFF 1
C7416
1
100PF
SIGNAL_MODEL=EMPTY
C7417 100PF
5% 50V 2 CERM 402
5% 50V 2 CERM 402
B
GND_CPUIMVP_SGND
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
PLACE_NEAR=Q7510.1:1mm PLACE_NEAR=Q7550.1:1mm
1
C7440
SIGNAL_MODEL=EMPTY
1000PF
5% 25V 2 NP0-C0G 402 SIGNAL_MODEL=EMPTY
1
R7440
CPU_AXG_SENSE_R
1
10
1
1000PF
5% 25V 2 NP0-C0G 402
12 90
R7412 67
CPUIMVP_FBA
12.7K2
1
1% 1/16W MF-LF 402
R7441
SIGNAL_MODEL=EMPTY
CPU_VCCSENSE_R OMIT
1
IN
5% 1/16W MF-LF 402
C7441
C7442
NOSTUFF
NONE 2 NONE NONE 402
1
OMIT
1
C7443
10
2
C7412 1000PF
CPU_AXG_SENSE_N
2
CPU_VCCSENSE_N
IN
12 90
5% 25V 2 NP0-C0G 402
10
1
2
CPU_VCCSENSE_P
IN
12 90
CPU_AXG_SENSE_P IN
12 90
5% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY
C7422
5% 1/16W MF-LF 402
R7413
CPUIMVP_FBA_R
1
1000PF
R7422
NOSTUFF
NONE 2 NONE NONE 402
67
CPUIMVP_FBB
8.06K2
1
5% 25V NP0-C0G 2 402
CPUIMVP_FBB_R
1% 1/16W MF-LF 402
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
A
R7423 10
1
2
5% 1/16W MF-LF 402
SYNC_MASTER=K91_ERIC
SYNC_DATE=10/08/2010
PAGE TITLE
CPU IMVP7 & AXG VCore Regulator DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
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74 OF 132 SHEET
67 OF 101
1
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8 69 68 67 66 64 49 7
7
6
5
4
3
2
1
PPVIN_S5_HS_COMPUTING_ISNS THESE TWO CAPS ARE FOR EMC
CRITICAL 1 6
376S0872
PHASE 1
5
68UF
20% 2 16V POLY-TANT CASE-D2E-SM
CRITICAL
D
Q7510
CPUIMVP_BOOT1_RC MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
DIRECTFET-MA
S
1
0
IN
IN
CPUIMVP_UGATE1
67
IN
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
10% 10V 402
1
GATE_NODE=TRUE
MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM
SWITCH_NODE=TRUE
CPUIMVP_PH1_SNUB
G
5
10.2
1% 1/16W MF-LF 402 2
DIRECTFET-MX
1% 1/16W MF-LF
376S0930
3
IN
CPUIMVP_BOOT2
IN
CPUIMVP_UGATE2
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
2 402
67 68
67
NOSTUFF 1
0.22UF
67
C7571
10% 10V 402
1
5
C7528
G
1 3
3
C7529 0.001UF 10% 50V 402
2 X7R
CPUIMVP_ISNS2_P
1
R7524
DIRECTFET-MX
50V 2 CERM 402
10.2 1% 1/16W MF-LF
2 402
CPUIMVP_ISUM_N
DIDT=TRUE
NOSTUFF
Q7525
C7522
67 68
NOSTUFF 1
C7572 330PF 10% 50V 402
2 CERM
4
376S0930
CPUIMVP_ISUM2_P CPUIMVP_ISUM1_P
86 72 71 69 67 64 53 51 46 41 22 8 7 6 101 88
THESE TWO CAPS ARE FOR EMC
CRITICAL
Q7530 IRF6710
376S0772
PHASE 3
PP5V_S0
1
S1
20% 2 16V POLY-TANT CASE-D2E-SM
2 5
4
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
10% 2 16V X5R 402
5
R7547 10K
5% 1/16W MF-LF 2 402
VDD
R7531
67
IN
TQFN
PWN
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
CRITICAL DH 8
PIMA104E-SM 67 49
DIDT=TRUE
1
GATE_NODE=TRUE
2 6
MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM
THRM PAD
CPUIMVP_LGATE3
C7538
DIRECTFET-MX
376S0930
C7539 0.001UF
10% 2 50V X7R 402
10%
2 50V X7R
6 7 12 14 48 68 101
CPUIMVP_ISNS3_N
R7534 10.2 1% 1/16W MF-LF
2 402
CPUIMVP_ISUM_N
C7532
67 68
NOSTUFF
2 50V CERM 402
1
C7573 330PF 10% 50V 402
4
2 CERM
CPUIMVP_ISUM3_P
CRITICAL
B
1
C7561 68UF
69 68 67 66 64 49 7
C
402
1
DIDT=TRUE
NOSTUFF
S 3
1
0.001UF
IRF6798MTRPBF 0.001UF 10%
G
DIDT=TRUE GATE_NODE=TRUE
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
49
1% 1/16W MF-LF 402 2
CPUIMVP_PH3_SNUB 1
Q7535 5
1
PPVCORE_S0_CPU
2 4
46.4
CRITICAL
SWITCH_NODE=TRUE
1 3
R75331
7
D
1% 1W MF 0612
CPUIMVP_ISNS3_P
2.2
5% 1/10W MF-LF 603 2
DIDT=TRUE
1UF
R7530
152S1019
1
R7532
CPUIMVP_PHASE3
9
3
GND
NOSTUFF
10% 10V 2 CERM 402
C7537
0.00075
PPVCORE_S0_CPU_PH3_L
0.22UF
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
DL 4
10UF
0.36UH-20%-40A-0.00075OHM 1 2 PPVCORE_S0_CPU_PH3
C7531
1
C7536
10% 10% 10% 16V 16V 2 16V X5R-CERM 2 X5R-CERM 2 X5R 0805 0805 402
CRITICAL
CPUIMVP_UGATE3
LX 7
10UF
L7530
CPUIMVP_BOOT3
BST 1
SKIP*
1
0
5% 1/16W MF-LF 402 2
MAX17491
20% 2 16V POLY-TANT CASE-D2E-SM
CRITICAL 1
SWITCH_NODE=TRUE
1
U7541 CPUIMVP_PWM3 2 CPUIMVP_SKIP 6
68UF
C7535
CRITICAL
S
1UF
1
C7534
CRITICAL 1
6
G
3
DIDT=TRUE
C7541
C7533
CRITICAL 1
68UF
1
D
CPUIMVP_BOOT3_RC 1
67
67
CRITICAL
C
6 7 12 14 48 68 101
CPUIMVP_ISNS2_N
49
1% 1/16W MF-LF 402 2
CPUIMVP_PH2_SNUB 1
D
PPVCORE_S0_CPU
2 4
46.4
S
1
0.001UF
10% 50V 2 X7R 402
IRF6798MTRPBF 0.001UF 10%
DIDT=TRUE GATE_NODE=TRUE
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
1% 1W MF 0612
R75231
7
1
CRITICAL
67 49
CRITICAL
SWITCH_NODE=TRUE
10% 2 50V CERM 402
4
2 6
D
1UF
R7520
2.2
DIDT=TRUE
C7527
0.00075
5% 1/10W MF-LF 603 2
CPUIMVP_LGATE2
IN
330PF
10UF
CRITICAL
152S1019
R75221
2 CERM
1
C7526
10% 10% 10% 16V 16V 2 X5R-CERM 2 X5R-CERM 2 16V X5R 0805 0805 402
PIMA104E-SM
NOSTUFF
DIDT=TRUE GATE_NODE=TRUE
MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM
20% 2 16V POLY-TANT CASE-D2E-SM
L7520
C7521
CPUIMVP_PHASE2
IN
10UF
68UF
0.36UH-20%-40A-0.00075OHM 2 PPVCORE_S0_CPU_PH2
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
CPUIMVP_ISUM_N
C7512
2 50V CERM 402
S
1
0
5% 1/16W MF-LF 402 2
R7514
C7524
CRITICAL 1
C7525
PPVCORE_S0_CPU_PH2_L 1
R7521
1
DIDT=TRUE
NOSTUFF 1
DIRECTFET-MA
DIDT=TRUE
PPVCORE_S0_CPU
CRITICAL 1
IRF6723M2DPBF S
1
12 14 48 68 101 6 7
CPUIMVP_ISNS1_N
49
C7523
20% 2 16V POLY-TANT CASE-D2E-SM
Q7510 G
2
CRITICAL 1
68UF
CRITICAL
D
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
2 4
46.4
CRITICAL
7
1
1 3
CPUIMVP_ISNS1_P
8
376S0872
PHASE 2
10% 50V 2 X7R 402
CPUIMVP_BOOT2_RC
1% 1W MF 0612
R75131
6 7
0.001UF
10% 50V 2 X7R 402
IRF6798MTRPBF 0.001UF 10%
DIDT=TRUE GATE_NODE=TRUE
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
67 49
Q7515
CPUIMVP_LGATE1
IN
2
D DIDT=TRUE
0.001UF
1
C7519
0.00075
5% 1/10W MF-LF 603 2
DIDT=TRUE
1
C7518
CRITICAL
2.2
CPUIMVP_PHASE1
1UF
1
R7510
152S1019
R75121
2 CERM
C7517
10UF
PIMA104E-SM
NOSTUFF
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
67
C7511
CRITICAL 1
C7516
10% 10% 10% 16V 16V 2 16V X5R-CERM 2 X5R-CERM 2 X5R 0805 0805 402
L7510
0.22UF
5% 1/16W MF-LF 402 2
67
20% 2 16V POLY-TANT CASE-D2E-SM
PPVCORE_S0_CPU_PH1_L 1
R7511
67 6
10UF
68UF
THESE TWO CAPS ARE FOR EMC
CRITICAL 1
0.36UH-20%-40A-0.00075OHM 2 PPVCORE_S0_CPU_PH1
4 1
CPUIMVP_BOOT1
C7514
C7515
CRITICAL
DIDT=TRUE
D
CRITICAL 1
IRF6723M2DPBF
G
3
C7513
CRITICAL 1
20% 2 16V POLY-TANT CASE-D2E-SM
PPVIN_S5_HS_COMPUTING_ISNS
CRITICAL 1
C7562
CRITICAL 1
68UF
C7563 68UF
20% 20% 2 16V 2 16V POLY-TANT POLY-TANT CASE-D2E-SM CASE-D2E-SM
CRITICAL 1
C7564 68UF
20% 2 16V POLY-TANT CASE-D2E-SM
67
CRITICAL 1
C7565 68UF
20% 2 16V POLY-TANT CASE-D2E-SM
CRITICAL 1
C7566
CRITICAL 1
68UF
20% 2 16V POLY-TANT CASE-D2E-SM
C7567 68UF
CRITICAL 1
C7568 68UF
20% 20% 2 16V 2 16V POLY-TANT POLY-TANT CASE-D2E-SM CASE-D2E-SM
CRITICAL 1
B
C7569 68UF
20% 2 16V POLY-TANT CASE-D2E-SM
THESE TWO CAPS ARE FOR EMC
CRITICAL 1
C7553 68UF
AXG PHASE
20% 2 16V POLY-TANT CASE-D2E-SM
CRITICAL 1
C7554 68UF
CRITICAL 1
C7555 10UF
CRITICAL 1
C7556 10UF
1
C7557 1UF
67
IN
2
CPUIMVP_BOOT1G
C7551
R7555 67
67
IN
IN
CPUIMVP_UGATE1G MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE GATE_NODE=TRUE
CPUIMVP_PHASE1G MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM
A
67
IN
5% 1/16W MF-LF 402
2
SON5X6
CPUIMVP_UGATE1G_R MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE GATE_NODE=TRUE
Additonal Input Bulk Caps
0.001UF 10%
2 50V X7R
402
5 BG
0.00075
L7550
0.36UH-20%-40A-0.00075OHM 1 2 PPVCORE_S0_AXG_L1 CPUIMVP_VSWG MIN_LINE_WIDTH=0.5 MM PIMA104E-SM 3 MIN_NECK_WIDTH=0.25 MM 152S1019 NOSTUFF SWITCH_NODE=TRUE 1 98 49 CPUIMVP_ISNS1G_P R7552 2.2 1 5% 1/10W MF-LF 2 603
PGND
376S0906
R7553 46.4
1% 1/16W MF-LF 402 2
CPUIMVP_AXG_SNUB
DIDT=TRUE SWITCH_NODE=TRUE
NOSTUFF 1
2 4
PPVCORE_S0_AXG
7 12 13 15 48
CPUIMVP_ISNS1G_N
98 49
1
R7554 10.2 1% 1/16W MF-LF
2 402
CPUIMVP_ISUMG_N
0.001UF
DIDT=TRUE GATE_NODE=TRUE
1% 1W MF 0612
DIDT=TRUE
C7552
10% 50V 2 CERM 402
CPUIMVP_LGATE1G MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
C7559
R7550
CRITICAL
VIN 1 VSW 6 7 8
4 TGR
10% 10V CERM 2 402
DIDT=TRUE
4.7
1
0.22UF
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
1
3 TG
CPUIMVP_BOOT1G_R MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE
5% 1/16W MF-LF 402
1
CRITICAL
Q7550 CSD58864Q5D
9
0
1
C7558
10% 2 50V X7R 402
CRITICAL
R7556
1
0.001UF
10% 10% 10% 20% 16V 16V 2 16V 2 16V X5R-CERM 2 X5R-CERM 2 X5R POLY-TANT 0805 0805 402 CASE-D2E-SM
67
SYNC_MASTER=K91_ERIC
NOSTUFF 1
CPU IMVP7 & AXG VCore Output
330PF 10%
DRAWING NUMBER
50V 2 CERM
Apple Inc.
402
CPUIMVP_ISUMG_P
7
6
5
4
SIZE
D REVISION
R 67
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
SYNC_DATE=09/22/2010
PAGE TITLE
C7574
3
2
BRANCH
PAGE
75 OF 132 SHEET
68 OF 101
1
A
8
7
6
5
4
3
2
1
D
D
CPU VCCIO (1.05V S0) Regulator
68 67 66 64 49 7 86 72 71 68 67 64 53 51 46 41 22 8 7 6 101 88
PPVIN_S5_HS_COMPUTING_ISNS PP5V_S0 CPUVCCIOS0_BOOT_RC
CRITICAL 1
R76011
20% 2 10V X5R 603
5% 1/10W MF-LF 603 2
90 12
CPU_VCCIOSENSE_N
1% 1/16W MF-LF 402 2
R7644 72
72
CPUVCCIOS0_EN
IN
OUT
2.74K
1% 1/16W MF-LF 402 2
R7645 2.74K
1% 1/16W MF-LF 2 402
C7602 1 2.2UF
C7604
B
10% 16V 2 X5R 603
47PF
1
5% 50V CERM 2 402
1
C7605 47PF
5% 2 50V CERM 402
1
PHASE 10
CPUVCCIOS0_LL
VO
LGATE 15
4
CPUVCCIOS0_VO
8
CRITICAL
CPUVCCIOS0_OCSET
7
OCSET
CPUVCCIOS0_PGOOD
9
PGOOD
RJK0365DPA-01 WPAK
CRITICAL 0.001
L7630
0.68UH-22A-2.7MOHM 1 2 PPCPUVCCIO_S0_REG_R 2
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE
CPUVCCIOS0_DRVL
FSEL
R7603
R7640
CRITICAL
1 2 3
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V
PIMB104T-SM
5
GND
PGND
0
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE
4
4
1% 1W MF-1 0612
PP1V05_S0 1 3
NO STUFF CRITICAL
C7649 20% 2V TANT CASE-B4-SM
C7623 1 1000PF
RJK0208DPA
G
5% 25V NP0-C0G 2 402
WPAK
1
0.047UF
2
C7648
2
1
R7641
XW7600 SM 1
Vout = 1.05V 21A Max Output f = 300 kHz
44 20 10 14 23 72
270UF 1 2 3
C7603 CPUVCCIOS0_AGND
101 35 39 16 17 6 7 9 12 13 22 67
NO STUFF CRITICAL
S
5% 1/16W MF-LF 2 402
10% 2 16V X7R 402
1
270UF
PLACE_NEAR=L7630.2:1.5mm
CRITICAL
Q7635
RTN
C
Q7630
4
D
1
5% 2 25V NP0-C0G 402 PLACE_NEAR=Q7630.1:1.5mm
5
CPUVCCIOS0_DRVH
SREF
CPUVCCIOS0_SREF
5
BOOT 12
C7622 1000PF
68UF
CRITICAL
UGATE 11
FB
2
1UF
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE
CPUVCCIOS0_FB
CPUVCCIOS0_FSEL
1
UTQFN
EN
6
CPUVCCIOS0_RTN
R76051
3
C7630
10% 2 16V X5R 402
1
C7621 1
20% 20% 16V 16V 2 POLY-TANT 2 POLY-TANT CASE-D2E-SM CASE-D2E-SM
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE
ISL95870
1% 1/16W MF-LF 2 402
R76301
CPUVCCIOS0_VBST
U7600
3.01K
16
3.01K
1
PVCC
1
R76041
1
2.2
VCC
CRITICAL
C7620 1 68UF
5% 1/10W MF-LF 603 2
PP5V_S0_CPUVCCIOS0_VCC MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V
14
CPU_VCCIOSENSE_P
13
90 12
CRITICAL
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE
10UF
2.2
C
C7601
98 48
CPUVCCIOS0_CS_P
98 48
CPUVCCIOS0_CS_N
20% 2V TANT CASE-B4-SM
B
3.01K
1% 1/16W MF-LF 402 2
2
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
C7640 1000PF 2
PLACE_NEAR=U7600.1:1mm
1
5% 25V NP0-C0G 402
1
R7642 3.01K
1% 1/16W MF-LF 2 402
(CPUVCCIOS0_OCSET) (CPUVCCIOS0_VO)
OCP = R7641 x 8.5uA / R7640 OCP = 25.6A Vout = 0.5V * (1 + Ra / Rb)
A
SYNC_MASTER=K91_ERIC
SYNC_DATE=10/08/2010
PAGE TITLE
CPU VCCIO (1.05V) Power Supply DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
76 OF 132 SHEET
69 OF 101
1
A
8
98 89 85 82 72 23 22 20 19 17 7 6 71 70 65 55 45 39 29 25 24
7
6
5
4
3
2
1
1.8V S0 Regulator
PP3V3_S5
22UF
20% 6.3V CERM 2 805
5% 25V NP0-C0G 2 402
152S1302
VDD
1 VIN 2
C7720 1
1
1000PF
3
CRITICAL
C7724
L7720 1.0UH-7A
U7720
D
PIMB053T-SM
ISL8014A 72
72
P1V8S0_EN
IN
OUT
QFN
5 EN
P1V8S0_PGOOD
7 PG
P1V8S0_SW
LX 14 LX 15
CRITICAL 17 THRM_PAD
11 12 PGND
9 10 SGND
PP1V8_S0 2
CRITICAL
CRITICAL 1
P1V8S0_FB
VFB 8 4 SYNCH
1
SWITCH_NODE=TRUE DIDT=TRUE
16 6 NC 13
C7723 47PF
R7720
NC NC NC
113K
1
C7721 22UF
5% 50V 2 CERM 402
1
20% 6.3V 2 CERM 805
6 7 14 17 20 22 25 71 87
D
Vout = 1.794V Max Current = 4A Freq = 1 MHz
1% 1/16W MF-LF 402 2
1.05V SUS LDO
Cougar Point-M requires JTAG pull-ups to be powered at 1.05V in Sus. Pull-ups (3) must be 51 ohms to support XDP (not required in production). 70mA is required to support pull-ups. Alternative is strong voltage dividers (200/100) to 3.3V Sus, which burns 100mW in all S-states.
CRITICAL
R77211
C7722 1
90.9K
CRITICAL XDP_PCH
22UF
1% 1/16W MF-LF 402 2
20% 6.3V CERM 2 805
U7740 72 71 45 22 20 19 18 17 16 7
TPS720105 SON
PP3V3_SUS
PP1V05_SUS
4 BIAS
Vout = 0.8V * (1 + Ra / Rb)
3 EN
NC 2
XDP_PCH
C7740 1 1UF
NC
XDP_PCH
THRM PAD 7
GND 5
1
C7741 2.2UF
10% 6.3V 2 CERM 402
C
7 23
Vout = 1.05V Max Current = 0.35A
OUT 1
6 IN
10% 2 6.3V X5R 402
C
1.5V S0 Regulator 98 29 25 24 23 22 20 19 17 7 6 89 85 82 72 71 70 65 55 45 39
PP3V3_S5 CRITICAL 1
1
C7750 22UF
VIN
U7710
2
ISL8009B
20% 6.3V CERM 805
CRITICAL
L7770 2.2UH-3.25A
DFN 72
72
IN
P1V5S0_EN
OUT
P1V5S0_PGOOD
2
EN
CRITICAL
LX
8
3
POR
VFB
6
4
SKIP
RSI
5
GND 7
1V5_S0_SW
1
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE
PP1V5_S0
Vout = 1.508V
IHLP1616BZ-SM 1
C7776
1
5% 50V CERM 402
THRM_PAD 9
Max Current = 0.8A
R7780 100K
47PF
353S2535
7 16 20 22 25 41 56
2
2 2
Freq = 1.6MHZ
1% 1/16W MF-LF 402
CRITICAL
1V5_S0_FB
1
C7771 22UF
1
2
R7781
20% 6.3V CERM 805
CAESAR IV 1.2V INT.VR CMPTS
113K
2
CRITICAL
1% 1/16W MF-LF 402
L7730
4.7UH-0.8A
72 36 25 7 6
B
PP3V3_ENET
ENET_SR_LX
1 2 PCAA031B-SM
Vout = 0.8V * (1 + Ra / Rb) 1
C7737 4.7UF 20%
2 6.3V X5R 402
1
36
B
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V SWITCH_NODE=TRUE DIDT=TRUE
C7738 0.1UF 10%
2 16V X5R 402
PP1V2_ENET
6 7 36 70
PP1V2_ENET
6 7 36 70
CRITICAL
CRITICAL 1
C7760
1
4V X5R 402
2
10UF 20%
2
CRITICAL
152S0771 CRITICAL
U7760
2.2UH-1.2A
SC194A
PCAA031B-SM
5% 1/16W MF-LF 402
0.1UF
L7760
MLP10
LX 10
1 VIN 72
IN
4 EN
P1V2S0_EN
P1V2S0_SYNC_PWM
353S2719
VOUT 5
P1V2S0_SW MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm
R7761
PP1V2_S0
2
XW7761 SM P1V2S0_FB
7 VID1
0
1
SWITCH_NODE=TRUE DIDT=TRUE
3 SYNC/PWM 6 VID0
1
1
CRITICAL 1
PLACE_NEAR=L7760.2:1MM
2 MODE
7
PGND
SYNC_MASTER=K91_ERIC
SYNC_DATE=11/01/2010
PAGE TITLE
Misc Power Supplies DRAWING NUMBER
20% 6.3V CERM 805
Apple Inc.
THRM
NOTICE OF PROPRIETARY PROPERTY:
PAD
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
6
SIZE
D REVISION
R
11
8
GND
C7761
6 7 87
Vout = 1.2V MAX CURRENT = 0.7A FREQ = 1MHZ
22UF
2 2
5% 1/16W MF-LF 402
8
C7736
10% 2 16V X5R 402
16V X5R 402
0
2
2 4V X5R 402
1
0.1UF 10%
R7760
A
C7735 10UF 20%
C7764
1 NO STUFF
2
1
1.2V S0 (GMUX) Regulator
PP3V3_S5
9
98 89 85 82 72 24 23 22 20 19 17 7 6 71 70 65 55 45 39 29 25
5
4
3
2
BRANCH
PAGE
77 OF 132 SHEET
70 OF 101
1
A
8
7
6
5
4
3
2
1
R7803 0
1
376S0945
CRITICAL
Q7820
CRITICAL
SIA427DJ
NOSTUFF
1
D
SIA427DJ
PP3V3_S5
S
98 29 25 24 23 22 20 19 17 7 6 89 85 82 72 71 70 65 55 45 39
7
SC70-6L
Q7800
4
3.3V S4 FET
3.3V_SUS FET
2
5% 1/16W MF-LF 402
PP3V3_SUS
7 16 17 18 19 20 22 45 70 72
R7802
D
5% 1/16W MF-LF 402
SOT563
2 72
IN
G
NOSTUFF
2
2
10% 16V X5R 402 2
C7800 0.01UF P3V3S3_S4
2
1
5 G
MOSFET
SiA427
CHANNEL
P-TYPE 8V/5V
RDS(ON)
26 mOhm @1.8V
LOADING
0.7? A (EDP)
72 71
2
IN
G 2
C7820
R7820 P3V3SUS_EN_L
S 4
3.3V SUS FET
3
D
3.3V S4 FET NOSTUFF
5.1K 1
5% 1/16W MF-LF 402
1
0.033UF
100K
SOT563
R7800 P3V3S4_EN_L
S
10% 16V X5R 402
D 3
Q7802 SSM6N15FEAPE
0.033UF
220K
SSM6N15FEAPE
7 45 52 53
1
G
Q7802
C7809
C7821
R7822 1
3
D
PP3V3_S4
NOSTUFF
NOSTUFF1 6
1
4
PP3V3_S5
S
7
SC70-6L 98 29 25 24 23 22 20 19 17 7 6 89 85 82 72 71 70 65 55 45 39
12K
1
PM_SUS_EN
0.01UF 1
P3V3SUS_SS
2
5% 1/16W MF-LF 402
10% 16V CERM 402
1
P3V3_S4_EN
5% 1/16W MF-LF 402
10% 16V CERM 402
2
5V_SUS FET
D
MOSFET
SiA427
CHANNEL
P-TYPE 8V/5V
RDS(ON)
26 mOhm @1.8V
LOADING
100? mA (EDP)
CRITICAL
Q7840 SIA413DJ
7
C7810
R7810 P3V3S3_EN_L
S 1
0.01UF
47K 1
P3V3S3_EN
P3V3S3_SS
2
1
5% 1/16W MF-LF 402
C
1
D G
2
72 71
IN
G
2
10% 16V CERM 402
MOSFET
SiA427
CHANNEL
P-TYPE 8V/5V
RDS(ON)
26 mOhm @1.8V
LOADING
3 A (EDP)
1
3.3K
PM_SUS_EN
1
C7840
R7840 P5VSUS_EN_L
S 2
5V SUS FET 0.01UF
P5VSUS_SS
2
1
5% 1/16W MF-LF 402
2
10% 16V CERM 402
3.3V S0 FET
Q7830
1
X5R
2
IN
PM_SLP_S3_R_L
G
S
1
S
6 8
SIA427DJ
S
1
SC70-6L
2
PP1V5_S3RS0_CPUDDR 7
3
10 13 15 29 72
98 29 25 24 23 22 20 19 17 7 6 89 85 82 72 71 70 65 55 45 39
PP3V3_S5
B
89
MOSFET
SI7108DN
CHANNEL
N-TYPE
1UF 10% 10V X5R 402
2
6 mOhm @4.5V
LOADING
5 A (EDP)
1
Q7872 SSM3K15FV
PP3V3_S0
89 87
D 3
13
P1V8GPU_EN
PP3V3_S0
R_BLEED EN
17
C_DELAY
NO STUFF
NC
1
GND
2
NO STUFF
PP1V8_GPUIFPX
0.11A (EDP)
B
CRITICAL
PP5V_S0
6 7 8 22 41 46 51 53 64 67 68 69 72 86 88 101
S
PP5V_S3
5.0V S0 FET
5
2
18 mOhm @4.5V
D
100 81 66 65 45 43 42 41 31 29 7 6
R7862
2.4A (EDP)
LOADING
1
C7861
220K 5% 1/16W MF-LF 402
PP1V8_S0 input side
2
R7860
6 7 14 17 20 22 25 70 87
10K
P5V0S0_EN_L
14 18
1
D
71 65 53 7 6
PP5V_S5
1
2
P-TYPE
RDS(ON)
5.5 MOHM @4.5V
LOADING
8 A (EDP)
20V/12V
2
C7860 0.01UF P5V0S0_SS
2
1
10% 16V CERM 402
3
SYNC_MASTER=K91_MARY
SYNC_DATE=10/14/2010
PP5V_S5_P5VSUSFET_R
Power FETs
71
1
PLACE_NEAR=Q7840.4:5mm
6
SI7615DN
CHANNEL
PAGE TITLE
5% 1/16W MF-LF 402
6 7 71 100
10% 16V X5R 402
MOSFET
SOD-VESM-HF
R7843 0
2 5% 1/16W MF-LF 402
Q7865 SSM3K15FV
1
0.033UF
C7843
1
72 71 48
IN
G
S
DRAWING NUMBER
2
PM_SLP_S3_R_L
Apple Inc.
2.2UF 20% 10V X5R-CERM 402
5
SIZE
D REVISION
R
2
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
U7880 default Turn on delay EN--> on is 200~650us.
7
PWRPK-1212-8
1
4 5 9 10 11 12
Q7860 SI7615DN
5.0V S0 FET
NO STUFF
8
LOADING
S 2
3
N-TYPE
THRM PAD
1000PF 5% 25V NP0-C0G 402
1 G
5V_SUS FET inuot filter
2
C7882
CHANNEL
C_SR
3
20% 10V CERM 402
DRAIN
EN_POL_CTRL
1
GPUFET_C_SR
SOURCE
16
NCP4543
19
0.1UF
CRITICAL
15
GPUFET_C_DELAY
A
2
10% 16V CERM 402
G
6 7 8
MOSFET
RDS(ON)
QFN
1
26 mOhm @1.8V
4
2
VCC
PP1V8_GPUIFPX load side
C7881
1
1.8V GPU FET
353S3256
U7880
IN
P-TYPE 8V/5V
RDS(ON)
P3V3GPU_EN
2
NCP4543IMN5RG-A
89
0.01UF
P3V3GPU_SS
2
SiA427
CHANNEL
1
0.1UF
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
IN
1K
MOSFET
C7870
5% 1/16W MF-LF 402
SOD-VESM-HF
1.8V GPU FET
2
R7870 P3V3GPU_EN_L
RDS(ON)
1
G
4
9
5% 1/16W MF-LF 402
1.5V S3/S0 FET TP_P1V5S3RS0_RAMP_DONEOUT
100 71 7 6
6 7 74 78 79 81 83
3.3V S0 GPU FET C7871
R7872 1 51K
20% 10V CERM 402
PP3V3_S0GPU
THRM PAD
GND
PLACE_NEAR=U7880.2:2.54mm
Q7870
PWRPK-1212-8-HF
3
2
5% 1/16W MF-LF 402
5.6 A (EDP)
CRITICAL
3.3V S0 GPU FET
SI7108DN
G
P1V5S3RS0FET_GATE_R
PG
402
Q7801
2
7
7 P1V5S3RS0FET_GATE1
5.5 mOhm @4.5V
LOADING
2
1
1UF
G
4
P-TYPE 20V/12V
RDS(ON)
10% 16V CERM 402
S
SHDN*
R7801 0
SI7615DN
CRITICAL
D
D 5
1
P3V3S0_SS
5% 1/16W MF-LF 402
4
TDFN
CRITICAL
C7802 1
C7880
0.01UF
2
4
MOSFET CHANNEL C7830
R7830
APN 376S0651
5
NO STUFF
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
2
402
D
VCC
ON
3.3V S0 FET
G
10% 16V
U7801 3
X5R
1
33K
2
10% 10V
5
2 5% 1/16W MF-LF 402
P3V3S0_EN_L 5 72 71 48
P1V5CPU_EN
IN
C7831
1
SLG5AP020 29
C 48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98
PP3V3_S0
0.033UF
47K
3
SOT563
2
2 mA (EDP)
1
D
SSM6N15FEAPE
20% 10V CERM 402
29 mOhm @4.5V
LOADING
4
Q7812
PP1V5_S3
0.1UF
RDS(ON)
CRITICAL
PP3V3_S5
R7832 1
PP5V_S5 C7801
P-TYPE 12V
SI7615DN
1.5V S3/S0 FET 66 29 28 26 7 6
SiA413
CHANNEL
PWRPK-1212-8
98 29 25 24 23 22 20 19 17 7 6 89 85 82 72 71 70 65 55 45 39
71 65 53 7 6
MOSFET
D
2
1
3.3V S3 FET
2
2
S
2 G IN
10% 16V X5R 402
10% 16V X5R 402
3
SOT563
72
C7811
S
4 5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
6 7 8 18 19 24 25 29 30 31 32 47 48 49 53 54 72 87
1
0.033UF
100K
SSM6N15FEAPE
PP3V3_S3
0.033UF
220K
3
R7812
D 6
Q7812
1
D 3
SOD-VESM-HF
7 22
1
G
SSM3K15FV
SC70-6L PP3V3_S5
C7841
R7842 1
PP5V_SUS
3
Q7842
SIA427DJ
D
CRITICAL
Q7810 98 29 25 24 23 22 20 19 17 7 6 89 85 82 72 71 70 65 55 45 39
S
PP5V_S5_P5VSUSFET_R
4
3.3V S3 FET
7
SC70-6L 71
4
3
2
BRANCH
PAGE
78 OF 132 SHEET
71 OF 101
1
A
5
4
State
S5 Rail Enables & PGOOD
SMC_PM_G2_ENABLE
Sleep (S3) Deep Sleep (S4) 72 65 44
OUT
72 65 44
IN
R7940
SMC_PM_G2_EN
SMC_PM_G2_EN
100
1
MAKE_BASE=TRUE
Deep Sleep (S5)
2
72 65
P3V3S5_EN
P3V3S5_EN
OUT
MAKE_BASE=TRUE
5% 1/16W MF-LF 402
Battery Off (G3Hot)
65 72
PM_SLP_S5_L
1
Run (S0)
3
PM_SLP_S4_L
1
PM_SLP_S3_L
1
1
1
1
0
0
1
1
0
0
1
0
0
0
0
0
0
0
1
72 65 44 42 29 17
IN
(PM_SLP_S4_L)
PM_SLP_S4_L
R7911
2
PM_SLP_S4_L:100K pull down in PCH page
5.1K 1
PP3V42_G3H
52 47 46 45 44 42 25 7 6 72 63 62
PLACE_NEAR=U7300.16:6mm 1
3.3V/5.0V S4 ENABLE
1
NO STUFF
2
NOSTUFF
100K 44 17
0
1
72
2 71 P3V3_S4_EN
5% 1/16W MF-LF 402
S5_PWRGD (old name RSMRST_PWRGD)-->SMC 65 SMC-->PM_DSW_PWRGD
44 72
OUT
PM_SLP_S5_L
IN
P3V3_S4_EN
OUT
98 29 25 24 23 22 20 19 17 7 6 89 85 82 72 71 70 65 55 45 39
72 44 29 17 6
2
CPUIMVP_VR_ON
U7940 74AUP1G3208 SOT891
CPUVCCIOS0_PGOOD
0
PP3V3_S5
98 89 85 82 29 25 24 23 22 20 19 17 7 6 72 71 70 65 55 45 39
1
72 71
PM_SUS_EN
PM_SUS_EN PM_SUS_EN
OUT
71 72
OUT
71 72
62 7245 4742 7 6 4625 6344 52
PM_PECI_PWRGD OUT
2
4
7
5% 1/16W MF-LF 402
70 45 22 20 19 18 17 16 72 71
Q4
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
Sus_PGOOD_CT 4 CT
353S2809
1
S0PGD_BJT_GND_R
100
65
1% 1/16W MF-LF 402 2
R7971 S0PGOOD_ISL 10K R79731 1% 1/16W MF-LF 402
8
15.0K
2
1% 1/16W MF-LF 402
U7960 ISL88042IRTEZ TDFN
(IPU)
PVCCSA_PGOOD 64
IN
V2MON MR* CRITICAL V3MON V4MON
SOT23-6
8
RST*
7
100
1
MR* 3
OUT
2
2
0.47UF
10% 6.3V CERM-X5R 402
10% 6.3V CERM-X5R 402
2
Q7922
NTR4101P PP3V3_ENET 6 32 31 30 29 25 24 19 18 8 7 6 87 71 54 53 49 48 47
PP3V3_S3
2
R79211
1
S
C7921
5% 1/16W MF-LF 402 2
10% 2 16V X5R 402
R7922 1
D
1
C7922 0.01UF
100K 2
P3V3ENET_SS
2
1
10% 16V CERM 402
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
Q7921 SSM3K15FV
7 25 36 70
3
G
0.033UF
10K
D 3
SOD-VESM-HF
PM_WLAN_EN_L
R7966 1
100
72 44 29 17 6
IN
1
PM_SLP_S3_L
2 85 72 45 44
SMC_S4_WAKESRC_EN MAKE_BASE=TRUE
SMC_S4_WAKESRC_ENOUT
Q7925
44 45 72 85
100
IN
WOL_EN
SOT-363 5
31
OUT
6
Q7925
D
S G
2N7002DW-X-G G
SOT-363 2
AP_PWR_EN
IN
18 31
S 1 4
2
(AC_EN_L)
AC_EN_L
Q7920
5% 1/16W MF-LF 402
2N7002DW-X-G 6 SOT-363
45 44 17 23 44 72 87 89
IN
SMC_ADAPTER_EN
2
G
R79291
S 1
SYNC_MASTER=K91_MARY
SYNC_DATE=07/22/2010
PAGE TITLE
NO STUFF
0
5% 1/16W MF-LF 402 2
Power Control 1/ENABLE
3
Q7920
D
2N7002DW-X-G
DRAWING NUMBER
SOT-363 5
(PM_SLP_S3_L)
G
Apple Inc.
S
5% 1/16W MF-LF 402
5
4
3
SIZE
D REVISION
R
4
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
ALL_SYS_PWRGD
6
S 2
D
2N7002DW-X-G
R7964 1
G
3
5% 1/16W MF-LF 402
19
2
B
SOT-23-HF
PM_RSMRST_L goes to U1800.C21
R7962 1
C7986
1
0.47UF
10% 6.3V 2 CERM-X5R 402
10% 6.3V CERM-X5R 402
PLACE_NEAR=U7720.5:6mm
C7988
6 17
S0PGOOD_ISL 330
1
3.3V ENET FET
D
353S2310
2
C7985 1UF
0.47UF
10% 6.3V CERM-X5R 402
PLACE_NEAR=U7710.2:6mm
PLACE_NEAR=U7760.4:6mm
1
CRITICAL PM_RSMRST_L
5% 1/16W MF-LF 402
ALL_SYS_PWRGD_R 2
C7931
OUT
THRM_PAD
C7981
64 72
2
2
R7963 1 NC
GND
100 5% 1/16W MF-LF 402
IN
VDD
9
15.0K
100 5% 1/16W MF-LF 402
1
OUT
C
S 2
5% 1/16W MF-LF 402 2
R7968 1
CPUVCCIOS0_PGOOD 72 69
0.47UF
10K
P5VS3_PGOOD
1
5% 1/16W MF-LF 402
IN
IN
C7987
PM_SLP_S3_ENET
R7965
2 7
3 5 PP1V5_DIV_VMON S0PGOOD_ISL R79611S0PGOOD_ISL PP1V05_VID_VMON6 1 PP5V_DIV_VMON
69 72
PVCCSA_EN
PLACE_NEAR=U7100.15:6mm PLACE_NEAR=U7600.3:6mm
63
R79671
P1V5S0_PGOOD
IN
PVCCSA_EN
PP3V3_S0
P1V8S0_PGOOD
R7972
1% 1/16W MF-LF 402 2
70 72
CPUVCCIOS0_EN OUT
ENET Enable Generation
NO STUFF
P1V5S0_PGOOD from U7710 70
G
5% 1/16W MF-LF 402 2
PP3V3_S0
6.04K
70 72
OUT
MAKE_BASE=TRUE
2
5% 1/16W MF-LF 402 2
0.001UF
R79571
Version in development) 70
72 64
D 3
100K
20% 2 50V CERM 402
Worst-Case Thresholds:
4
10K
1% 1/16W MF-LF 402 2
OUT
7 16 17 18 19 20 22 45 70 71 72
GND
VMON_Q4_BASE
PP5V_S0 S0PGOOD_ISL S0PGOOD_ISL PP1V5_S3RS0_CPUDDR C7960 1 PP1V05_S0 S0PGOOD_ISL 1 0.1uF R7960 S0PGOOD_ISL 20% 10V 1 6.04K R7970 S0PGOOD_ISL CERM 2 1% 402 1 1/16W MF-LF 402 2
U7930
RESET* 1
TPS3808G33DBVRG4
S0 Rail PGOOD Circuitry
101 86 67 46 6 22 53 6929 15 13 10 7 72 71
5 SENSE
7 PP3V3_SUS
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
88 68 51 8 7 41 64 71
P1V5S0_EN P1V2S0_EN
R79331
20% 10V CERM 2 402
VDD
Q2: 0.XXXV Q3: 0.640V 3.3V w/Divider: 2.345V Q4: 0.660V
Thresholds: (ISL VDD: 2.734V-3.010V V2MON: 2.815V-3.099V V3MON: 0.572V-0.630V V4MON: 0.572V-0.630V
PP3V3_SUS
2
PP1V05_S0
2
70 72
VFRQ Low: Fix Frequency VFRQ High: Variable Frequency
0.1uF
CRITICAL
3
35 23 22 20 17 16 14 13 12 10 9 7 6 101 72 69 67 44 39
1K
OUT
C7930
CRITICAL
2
NC
5% 1/16W MF-LF 402
SOD-VESM-HF
PLACE_NEAR=U7930.6:2.3mm 1
R7955 1
P1V8S0_EN
PP3V3_S5
No stuff C7931, 12ms Min delay time U7930 Sense input threhold is 3.07V
ASMCC0179
Q3
1
B
98 29 25 24 23 22 20 19 17 7 6 89 85 82 72 71 70 65 55 45 39
DFN2015H4-8
8
NC VMON_Q3_BASE
5% 1/16W MF-LF 402
PP1V5_S3RS0
Q2
CPUVCCIOS0_EN MAKE_BASE=TRUE
1
SSM3K15FV
6
6
Q1
2
48 71 72
23 44 72 87 89
Q7950 5
72 69
CHGR_VFRQ OUT
1
VMON_Q2_BASE
R7931
Q7931
2
3.3V SUS Detect
5% 1/16W MF-LF 402
1K
OUT
MAKE_BASE=TRUE
1
ALL_SYS_PWRGD
R7953
PP1V5_S3RS0_CPUDDR 1
0
1
S0PGD_C
R7954
72 71 29 15 13 10 7
P1V8S0_EN
P1V5S0_EN
72 70
100K
5% 1/16W MF-LF 402
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 2 402
48 71 72
PM_SLP_S3_R_L
PLACE_NEAR=U7720.5:6mm
MAKE_BASE=TRUE
NO STUFF
150K
7.15K
48 71 72
OUT
5% 1/16W MF-LF 402
1
P1V2S0_EN
72 70
2
44
R7956
R7952
5% 1/16W MF-LF 402
PLACE_NEAR=U7760.4:6mm
PP3V42_G3H
GND
1
1
5.1K
72 70
C
PP3V3_S0
2
1
OUT
PM_SLP_S3_R_L
R7986
10K
5% 1/16W MF-LF 402
PLACE_NEAR=U7100.15:6mm PLACE_NEAR=U7600.3:6mm
MAKE_BASE=TRUE
6
S0 Rail PGOOD (BJT Version)
1K
5% 1/16W MF-LF 402
1
R7988
20K
PM_SLP_S3_R_L
MAKE_BASE=TRUE
Y 4
PM_SLP_SUS_L:100K pull down on PCH page PM_SLP_SUS_L 17 IN
5% 1/16W MF-LF 402
VMON_3V3_DIV 1
R7985
2
20K
2
1 A
R7975
15.0K
R7981
2
5% 1/16W MF-LF 402
1
2
NO STUFF
R7951
PM_SLP_S3_R_L
CHGR VFRQ Generation
PLACE_NEAR=U7400.7:5mm
1
72 71 48
33K
3 B
72 69
R7987
2
VCC
SMC_BATLOW_L:100K pull up on SMC page SMC_BATLOW_L 45 44 IN
67
OUT
PLACE_NEAR=U7400.7:5mm
1% 1/16W MF-LF 2 402
D
10% 6.3V CERM-X5R 402
MAKE_BASE=TRUE
5
20% 10V CERM 2 402
R7917 83 82 79 53 51 50 40 39 36 23 22 20 7 18 17 16 32 28 26 48 47 45 71 61 60 89 88 87
66 72
C7912
2
(PM_SLP_S3_R_L)
100 2
PM_SLP_S3_L:100K pull down in PCH page
0.1uF
PLACE_NEAR=U7400.7:5mm
98 72 49 35 19 6 12 25 41 56 84
10% 6.3V CERM-X5R 402
5% 1/16W MF-LF 402
C7940
R7974
1
IN
PP3V3_S5
CPUVCORE ENABLE
5% 1/16W MF-LF 402
71 72
OUT
S0 ENABLE PM_SLP_S3_L
PLACE_NEAR=U7940.1:2.3mm 1
2
OUT
DDRREG_EN
71 72
R7978
0
P3V3S3_EN
PLACE_NEAR=U1800.G18:5mm
3.3V/5.0V Sus ENABLE
1
DDRREG_EN
MAKE_BASE=TRUE
PM_SLP_S5_L:100K pull down on PCH page
R7976
P3V3S3_EN
MAKE_BASE=TRUE
0.47UF
2
S5_PWRGD MAKE_BASE=TRUE
C
C7910
1
S5_PWRGD
5% 1/16W MF-LF 402
52
OUT
R7916
5% 1/16W MF-LF 402 2
0
TPAD_VBUS_EN
NO STUFF 1
0.47UF
R7941
1
5% 1/16W MF-LF 402
PLACE_NEAR=Q7812.2:6mm
72 66
PLACE_NEAR=U7201.20:7mm 1
ALL_SYS_PWRGD
3.3K
5% 1/16W MF-LF 402
0.0033UF
89 87 72 44 23
R7913
R7912
2
5% 1/16W MF-LF 402
C7942
10% 2 50V CERM 402
65 72 17 29 42 44
PLACE_NEAR=U5701.4:6mm
MAKE_BASE=TRUE
D
72 65 44
PM_SLP_S4_L OUT
MAKE_BASE=TRUE
72 71
1
PLACE_NEAR=U7201.21:7mm
A
2 3.3V,5V S3 ENABLE 2
6
1
7
0
8
2
BRANCH
PAGE
79 OF 132 SHEET
72 OF 101
1
A
8
7
6
5
4
3
2
1
Page Notes Power aliases required by this page: - =PP1V2_GPU_PEX_PLLXVDD - =PP1V2_GPU_PEX_IOVDDQ - =PP1V2_GPU_PEX_IOVDD Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE)
D
D 90 8
90 8
90 8
90 8
90 8
90 8
90 8
90 8
90 8
C
90 8
IN
PEG_R2D_C_P<0>
C8020
0.1UF
PEG_R2D_C_N<0>
C8021
0.1UF
PEG_R2D_C_P<1>
0.1UF
IN
C8022 C8023
0.1UF
IN
PEG_R2D_C_N<1>
IN
PEG_R2D_C_P<2>
IN
IN
IN
IN
PEG_R2D_C_N<2>
C8024 C8025
0.1UF 0.1UF
PEG_R2D_C_P<3>
C8026
0.1UF
PEG_R2D_C_N<3>
C8027
0.1UF
1
1 1
1 1
1 1
IN
PEG_R2D_C_P<4>
C8028
0.1UF
C8029
0.1UF
IN
PEG_R2D_C_N<4>
1
PEG_R2D_C_P<5>
C8030
0.1UF
1
IN
90 8
IN
PEG_R2D_C_N<5>
C8031
0.1UF
IN
PEG_R2D_C_P<6>
C8032
0.1UF
90 8
IN
PEG_R2D_C_N<6>
C8033
0.1UF
IN
PEG_R2D_C_P<7>
C8034
0.1UF
90 8
IN
PEG_R2D_C_N<7>
C8035
0.1UF
90 8
90 8
1
1
1
1 1
1 1
2 10%6.3VX5R 201 2 10%6.3VX5R 201
PEG_R2D_P<0> PEG_R2D_N<0>
73 90
73 90
90 73
90 73
PEG_D2R_C_P<0>
C8055
PEG_D2R_C_N<0>
C8056
0.1UF 0.1UF 0.1UF
2 10%6.3VX5R 201 2 10%6.3VX5R 201
PEG_R2D_P<1>
73 90
90 73
PEG_D2R_C_P<1>
C8057
PEG_R2D_N<1>
73 90
90 73
PEG_D2R_C_N<1>
C8058
2 10%6.3VX5R 201 2 10%6.3VX5R 201
PEG_R2D_P<2>
2 10%6.3VX5R 201 2 10%6.3VX5R 201
PEG_R2D_P<3>
2 10%6.3VX5R 201 2 10%6.3VX5R 201
PEG_R2D_N<2>
PEG_R2D_N<3> PEG_R2D_P<4> PEG_R2D_N<4>
73 90
73 90
73 90
73 90
73 90
73 90
90 73
90 73
90 73
90 73
0.1UF
PEG_D2R_C_P<2> PEG_D2R_C_N<2>
C8059 C8060
0.1UF 0.1UF
PEG_D2R_C_P<3>
C8061
0.1UF
PEG_D2R_C_N<3>
C8062
0.1UF
1
1 1
1
1 1
PEG_D2R_C_P<4>
C8063 C8064
0.1UF
90 73
PEG_D2R_C_N<4>
1
PEG_D2R_C_P<5>
C8065
0.1UF
1
PEG_R2D_N<5>
73 90
90 73
PEG_D2R_C_N<5>
C8066
0.1UF
2 10%6.3VX5R 201 2 10%6.3VX5R 201
PEG_R2D_P<6>
90 73
PEG_D2R_C_P<6>
C8067
0.1UF
73 90
PEG_R2D_N<6>
73 90
90 73
PEG_D2R_C_N<6>
C8068
0.1UF
2 10%6.3VX5R 201 2 10%6.3VX5R 201
PEG_R2D_P<7>
90 73
PEG_D2R_C_P<7>
C8069
0.1UF
73 90
PEG_R2D_N<7>
90 73
PEG_D2R_C_N<7>
C8070
0.1UF
73 90
90 73
PEG_D2R_P<0> PEG_D2R_N<0>
90 73
OUT
OUT
8 90 90 73
8 90
90 73 90 73
2 10%6.3VX5R 201 2 10%6.3VX5R 201
PEG_D2R_P<1>
2 10%6.3VX5R 201 2 10%6.3VX5R 201
PEG_D2R_P<2>
OUT
8 90
OUT
8 90
90 73 90 73
PEG_D2R_N<1>
90 73
2 10%6.3VX5R 201 2 10%6.3VX5R 201
PEG_D2R_N<2>
OUT
8 90 90 73 90 73
OUT
90 73
PEG_D2R_P<3>
90 73
OUT
OUT
1
1
1 1
1 1
8 90
90 73
IN
FCBGA
PCIE_TX0P Y33 PCIE_TX0N Y32
PEG_D2R_C_P<0> PEG_D2R_C_N<0>
PEG_R2D_P<1> PEG_R2D_N<1>
Y35 PCIE_RX1P W36 PCIE_RX1N
(1 OF 9) PCIE
PCIE_TX1P W33 PCIE_TX1N W32
PEG_D2R_C_P<1> PEG_D2R_C_N<1>
PEG_R2D_P<2> PEG_R2D_N<2>
W38 PCIE_RX2P V37 PCIE_RX2N
PCIE_TX2P U33 PCIE_TX2N U32
PEG_D2R_C_P<2> PEG_D2R_C_N<2>
PEG_R2D_P<3> PEG_R2D_N<3>
V35 PCIE_RX3P U36 PCIE_RX3N
PCIE_TX3P U30 PCIE_TX3N U29
PEG_D2R_C_P<3> PEG_D2R_C_N<3>
PEG_R2D_P<4> PEG_R2D_N<4>
U38 PCIE_RX4P T37 PCIE_RX4N
PCIE_TX4P T33 PCIE_TX4N T32
PEG_D2R_C_P<4> PEG_D2R_C_N<4>
PEG_R2D_P<5> PEG_R2D_N<5>
T35 PCIE_RX5P R36 PCIE_RX5N
PCIE_TX5P T30 PCIE_TX5N T29
PEG_D2R_C_P<5> PEG_D2R_C_N<5>
PEG_R2D_P<6> PEG_R2D_N<6>
R38 PCIE_RX6P P37 PCIE_RX6N
PCIE_TX6P P33 PCIE_TX6N P32
PEG_D2R_C_P<6> PEG_D2R_C_N<6>
PEG_R2D_P<7> PEG_R2D_N<7>
P35 PCIE_RX7P N36 PCIE_RX7N
PCIE_TX7P P30 PCIE_TX7N P29
PEG_D2R_C_P<7> PEG_D2R_C_N<7>
N38 PCIE_RX8P M37 PCIE_RX8N
PCIE_TX8P N33 PCIE_TX8N N32
NC NC
PCIE_TX9P N30 PCIE_TX9N N29
NC NC
U8000
OMIT
2 10%6.3VX5R 201 2 10%6.3VX5R 201
PEG_D2R_P<4> PEG_D2R_N<4>
OUT
8 90
NC NC
2 10%6.3VX5R 201 2 10%6.3VX5R 201
PEG_D2R_P<5>
OUT
8 90
NC NC
M35 PCIE_RX9P L36 PCIE_RX9N
PEG_D2R_N<5>
OUT
8 90
NC NC
L38 PCIE_RX10P K37 PCIE_RX10N
PCIE_TX10P L33 PCIE_TX10N L32
NC NC
2 10%6.3VX5R 201 2 10%6.3VX5R 201
PEG_D2R_P<6>
OUT
8 90
K35 PCIE_RX11P J36 PCIE_RX11N
PCIE_TX11P L30 PCIE_TX11N L29
PEG_D2R_N<6>
NC NC
NC NC
OUT
8 90
PCIE_TX12P K33 PCIE_TX12N K32
2 10%6.3VX5R 201 2 10%6.3VX5R 201
PEG_D2R_P<7>
NC NC
J38 PCIE_RX12P H37 PCIE_RX12N
NC NC
OUT
8 90
PEG_D2R_N<7>
PCIE_TX13P J33 PCIE_TX13N J32
8 90
NC NC
H35 PCIE_RX13P G36 PCIE_RX13N
OUT
NC NC
NC NC
G38 PCIE_RX14P F37 PCIE_RX14N
PCIE_TX14P K30 PCIE_TX14N K29
NC NC
NC NC
F35 PCIE_RX15P E37 PCIE_RX15N
PCIE_TX15P H33 PCIE_TX15N H32
NC NC
OUT
8 90
90 73
93 16
IN
93 16
IN
NOSTUFF 89 87 86 81 8
AA38 PCIE_RX0P Y37 PCIE_RX0N
PM_ALL_GPU_PGOOD
R8003
1
0 5% 1/16W MF-LF 402
2 87 8
IN
EG_RESET_L
73 90
73 90 73 90
73 90 73 90
73 90 73 90
73 90 73 90
73 90 73 90
R8000
1
0
2
PEG_CLK100M_P PEG_CLK100M_N
AB35 PCIE_REFCLKP AA36 PCIE_REFCLKN
GPU_PWRGOOD
AH16 PWRGOOD
GPU_RESET_R_L
PCIE_CALRP Y30 PCIE_CALRN Y29
1
R8004
73 90 73 90
73 90 73 90
C
PEG_CALRP PEG_CALRN
AA30 PERST*
R80011
1
R8002
2.0K
5% 1/16W MF-LF 402
10K
1.27K
1% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
B
73 90
8 90 90 73
PEG_D2R_N<3>
PEG_R2D_P<0> PEG_R2D_N<0>
8 90
90 73
90 73
PEG_R2D_P<5>
2 10%6.3VX5R 201 2 10%6.3VX5R 201
90 73
1
0.1UF
2 10%6.3VX5R 201 2 10%6.3VX5R 201
73 90
1
WHISTLER 40NM-ES
90 8
100 80 78 74 7
1% 1/16W MF-LF 2 402
PP1V0_S0GPU_ISNS
B
A
SYNC_MASTER=K92_SUMA
SYNC_DATE=06/15/2010
PAGE TITLE
Whistler PCI-E DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
80 OF 132 SHEET
73 OF 101
1
A
8
7
6
5
4
3
2
1 Page Notes
CRITICAL
L8150
Power aliases required by this page:
120OHM-0.3A PP1V5_S0GPU_ISNS
C8100 10UF
20% 2 10V X5R 603
1
C8101 10UF
1
C8102 10UF
20% 2 10V X5R 603
1
C8103 10UF
20% 2 10V X5R 603
20% 2 10V X5R 603
100 80 78 74 7
1
C8104 10UF
20% 2 10V X5R 603
D 1
C8105
1
1UF
10% 2 25V X5R 402
1
C8115 0.1UF
10% 6.3V 2 X5R 201
C8106
1
1UF
10% 2 25V X5R 402
1
C8107
10% 2 25V X5R 402
C8116 0.1UF
10% 6.3V 2 X5R 201
1
1UF
1
C8108
10% 2 25V X5R 402
C8117 0.1UF
10% 6.3V 2 X5R 201
1
1UF
1
C8109
10% 2 25V X5R 402
C8118 0.1UF
10% 6.3V 2 X5R 201
1
1UF
1
C8110
10% 2 25V X5R 402
C8119 0.1UF
10% 6.3V 2 X5R 201
1
1UF
1
C8120 0.1UF
10% 6.3V 2 X5R 201
C8111
1
1UF
10% 2 25V X5R 402
1
C8112
10% 2 25V X5R 402
C8121 0.1UF
10% 6.3V 2 X5R 201
1
1UF
1
C8113
10% 2 25V X5R 402
C8122 0.1UF
10% 6.3V 2 X5R 201
1
1UF
1
C8123 0.1UF
10% 6.3V 2 X5R 201
C8114 1UF
10% 2 25V X5R 402
1
C8124 0.1UF
10% 6.3V 2 X5R 201
L8120
120OHM-0.3A 100 80 78 74 7
PP1V8_S0GPU_ISNS
1
PP1V8_GPU_VDD_CT
2
1
C8125
1
10UF
20% 10V 2 X5R 603
C
219mA
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V
0402
CRITICAL
C8126
1
1UF
10% 25V 2 X5R 402
C8127
1
1UF
10% 25V 2 X5R 402
C8128
1
1UF
C8129 0.1UF
10% 6.3V 2 X5R 201
10% 25V 2 X5R 402
AC7 AD11 AF7 AG10 AJ7 AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10 J7 J9 K8 K11 K13 L7 L12 L16 L21 L23 L26 M11 N11 P7 R11 U7 U11 Y7 Y11
VDDR1_AC7 VDDR1_AD11 VDDR1_AF7 VDDR1_AG10 VDDR1_AJ7 VDDR1_AK8 VDDR1_AL9 VDDR1_G11 VDDR1_G14 VDDR1_G17 VDDR1_G20 VDDR1_G23 VDDR1_G26 VDDR1_G29 VDDR1_H10 VDDR1_J7 VDDR1_J9 VDDR1_K8 VDDR1_K11 VDDR1_K13 VDDR1_L7 VDDR1_L12 VDDR1_L16 VDDR1_L21 VDDR1_L23 VDDR1_L26 VDDR1_M11 VDDR1_N11 VDDR1_P7 VDDR1_R11 VDDR1_U7 VDDR1_U11 VDDR1_Y7 VDDR1_Y11
AF26 AF27 AG26 AG27
VDD_CT_AF26 VDD_CT_AF27 VDD_CT_AG26 VDD_CT_AG27
10UF
C8132
83 81 79 78 71 7 6
PP3V3_S0GPU
0.1UF
1UF
20% 10V 2 X5R 603 74
C8131
1
10% 25V 2 X5R 402
60 mA
10% 6.3V 2 X5R 201
AF23 AF24 AG23 AG24
VDDR3_AF23 VDDR3_AF24 VDDR3_AG23 VDDR3_AG24
GND_GPU_PLL
1
C8133
1
10UF
20% 2 10V X5R 603
C8134
1
1UF
10% 2 25V X5R 402
C8135
1
10% 2 25V X5R 402
C8136 1UF
1UF
10% 2 25V X5R 402
CRITICAL
AF13 AF15 AG13 AG15
VDDR4_AF13 VDDR4_AF15 VDDR4_AG13 VDDR4_AG15
L8131
470OHM-1A-150MOHM 100 80 78 74 7
PP1V8_S0GPU_ISNS
1
PP1V8_GPU_MEM_PLL
2
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V
0603 1
C8137
1
C8138
1
1UF
10UF
20% 2 10V X5R 603
B
74
PP1V8_GPU_VDDR4 TBD mA
10% 2 25V X5R 402
C8139
1
1UF
10% 2 25V X5R 402
C8140
1
0.1UF
10% 2 6.3V X5R 201
C8141
CRITICAL
NC NC
M20 NC/VDDRHA M21 NC/VSSRHA
NC NC
U12 NC/VSSRHB V12 NC/VDDRHB
150mA
L8132
PP1V8_S0GPU_ISNS
1
PP1V8_GPU_PLL
2
H7 MPV18_H7 H8 MPV18_H8
1
C8142
1
10UF
20% 2 10V X5R 603
XW8100 SM 1
75mA
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V 74
0402
C8143
1
1UF
10% 2 25V X5R 402
C8144
74
0.1UF
PP1V0_GPU_PLL
PP1V8_S0GPU_ISNS
10% 6.3V 2 X5R 201
AN10 SPVSS
GPU_VDD_SENSE
81
OUT
81
OUT
1
GPU_GND_SENSE
PP1V8_GPU_PCIE_VDDR
2
AF28 FB_VDDC
NC
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
504mA
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V
0603
CRITICAL
1
C8145 10UF
PP1V0_S0GPU_ISNS
AN9 SPV10
GND_GPU_PLL
FERR-220-OHM-2A 100 80 78 74 7
AM10 SPV18
120mA
2
L8140
20% 10V 2 X5R 603
1
C8146 1UF
10% 25V 2 X5R 402
1
C8147 1UF
10% 25V 2 X5R 402
1
C8148 1UF
10% 25V 2 X5R 402
1
C8149 0.1UF
10% 6.3V 2 X5R 201
1
C8150 0.1UF
10% 6.3V 2 X5R 201
7 73 74 78 80 100
L8155
FERR-120-OHM-3A 1
PP1V0_GPU_PCIE_VDDC
2
CRITICAL
A
1
C8151 10UF
20% 10V 2 X5R 603
8
1920mA
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1V
0603 1
C8152 1UF
10% 25V 2 X5R 402
7
1
C8153 1UF
10% 25V 2 X5R 402
1
C8154 1UF
10% 25V 2 X5R 402
1
C8155 1UF
10% 25V 2 X5R 402
VDDR4_AD12 VDDR4_AF11 VDDR4_AF12 VDDR4_AG11
0.1UF
10% 6.3V 2 X5R 201
120OHM-0.3A 100 80 78 74 7
AD12 AF11 AF12 AG11
1
C8156 1UF
10% 25V 2 X5R 402
6
1
C8157 1UF
10% 25V 2 X5R 402
1
C8158 1UF
10% 25V 2 X5R 402
AG28 FB_VDDCI AH29 FB_GND AA31 AA32 AA33 AA34 AB37 V28 W29 W30 Y31 G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28
PCIE_VDDR_AA31 PCIE_VDDR_AA32 PCIE_VDDR_AA33 PCIE_VDDR_AA34 PCIE_VDDR_AB37 PCIE_VDDR_V28 PCIE_VDDR_W29 PCIE_VDDR_W30 PCIE_VDDR_Y31 PCIE_VDDC_G30 PCIE_VDDC_G31 PCIE_VDDC_H29 PCIE_VDDC_H30 PCIE_VDDC_J29 PCIE_VDDC_J30 PCIE_VDDC_L28 PCIE_VDDC_M28 PCIE_VDDC_N28 PCIE_VDDC_R28 PCIE_VDDC_T28 PCIE_VDDC_U28
5
ISOLATED CORE I/O
C8130
1
1
C81C1 0.1UF
10% 2 25V X5R 402
81 48 7 6
PLL
1
C81C0 1UF
OMIT
LEVEL TRNSL
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1V
1
10% 2 6.3V X5R 201
Signal aliases required by this page: (NONE) BOM options provided by this page:
I/O
PP1V0_GPU_PLL
2 0603
0402
=PPVCORE_GPU =PP1V5R1V35_GPU_FB_VDDR1 =PP1V8_GPU_VDD_CT =PP1V0_GPU_PLL =PP3V3_GPU_VDDR3 =PP3V3_GPU_VDDR4 =PP1V8_GPU_MEM_PLL =PP1V8_GPU_PLL =PP1V8_GPU_PCIE_VDDR =PP1V8_GPU_PCIE_VDDC
D
(NONE)
VOLT SENSE
1
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V
(7 OF 9)
PCIE
PP1V0_S0GPU_ISNS
PP1V8_GPU_VDDR4
2
FCBGA
L8130
100 80 78 74 73 7
1
U8000
CRITICAL 470OHM-1A-150MOHM
PP1V8_S0GPU_ISNS
WHISTLER 40NM-ES
MEM I/O
1
TBD mA
CORE
100 77 76 75 7
-
VDDC_AA15 VDDC_AA17 VDDC_AA20 VDDC_AA22 VDDC_AA24 VDDC_AA27 VDDC_AB16 VDDC_AB18 VDDC_AB21 VDDC_AB23 VDDC_AB26 VDDC_AB28 VDDC_AC17 VDDC_AC20 VDDC_AC22 VDDC_AC24 VDDC_AC27 VDDC_AD18 VDDC_AD21 VDDC_AD23 VDDC_AD26 VDDC_AF17 VDDC_AF20 VDDC_AF22 VDDC_AG16 VDDC_AG18 VDDC_AG21 VDDC_AH22 VDDC_AH27 VDDC_AH28 VDDC_M26 VDDC_N24 BIF_VDDC_N27 VDDC_R18 VDDC_R21 VDDC_R23 VDDC_R26 VDDC_T17 VDDC_T20 VDDC_T22 VDDC_T24 BIF_VDDC_T27 VDDC_U16 VDDC_U18 VDDC_U21 VDDC_U23 VDDC_U26 VDDC_V17 VDDC_V20 VDDC_V22 VDDC_V24 VDDC_V27 VDDC_Y16 VDDC_Y18 VDDC_Y21 VDDC_Y23 VDDC_Y26 VDDC_Y28
AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 AG21 AH22 AH27 AH28 M26 N24 N27 R18 R21 R23 R26 T17 T20 T22 T24 T27 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28
VDDCI_AA13 VDDCI_AB13 VDDCI_AC12 VDDCI_AC15 VDDCI_AD13 VDDCI_AD16 VDDCI_M15 VDDCI_M16 VDDCI_M18 VDDCI_M23 VDDCI_N13 VDDCI_N15 VDDCI_N17 VDDCI_N20 VDDCI_N22 VDDCI_R12 VDDCI_R13 VDDCI_R16 VDDCI_T12 VDDCI_T15 VDDCI_V15 VDDCI_Y13
AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13
4
1
C8160 1UF
10% 25V 2 X5R 402
1
C8170
1
C8161 1UF
10% 25V 2 X5R 402
1
1UF
10% 25V 2 X5R 402
PPVCORE_GPU
C8171
1
1UF
10% 25V 2 X5R 402
1
1UF
10% 25V 2 X5R 402
C8162
C8172
1
1UF
10% 25V 2 X5R 402
1
1UF
10% 25V 2 X5R 402
C8163
C8173
1
1UF
10% 25V 2 X5R 402
1
1UF
10% 25V 2 X5R 402
C8164
C8174
1
1UF
10% 25V 2 X5R 402
1
1UF
10% 25V 2 X5R 402
C8165
C8175
1
1UF
1
1
C8167 1UF
10% 25V 2 X5R 402
1UF
10% 25V 2 X5R 402
C8166
C8176
1
1UF
10% 25V 2 X5R 402
1
C8168 1UF
10% 25V 2 X5R 402
10% 25V 2 X5R 402
C8177
1
1UF
10% 25V 2 X5R 402
C8178
1
1UF
10% 25V 2 X5R 402
1
1UF
10% 25V 2 X5R 402
C8169
C8179 1UF
10% 25V 2 X5R 402
C 1
C8180 1UF
10% 2 25V X5R 402
1
C8190 10UF
20% 10V 2 X5R 603
1
C8181 1UF
10% 2 25V X5R 402
1
C8191 10UF
20% 10V 2 X5R 603
1
C8182 1UF
10% 2 25V X5R 402
1
C8192 10UF
20% 10V 2 X5R 603
1
C8183 1UF
10% 2 25V X5R 402
1
C8193 10UF
20% 10V 2 X5R 603
1
C8184 1UF
10% 2 25V X5R 402
1
C8194 10UF
20% 10V 2 X5R 603
1
C8185 1UF
10% 2 25V X5R 402
1
C8195 10UF
20% 10V 2 X5R 603
1
C8186 1UF
1
1
C8187 1UF
10% 2 25V X5R 402
C8196 10UF
20% 10V 2 X5R 603
1
1
C8188 1UF
10% 2 25V X5R 402
10% 2 25V X5R 402
C8197 10UF
20% 10V 2 X5R 603
1
C8198 10UF
20% 10V 2 X5R 603
1
C8189 1UF
10% 2 25V X5R 402
1
C8199 10UF
20% 10V 2 X5R 603
B
1
C81A0
1
1UF
10% 2 25V X5R 402
1
C81B0 10UF
20% 10V 2 X5R 603
C81A1
1
1UF
10% 2 25V X5R 402
1
C81B1 10UF
20% 10V 2 X5R 603
C81A2 1UF
10% 2 25V X5R 402
1
1
C81A3 1UF
10% 2 25V X5R 402
1
C81A4 1UF
10% 2 25V X5R 402
1
C81A5 1UF
10% 2 25V X5R 402
1
C81A6 1UF
10% 2 25V X5R 402
1
C81A7
1
1UF
10% 2 25V X5R 402
C81A8 1UF
10% 2 25V X5R 402
1
C81A9 1UF
10% 2 25V X5R 402
C81B2 10UF
20% 10V 2 X5R 603
SYNC_MASTER=K92_SUMA
SYNC_DATE=06/15/2010
PAGE TITLE
Whistler CORE/FB POWER DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
3
2
BRANCH
PAGE
81 OF 132 SHEET
74 OF 101
1
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1 Page Notes
D
97 76 6
BI
97 76 6
BI
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BI
97 76 6
BI
97 76 6
BI
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BI
97 76 6
BI
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BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
C
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
B
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI
97 76 6
BI 75 75
PP1V5_S0GPU_ISNS GPU:WHISTLER R8210 1 243 2 243
C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13 J13 H11 G10 G8 K9 K10 G9 A8 C8 E8 A6 C6 E6 A5
DQA1_0/DQA_32 DQA1_1/DQA_33 DQA1_2/DQA_34 DQA1_3/DQA_35 DQA1_4/DQA_36 DQA1_5/DQA_37 DQA1_6/DQA_38 DQA1_7/DQA_39 DQA1_8/DQA_40 DQA1_9/DQA_41 DQA1_10/DQA_42 DQA1_11/DQA_43 DQA1_12/DQA_44 DQA1_13/DQA_45 DQA1_14/DQA_46 DQA1_15/DQA_47 DQA1_16/DQA_48 DQA1_17/DQA_49 DQA1_18/DQA_50 DQA1_19/DQA_51 DQA1_20/DQA_52 DQA1_21/DQA_53 DQA1_22/DQA_54 DQA1_23/DQA_55 DQA1_24/DQA_56 DQA1_25/DQA_57 DQA1_26/DQA_58 DQA1_27/DQA_59 DQA1_28/DQA_60 DQA1_29/DQA_61 DQA1_30/DQA_62 DQA1_31/DQA_63
FB_A_VREFD FB_A_VREFS
L18 L20
MVREFDA MVREFSA
L27 N12 AG12
FB_CALRN0 FB_CALRN1 FB_CALRN2
2
M27 M12 AH12
402 1% 1/16W MF-LF
R8212 1
DQA0_0/DQA_0 DQA0_1/DQA_1 DQA0_2/DQA_2 DQA0_3/DQA_3 DQA0_4/DQA_4 DQA0_5/DQA_5 DQA0_6/DQA_6 DQA0_7/DQA_7 DQA0_8/DQA_8 DQA0_9/DQA_9 DQA0_10/DQA_10 DQA0_11/DQA_11 DQA0_12/DQA_12 DQA0_13/DQA_13 DQA0_14/DQA_14 DQA0_15/DQA_15 DQA0_16/DQA_16 DQA0_17/DQA_17 DQA0_18/DQA_18 DQA0_19/DQA_19 DQA0_20/DQA_20 DQA0_21/DQA_21 DQA0_22/DQA_22 DQA0_23/DQA_23 DQA0_24/DQA_24 DQA0_25/DQA_25 DQA0_26/DQA_26 DQA0_27/DQA_27 DQA0_28/DQA_28 DQA0_29/DQA_29 DQA0_30/DQA_30 DQA0_31/DQA_31
FB_A1_DQ<0> FB_A1_DQ<1> FB_A1_DQ<2> FB_A1_DQ<3> FB_A1_DQ<4> FB_A1_DQ<5> FB_A1_DQ<6> FB_A1_DQ<7> FB_A1_DQ<8> FB_A1_DQ<9> FB_A1_DQ<10> FB_A1_DQ<11> FB_A1_DQ<12> FB_A1_DQ<13> FB_A1_DQ<14> FB_A1_DQ<15> FB_A1_DQ<16> FB_A1_DQ<17> FB_A1_DQ<18> FB_A1_DQ<19> FB_A1_DQ<20> FB_A1_DQ<21> FB_A1_DQ<22> FB_A1_DQ<23> FB_A1_DQ<24> FB_A1_DQ<25> FB_A1_DQ<26> FB_A1_DQ<27> FB_A1_DQ<28> FB_A1_DQ<29> FB_A1_DQ<30> FB_A1_DQ<31>
7 74 75 76 77 100
402 1% 1/16W MF-LF
R8211 1
C37 C35 A35 E34 G32 D33 F32 E32 D31 F30 C30 A30 F28 C28 A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18
FB_A0_DQ<0> FB_A0_DQ<1> FB_A0_DQ<2> FB_A0_DQ<3> FB_A0_DQ<4> FB_A0_DQ<5> FB_A0_DQ<6> FB_A0_DQ<7> FB_A0_DQ<8> FB_A0_DQ<9> FB_A0_DQ<10> FB_A0_DQ<11> FB_A0_DQ<12> FB_A0_DQ<13> FB_A0_DQ<14> FB_A0_DQ<15> FB_A0_DQ<16> FB_A0_DQ<17> FB_A0_DQ<18> FB_A0_DQ<19> FB_A0_DQ<20> FB_A0_DQ<21> FB_A0_DQ<22> FB_A0_DQ<23> FB_A0_DQ<24> FB_A0_DQ<25> FB_A0_DQ<26> FB_A0_DQ<27> FB_A0_DQ<28> FB_A0_DQ<29> FB_A0_DQ<30> FB_A0_DQ<31>
MAA0_0/MMA_0 MAA0_1/MMA_1 MAA0_2/MMA_2 MAA0_3/MMA_3 MAA0_4/MMA_4 MAA0_5/MMA_5 MAA0_6/MMA_6 MAA0_7/MMA_7
G24 J23 H24 J24 H26 J26 H21 G21
MAA1_0/MMA_8 MAA1_1/MMA_9 MAA1_2/MMA_10 MAA1_3/MMA_11 MAA1_4/MMA_12 MAA1_5/MMA_13_BA2 MAA1_6/MMA_14_BA0 MAA1_7/MMA_A15_BA1
H19 H20 L13 G16 J16 H16 J17 H17
U8000 WHISTLER 40NM-ES FCBGA
(4 OF 9) MEM INTERFACE A
OMIT
FB_A0_A<0> FB_A0_A<1> FB_A0_A<2> FB_A0_A<3> FB_A0_A<4> FB_A0_A<5> FB_A0_A<6> FB_A0_A<7> FB_A1_A<0> FB_A1_A<1> FB_A1_A<2> FB_A1_A<3> FB_A1_A<4> FB_A1_A<5> FB_A1_A<6> FB_A1_A<7>
OUT
6 76 97
97 77 6
BI
OUT
6 76 97
97 77 6
BI
OUT
6 76 97
97 77 6
BI
OUT
6 76 97
97 77 6
BI
OUT
6 76 97
97 77 6
BI
OUT
6 76 97
97 77 6
BI
OUT
6 76 97
97 77 6
BI
OUT
6 76 97
97 77 6
BI
97 77 6
BI
97 77 6
BI
97 77 6
BI
OUT
6 76 97
OUT
6 76 97
OUT
6 76 97 97 77 6
BI
97 77 6
BI
6 76 97
OUT OUT
6 76 97
OUT
6 76 97
OUT
6 76 97
97 77 6
BI
97 77 6
BI
97 77 6
BI
97 77 6
BI
6 76 97
OUT
WCKA0_0/DQMA_0 A32 C32 WCKA0_0*/DQMA_1
FB_A0_WCLK_P<0> FB_A0_WCLK_N<0>
BI
6 76 97
97 77 6
BI
BI
6 76 97
97 77 6
BI
WCKA0_1/DQMA_2 D23 E22 WCKA0_1*/DQMA_3
FB_A0_WCLK_P<1> FB_A0_WCLK_N<1>
97 77 6 6 76 97
BI
BI BI
6 76 97
WCKA1_0/DQMA_4 C14 A14 WCKA1_0*/DQMA_5
FB_A1_WCLK_P<0> FB_A1_WCLK_N<0>
WCKA1_1/DQMA_6 E10 D9 WCKA1_1*/DQMA_7 EDCA0_0/QSA_0/RDQSA_0 EDCA0_1/QSA_1/RDQSA_1 EDCA0_2/QSA_2/RDQSA_2 EDCA0_3/QSA_3/RDQSA_3 EDCA1_0/QSA_4/RDQSA_4 EDCA1_1/QSA_5/RDQSA_5 EDCA1_2/QSA_6/RDQSA_6 EDCA1_3/QSA_7/RDQSA_7 DDBIA0_0/QSA_0B/WDQSA_0 DDBIA0_1/QSA_1B/WDQSA_1 DDBIA0_2/QSA_2B/WDQSA_2 DDBIA0_3/QSA_3B/WDQSA_3 DDBIA1_0/QSA_4B/WDQSA_4 DDBIA1_1/QSA_5B/WDQSA_5 DDBIA1_2/QSA_6B/WDQSA_6 DDBIA1_3/QSA_7B/WDQSA_7
FB_A1_WCLK_P<1> FB_A1_WCLK_N<1>
C34 D29 D25 E20
FB_A0_EDC<0> FB_A0_EDC<1> FB_A0_EDC<2> FB_A0_EDC<3>
E16 E12 J10 D7
FB_A1_EDC<0> FB_A1_EDC<1> FB_A1_EDC<2> FB_A1_EDC<3>
A34 E30 E26 C20
FB_A0_DBI_L<0> FB_A0_DBI_L<1> FB_A0_DBI_L<2> FB_A0_DBI_L<3>
C16 C12 J11 F8
FB_A1_DBI_L<0> FB_A1_DBI_L<1> FB_A1_DBI_L<2> FB_A1_DBI_L<3>
ADBIA0/ODTA0 J21 ADBIA1/ODTA1 G19
BI
97 77 6
BI
BI
6 76 97
97 77 6
BI
BI
6 76 97
97 77 6
BI
97 77 6
BI
97 77 6
BI
97 77 6
BI
6 76 97
BI
6 76 97
BI BI
6 76 97
97 77 6
BI
BI
6 76 97
97 77 6
BI
BI
6 76 97
97 77 6
BI
BI
6 76 97
97 77 6
BI
97 77 6
BI
BI
6 76 97
BI
6 76 97
97 77 6
BI
BI
6 76 97
97 77 6
BI
BI
6 76 97
97 77 6
BI
97 77 6
BI
BI
6 76 97
BI
6 76 97
BI
6 76 97
BI
6 76 97
97 77 6
BI
97 77 6
BI
97 77 6
BI
97 77 6
BI
BI
6 76 97
97 77 6
BI
BI
6 76 97
97 77 6
BI
BI
6 76 97
97 77 6
BI
BI
6 76 97
97 77 6
BI
97 77 6 6 76 97
BI
BI BI
6 76 97
97 77 6
BI
97 77 6
BI
CLKA0 H27 CLKA0* G27
FB_A0_CLK_P FB_A0_CLK_N
OUT
76 97
97 77 6
BI
OUT
76 97
97 77 6
BI
CLKA1 J14 CLKA1* H14
FB_A1_CLK_P FB_A1_CLK_N
97 77 6 76 97
BI
OUT OUT
76 97
97 77 6
BI
97 77 6
BI
RASA0* K23 RASA1* K19
FB_A0_RAS_L FB_A1_RAS_L
OUT
76 97
97 77 6
BI
OUT
76 97
97 77 6
BI
CASA0* K20 CASA1* K17
FB_A0_CAS_L FB_A1_CAS_L
97 77 6 76 97
BI
OUT OUT
76 97
CSA0_0* K24 CSA0_1* K27 CSA1_0* M13 CSA1_1* K16
MEM_CALRN0 MEM_CALRN1 MEM_CALRN2
FB_A0_ABI_L FB_A1_ABI_L
97 77 6
FB_A0_CS_L
OUT
76 97
NC
FB_A1_CS_L
OUT
FB_A0_CKE_L FB_A1_CKE_L
WEA0* K26 WEA1* L15 MAA0_8 H23 MAA1_8 J19
BI
97 77 6
BI
97 77 6
BI
97 77 6
BI
97 77 6
BI
97 77 6
BI
97 77 6
BI
76 97
NC
CKEA0 K21 CKEA1 J20
97 77 6
AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6 AG4 AH5 AH6 AJ4 AK3 AF8 AF9 AG8 AG7 AK9 AL7 AM8 AM7 AK1 AL4 AM6 AM1 AN4 AP3 AP1 AP5
FB_B1_DQ<0> FB_B1_DQ<1> FB_B1_DQ<2> FB_B1_DQ<3> FB_B1_DQ<4> FB_B1_DQ<5> FB_B1_DQ<6> FB_B1_DQ<7> FB_B1_DQ<8> FB_B1_DQ<9> FB_B1_DQ<10> FB_B1_DQ<11> FB_B1_DQ<12> FB_B1_DQ<13> FB_B1_DQ<14> FB_B1_DQ<15> FB_B1_DQ<16> FB_B1_DQ<17> FB_B1_DQ<18> FB_B1_DQ<19> FB_B1_DQ<20> FB_B1_DQ<21> FB_B1_DQ<22> FB_B1_DQ<23> FB_B1_DQ<24> FB_B1_DQ<25> FB_B1_DQ<26> FB_B1_DQ<27> FB_B1_DQ<28> FB_B1_DQ<29> FB_B1_DQ<30> FB_B1_DQ<31>
OUT
76 97
97 77 6
BI
OUT
76 97
97 77 6
BI
FB_A0_WE_L FB_A1_WE_L
OUT
76 97
75
OUT
76 97
75
FB_A0_A<8> FB_A1_A<8>
OUT
6 76 97
OUT
6 76 97
R82501
C5 C3 E3 E1 F1 F3 F5 G4 H5 H6 J4 K6 K5 L4 M6 M1 M3 M5 N4 P6 P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1 Y3 Y5
FB_B0_DQ<0> FB_B0_DQ<1> FB_B0_DQ<2> FB_B0_DQ<3> FB_B0_DQ<4> FB_B0_DQ<5> FB_B0_DQ<6> FB_B0_DQ<7> FB_B0_DQ<8> FB_B0_DQ<9> FB_B0_DQ<10> FB_B0_DQ<11> FB_B0_DQ<12> FB_B0_DQ<13> FB_B0_DQ<14> FB_B0_DQ<15> FB_B0_DQ<16> FB_B0_DQ<17> FB_B0_DQ<18> FB_B0_DQ<19> FB_B0_DQ<20> FB_B0_DQ<21> FB_B0_DQ<22> FB_B0_DQ<23> FB_B0_DQ<24> FB_B0_DQ<25> FB_B0_DQ<26> FB_B0_DQ<27> FB_B0_DQ<28> FB_B0_DQ<29> FB_B0_DQ<30> FB_B0_DQ<31>
DQB0_0/DQB_0 DQB0_1/DQB_1 DQB0_2/DQB_2 DQB0_3/DQB_3 DQB0_4/DQB_4 DQB0_5/DQB_5 DQB0_6/DQB_6 DQB0_7/DQB_7 DQB0_8/DQB_8 DQB0_9/DQB_9 DQB0_10/DQB_10 DQB0_11/DQB_11 DQB0_12/DQB_12 DQB0_13/DQB_13 DQB0_14/DQB_14 DQB0_15/DQB_15 DQB0_16/DQB_16 DQB0_17/DQB_17 DQB0_18/DQB_18 DQB0_19/DQB_19 DQB0_20/DQB_20 DQB0_21/DQB_21 DQB0_22/DQB_22 DQB0_23/DQB_23 DQB0_24/DQB_24 DQB0_25/DQB_25 DQB0_26/DQB_26 DQB0_27/DQB_27 DQB0_28/DQB_28 DQB0_29/DQB_29 DQB0_30/DQB_30 DQB0_31/DQB_31
FB_B_VREFD FB_B_VREFS
Y12 MVREFDB AA12 MVREFSB
GPU_TEST_EN
AD28 TESTEN
GPU_CLK_TEST_P GPU_CLK_TEST_N
AK10 CLKTESTA AL10 CLKTESTB
402 1%
R8214 1 402 1%
R8215 1
FCBGA
OMIT
MAB1_0/MAB_8 MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12 MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1
P8 T9 P9 N7 N8 N9 U9 U8
FB_B0_A<0> FB_B0_A<1> FB_B0_A<2> FB_B0_A<3> FB_B0_A<4> FB_B0_A<5> FB_B0_A<6> FB_B0_A<7>
Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9
FB_B1_A<0> FB_B1_A<1> FB_B1_A<2> FB_B1_A<3> FB_B1_A<4> FB_B1_A<5> FB_B1_A<6> FB_B1_A<7>
OUT
6 77 97
OUT
6 77 97
OUT
6 77 97
OUT
6 77 97
OUT
6 77 97
Signal aliases required by this page:
OUT
6 77 97
(NONE)
OUT
6 77 97
OUT
6 77 97
OUT
6 77 97
OUT
6 77 97
OUT
6 77 97
OUT
6 77 97
OUT
6 77 97
OUT
6 77 97
OUT
6 77 97
OUT
6 77 97
6 77 97
BI
6 77 97
WCKB0_1/DQMB_2 T3 WCKB0_1*/DQMB_3 T5
FB_B0_WCLK_P<1> FB_B0_WCLK_N<1>
BI
6 77 97
BI
6 77 97
WCKB1_0/DQMB_4 AE4 WCKB1_0*/DQMB_5 AF5
FB_B1_WCLK_P<0> FB_B1_WCLK_N<0>
BI
6 77 97
BI
6 77 97
WCKB1_1/DQMB_6 AK6 WCKB1_1*/DQMB_7 AK5
FB_B1_WCLK_P<1> FB_B1_WCLK_N<1>
BI
6 77 97
BI
6 77 97
BI
6 77 97
BI
6 77 97
BI
6 77 97
BI
6 77 97
BI
6 77 97
BI
6 77 97
BI
6 77 97
BI
6 77 97
BI
6 77 97
BI
6 77 97
BI
6 77 97
BI
6 77 97
BI
6 77 97
BI
6 77 97
BI
6 77 97
BI
6 77 97
BI
6 77 97
EDCB0_0/QSB_0/RDQSB_0 EDCB0_1/QSB_1/RDQSB_1 EDCB0_2/QSB_2/RDQSB_2 EDCB0_3/QSB_3/RDQSB_3
F6 K3 P3 V5
FB_B0_EDC<0> FB_B0_EDC<1> FB_B0_EDC<2> FB_B0_EDC<3>
EDCB1_0/QSB_4/RDQSB_4 EDCB1_1/QSB_5/RDQSB_5 EDCB1_2/QSB_6/RDQSB_6 EDCB1_3/QSB_7/RDQSB_7
AB5 AH1 AJ9 AM5
FB_B1_EDC<0> FB_B1_EDC<1> FB_B1_EDC<2> FB_B1_EDC<3>
DDBIB0_0/QSB_0B/WDQSB_0 DDBIB0_1/QSB_1B/WDQSB_1 DDBIB0_2/QSB_2B/WDQSB_2 DDBIB0_3/QSB_3B/WDQSB_3
G7 K1 P1 W4
FB_B0_DBI_L<0> FB_B0_DBI_L<1> FB_B0_DBI_L<2> FB_B0_DBI_L<3>
DDBIB1_0/QSB_4B/WDQSB_4 DDBIB1_1/QSB_5B/WDQSB_5 DDBIB1_2/QSB_6B/WDQSB_6 DDBIB1_3/QSB_7B/WDQSB_7
AC4 AH3 AJ8 AM3
FB_B1_DBI_L<0> FB_B1_DBI_L<1> FB_B1_DBI_L<2> FB_B1_DBI_L<3>
ADBIB0/ODTB0 T7 ADBIB1/ODTB1 W7
FB_B0_ABI_L FB_B1_ABI_L FB_B0_CLK_P FB_B0_CLK_N
OUT
77 97
OUT
77 97
CLKB1 AD8 CLKB1* AD7
FB_B1_CLK_P FB_B1_CLK_N
OUT
77 97
OUT
77 97
RASB0* T10 RASB1* Y10
FB_B0_RAS_L FB_B1_RAS_L
OUT
77 97
OUT
77 97
CASB0* W10 CASB1* AA10
FB_B0_CAS_L FB_B1_CAS_L
OUT
77 97
OUT
77 97
FB_B0_CS_L
OUT
77 97
FB_B1_CS_L
OUT
77 97
NC
CSB1_0* AD10 CSB1_1* AC10
NC
CKEB0 U10 CKEB1 AA11
FB_B0_CKE_L FB_B1_CKE_L
OUT
77 97
OUT
77 97
WEB0* N10 WEB1* AB11
FB_B0_WE_L FB_B1_WE_L
OUT
77 97
OUT
77 97
FB_B0_A<8> FB_B1_A<8>
OUT
6 77 97
OUT
6 77 97
MAB0_8 T8 MAB1_8 W8 DRAM_RST AH11
NOSTUFF
2
C8251
10% 16V 2 X5R 402-1
100 77 76 75 74 7
PP1V5_S0GPU_ISNS
GPU_CLK_TEST_RC_P 1
PP1V5_S0GPU_ISNS
40.2
R8202
PP1V5_S0GPU_ISNS
GPU:WHISTLER 1
A PLACE_NEAR=U8000.L18:2.54MM
R8200
PLACE_NEAR=U8000.L20:2.54MM
40.2
PLACE_NEAR=U8000.L18:2.54MM
100
GPU:WHISTLER
100
1% 1/16W MF-LF 2 402
1
C8200
GPU:WHISTLER
0.1UF
1% 1/16W MF-LF 2 402
100 77 76 75 74 7
FB_B_VREFD
R8205
1
C8201 0.1UF
100 1% 1/16W MF-LF 2 402
1
1
R82601
C8252
R8262 FB_RESET_RC_L
1
51
2
FB_RESET_L
C8260 120PF
GPU_CLK_TEST_RC_N 1
R8252 51.1
NOSTUFF
1% 1/16W MF-LF 2 402
R8206
C8202
40.2
0.1UF
10% 2 16V X5R 402-1
1% 1/16W MF-LF
402 PLACE_NEAR=U8000.AA12:2.54MM 2
FB_B_VREFS PLACE_NEAR=U8000.AA12:2.54MM
R8207
10% 16V 2 X5R 402-1
SYNC_MASTER=K92_MLB
75
100
1% 1/16W MF-LF 2 402
1
SYNC_DATE=08/03/2010
PAGE TITLE
PLACE_NEAR=U8000.AA12:2.54MM 1
Whistler FRAME BUFFER I/F
C8203
DRAWING NUMBER
0.1UF
10% 16V 2 X5R 402-1
Apple Inc.
5
4
SIZE
D REVISION
R
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
6
76 77 97
5% 50V 2 CERM 402
NOTICE OF PROPRIETARY PROPERTY:
7
OUT
5% 1/16W MF-LF 402 1
5% 1/16W MF-LF 402 2
10% 16V 2 X5R 402-1
2
5% 1/16W MF-LF 402
5.1K
0.1UF
GPU:WHISTLER
8
10
1 75
GPU:WHISTLER
10% 16V 2 X5R 402-1
51.1 1% 1/16W MF-LF 402 2
PP1V5_S0GPU_ISNS
PLACE_NEAR=U8000.Y12:2.54MM 1
75
PLACE_NEAR=U8000.L20:2.54MM
R8203
75
NOSTUFF
1% 1/16W MF-LF 2 402
PLACE_NEAR=U8000.Y12:2.54MM
1
1
R8201
PLACE_NEAR=U8000.Y12:2.54MM
1% 1/16W MF-LF 2 402
PLACE_NEAR=U8000.L20:2.54MM
FB_A_VREFD PLACE_NEAR=U8000.L18:2.54MM
40.2
FB_A_VREFS
1% 1/16W MF-LF 2 402
R82511
R8204
1
GPU:WHISTLER
NOSTUFF 1
0.1UF
GPU:WHISTLER
B
GPU_FB_RESET_L 1
2
100 77 76 75 74 7
C
6 77 97
BI
CLKB0 L9 CLKB0* L8
CSB0_0* P10 CSB0_1* L10
D
R8261
1/16W MF-LF
243
BOM options provided by this page: (NONE)
BI
5% 1/16W MF-LF 402 2
GPU:WHISTLER FB_CALRP0 1/16W MF-LF FB_CALRP1 FB_CALRP2 243 2 243
- =PP1V5R1V35_FB_REF
FB_B0_WCLK_P<0> FB_B0_WCLK_N<0>
10K
MEM_CALRP0 MEM_CALRP1 MEM_CALRP2
Power aliases required by this page: - =PP1V5R1V35_FB_CAL
WCKB0_0/DQMB_0 H3 WCKB0_0*/DQMB_1 H1
243 2 GPU:WHISTLER
402 1% 1/16W MF-LF
76 75 74 7 100 77
MAB0_0/MAB_0 MAB0_1/MAB_1 MAB0_2/MAB_2 MAB0_3/MAB_3 MAB0_4/MAB_4 MAB0_5/MAB_5 MAB0_6/MAB_6 MAB0_7/MAB_7
(5 OF 9) MEM INTERFACE B
DQB1_0/DQB32 DQB1_1/DQB33 DQB1_2/DQB34 DQB1_3/DQB35 DQB1_4/DQB36 DQB1_5/DQB37 DQB1_6/DQB38 DQB1_7/DQB39 DQB1_8/DQB40 DQB1_9/DQB41 DQB1_10/DQB42 DQB1_11/DQB43 DQB1_12/DQB44 DQB1_13/DQB45 DQB1_14/DQB46 DQB1_15/DQB47 DQB1_16/DQB48 DQB1_17/DQB49 DQB1_18/DQB50 DQB1_19/DQB51 DQB1_20/DQB52 DQB1_21/DQB53 DQB1_22/DQB54 DQB1_23/DQB55 DQB1_24/DQB56 DQB1_25/DQB57 DQB1_26/DQB58 DQB1_27/DQB59 DQB1_28/DQB60 DQB1_29/DQB61 DQB1_30/DQB62 DQB1_31/DQB63
402 1% 1/16W MF-LF
R8213 1
U8000 WHISTLER 40NM-ES
3
2
BRANCH
PAGE
82 OF 132 SHEET
75 OF 101
1
A
8
7
6
5
4
3
2
GPU:WHISTLER is the BOM option called out on ALL Rs and Cs on this page!
32MX32-1.25GHZ-MFL
Page Notes U8400
Power aliases required by this page:
(NONE) BOM options provided by this page: GPU:WHISTLER is the BOM option called out on all Rs and Cs on this page
97 75 6
IN
97 75 6
IN
97 75 6 97 75 6
IN IN
D
97 75 6
IN
75 6 97 75 6 97
IN
97 75 6
IN
1
R8401 1R8402 60.4
1% 1/16W MF-LF 2 402 97 75
IN
97 75
IN
60.4 1% 1/16W MF-LF 2 402
97 75
97 75
IN
IN
IN
97 75
IN
97 75
IN
97 75
IN
1
R8400
1% 1/20W MF 201 2
H11 K10 K11 H10
FB_A0_A<2> FB_A0_A<5> FB_A0_A<4> FB_A0_A<3>
BA0/A2 BA1/A5 BA2/A4 BA3/A3
DBI0* DBI1* DBI2* DBI3*
(1 OF 2)
OMIT
R84041
R84031
120
97 77 76 75
IN
120
1% 1/20W MF 201 2
1% 1/20W MF 201 2
97 75 6
97 75 6
BI BI
97 75 6
BI
97 75 6 97 75 6
C
IN
97 75 6
97 75 6
97 75 6 97 75 6
BI
IN IN
IN IN
FB_A0_A<7> FB_A0_A<1> FB_A0_A<0> FB_A0_A<6> FB_A0_CKE_L
K4 H5 H4 K5 J3
FB_A0_CLK_P FB_A0_CLK_N FB_A0_CS_L FB_A0_WE_L FB_A0_CAS_L FB_A0_RAS_L FB_A0_ZQ FB_A0_MF FB_A0_SEN FB_RESET_L
J12 J11 G12 L12 L3 G3 J13 J1 J10 J2
A8/A7 A9/A1 A10/A0 A11/A6 CKE*
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
CK CK* CS* WE* CAS* RAS* ZQ MF (MF=0) SEN RESET*
J4 ABI*
FB_A0_ABI_L
C2 C13 R13 R2
FB_A0_EDC<0> FB_A0_EDC<1> FB_A0_EDC<3> FB_A0_EDC<2>
EDC0 EDC1 EDC2 EDC3
D4 WCK01 D5 WCK01*
FB_A0_WCLK_P<0> FB_A0_WCLK_N<0>
P4 WCK23 P5 WCK23*
FB_A0_WCLK_P<1> FB_A0_WCLK_N<1>
U8400 32MX32-1.25GHZ-MFL
NC
BGA H5GQ1H24AFR-T2C 100 77 74 7 76 75
PP1V5_S0GPU_ISNS
1
C8400 4.7UF
20% 2 6.3V X5R 402
1
C8403 4.7UF
20% 6.3V 2 X5R 402
1
B
C8406 1UF
10% 6.3V 2 CERM-X5R 402
1
C8410 1UF
10% 6.3V 2 CERM-X5R 402
1
C8414 1UF
10% 2 6.3V CERM-X5R 402
1
C8418 0.1UF
10% 6.3V 2 X5R 201
A
1
C8422 0.1UF
10% 2 6.3V X5R 201
1
C8401 4.7UF
20% 6.3V 2 X5R 402
1
C8404 4.7UF
20% 6.3V 2 X5R 402
1
C8407 1UF
10% 6.3V 2 CERM-X5R 402
1
C8411 1UF
10% 6.3V 2 CERM-X5R 402
1
C8415 1UF
10% 2 6.3V CERM-X5R 402
1
C8419 0.1UF
10% 6.3V 2 X5R 201
1
C8423 0.1UF
10% 6.3V 2 X5R 201
1
C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10
C8402 4.7UF
20% 2 6.3V X5R 402
1
C8405 4.7UF
20% 6.3V 2 X5R 402
1
C8408 1UF
10% 6.3V 2 CERM-X5R 402
1
C8412 1UF
10% 6.3V 2 CERM-X5R 402
1
C8416 0.1UF
10% 2 6.3V X5R 201
1
C8420 0.1UF
10% 6.3V 2 X5R 201
1
C8424 0.1UF
10% 2 6.3V X5R 201
76 76 76
8
D2 D13 P13 P2
FB_A0_DBI_L<0> FB_A0_DBI_L<1> FB_A0_DBI_L<3> FB_A0_DBI_L<2>
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
1
C8409 1UF
10% 6.3V 2 CERM-X5R 402
1
C8413 1UF
10% 6.3V 2 CERM-X5R 402
1
C8417 0.1UF
10% 6.3V 2 X5R 201
1
C8421 0.1UF
10% 6.3V 2 X5R 201
1
C8425 0.1UF
10% 6.3V 2 X5R 201
FB_A0_VREFC FB_A0_VREFD1 FB_A0_VREFD2
(2 OF 2)
OMIT
VDD
B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14
A5 J5 U5
FB_A0_DQ<0> FB_A0_DQ<1> FB_A0_DQ<2> FB_A0_DQ<3> FB_A0_DQ<4> FB_A0_DQ<5> FB_A0_DQ<6> FB_A0_DQ<7> FB_A0_DQ<8> FB_A0_DQ<9> FB_A0_DQ<10> FB_A0_DQ<11> FB_A0_DQ<14> FB_A0_DQ<13> FB_A0_DQ<12> FB_A0_DQ<15> FB_A0_DQ<31> FB_A0_DQ<30> FB_A0_DQ<29> FB_A0_DQ<28> FB_A0_DQ<26> FB_A0_DQ<27> FB_A0_DQ<24> FB_A0_DQ<25> FB_A0_DQ<20> FB_A0_DQ<23> FB_A0_DQ<21> FB_A0_DQ<22> FB_A0_DQ<17> FB_A0_DQ<18> FB_A0_DQ<16> FB_A0_DQ<19>
BI
6 75 97
BI
6 75 97
NC
FB_A0_A<8>
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
1% 1/16W MF-LF 2 402
76
60.4 1% 1/16W MF-LF 2 402
10% 6.3V 2 CERM-X5R 402
C8450
C8453
1
1% 1/16W MF-LF 2 402
20% 6.3V 2 X5R 402
C8431
VSSQ
IN
97 75
IN
1% 1/16W MF-LF 2 402
1% 1/20W MF 201 2
1
R8454
R84531
120
10% 2 6.3V CERM-X5R 402
1% 1/20W MF 201 2
1
2.37K
1% 1/16W MF-LF 2 402
76
1
C8432
C8456
C8460 1UF
1UF
10% 6.3V 2 CERM-X5R 402
10% 6.3V 2 CERM-X5R 402
1
C8451
1
4.7UF
20% 2 6.3V X5R 402
1
C8454
4.7UF
20% 6.3V 2 X5R 402
1
4.7UF
20% 2 6.3V X5R 402
C8452
C8455 4.7UF
20% 6.3V 2 X5R 402
1
C8457 1UF
10% 6.3V 2 CERM-X5R 402
1
C8458 1UF
10% 6.3V 2 CERM-X5R 402
1
C8459 1UF
10% 6.3V 2 CERM-X5R 402
1
R8433
1
5.49K 1% 1/16W MF-LF 2 402
C8461 1UF
10% 6.3V 2 CERM-X5R 402
C8464
10% 6.3V 2 CERM-X5R 402
1UF
10% 6.3V 2 CERM-X5R 402
C8468 0.1UF
10% 6.3V 2 X5R 201
PP1V5_S0GPU_ISNS
75 74 7 100 77 76
1
R8434
1
2.37K
1% 1/16W MF-LF 2 402
1
C8462 1UF
10% 6.3V 2 CERM-X5R 402
1
C8463 1UF
10% 6.3V 2 CERM-X5R 402
1
1% 1/16W MF-LF 2 402
1UF
10% 6.3V 2 CERM-X5R 402
1
C8469 0.1UF
10% 2 6.3V X5R 201
C8466 0.1UF
10% 6.3V 2 X5R 201
1
C8470 0.1UF
10% 6.3V 2 X5R 201
1
C8472 0.1UF
1
1
C8473 0.1UF
10% 6.3V 2 X5R 201
1
C8474 0.1UF
10% 6.3V 2 X5R 201
C8467 0.1UF
10% 6.3V 2 X5R 201
1
C8471 0.1UF
10% 2 6.3V X5R 201
1
C8475 0.1UF
10% 6.3V 2 X5R 201
C8435 1UF
10% 6.3V 2 CERM-X5R 402
76 76 76
6
1
1UF
10% 6.3V 2 CERM-X5R 402
FB_A0_VREFD2
5.49K
C8465
1
C8434 10% 6.3V 2 X5R 201
R8435
1
1UF
C8433
1
76
1
FB_A0_VREFD1 1
IN IN
97 75
IN
97 75
IN
97 75
IN
97 75
IN
97 77 76 75
97 75 6
IN
IN
97 75 6
BI
97 75 6
BI
97 75 6
BI
97 75 6
BI
97 75 6
IN
97 75 6
IN
97 75 6
IN
97 75 6
IN
C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10
PP1V5_S0GPU_ISNS
R8432
97 75
K4 H5 H4 K5 J3
FB_A1_CLK_P FB_A1_CLK_N FB_A1_CS_L FB_A1_WE_L FB_A1_CAS_L FB_A1_RAS_L FB_A1_ZQ FB_A1_MF FB_A1_SEN FB_RESET_L
J12 J11 G12 L12 L3 G3 J13 J1 J10 J2
(1 OF 2)
OMIT
DBI0* DBI1* DBI2* DBI3*
D2 D13 P13 P2
FB_A1_DBI_L<0> FB_A1_DBI_L<1> FB_A1_DBI_L<2> FB_A1_DBI_L<3>
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2
FB_A1_DQ<1> FB_A1_DQ<0> FB_A1_DQ<3> FB_A1_DQ<2> FB_A1_DQ<4> FB_A1_DQ<6> FB_A1_DQ<5> FB_A1_DQ<7> FB_A1_DQ<9> FB_A1_DQ<8> FB_A1_DQ<11> FB_A1_DQ<10> FB_A1_DQ<12> FB_A1_DQ<13> FB_A1_DQ<14> FB_A1_DQ<15> FB_A1_DQ<21> FB_A1_DQ<22> FB_A1_DQ<23> FB_A1_DQ<20> FB_A1_DQ<18> FB_A1_DQ<19> FB_A1_DQ<17> FB_A1_DQ<16> FB_A1_DQ<31> FB_A1_DQ<30> FB_A1_DQ<28> FB_A1_DQ<29> FB_A1_DQ<25> FB_A1_DQ<27> FB_A1_DQ<24> FB_A1_DQ<26>
A8/A7 A9/A1 A10/A0 A11/A6 CKE* CK CK* CS* WE* CAS* RAS* ZQ MF (MF=0) SEN RESET*
J4 ABI*
FB_A1_ABI_L
C2 C13 R13 R2
FB_A1_EDC<0> FB_A1_EDC<1> FB_A1_EDC<2> FB_A1_EDC<3>
FB_A1_WCLK_P<0> FB_A1_WCLK_N<0>
EDC0 EDC1 EDC2 EDC3
D4 WCK01 D5 WCK01* P4 WCK23 P5 WCK23*
FB_A1_WCLK_P<1> FB_A1_WCLK_N<1>
5
NC
BGA H5GQ1H24AFR-T2C
75 74 7 100 77 76
1
IN
120
1% 1/20W MF 201 2
1UF
10% 6.3V 2 CERM-X5R 402
VDDQ
120
4.7UF
1UF
A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14
97 75
60.4
PP1V5_S0GPU_ISNS
1
5.49K
IN
75 6 97 97 75 6
6 75 97
20% 6.3V 2 X5R 402
FB_A0_VREFC
R8431
IN
75 6 97
R84501
4.7UF
C8430 1UF
1
97 75 6
R8451 1R8452
FB_A1_A<7> FB_A1_A<1> FB_A1_A<0> FB_A1_A<6> FB_A1_CKE_L
BA0/A2 BA1/A5 BA2/A4 BA3/A3
32MX32-1.25GHZ-MFL IN
1 1
IN
NC
75 74 7 100 77 76
2.37K
IN
97 75 6
H11 K10 K11 H10
FB_A1_A<2> FB_A1_A<5> FB_A1_A<4> FB_A1_A<3>
U8450
100 77 76 75 74 7
R8430
IN
97 75 6
1
PP1V5_S0GPU_ISNS 1
IN
97 75 6
PP1V5_S0GPU_ISNS
1
J14 VREFC A10 VREFD U10
7
VSS
B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10
A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2
97 75 6
6 75 97
100 77 76 75 74 7
PP1V5_S0GPU_ISNS
120
BGA H5GQ1H24AFR-T2C
BGA H5GQ1H24AFR-T2C
Signal aliases required by this page:
77 76 75 74 7 100
U8450
32MX32-1.25GHZ-MFL
- =PP1V5R1V35_S0_FB_VDD
1
FB_A1_VREFC FB_A1_VREFD1 FB_A1_VREFD2
4
B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14
(2 OF 2)
OMIT
VDD
VSS
B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10
A5 J5 U5
PP1V5_S0GPU_ISNS
75 74 7 100 77 76
FB_A1_A<8>
R8480
1
2.37K
1% 1/16W MF-LF 2 402
FB_A1_VREFC
1% 1/16W MF-LF 2 402
1
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
IN
D
C
6 75 97
R8484
1
2.37K
C8484 1UF
1% 1/16W MF-LF 2 402
76
5.49K
6 75 97
BI
1
C8480
10% 6.3V 2 CERM-X5R 402
R8481
6 75 97
BI
PP1V5_S0GPU_ISNS
1UF
1
6 75 97
BI
NC
100 77 76 75 74 7
1
76
NC
BI
10% 6.3V 2 CERM-X5R 402
FB_A1_VREFD2 1
R8485
C8481
1
5.49K
1UF
C8485 1UF
1% 1/16W MF-LF 2 402
10% 6.3V 2 CERM-X5R 402
10% 6.3V 2 CERM-X5R 402
B
VDDQ
VSSQ
J14 VREFC A10 U10 VREFD
3
A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14
PP1V5_S0GPU_ISNS
75 74 7 100 77 76
1
R8482
1
2.37K
1% 1/16W MF-LF 2 402
76
C8482 1UF
10% 6.3V 2 CERM-X5R 402
FB_A1_VREFD1 1
R8483 5.49K
1% 1/16W MF-LF 2 402
1
C8483 1UF
10% 6.3V 2 CERM-X5R 402
SYNC_MASTER=K92_MLB
SYNC_DATE=08/19/2010
PAGE TITLE
GDDR5 Frame Buffer A DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
84 OF 132 SHEET
76 OF 101
1
A
8
7
6
5
4
3
2
Page Notes
(NONE) BOM options provided by this page: (NONE)
97 75 6
IN
97 75 6
IN
97 75 6 97 75 6
IN IN
D
97 75 6
IN
75 6 97 75 6 97
IN
97 75 6
IN
1
R8501 1R8502 60.4
1% 1/16W MF-LF 2 402 97 75
IN
97 75
IN
60.4 1% 1/16W MF-LF 2 402
97 75
97 75
IN
IN
IN
97 75
IN
97 75
IN
97 75
IN
1
R8500
1% 1/20W MF 201 2
H11 K10 K11 H10
FB_B0_A<2> FB_B0_A<5> FB_B0_A<4> FB_B0_A<3>
BA0/A2 BA1/A5 BA2/A4 BA3/A3
DBI0* DBI1* DBI2* DBI3*
(1 OF 2)
OMIT
R85041
R85031
120
97 77 76 75
IN
120
1% 1/20W MF 201 2
1% 1/20W MF 201 2
97 75 6
97 75 6
BI BI
97 75 6
BI
97 75 6 97 75 6
C
IN
97 75 6
97 75 6
97 75 6 97 75 6
BI
IN IN
IN IN
FB_B0_A<7> FB_B0_A<1> FB_B0_A<0> FB_B0_A<6> FB_B0_CKE_L
K4 H5 H4 K5 J3
FB_B0_CLK_P FB_B0_CLK_N FB_B0_CS_L FB_B0_WE_L FB_B0_CAS_L FB_B0_RAS_L FB_B0_ZQ FB_B0_MF FB_B0_SEN FB_RESET_L
J12 J11 G12 L12 L3 G3 J13 J1 J10 J2
A8/A7 A9/A1 A10/A0 A11/A6 CKE*
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
CK CK* CS* WE* CAS* RAS* ZQ MF (MF=0) SEN RESET*
J4 ABI*
FB_B0_ABI_L
C2 C13 R13 R2
FB_B0_EDC<0> FB_B0_EDC<1> FB_B0_EDC<3> FB_B0_EDC<2>
EDC0 EDC1 EDC2 EDC3
D4 WCK01 D5 WCK01*
FB_B0_WCLK_P<0> FB_B0_WCLK_N<0>
P4 WCK23 P5 WCK23*
FB_B0_WCLK_P<1> FB_B0_WCLK_N<1>
U8500 32MX32-1.25GHZ-MFL
NC
BGA H5GQ1H24AFR-T2C
PP1V5_S0GPU_ISNS
1
C8500 4.7UF
20% 2 6.3V X5R 402
1
C8503 4.7UF
20% 6.3V 2 X5R 402
1
B
C8506 1UF
10% 6.3V 2 CERM-X5R 402
1
C8510 1UF
10% 6.3V 2 CERM-X5R 402
1
C8514 1UF
10% 2 6.3V CERM-X5R 402
1
C8518 0.1UF
10% 6.3V 2 X5R 201
A
1
C8522 0.1UF
10% 2 6.3V X5R 201
1
C8501 4.7UF
20% 6.3V 2 X5R 402
1
C8504 4.7UF
20% 6.3V 2 X5R 402
1
C8507 1UF
10% 6.3V 2 CERM-X5R 402
1
C8511 1UF
10% 6.3V 2 CERM-X5R 402
1
C8515 1UF
10% 2 6.3V CERM-X5R 402
1
C8519 0.1UF
10% 6.3V 2 X5R 201
1
C8523 0.1UF
10% 6.3V 2 X5R 201
1
C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10
C8502 4.7UF
20% 2 6.3V X5R 402
1
C8505 4.7UF
20% 6.3V 2 X5R 402
1
C8508 1UF
10% 6.3V 2 CERM-X5R 402
1
C8512 1UF
10% 6.3V 2 CERM-X5R 402
1
C8516 0.1UF
10% 2 6.3V X5R 201
1
C8520 0.1UF
10% 6.3V 2 X5R 201
1
C8524 0.1UF
10% 2 6.3V X5R 201
77 77 77
8
D2 D13 P13 P2
FB_B0_DBI_L<0>BI FB_B0_DBI_L<1>BI FB_B0_DBI_L<3>BI FB_B0_DBI_L<2>BI
1
C8509 1UF
10% 6.3V 2 CERM-X5R 402
1
C8513 1UF
10% 6.3V 2 CERM-X5R 402
1
C8517 0.1UF
10% 6.3V 2 X5R 201
1
C8521 0.1UF
10% 6.3V 2 X5R 201
1
C8525 0.1UF
10% 6.3V 2 X5R 201
FB_B0_VREFC FB_B0_VREFD1 FB_B0_VREFD2
(2 OF 2)
OMIT
VDD
B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14
A5 J5 U5
FB_B0_DQ<0> FB_B0_DQ<1> FB_B0_DQ<2> FB_B0_DQ<3> FB_B0_DQ<4> FB_B0_DQ<5> FB_B0_DQ<6> FB_B0_DQ<7> FB_B0_DQ<8> FB_B0_DQ<9> FB_B0_DQ<10> FB_B0_DQ<11> FB_B0_DQ<12> FB_B0_DQ<13> FB_B0_DQ<14> FB_B0_DQ<15> FB_B0_DQ<31> FB_B0_DQ<30> FB_B0_DQ<29> FB_B0_DQ<28> FB_B0_DQ<25> FB_B0_DQ<26> FB_B0_DQ<27> FB_B0_DQ<24> FB_B0_DQ<23> FB_B0_DQ<22> FB_B0_DQ<19> FB_B0_DQ<21> FB_B0_DQ<20> FB_B0_DQ<18> FB_B0_DQ<17> FB_B0_DQ<16> NC
FB_B0_A<8>
6 75 97
PP1V5_S0GPU_ISNS
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
1% 1/16W MF-LF 2 402
77
60.4 1% 1/16W MF-LF 2 402
BI
6 75 97
BI
6 75 97
10% 6.3V 2 CERM-X5R 402
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
120
1% 1/20W MF 201 2
C8550
C8553
1% 1/16W MF-LF 2 402
20% 6.3V 2 X5R 402
C8531
VSSQ
97 75
IN
1
R8554
R85531
120
10% 2 6.3V CERM-X5R 402
1% 1/20W MF 201 2
1
2.37K
1% 1/16W MF-LF 2 402
77
1
C8532
C8556
C8560 1UF
1UF
10% 6.3V 2 CERM-X5R 402
10% 6.3V 2 CERM-X5R 402
1
C8551
1
4.7UF
20% 2 6.3V X5R 402
1
C8554
4.7UF
20% 6.3V 2 X5R 402
1
4.7UF
20% 2 6.3V X5R 402
C8552
C8555 4.7UF
20% 6.3V 2 X5R 402
1
C8557 1UF
10% 6.3V 2 CERM-X5R 402
1
C8558 1UF
10% 6.3V 2 CERM-X5R 402
1
C8559 1UF
10% 6.3V 2 CERM-X5R 402
1
R8533
1
5.49K 1% 1/16W MF-LF 2 402
C8561 1UF
10% 6.3V 2 CERM-X5R 402
C8564
10% 6.3V 2 CERM-X5R 402
1UF
10% 6.3V 2 CERM-X5R 402
C8568 0.1UF
10% 6.3V 2 X5R 201
PP1V5_S0GPU_ISNS
75 74 7 100 77 76
1
R8534
1
2.37K
1% 1/16W MF-LF 2 402
1
C8562 1UF
10% 6.3V 2 CERM-X5R 402
1
C8563 1UF
10% 6.3V 2 CERM-X5R 402
1
1% 1/16W MF-LF 2 402
1UF
10% 6.3V 2 CERM-X5R 402
1
C8569 0.1UF
10% 2 6.3V X5R 201
C8566 0.1UF
10% 6.3V 2 X5R 201
1
C8570 0.1UF
10% 6.3V 2 X5R 201
1
C8572 0.1UF
1
1
C8573 0.1UF
10% 6.3V 2 X5R 201
1
C8574 0.1UF
10% 6.3V 2 X5R 201
C8567 0.1UF
10% 6.3V 2 X5R 201
1
C8571 0.1UF
10% 2 6.3V X5R 201
1
C8575 0.1UF
10% 6.3V 2 X5R 201
C8535 1UF
10% 6.3V 2 CERM-X5R 402
77 77 77
6
1
1UF
10% 6.3V 2 CERM-X5R 402
FB_B0_VREFD2
5.49K
C8565
1
C8534 10% 6.3V 2 X5R 201
R8535
1
1UF
C8533
1
77
1
FB_B0_VREFD1 1
IN
97 75
IN
97 75
IN
97 75
IN
97 75
IN
97 77 76 75
97 75 6
IN
IN
97 75 6
BI
97 75 6
BI
97 75 6
BI
97 75 6
BI
97 75 6
IN
97 75 6
IN
97 75 6
IN
97 75 6
IN
C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10
PP1V5_S0GPU_ISNS
R8532
IN
K4 H5 H4 K5 J3
FB_B1_CLK_P FB_B1_CLK_N FB_B1_CS_L FB_B1_WE_L FB_B1_CAS_L FB_B1_RAS_L FB_B1_ZQ FB_B1_MF FB_B1_SEN FB_RESET_L
J12 J11 G12 L12 L3 G3 J13 J1 J10 J2
(1 OF 2)
OMIT
DBI0* DBI1* DBI2* DBI3*
D2 D13 P13 P2
FB_B1_DBI_L<0>BI FB_B1_DBI_L<1>BI FB_B1_DBI_L<2>BI FB_B1_DBI_L<3>BI
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2
FB_B1_DQ<0> FB_B1_DQ<3> FB_B1_DQ<1> FB_B1_DQ<2> FB_B1_DQ<6> FB_B1_DQ<5> FB_B1_DQ<7> FB_B1_DQ<4> FB_B1_DQ<8> FB_B1_DQ<9> FB_B1_DQ<10> FB_B1_DQ<11> FB_B1_DQ<12> FB_B1_DQ<13> FB_B1_DQ<14> FB_B1_DQ<15> FB_B1_DQ<23> FB_B1_DQ<22> FB_B1_DQ<21> FB_B1_DQ<20> FB_B1_DQ<19> FB_B1_DQ<18> FB_B1_DQ<16> FB_B1_DQ<17> FB_B1_DQ<31> FB_B1_DQ<26> FB_B1_DQ<30> FB_B1_DQ<29> FB_B1_DQ<27> FB_B1_DQ<28> FB_B1_DQ<24> FB_B1_DQ<25>
A8/A7 A9/A1 A10/A0 A11/A6 CKE* CK CK* CS* WE* CAS* RAS* ZQ MF (MF=0) SEN RESET*
J4 ABI*
FB_B1_ABI_L
C2 C13 R13 R2
FB_B1_EDC<0> FB_B1_EDC<1> FB_B1_EDC<2> FB_B1_EDC<3>
FB_B1_WCLK_P<0> FB_B1_WCLK_N<0>
EDC0 EDC1 EDC2 EDC3
D4 WCK01 D5 WCK01* P4 WCK23 P5 WCK23*
FB_B1_WCLK_P<1> FB_B1_WCLK_N<1>
5
NC
BGA H5GQ1H24AFR-T2C
75 74 7 100 77 76
1
97 75
120
1% 1/20W MF 201 2
1UF
10% 6.3V 2 CERM-X5R 402
VDDQ
IN
1% 1/16W MF-LF 2 402
PP1V5_S0GPU_ISNS
1UF
A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14
97 75
60.4
6 75 97
4.7UF
1
IN
FB_B1_A<7> FB_B1_A<1> FB_B1_A<0> FB_B1_A<6> FB_B1_CKE_L
BA0/A2 BA1/A5 BA2/A4 BA3/A3
32MX32-1.25GHZ-MFL IN
1
5.49K
IN
75 6 97 97 75 6
R85501
20% 6.3V 2 X5R 402
FB_B0_VREFC
R8531
IN
75 6 97
R8551 1R8552
4.7UF
C8530 1UF
1
97 75 6
1
77 77
1 1
IN
NC
75 74 7 100 77 76
2.37K
IN
97 75 6
H11 K10 K11 H10
FB_B1_A<2> FB_B1_A<5> FB_B1_A<4> FB_B1_A<3>
U8550
100 77 76 75 74 7
R8530
IN
97 75 6 6 75 97
PP1V5_S0GPU_ISNS 1
IN
97 75 6 6 75 97
1
J14 VREFC A10 VREFD U10
7
VSS
B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10
A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2
97 75 6 6 75 97
100 77 76 75 74 7
PP1V5_S0GPU_ISNS
120
BGA H5GQ1H24AFR-T2C
BGA H5GQ1H24AFR-T2C
Signal aliases required by this page:
100 77 74 7 76 75
32MX32-1.25GHZ-MFL
32MX32-1.25GHZ-MFL
- =PP1V5R1V35_S0_FB_VDD
77 76 75 74 7 100
U8550
U8500
Power aliases required by this page:
1
FB_B1_VREFC FB_B1_VREFD1 FB_B1_VREFD2
4
B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14
(2 OF 2)
OMIT
VDD
VSS
B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10
A5 J5 U5
PP1V5_S0GPU_ISNS
75 74 7 100 77 76
FB_B1_A<8>
R8580
1
2.37K
1% 1/16W MF-LF 2 402
FB_B1_VREFC
1% 1/16W MF-LF 2 402
1
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
BI
6 75 97
IN
D
C
6 75 97
R8584
1
2.37K
C8584 1UF
1% 1/16W MF-LF 2 402
77
5.49K
6 75 97
1
C8580
10% 6.3V 2 CERM-X5R 402
R8581
6 75 97
PP1V5_S0GPU_ISNS
1UF
1
6 75 97
NC
100 77 76 75 74 7
1
77
NC
6 75 97
10% 6.3V 2 CERM-X5R 402
FB_B1_VREFD2 1
R8585
C8581
1
5.49K
1UF
C8585 1UF
1% 1/16W MF-LF 2 402
10% 6.3V 2 CERM-X5R 402
10% 6.3V 2 CERM-X5R 402
B
VDDQ
VSSQ
J14 VREFC A10 U10 VREFD
3
A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14
PP1V5_S0GPU_ISNS
75 74 7 100 77 76
1
R8582
1
2.37K
1% 1/16W MF-LF 2 402
77
C8582 1UF
10% 6.3V 2 CERM-X5R 402
FB_B1_VREFD1 1
R8583 5.49K
1% 1/16W MF-LF 2 402
1
C8583 1UF
10% 6.3V 2 CERM-X5R 402
SYNC_MASTER=K92_MLB
SYNC_DATE=08/19/2010
PAGE TITLE
GDDR5 Frame Buffer B DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
85 OF 132 SHEET
77 OF 101
1
A
YES
K91F SAMSUNG 512M
NO
NO
NO
K91F HYNIX 512M
NO
YES
NO
K91F SAMSUNG 1G
YES
NO
NO
K91F HYNIX 1G
YES
YES
NO
NOSTUFF
VRAM_DVP2
VRAM_DVP1
TP_DVPCLK
NOTE: AMD STRAPS FOR IDENTIFYING VRAM VENDOR & SIZE FOR WHISTLER K92 Samsung 1G - NOSTUFF R8613, NOSTUFF R8612, STUFF R8611 K92 Hynix 1G STUFF R8613, NOSTUFF R8612, STUFF R8611 512M 512M 1G 1G
- NOSTUFF R8613, NOSTUFF R8612, - NOSTUFF R8613, STUFF R8612, STUFF R8613, NOSTUFF R8612, STUFF R8613, STUFF R8612,
NOSTUFF NOSTUFF NOSTUFF NOSTUFF
R8611 R8611 R8611 R8611
NO STRAP CHANGES ARE REQUIRED FOR SEYMOUR BASED SYSTEMS
83 81 79 78 74 71 7 6
PP3V3_S0GPU 1
1
R8600
R8601
4.7K
AU1 AU3 AW3 AP6 AW5 AU5 AR6 AW6 AU6 AT7 AV7 AN7 AV9 AT9 AR10 AW10 AU10 AP10 AV11 AT11 AR12 AW12 AU12 AP12
4.7K
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
NC NC
79 79 79 79 79 79 81 79 87 79 79 79 79 79 79 79 79 81 79 100 80 78 74 7
PP1V8_S0GPU_ISNS
81 79 79
1
R8602
79
499
79
1% 1/16W MF-LF 402 2
81 79 86 79 79 79
1
C8600 1 R8603 249 0.1UF
10% 16V X5R 2 402-1
B
79
1% 1/16W MF-LF 402 2
79 79 79 79
79 79 79
CRITICAL
79
L8600
79
470OHM-1A-150MOHM 100 74 7 80 78
PP1V8_S0GPU_ISNS
1
VOLTAGE=1.8V
79
2
79
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V
0603 1
C8601
1
10UF
20% 10V 2 X5R 603
C8602
1
1UF
10% 25V 2 X5R 402
10% 16V 2 X5R 402-1
L8601
1
1
2
TP_GPU_JTAG_TRST_L TP_GPU_JTAG_TDI TP_GPU_JTAG_TCK TP_GPU_JTAG_TMS TP_GPU_JTAG_TDO
AM23 AN23 AK23 AL24 AM24
JTAG_TRST* JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO
NC_GPU_GENERICA NC_GPU_GENERICB NC_GPU_GENERICC DP_CA_DET_EG_R NC_GPU_GENERICE NC_GPU_GENERICF NC_GPU_GENERICG
AJ19 AK19 AJ20 AK20 AJ24 AH26 AH24
GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 GENERICF_HPD5 GENERICG_HPD6
DP_EG_HPD
AK24 HPD1
C8604
20% 2 10V X5R 603
1
C8605 1UF
10% 2 25V X5R 402
1
PP1V8_GPU_DPLL (GND_GPU_DPLL)
125mA
C8606
97 79
IN
GPU_CLK27M
AW34 XO_IN
97 79
IN
GPU_CLK100M
AW35 XO_IN2
0.1UF
10% 2 16V X5R 402-1
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
98 50
IN
98 50
OUT
L8602
PP1V8_S0GPU_ISNS
1
2
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V
0402 1
XW8601 SM 1
C8607 10UF
20% 10V 2 X5R 603
2
1
C8608 1UF
10% 25V 2 X5R 402
1
PP1V8_GPU_TSVDD (GND_GPU_TSVSS)
20mA
NC
AK32 TS_FDO
NC
AL31 TSA/NC AJ32 TSVDD AJ33 TSVSS
0.1UF
10% 16V 2 X5R 402-1
8
7
84 97
TX1P_DPA1P AU26 TX1M_DPA1N AV25
DP_EXTA_ML_C_P<1> DP_EXTA_ML_C_N<1>
OUT
84 97
- =PP1V8_GPU_DPLL
OUT
84 97
- =PP1V0_GPU_DPLL
TX2P_DPA0P AT27 TX2M_DPA0N AR26
DP_EXTA_ML_C_P<0> DP_EXTA_ML_C_N<0>
OUT
84 97
OUT
84 97
TXCBP_DPB3P AR30 TXCBM_DPB3N AT29
DP_T29SNK0_ML_C_P<3> DP_T29SNK0_ML_C_N<3>
OUT
6 33 95
OUT
6 33 95
TX3P_DPB2P AV31 TX3M_DPB2N AU30
DP_T29SNK0_ML_C_P<2> DP_T29SNK0_ML_C_N<2>
OUT
6 33 95
OUT
6 33 95
TX4P_DPB1P AR32 TX4M_DPB1N AT31
DP_T29SNK0_ML_C_P<1> DP_T29SNK0_ML_C_N<1>
OUT
6 33 95
OUT
6 33 95
TX5P_DPB0P AT33 TX5M_DPB0N AU32
DP_T29SNK0_ML_C_P<0> DP_T29SNK0_ML_C_N<0>
OUT
6 33 95
OUT
6 33 95
TXCCP_DPC3P AU14 TXCCM_DPC3N AV13
DP_T29SNK1_ML_C_P<3> DP_T29SNK1_ML_C_N<3>
OUT
6 33 95
OUT
6 33 95
TX0P_DPC2P AT15 TX0M_DPC2N AR14
DP_T29SNK1_ML_C_P<2> DP_T29SNK1_ML_C_N<2>
OUT
6 33 95
OUT
6 33 95
TX1P_DPC1P AU16 TX1M_DPC1N AV15
DP_T29SNK1_ML_C_P<1> DP_T29SNK1_ML_C_N<1>
OUT
6 33 95
OUT
6 33 95
TX2P_DPC0P AT17 TX2M_DPC0N AR16
DP_T29SNK1_ML_C_P<0> DP_T29SNK1_ML_C_N<0>
OUT
6 33 95
OUT
6 33 95
TXCDP_DPD3P AU20 TXCDM_DPD3N AT19
NC NC
TX3P_DPD2P AT21 TX3M_DPD2N AR20
NC NC
TX4P_DPD1P AU22 TX4M_DPD1N AV21
NC NC
TX5P_DPD0P AT23 TX5M_DPD0N AR22
NC NC
R AD39 R* AD37
NC NC
G AE36 G* AD35
NC NC
B AF37 B* AE38
NC NC
HSYNC AC36 VSYNC AC38
- =PP3V3_GPU_I2C - =PP1V8_GPU_VREFG
- =PP1V0_GPU_TS
PP3V3_S0GPU 6 7 71 74 78 79 81 83 Straps for audio on DP and HDMI
R86041
5
R8605 10K
5% 1/16W MF-LF 402 2
PP1V8_S0GPU_ISNS
5% 1/16W MF-LF 2 402
7 74 78 80 100
VARY_BL AK27 DIGON AJ27
U8000 FCBGA (3 OF 9)
NC NC
G2/NC AD30 G2*/NC AD31
NC NC
B2/NC AF30 B2*/NC AF31
NC NC
C/NC AC32 Y/NC AD32 COMP/NC AF32
NC NC NC
H2SYNC/GENLK_CLK AD29 V2SYNC/GENLK_VSYNC AC29
NC NC
VDD2DI/NC AG31 VSS2DI/NC AG32
NC NC
A2VDD/NC AG33
NC
A2VDDQ/NC AD33
NC
XW8602 SM
GND_GPU_TVSSQ
1
2
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm NC VOLTAGE=0V
DP_EG_DDC_CLK DP_EG_DDC_DATA
NC_LVDS_EG_B_CLK_P NC_LVDS_EG_B_CLK_N
TXOUT_U0P_DPF2P AJ38 TXOUT_U0N_DPF2N AK37
LVDS_EG_B_DATA_P<0> LVDS_EG_B_DATA_N<0>
TXOUT_U1P_DPF1P AH35 TXOUT_U1N_DPF1N AJ36
LVDS_EG_B_DATA_P<1> LVDS_EG_B_DATA_N<1>
TXOUT_U2P_DPF0P AG38 TXOUT_U2N_DPF0N AH37
LVDS_EG_B_DATA_P<2> LVDS_EG_B_DATA_N<2>
TXOUT_U3P AF35 TXOUT_U3N AG36 TXCLK_LP_DPE3P AP34 TXCLK_LN_DPE3N AR34
OUT
79 87
1
R8606
79
10K
79
OUT
87 97
OUT
87 97
OUT
87 97
OUT
87 97
OUT
87 97
OUT
NC_LVDS_EG_B_DATA_P<3> NC_LVDS_EG_B_DATA_N<3>
79 97
OUT
87 97
OUT
87 97
TXOUT_L0P_DPE2P AW37 TXOUT_L0N_DPE2N AU35
LVDS_EG_A_DATA_P<0> LVDS_EG_A_DATA_N<0>
OUT
87 97
OUT
87 97
TXOUT_L1P_DPE1P AR37 TXOUT_L1N_DPE1N AU39
LVDS_EG_A_DATA_P<1> LVDS_EG_A_DATA_N<1>
OUT
87 97
OUT
87 97
TXOUT_L2P_DPE0P AP35 TXOUT_L2N_DPE0N AR35
LVDS_EG_A_DATA_P<2> LVDS_EG_A_DATA_N<2>
OUT
87 97
NC_LVDS_EG_A_DATA_P<3> NC_LVDS_EG_A_DATA_N<3>
B
87 97
79 97
LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N
OUT
5% 1/16W MF-LF 2 402
87 97
79 97 79 97
79 83 79 83
DP_EG_AUXCH_P DP_EG_AUXCH_N
BI
8 83 97
BI
8 83 97
AUX2P AN20 AUX2N AM20
DP_T29SNK0_AUXCH_C_P DP_T29SNK0_AUXCH_C_N
BI
6 33 95
BI
6 33 95
DDCCLK_AUX3P AL30 DDCDATA_AUX3N AM30
DP_T29SNK1_AUXCH_C_P DP_T29SNK1_AUXCH_C_N
BI
6 33 95
BI
6 33 95
AUX1P AM27 AUX1N AL27
TXCLK_UP_DPF3P AK35 TXCLK_UN_DPF3N AL36
TXOUT_L3P AN36 TXOUT_L3N AP37 OUT
LVDS_EG_BLK_PWM EG_LCD_PWR_EN
LVDS CNTL
OMIT
BI
NC NC
SYNC_MASTER=K92_MLB
SYNC_DATE=12/01/2010
PAGE TITLE
Whistler LVDS/DP/GPIO
NC NC
DDCCLK_AUX5P AN21 DDCDATA_AUX5N AM21
4
C
1
10K
DRAWING NUMBER
LVDS_EG_DDC_CLK LVDS_EG_DDC_DATA
OUT BI
83
Apple Inc.
83
SIZE
D REVISION
R
NC NC
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
NC NC
VOLTAGE=0V
6
D
NC
R2/NC AC30 R2*/NC AC31
DDCCLK_AUX4P AL29 DDCDATA_AUX4N AM29
BOM options provided by this page: (NONE)
VDD1DI AC33 VSS1DI AC34
DDC2CLK AM19 DDC2DATA AL19
Signal aliases required by this page: (NONE)
GPU_AUD_1 GPU_AUD_0
AVDD AD34 AVSSQ AE34
DDCCLK_AUX7P AK30 DDCDATA_AUX7N AK29
GND_GPU_TSVSS MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm
84 97
DDC6CLK AJ30 DDC6DATA AJ31
C8609
Page Notes Power aliases required by this page:
OUT
DDC1CLK AM26 DDC1DATA AN26
AF29 DPLUS AG29 DMINUS
GPU_TDIODE_P GPU_TDIODE_N
120OHM-0.3A 100 74 7 80 78
AV33 XTALIN AU34 XTALOUT
84 97
1
OUT
R2SET/NC AA29
AN31 DPLL_VDDC
OUT
2
DP_EXTA_ML_C_P<2> DP_EXTA_ML_C_N<2>
RSET AB34
AM32 DPLL_PVDD AN32 DPLL_PVSS
75mA
NC NC
GND_GPU_DPLL CRITICAL
GPIO_0 GPIO_1 GPIO_2 GPIO_3_SMBDATA GPIO_4_SMBCLK GPIO_5_AC_BATT GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16 GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21_BB_EN GPIO_22_ROMCS* GPIO_23_CLKREQ*
AH13 VREFG
GPU_VREFG
PP1V0_GPU_DPLL
10UF
A
AH20 AH18 AN16 AH23 AJ23 AH17 AJ17 AK17 AJ13 AH15 AJ16 AK16 AL16 AM16 AM14 AM13 AK14 AG30 AN14 AM17 AL13 AJ14 AK13 AN13
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1V 1
XW8600 SM
GPU_PCIE_TX_PWR GPU_GPIO_TX_DEEMP GPU_PCIE_GEN2 GPU_SMB_DAT GPU_SMB_CLK GPU_AC_BATT GPU_VCORE_VID0 EG_BKLT_EN GPU_ROM_SO GPU_ROM_SI GPU_ROM_SCLK GPU_CONFIG_0 GPU_CONFIG_1 GPU_CONFIG_2 DP_T29SNK0_HPD_GPU GPU_VCORE_VID1 GPU_VCORE_VID2 SMC_GFX_THROTTLE_R_L DP_T29SNK1_HPD_GPU SMC_GFX_OVERTEMP_R_L GPU_VCORE_VID3 FBVDD_ALTVO GPU_ROM_CS_L PEX_CLKREQ_L_R
2 0603
AJ21 SWAPLOCKA AK21 SWAPLOCKB
OUT
84 97
TX0P_DPA2P AT25 TX0M_DPA2N AR24
A2VSSQ/TSVSSQ AF33
0.1UF
470OHM-1A-150MOHM PP1V0_S0GPU_ISNS
OMIT
C8603
CRITICAL 100 73 7 80 74
83 79
DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23
AK26 SCL AJ26 SDA
GPU_I2C_SCL GPU_I2C_SDA
C
FCBGA (2 OF 9)
AR1 DVPCLK
DVPDATA<0> DVPDATA<1> DVPDATA<2> DVPDATA<3> TP_DVPDATA<4> TP_DVPDATA<5> TP_DVPDATA<6> TP_DVPDATA<7> TP_DVPDATA<8> TP_DVPDATA<9> TP_DVPDATA<10> TP_DVPDATA<11> TP_DVPDATA<12> TP_DVPDATA<13> TP_DVPDATA<14> TP_DVPDATA<15> TP_DVPDATA<16> TP_DVPDATA<17> TP_DVPDATA<18> TP_DVPDATA<19> TP_DVPDATA<20> TP_DVPDATA<21> TP_DVPDATA<22> TP_DVPDATA<23>
VRAM_DVP0
D K91FSamsung K91FHynix K91FSamsung K91FHynix
TP_DVPCNTL<0> TP_DVPCNTL<1> TP_DVPCNTL<2>
DP_EXTA_ML_C_P<3> DP_EXTA_ML_C_N<3>
LVTMDP
5% 1/16W MF-LF 402 2
10K
3
TXCAP_DPA3P AU24 TXCAM_DPA3N AV23
WHISTLER 40NM-ES
R86131
5% 1/16W MF-LF 402 2
10K
DPA
R86121
5% 1/16W MF-LF 402 2
10K
DPB
NO
R86111
5% 1/16W MF-LF 402 2
10K
MULTI GFX
YES
R86101
DPC
YES
I2C
NO
U8000 WHISTLER 40NM-ES
DPD
NO
AP8 DVPCNTL_0 AW8 DVPCNTL_1 AR3 DVPCNTL_2
DAC1
VRAM_DVP2 (STUFF R8611?)
4
GPIO
K92 HYNIX 1G
VRAM_DVP1 (STUFF R8612?)
AR8 DVPCNTL_MVP_0 AU8 DVPCNTL_MVP_1
PLL/CLK
K92 SAMSUNG 1G
VRAM_DVP0 (STUFF R8613?)
5 TP_DVPCNTL_M<0> TP_DVPCNTL_M<1>
DDC/AUX
VRAM BOM OPTION TABLE
6
PP1V8_S0GPU_ISNS
DAC2
7 100 80 78 74 7
THERMAL
8
3
2
BRANCH
PAGE
86 OF 132 SHEET
78 OF 101
1
A
8
7
6
5
4
3
2
1 Unused signals
Native Func GP
79 78
GPU_PCIE_TX_PWR
79 78
GP GPU_GPIO_TX_DEEMP
GPU_PCIE_GEN2
GP
79 78
GPU_SMB_DAT
GP
79 78
GPU_SMB_CLK
GP
GPU_AC_BATT
GP
79 78
T29 HPD GPU isolation
Native Func
GPIOs GPU_PCIE_TX_PWR
GP
GPU_VCORE_VID2
81 79 78
78 79
79 78
GP SMC_GFX_THROTTLE_R_L
78 79
79 78
GP DP_T29SNK1_HPD_GPU
MAKE_BASE=TRUE
SMC_GFX_THROTTLE_R_L
D
81 79 78
78 79
GPU_SMB_CLK GPU_AC_BATT MAKE_BASE=TRUE
GPU_VCORE_VID0
GP
GPU_ROM_SO
GP
79 78
GPU_ROM_SI
GP
79 78
EG_BKLT_EN MAKE_BASE=TRUE
GPU_ROM_SO MAKE_BASE=TRUE
GPU_ROM_SI MAKE_BASE=TRUE
79 78
GPU_ROM_SCLK
GP
GPU_CONFIG_0
GP
79 78
GPU_CONFIG_1
GP
79 78
GPU_CONFIG_2
GP
79 78
79 78
DP_T29SNK0_HPD_GPU GP
GPU_ROM_SCLK MAKE_BASE=TRUE
GPU_CONFIG_0 MAKE_BASE=TRUE
GPU_CONFIG_1 MAKE_BASE=TRUE
GPU_CONFIG_2 MAKE_BASE=TRUE
DP_T29SNK0_HPD_GPU MAKE_BASE=TRUE
GP
GPU_VCORE_VID1
79 78
GPU_VCORE_VID1
78 79
81 79 78
GPU_VCORE_VID3 FBVDD_ALTVO
GP
86 79 78
79 78
GP
GPU_ROM_CS_L
GPU_ROM_CS_L
GP
79 78
NC_GPU_GENERICA
GP
78 79
79 78
NC_GPU_GENERICB
GP
78 79
NC_GPU_GENERICA MAKE_BASE=TRUE
78 79
79 78
NC_GPU_GENERICC
79 78
DP_CA_DET_EG_R
GP
78 79
79 78
NC_GPU_GENERICE
GP
78 79
79 78
NC_GPU_GENERICF
GP
78 79
GP
79 78
NC_GPU_GENERICG DP_EG_HPD
GP
78 79
5% 1/16W MF-LF 2 402
78 79
78 79
PP3V3_S0
78 79
NC_GPU_GENERICE
NC_LVDS_EG_B_CLK_P
79 79 78
NC_LVDS_EG_B_CLK_N
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
97 79 78
NC_LVDS_EG_A_DATA_P<3>
97 79 78
NC_LVDS_EG_A_DATA_N<3>
97 79 78
NC_LVDS_EG_B_DATA_P<3>
97 79 78
NC_LVDS_EG_B_DATA_N<3>
MAKE_BASE=TRUE
NO_TEST=TRUE
83 81 79 78 74 71 7 6 78 79
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
SOT833
5
78 79 83
U8741Y 3 6
DP_T29SNK1_HPD
A
B
DP_T29SNK1_HPD_GPU
78 79
ISOLATION R’s for GPU Int Temp Sense
08
NOSTUFF
R8780 GPU_SMB_DAT
GPU_PCIE_TX_PWR
79 78
GPU_GPIO_TX_DEEMP
79 78
GPU_PCIE_GEN2
NOSTUFF
R87011 10K
1% 1/16W MF-LF 402 2
10K
1% 1/16W MF-LF 402 2
79 78
GPU_AC_BATT
NOSTUFF
79 78
R87051
GPU_ROM_SI
1
GPU_ROM:YES
10K
1% 1/16W MF-LF 402 2
10K
1% 1/16W MF-LF 402 2
B
87 79 78
EG_BKLT_EN
79 78
GPU_ROM_SO
79 78
GPU_ROM_SI
NOSTUFF
10K
1% 1/16W MF-LF 402 2
U8701
GPU_ROM_SCLK_R
6 C
M25P10A
GPU_ROM_CS_L_R
1 S*
GPU_ROM_CS_L
GPU_ROM_WP_L NO STUFF
1
R8722
2
0
5% 1/16W MF-LF 402
5% 1/16W MF-LF 2 402
NOSTUFF 1
R8708
1
PP3V3_GPU_OSC_100M
2
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
0402
GPU_ROM_SO 78
2
79
5% 1/16W MF-LF 402
1
CRITICAL
C8702
C8703
0.1UF
GPU_ROM:YES
3 W*
GPU Reference Clocks
1
0.1UF
10% 2 16V X5R 402-1
10% 16V 2 X5R 402-1
R8730
OMIT_TABLE 7 HOLD* THRM VSS PAD 4 9
GPU_ROM_SCLK
79 78
GPU_CONFIG_0
R87101 10K
1% 1/16W MF-LF 402 2
GPU_OSC_27M_XTALIN GPU_OSC_27M_XTALOUT
10K
CRITICAL
CRITICAL
3
C8700 1
NO STUFF NO STUFF 1 1
10K
R8750
1% 1/16W MF-LF 402 2
2.2K
5% 1/16W MF-LF 402 2
83 78
GPU_ROM:YES
NOSTUFF
NOSTUFF
R87121
R87131
R87141
10K
GPU_CLK100M
OUT
78 97
GPU_CLK27M
OUT
78 97
R8731 GPU_CLK27M_R
1
0
2
5% 1/16W MF-LF 402
SSEL0 7 SSEL1 3
B
30PF
5% 50V CERM 2 402
PP3V3_S0GPU
C8701
2
5% 50V 2 CERM 402
NOSTUFF
R87111
83 17 8
1% 1/16W MF-LF 402 2
1
30PF
0
5% 1/16W MF-LF 402
TDFN 1 XIN/CLKIN SSCLK 5 10 XOUT REFCLK 9
Y8700 SM-2.5X2.0MM
IN
GPU_CONFIG_1
10K
1
U8700
1% 1/16W MF-LF 402 2
83 78
1% 1/16W MF-LF 402 2
GPU_CLK100M_R
SL16010DC
PP3V3_S0
79 78
79 78
33
GPU_ROM_SO_R
33
98 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 89 88 87 84 83 82 79 72 71
1% 1/16W MF-LF 402 2
86 79 78
1
Q2
UFDFPN8
5% 1/16W MF-LF 402
1
R8726
1
2
L8702
120OHM-0.3A
GPU_ROM:YES
8 VCC
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
2 4
10K
C
PP3V3_GPU_OSC_27M
2 0402
1
NOSTUFF
A
5% 1/16W MF-LF 402 2
R8724 33
1
20% 2 10V CERM 402
0
5% 1/16W MF-LF 402 2
PP3V3_S0GPU
27MHZ-15PPM-18PF
R87091
79 78
10K
2
C8721
83 81 79 78 74 71 7 6
0.1UF
5 D
GPU_ROM_SCLK
83 81 79 78 74 71 7 6
79 78
33
1
GPU_ROM_SI_R
GPU_ROM:YES
R87071
83 17 8
R8751 2.2K
5% 1/16W MF-LF 402 2
R87521 R87531 4.7K 5% 1/16W MF-LF 402
2
4.7K 5% 1/16W MF-LF 402
83 81 79 78 74 71 7 6
PP3V3_S0GPU
2
NO STUFF
R87961 R87971
DP_EG_DDC_CLK
BI
DP_EG_DDC_DATA
IN
DP_IG_DDC_CLK
BI
DP_IG_DDC_DATA
2.2K
5% 1/16W MF-LF 402
2 79 78
SMC_GFX_OVERTEMP_R_L
79 78
SMC_GFX_THROTTLE_R_L
79 78
DP_CA_DET_EG_R
R8791
0
1
2
PEX_CLKREQ_L_R
R8795
0
1
2
2.2K
5% 1/16W MF-LF 402
79 78
DP_CA_DET_EG 5%
PEX_CLKREQ_L 5%
IN
1/16W MF-LF 402 1/16W MF-LF 402
OUT
87
8 87
2
R8798 R8799
10K
0
1
2
0
1
2
5%
1/16W
5%
1/16W MF-LF 402
1% 1/16W MF-LF 402 2
GPU_CONFIG_2
SMC_GFX_OVERTEMP_L
OUT
44
SMC_GFX_THROTTLE_L
IN
44
MF-LF 402
EG_LCD_PWR_EN
OUT
78 87
EG_BKLT_EN
OUT
78 79 87
FBVDD_ALTVO
OUT
78 79 86
SYNC_MASTER=K92_MLB
FBVDD_ALTVO
SYNC_DATE=11/23/2010
PAGE TITLE
1
PEX_CLKREQ_L_R
1
R8793
R8794
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
10K
2
Whistler GPIOs & STRAPs
1
R8792 10K
10K
DRAWING NUMBER
Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
7
6
5
SIZE
D REVISION
R
2
NOTICE OF PROPRIETARY PROPERTY:
8
6 31 44 47 50 96
120OHM-0.3A
R87201 R87211
R8725 79 78
NOSTUFF
SMBUS_SMC_0_S0_SCL
2
L8703
PP3V3_S0GPU
5% 1/16W MF-LF 402
GPU_ROM:YES
R87061
0
NOSTUFF
79 78
GPU_SMB_CLK
6 31 44 47 50 96
5% 1/16W MF-LF 402
GPU_SMB_DAT
79 78
1
1% 1/16W MF-LF 402 2
VDD1 4 VDD2 8
10K
1% 1/16W MF-LF 402 2
NOSTUFF
R87041
GPU_SMB_CLK
79 78
10K
GPU_ROM:YES GPU_ROM:YES
R8703
SMBUS_SMC_0_S0_SDA
2
R8781
R87021
83 81 79 78 74 71 7 6
NOSTUFF 1
0
5% 1/16W MF-LF 402
R8723
79 78
1
11 THM PAD
79 78
97 78 79
8 74LVC2G08GT
78 79
NO_TEST=TRUE
DP_EG_HPD
6 VSS1 2 VSS2
C
NC_LVDS_EG_B_DATA_N<3>
D
48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98
79 78
1% 1/16W MF-LF 402 2
97 78 79
NO_TEST=TRUE
PP3V3_S0GPU
10K
NC_LVDS_EG_B_DATA_P<3>
NO_TEST=TRUE
4
R8700
97 78 79
NO_TEST=TRUE
Config Straps
NOSTUFF 1
97 78 79
NC_LVDS_EG_A_DATA_N<3>
NO_TEST=TRUE
PP3V3_S0GPU
NO_TEST=TRUE
NC_GPU_GENERICG
83 33
83 81 79 78 74 71 7 6
NC_LVDS_EG_A_DATA_P<3>
78 79
NC_GPU_GENERICF MAKE_BASE=TRUE
NC_LVDS_EG_B_CLK_N
DP_T29SNK0_HPD_GPU 78
0
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
78 79
R8741
78 79
DP_CA_DET_EG_R MAKE_BASE=TRUE
78 79
NC_LVDS_EG_B_CLK_P
79 78
1
NO_TEST=TRUE
NC_GPU_GENERICC MAKE_BASE=TRUE
TP_GPU_JTAG_TRST_L
4
NO_TEST=TRUE
NC_GPU_GENERICB MAKE_BASE=TRUE
GP
TP_GPU_JTAG_TMS
MAKE_BASE=TRUE
MAKE_BASE=TRUE
78 79
MAKE_BASE=TRUE
78 79
TP_GPU_JTAG_TMS TP_GPU_JTAG_TRST_L
PP3V3_GPU_VDD33_R
PEX_CLKREQ_L_R
78 79
79 78
08
78 79
78 79
TP_GPU_JTAG_TDO
79 78
U8741Y 7 B
TP_GPU_JTAG_TDO
20%
A
2
78 79 86
MAKE_BASE=TRUE
PEX_CLKREQ_L_R
1
78 79 81
FBVDD_ALTVO MAKE_BASE=TRUE
79 78
83 79 78
GPU_VCORE_VID3
DP_T29SNK0_HPD
78 79
TP_GPU_JTAG_TDI
MAKE_BASE=TRUE
402 8 74LVC2G08GT SOT833
2 10V CERM
CRITICAL
78 79 83 33
MAKE_BASE=TRUE
78 79 87
78 79
SMC_GFX_OVERTEMP_R_L
TP_GPU_JTAG_TCK
MAKE_BASE=TRUE
TP_GPU_JTAG_TDI MAKE_BASE=TRUE
0.1UF 78 79
MAKE_BASE=TRUE
78 79
78 79 81
MAKE_BASE=TRUE
SMC_GFX_OVERTEMP_R_L GP
78 79 81
MAKE_BASE=TRUE
EG_BKLT_EN
81 79 78
GPU_SMB_DAT MAKE_BASE=TRUE
87 79 78
DP_T29SNK1_HPD_GPU MAKE_BASE=TRUE
GP
MAKE_BASE=TRUE
GPU_VCORE_VID0
C8741
1
78 79
MAKE_BASE=TRUE
GPU_PCIE_GEN2 MAKE_BASE=TRUE
GP
78 79 81
MAKE_BASE=TRUE
GPU_GPIO_TX_DEEMP MAKE_BASE=TRUE
79 78
72 79 82 83 84 87 88 89 35 36 39 40 41 45 47 48 6 7 12 16 17 18 79 78 19 20 22 23 25 26 28 32 49 50 51 53 56 60 61 71 98 79 78
PP3V3_S0
GPU_VCORE_VID2
78 79
TP_GPU_JTAG_TCK
79 78
GPIOs
4
3
2
BRANCH
PAGE
87 OF 132 SHEET
79 OF 101
1
A
8
7
6
5
4
3
2
1 Page Notes
80
80
PP1V8_GPU_DP_CD PP1V0_GPU_DP_CD
AP20 AP21
DPCD/DPC_VDD18_AP20 DPCD/DPC_VDD18_AP21
AP13 AT13
DPCD/DPC_VDD10_AP13 DPCD/DPC_VDD10_AT13
AN17 AP16 AP17 AW14 AW16
DP/DPC_VSSR_AN17 DP/DPC_VSSR_AP16 DP/DPC_VSSR_AP17 DP/DPC_VSSR_AW14 DP/DPC_VSSR_AW16
DPAB/DPA_VDD18_AN24 AN24 DPAB/DPA_VDD18_AP24 AP24
U8000 FCBGA
PP1V8_GPU_DP_AB
Power aliases required by this page: 80
- =PP1V8_GPU_DP_AB - =PP1V8_GPU_DP_CD
WHISTLER (6 OF 9) 40NM-ES
DPAB/DPA_VDD10_AP31 AP31 DPAB/DPA_VDD10_AP32 AP32
OMIT
DP/DPA_VSSR_AN27 DP/DPA_VSSR_AP27 DP/DPA_VSSR_AP28 DP/DPA_VSSR_AW24 DP/DPA_VSSR_AW26
PP1V0_GPU_DP_AB
- =PP1V8_GPU_DP_EF
80
- =PP1V0_GPU_DP_AB - =PP1V0_GPU_DP_CD
AN27 AP27 AP28 AW24 AW26
- =PP1V0_GPU_DP_EF Signal aliases required by this page: (NONE)
D
DP/DPD_VSSR_AN19 DP/DPD_VSSR_AP18 DP/DPD_VSSR_AP19 DP/DPD_VSSR_AW20 DP/DPD_VSSR_AW22
AW18
DPCD_CALR
R8802 1
150
GPU_DP_CD_CALR
2
1% 1/16W MF-LF 402
80
80
80
80
C
PP1V8_GPU_DP_EF PP1V0_GPU_DP_EF
150
DP/DPB_VSSR_AN29 DP/DPB_VSSR_AP29 DP/DPB_VSSR_AP30 DP/DPB_VSSR_AW30 DP/DPB_VSSR_AW32
80
AB39 E39 F34 F39 G33 G34 H31 H34 H39 J31 J34 K31 K34 K39 L31 L34 M34 M39 N31 N34 P31 P34 P39 R34 T31 T34 T39 U31 U34 V34 V39 W31 W34 Y34 Y39
AN29 AP29 AP30 AW30 AW32
R8800 GPU_DP_AB_CALR
DPAB_CALR AW28
1
DPEF/DPE_VDD18_AH34 DPEF/DPE_VDD18_AJ34
DPAB_VDD18/DPA_PVDD_AU28 AU28 DP_VSSR/DPA_PVSS_AV27 AV27
PP1V8_GPU_DP_AB
AL33 AM33
DPEF/DPE_VDD10_AL33 DPEF/DPE_VDD10_AM33
DPAB_VDD18/DPB_PVDD_AV29 AV29 DP_VSSR/DPB_PVSS_AR28 AR28
PP1V8_GPU_DP_AB
DPCD_VDD18/DPC_PVDD_AU18 AU18 DP_VSSR/DPC_PVSS_AV17 AV17
PP1V8_GPU_DP_CD
DPCD_VDD18/DPD_PVDD_AV19 AV19 DP_VSSR/DPD_PVSS_AR18 AR18
PP1V8_GPU_DP_CD
AN34 AP39 AR39 AU37
DP/DPE_VSSR_AN34 DP/DPE_VSSR_AP39 DP/DPE_VSSR_AR39 DP/DPE_VSSR_AU37
PP1V8_GPU_DP_EF
AF34 AG34
DPEF/DPF_VDD18_AF34 DPEF/DPF_VDD18_AG34
DPEF_VDD18/DPE_PVDD_AM37 AM37 DP_VSSR/DPE_PVSS_AN38 AN38
PP1V8_GPU_DP_EF
PP1V0_GPU_DP_EF
AK33 AK34
DPEF/DPF_VDD10_AK33 DPEF/DPF_VDD10_AK34
DPEF_VDD18/DPF_PVDD_AL38 AL38 DP_VSSR/DPF_PVSS_AM35 AM35
PP1V8_GPU_DP_EF
AF39 AH39 AK39 AL34 AM34
DP/DPF_VSSR_AF39 DP/DPF_VSSR_AH39 DP/DPF_VSSR_AK39 DP/DPF_VSSR_AL34 DP/DPF_VSSR_AM34
AM39
DPEF_CALR
GPU_DP_EF_CALR
2
PP1V0_GPU_DP_AB
AH34 AJ34
R8801 1
DPAB/DPB_VDD10_AN33 AN33 DPAB/DPB_VDD10_AP33 AP33
(NONE)
80
80
150
2
1% 1/16W MF-LF 402
80
80
80
80
80
1% 1/16W MF-LF 402
L8801
L8800
300mA PP1V8_GPU_DP_AB
470OHM-1A-150MOHM 78 74 7 100 80
PP1V8_S0GPU_ISNS
1
2
1
C8800 10UF
1
C8801 1UF
10% 25V 2 X5R 402
20% 10V 2 X5R 603
B
1
1
1
C8812
1
10UF
20% 2 10V X5R 603
C8813
1
1UF
C8803
1
10UF
20% 2 10V X5R 603
C8804
100 80 78 74 73 7
PP1V0_S0GPU_ISNS
1
80
10% 2 25V X5R 402
10% 2 25V X5R 402
1
C8806 10UF
20% 2 10V X5R 603
1
C8807 1UF
10% 2 25V X5R 402
1
C8815 10UF
20% 10V 2 X5R 603
1
C8816 1UF
10% 25V 2 X5R 402
L8803
80 100 80 78 74 73 7
1
0.1UF
10% 2 16V X5R 402-1
1
80
C8817 0.1UF
10% 16V 2 X5R 402-1
220mA PP1V0_GPU_DP_EF
470OHM-1A-150MOHM PP1V0_S0GPU_ISNS
80
AF21 AG2 AG6 AG9 AG17 AG20 AG22 AH21 AJ2 AJ6 AJ10 AJ11 AJ28 AK7 AK11 AK31 AL2 AL6 AL8 AL11 AL14 AL17 AL20 AL23 AL26 AL32 AM9 AM11 AM31 AN2 AN6 AN8 AN11 AN30 AP7 AP9 AP11 AR5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 C1 C39 E5 E35 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25 F27 F29
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1V 1
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V
0603
2
C8814
300mA PP1V8_GPU_DP_EF
2
A39 VSS_MECH_A39 AW1 VSS_MECH_AW1 AW39 VSS_MECH_AW39
OMIT
A3 A37 AA2 AA6 AA16 AA18 AA21 AA23 AA26 AA28 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC2 AC6 AC11 AC13 AC16 AC18 AC21 AC23 AC26 AC28 AD9 AD15 AD17 AD20 AD22 AD24 AD27 AE2 AE6 AF10 AF16 AF18
C8805
220mA PP1V0_GPU_DP_CD
0603
10% 2 16V X5R 402-1
L8802
1
1UF
470OHM-1A-150MOHM
0.1UF
470OHM-1A-150MOHM 78 74 7 100 80
1
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V
PCIE_VSS_G33 PCIE_VSS_G34 PCIE_VSS_H31 PCIE_VSS_H34 PCIE_VSS_H39 PCIE_VSS_J31 PCIE_VSS_J34 PCIE_VSS_K31 PCIE_VSS_K34 PCIE_VSS_K39 PCIE_VSS_L31 PCIE_VSS_L34 PCIE_VSS_M34 PCIE_VSS_M39 PCIE_VSS_N31 PCIE_VSS_N34 PCIE_VSS_P31 PCIE_VSS_P34 PCIE_VSS_P39 PCIE_VSS_R34 PCIE_VSS_T31 PCIE_VSS_T34 PCIE_VSS_T39 PCIE_VSS_U31 PCIE_VSS_U34 PCIE_VSS_V34 PCIE_VSS_V39 PCIE_VSS_W31 PCIE_VSS_W34 PCIE_VSS_Y34 PCIE_VSS_Y39
(8 OF 9)
GND_A3 GND_A37 GND_AA2 GND_AA6 GND_AA16 GND_AA18 GND_AA21 GND_AA23 GND_AA26 GND_AA28 GND_AB12 GND_AB15 GND_AB17 GND_AB20 GND_AB22 GND_AB24 GND_AB27 GND_AC2 GND_AC6 GND_AC11 GND_AC13 GND_AC16 GND_AC18 GND_AC21 GND_AC23 GND_AC26 GND_AC28 GND_AD9 GND_AD15 GND_AD17 GND_AD20 GND_AD22 GND_AD24 GND_AD27 GND_AE2 GND_AE6 GND_AF10 GND_AF16 GND_AF18
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1V
L8805
2
1
2 0603
C8802
300mA PP1V8_GPU_DP_CD
0603
PP1V8_S0GPU_ISNS
1
10% 16V 2 X5R 402-1
L8804
PP1V8_S0GPU_ISNS
PP1V0_S0GPU_ISNS
0.1UF
470OHM-1A-150MOHM 78 74 7 100 80
100 80 78 74 73 7 80
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V
0603
220mA PP1V0_GPU_DP_AB
470OHM-1A-150MOHM
PCIE_VSS_AB39 PCIE_VSS_E39 PCIE_VSS_F34 U8000 FCBGA PCIE_VSS_F39
2
80
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1V
0603
C8808
1
0.1UF
C8809 10UF
10% 2 16V X5R 402-1
20% 2 10V X5R 603
1
C8810 1UF
10% 2 25V X5R 402
1
C8811
GND_AF21 GND_AG2 GND_AG6 GND_AG9 GND_AG17 GND_AG20 GND_AG22 GND_AH21 GND_AJ2 GND_AJ6 GND_AJ10 GND_AJ11 GND_AJ28 GND_AK7 GND_AK11 GND_AK31 GND_AL2 GND_AL6 GND_AL8 GND_AL11 GND_AL14 GND_AL17 GND_AL20 GND_AL23 GND_AL26 GND_AL32 GND_AM9 GND_AM11 GND_AM31 GND_AN2 GND_AN6 GND_AN8 GND_AN11 GND_AN30 GND_AP7 GND_AP9 GND_AP11 GND_AR5 GND_B7 GND_B9 GND_B11 GND_B13 GND_B15 GND_B17 GND_B19 GND_B21 GND_B23 GND_B25 GND_B27 GND_B29 GND_B31 GND_B33 GND_C1 GND_C39 GND_E5 GND_E35 GND_F7 GND_F9 GND_F11 GND_F13 GND_F15 GND_F17 GND_F19 GND_F21 GND_F23 GND_F25 GND_F27 GND_F29
U8000 FCBGA
(9 OF 9) 40NM-ES
AN19 AP18 AP19 AW20 AW22
PP1V8_GPU_DP_AB
WHISTLER
DPCD/DPD_VDD10_AP14 DPCD/DPD_VDD10_AP15
DPAB/DPB_VDD18_AP25 AP25 DPAB/DPB_VDD18_AP26 AP26
WHISTLER 40NM-ES
AP14 AP15
DP A/B PWR
PP1V0_GPU_DP_CD
DP E/F PWR
80
DPCD/DPD_VDD18_AP22 DPCD/DPD_VDD18_AP23
DP OLL POWER
80
AP22 AP23
DP C/D PWR
BOM options provided by this page:
D
PP1V8_GPU_DP_CD
OMIT
GND_F31 GND_F33 GND_G2 GND_G6 GND_H9 GND_J2 GND_J6 GND_J8 GND_J27 GND_K7 GND_K14 GND_L2 GND_L6 GND_L11 GND_L17 GND_L22 GND_L24 GND_M17 GND_M22 GND_M24 GND_N2 GND_N6 GND_N16 GND_N18 GND_N21 GND_N23 GND_N26 GND_R2 GND_R6 GND_R15 GND_R17 GND_R20 GND_R22 GND_R24 GND_R27 GND_T11 GND_T13 GND_T16 GND_T18 GND_T21 GND_T23 GND_T26 GND_U2 GND_U6 NC/GND GND_U15 GND_U17 GND_U20 GND_U22 GND_U24 GND_U27 GND_V11 NC/GND GND_V16 GND_V18 GND_V21 GND_V23 GND_V26 GND_W2 GND_W6 GND_Y15 GND_Y17 GND_Y20 GND_Y22 GND_Y24 GND_Y27 GND/PX_EN
F31 F33 G2 G6 H9 J2 J6 J8 J27 K7 K14 L2 L6 L11 L17 L22 L24 M17 M22 M24 N2 N6 N16 N18 N21 N23 N26 R2 R6 R15 R17 R20 R22 R24 R27 T11 T13 T16 T18 T21 T23 T26 U2 U6 U13 U15 U17 U20 U22 U24 U27 V11 V13 V16 V18 V21 V23 V26 W2 W6 Y15 Y17 Y20 Y22 Y24 Y27 AL21
C
B
NC
0.1UF
10% 2 16V X5R 402-1
A
SYNC_MASTER=K92_SUMA
SYNC_DATE=06/15/2010
PAGE TITLE
Whistler DP PWR/GNDs DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
88 OF 132 SHEET
80 OF 101
1
A
8 100 65 45 43 29 7 6 42 41 31 71 66
7
6 5 GPU VCore Regulator
1
1
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V
C8902 1
10
0.01uF
86 49 7
10% 2 16V CERM 402
CRITICAL
D
20% 16V POLY-TANT 2 D3L
PP5V_S3_GFXIMVP6_VDD 1
16
1uF
VDD
R8905 2
GFXIMVP6_RBIAS
48
89 87 86 73 8
1
OUT
81 81
1
R8910
81
10K
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
81 81 89 87
IN
1
R8924 100
1% 1/16W MF-LF 402 2
1
1
MIN_NECK_WIDTH=0.10 mm MIN_LINE_WIDTH=0.25 mm VOLTAGE=0V
20
1
C8920
VIN
14
UGATE
18
BOOT
17
2
2
28 31 23 24 25 26 27 29 30 32
8 9
C8923
CRITICAL
D
GFXIMVP6_UGATE
4
Q8950
G
RJK0365DPA-02
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
SOFT
WPAK
GATE_NODE=TRUE DIDT=TRUE
GFXIMVP6_BOOT
S
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
CRITICAL
C8956 1
1 2 3
0.22UF
IMON
10% 16V X7R 2 603
PGOOD VID0 VID1 VID2 VID3 VID4 VR_ON AF_EN FDE
PHASE
1% 1W MF-1 0612
0.56UH-31A 1
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
2
PPVCORE_GPU_REG_R
FDU1040D-SM
SWITCH_NODE=TRUE DIDT=TRUE
Vout = 0.75V - 0.90V
0.001
L8920
GFXIMVP6_PHASE
19
R8940
CRITICAL
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V
2 4
PPVCORE_GPU
1 3
5
C8969 1
D
GFXIMVP6_LGATE
21
CRITICAL
Q8951
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
4
GATE_NODE=TRUE
RJK0208DPA
G
20% 6.3V 2 X5R 603
1
WPAK
C8967
10% 6.3V 2 X5R-CERM 603
VSEN RTN
C8942 1
20% 6.3V 2 X5R 603
10UF
10% 50V 2 X7R 402
330UF
20% 2.0V 3 POLY-TANT 2 D2T-SM2
CRITICAL 1
C8965
CRITICAL
10UF
20% 2 6.3V X5R 603
30A max output (L8920 limit)
CRITICAL
10UF
C8968 1
0.001UF LGATE
6 7 48 74 81
CRITICAL
C8966 1
CRITICAL
1
C8943 330UF
C
20% 3 2 2.0V POLY-TANT D2T-SM2
1 2 3
C8921 1 10% 50V CERM 2 402
1
R89091
1
7.15K
330PF
GFXIMVP6_COMP_RC MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.3MM 1
R8950 150K
2
VW
C8922
R89031
10% 2 50V X7R 402
1
1K
GFXIMVP6_COMP
5
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM 1
COMP
VO
OCSET
10% 2 50V CERM 402
6
ISP ISN
R8953
7
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
ICOMP
VDIFF PGND
VSS
VID4
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
1% 1/16W MF-LF 402
THRM_PAD
1
VID2
VID1 0
VID0 1
0.74675V
K18
Balanced
5% 50V COG 2 402
1
0
0
1
0
0.82400V
-
K18
0
1
1
1
1
0.90125V
-
-
Max perf K18
B
C8971 1
68PF 1
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
(PPVCORE_GPU_REG)
1% 1/16W MF-LF 2 402
GPU VCore Setpoints not up-to-date!
2
5% 50V CERM 402-1
C8972 1 0.001UF
10% 50V CERM 2 402
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V
XW8900 SM
PP3V3_S0GPU
C8906 1
1
9.09K
GND_GFXIMVP6_AGND
83 81 79 78 74 71 7 6
Max Batt
0
R8901
GFXIMVP6_DROOP 353S2289
VID3
1
2
9.76K
10
Voltage
1
330PF
GFXIMVP6_DFB
R8902
GFXIMVP6_VDIFF
10% 25V CERM 402
1% 1/16W MF-LF 402
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM
11
1% 1/16W MF-LF 2 402
20
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.3MM
13
GPU VCore Setpoints
7.32K2
1
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
33
C8951
0.0068UF 2 GFXIMVP6_VDIFF_RC 1
R8900
GFXIMVP6_OCSET
3
3.01K
15
1% 1/16W MF-LF 402
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM
FB
1
150
GFXIMVP6_VO
12
GFXIMVP6_VSUM
GFXIMVP6_FB MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
R8951
1% 1/16W MF-LF 402 2
C8952 330PF
1% 1/16W MF-LF 2 402
GFXIMVP6_PHASE_VSUM
10% 50V 2 CERM 402
0.001UF
1% 1/16W MF-LF 402 2
10% 50V CERM 402
C8953 680pF
4
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
C8950
2
5
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
GFXIMVP6_IMON
GFXIMVP6_VW
PLACE_NEAR=U8900.9:7mm
B
GFXIMVP6_VIN
QFN
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
10% 50V 2 CERM 402 (GFXIMVP6_AGND)
10% 2 50V CERM 402
100
2
U8900
0.001UF 0.001UF
5% 1/16W MF-LF 402
1
1K
5% 1/16W MF-LF 402 2
S
R8925 1% 1/16W MF-LF 402
GFXIMVP6_SOFT
GFXIMVP6_VSEN_P GFXIMVP6_VSEN_N
0.001UF
R8908 1
R89301
2
5% 1/16W MF-LF 402
GPU_GND_SENSE
D
4.7UF
R8920 1
20% 2 16V POLY-TANT CASE-D2E-SM
DIDT=TRUE
PLACE_NEAR=U8900.8:7mm
GPU_VDD_SENSE
0.001UF
PVCC
ISL6263C
PM_ALL_GPU_PGOOD GFXIMVP6_VID0 GFXIMVP6_VID1 GFXIMVP6_VID2 GFXIMVP6_VID3 GFXIMVP6_VID4 GPUVCORE_EN GFXIMVP6_AF_EN GFXIMVP6_FDE
OUT
PP3V3_S0GPU 10K
RBIAS
0.033UF 10% 16V X5R 402
R89071
1
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
C8904 2
MIN_NECK_WIDTH=0.10 mm MIN_LINE_WIDTH=0.25 mm VOLTAGE=1.25V
C8931 68UF
10% 2 50V X7R 402
10% 25V 2 X5R 603-1
CRITICAL
150K 1 1% 1/16W MF-LF 402
20
1
C8934
C8901
10% 2 10V X5R 402
PPVCORE_GPU
CRITICAL 1
1UF
X5R 603-1
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V
1% 1/16W MF-LF 402
C
C8932 1UF 10% C8933 1 2 25V
C8930 1 68UF
2
PPVIN_S5_HS_GPU_ISNS
1
22
1
74
1
C8903
1
2.2UF
R8904
74
2
PP5V_S3_GFXIMVP6_PVCC
2
20% 10V X5R-CERM 2 402
81 74 48 7 6
3
R8911
PP5V_S3
5% 1/16W MF-LF 402
83 78 74 71 7 6 81 79
4
2
K91F Default Vcore Setpoints
PLACE_NEAR=U8900.33:2mm PLACE_NEAR=U8900.15:2mm
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
GPUVID_1P11V
GPUVID4_0,GPUVID3_0,GPUVID2_1,GPUVID1_1,GPUVID0_1
TABLE_BOMGROUP_ITEM
R8990 79 78
IN
GPU_VCORE_VID0
1
0
2
5% 1/16W MF-LF 402
GPUVID0_1
GPUVID1_1
GPUVID2_1
GPUVID3_1
GPUVID4_1
R89871
R89841
R89821
R89951
R89911
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402 2
2.2K
2.2K
2.2K
2.2K
2.2K
GFXIMVP6_VID0 GFXIMVP6_VID1 GFXIMVP6_VID2 GFXIMVP6_VID3 GFXIMVP6_VID4
R8993
A
79 78
IN
GPU_VCORE_VID1
1
0
2
5% 1/16W MF-LF 402
79 78
IN
1
0
81 81 81 81
VIMON = In K9x, VIMON = VIMON =
31 x Io x Rsns x (1 + Ris2/Ris1) the equation will be: 31 x Io x R8940 x (1+ R8902/R8901) 31x Io x 1mOhm x 2.074 = Io x 64.29 mV/A
GPUVID0_0
GPUVID1_0
GPUVID2_0
GPUVID3_0
GPUVID4_0
R89881
R89851
R89831
R89961
R89921
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402 2
2.2K
2
5% 1/16W MF-LF 402
79 78
IN
GPU_VCORE_VID3
1
2.2K
2.2K
2.2K
DRAWING NUMBER
Apple Inc.
2.2K
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
7
6
SIZE
D REVISION
R
5% 1/16W MF-LF 402
8
SYNC_DATE=12/21/2010
GPU (Whistler) CORE SUPPLY
R8998 0
SYNC_MASTER=K91_ERIC PAGE TITLE
R8994 GPU_VCORE_VID2
81
5
4
3
2
BRANCH
PAGE
89 OF 132 SHEET
81 OF 101
1
A
8
7
6
5
4
3
2
1
D
D 87
LCD_PWR_EN
IN
R90941 10K
LCD (LVDS) INTERFACE
5% 1/16W MF-LF 402 2
CRITICAL
U9000
CRITICAL
FPF1009 1 ON 29 25 24 23 22 20 19 17 7 6 98 89 85 72 71 70 65 55 45 39
PP3V3_S5
1
C9009 0.1UF
L9000
MFET-2X2
FERR-250-OHM
2 VIN_1
VOUT_1 4
3 VIN_2
VOUT_2 5 THRM PAD 7
GND 6
PP3V3_SW_LCD_UF
1
C9011
1
0.1UF
2
SM
C9001 1
C9012
C9002 1
0.1UF
10UF
10% 2 16V X5R 402-1
10% 16V 2 X5R 402-1
1
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V
0.001UF
10% 50V 2 X7R 402
10% 16V 2 X5R 402-1
20% 6.3V 2 X5R 603
CRITICAL
J9000
20474-040E-11 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 79 72 71
C
F-RT-SM 41 42
PP3V3_S0
R90101
100K pull-ups are for
100K
5% 1/16W MF-LF 402 2
no-panel case (development). Panel has 2K pull-ups
83 6 83 6
1
R9011
6
100K
PP3V3_SW_LCD
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V
5% 1/16W MF-LF 2 402
NC
LVDS_DDC_CLK LVDS_DDC_DATA 97 83 6
C9010 1
97 83 6
LVDS_CONN_A_DATA_N<0> LVDS_CONN_A_DATA_P<0>
0.001UF
10% 50V 2 X7R 402
97 83 6 97 83 6
CRITICAL
L9010
90-OHM-100MA
97 83 6
DLP11S SYM_VER-1
97 83 6
97 83
LVDS_CONN_A_CLK_N
4
3
97 83
LVDS_CONN_A_CLK_P
1
2
97 6 97 6
Place close to the connector
97 83 6 97 83 6
97 83 6 97 83 6
CRITICAL
L9011
B
90-OHM-100MA
97 83 6
DLP11S SYM_VER-1
97 83 6
97 83
LVDS_CONN_B_CLK_N
4
3
97 83
LVDS_CONN_B_CLK_P
1
2
LVDS_CONN_A_DATA_N<1> LVDS_CONN_A_DATA_P<1> LVDS_CONN_A_DATA_N<2> LVDS_CONN_A_DATA_P<2> LVDS_CONN_A_CLK_F_N LVDS_CONN_A_CLK_F_P LVDS_CONN_B_DATA_N<0> LVDS_CONN_B_DATA_P<0> LVDS_CONN_B_DATA_N<1> LVDS_CONN_B_DATA_P<1> LVDS_CONN_B_DATA_N<2> LVDS_CONN_B_DATA_P<2>
LVDS_CONN_B_CLK_F_N LVDS_CONN_B_CLK_F_P LED_RETURN_6 LED_RETURN_5 LED_RETURN_4 LED_RETURN_3 LED_RETURN_2 LED_RETURN_1 97 6 97 6
88 6
Place close to the connector
88 6 88 6 88 6 88 6 88 6
NC
100 88 8 6
PPVOUT_S0_LCDBKLT
C9000 0.001UF
1
C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
B
518S0651
43 44
10% 50V CERM 2 402
A
SYNC_MASTER=K18_MLB
SYNC_DATE=04/27/2010
PAGE TITLE
LVDS Display Connector DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
90 OF 132 SHEET
82 OF 101
1
A
7
6
5
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
All emulated LVDS outputs require this termination
R92021
R9220 1
357
LVDS_CONN_A_CLK_P
2
1
OUT
5% 1/16W MF-LF 402 2
1% 1/20W MF 201
C9220 0.1UF
10K
82 97
6
IN
LVDS_A_CLK_P
2
1
PP3V3_S0
PLACE_NEAR=U9600.A6:7mm 97 87
3
DP AUX, DDC, & HPD muxing to IG/EG
LVDS Transmitter Termination D
4
20% 10V 2 CERM 402
18
8
1
D
C9230 0.1UF
20% 10V 2 CERM 402
VDD
PLACE_NEAR=U9600.A7:7mm
U9220
R9222
97 87
IN
LVDS_A_CLK_N
1
357
97 87
IN
LVDS_CONN_A_CLK_N
2
1% 1/20W MF 201
1
PLACE_NEAR=U9600.B9:7mm IN
LVDS_A_DATA_N<0>
IN
LVDS_A_DATA_P<1>
357
2
LVDS_CONN_A_DATA_P<0>
OUT
6 82 97
R9227 1
1
357
1% 1/20W MF 201
357
2
LVDS_CONN_A_DATA_N<0>
OUT
LVDS_CONN_A_DATA_P<1>
2
OUT
LVDS_A_DATA_N<1>
357
IN
79 17 8
IN
79 17 8
BI
79 78
IN
79 78
BI
14 13
DAUX2+ DAUX2-
DP_IG_DDC_CLK DP_IG_DDC_DATA
12 11
DDC_CLK1 DDC_DAT1
DP_EG_DDC_CLK DP_EG_DDC_DATA
9
DDC_CLK2 DDC_DAT2
8
DP_IG_HPD
10
HPD_1
OUT
DP_EG_HPD
7
HPD_2
100K
87
IN
DP_MUX_SEL_EG
IN
DP_MUX_EN
5 15
DP_EXTA_AUXCH_C_P DP_EXTA_AUXCH_C_N
20
AUX+ AUX-
CRITICAL
1
DDC_CLK DDC_DAT
2
HPDIN
4
DP_EXTA_DDC_CLK DP_EXTA_DDC_DATA
3
OUT
BI
84 97
BI
84 97
OUT BI
84 84
T29/DP HOT PLUG IN
(DP_EXTA_HPD)
T29_DP_HPD:MUX_GMUX
GPU_SEL
R9206
XSD*
DP_EXTA_HPD
5% 1/16W MF-LF 402 2
2
GND 98 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 89 88 87 84 83 82 79 72 71
6 82 97
0
1
5% 1/16W MF-LF 402
C
PP3V3_S0 T29_DP_HPD:ALL_OR
1% 1/20W MF 201 97 87
BI
DP_EG_AUXCH_P DP_EG_AUXCH_N
OUT
5% 1/16W MF-LF 402 2
LVDS_CONN_A_DATA_N<1>
97 78 8
DAUX1+ DAUX1-
17 8
100K
2
BI
87
R9232 1
97 78 8
17 16
19
PLACE_NEAR=U9600.C10:7mm IN
BI
DP_IG_AUX_CH_P DP_IG_AUX_CH_N
79 78
R92041 R92051
201
97 87
BI
92 17 8
6 82 97
1%
PLACE_NEAR=U9600.A9:7mm 1/20W MF
C
92 17 8
6 82 97
1% 1/20W MF 201
R9230 97 87
BGA
82 97
R9225
LVDS_A_DATA_P<0> PLACE_NEAR=U9600.A8:7mm
97 87
CBTL03062 OUT
C9210 1
R9235
LVDS_A_DATA_P<2>
1
357
2
LVDS_CONN_A_DATA_P<2>
OUT
6 82 97
1% 1/20W MF 201
PLACE_NEAR=U9600.B10:7mm
79
CRITICAL T29_DP_HPD:ALL_OR 8 74LVC2G32GT 5 SOT833 33 DP_T29SNK0_HPD A
79 33
DP_T29SNK1_HPD
6
U9210Y
3
0.1UF
20% 10V CERM 2 402
T29_HOTPLUG_DET_OR
B
4
PLACE_NEAR=U9600.A10:7mm
LVDS_A_DATA_N<2>
1
1
IN
LVDS_B_CLK_N
B
IN
1
357
LVDS_CONN_B_CLK_N
2
LVDS_B_DATA_P<0>
1
IN
LVDS_B_DATA_N<0>
LVDS_B_DATA_P<1>
97 87
IN
LVDS_B_DATA_N<1>
1
357
IN
OUT
82 97
357
Q9280 SSM3K15FV SOD-VESM-HF
2
LVDS_CONN_B_DATA_P<0>
OUT
6 82 97
84 45
357
2
LVDS_CONN_B_DATA_N<0>
OUT
6 82 97
LVDS_CONN_B_DATA_P<1>
OUT
6 82 97
1% 1/20W MF 201
2
81 79 78 74 71 7 6
357
2
LVDS_B_DATA_P<2>
LVDS_CONN_B_DATA_N<1>
OUT
6 82 97
LVDS_CONN_B_DATA_P<2>
OUT
6 82 97
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
1
357
IN
LVDS_B_DATA_N<2> PLACE_NEAR=U9600.A5:7mm
5% 1/16W MF-LF 402 2
2
C9270
1
357
R92721
1
DP_A_EXT_HPD
R9281 100K
5% 1/16W MF-LF 2 402
B
20% 10V CERM 2 402
2
LVDS_CONN_B_DATA_N<2>
OUT
6 82 97
VCC
87
IN
LVDS_DDC_SEL_EG
13
87
IN
LVDS_DDC_SEL_IG
5
1% 1/20W MF 201
6
12
U9270 QFN1
C1 C2 C3 C4
R9271 20K
5% 1/16W MF-LF 2 402
R9273 20K
5% 1/16W MF-LF 402 2
14
1
1
20K
0.1UF
1% 1/20W MF 201
R9257 97 87
20K
PP3V3_S0
R9255
PLACE_NEAR=U9600.C5:7mm
A
IN
T29_DP_HPD:MCU_GMUX
1
PP3V3_S0GPU
R92701
R9252 1
83 84 87 88 89 98 40 41 45 47 48 49 50 51 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 53 56 60 61 71 72 79 82
LVDS DDC MUX
1% 1/20W MF 201
1% 1/20W MF 201 97 87
5% 1/16W MF-LF 2 402
1
LVDS_EG_DDC_CLK
IN
78
4
LVDS_IG_DDC_CLK LVDS_DDC_CLK
IN
18
OUT
A1 2 B1 A2 3 B2 8
LVDS_EG_DDC_DATA
11
LVDS_IG_DDC_DATA LVDS_DDC_DATA
A3 9 B3
6 82
SYNC_MASTER=K92_MLB
SYNC_DATE=11/21/2010
PAGE TITLE BI
Muxed Graphics Support
78
DRAWING NUMBER
A4 B4 10 GND THRM CRITICAL 7 15
BI
18
BI
6 82
Apple Inc.
7
6
5
4
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
87
R9247 1
PLACE_NEAR=U9600.A1:7mm
PLACE_NEAR=U9600.B3:7mm
OUT
T29_DP_HPD:MCU_GMUX
1% 1/20W MF 201
R9250 97 87
DP_HOTPLUG_DET
B
4
R9245
PLACE_NEAR=U9600.A3:7mm IN
SOT833 7
U9210Y
82 97
PP3V3_S0
PLACE_NEAR=U9600.A2:7mm
97 87
OUT
R9242 1% 1/20W MF 201
97 87
LVDS_CONN_B_CLK_P
2
IN
G 1
97 87
84
2
1% 1/20W MF 201
PLACE_NEAR=U9600.C8:7mm
PLACE_NEAR=U9600.C9:7mm
(DP_EXTA_HPD)
T29_DP_HPD:ALL_OR 74LVC2G32GT
A
S
LVDS_B_CLK_P
1
6 82 97
2
IN
8 OUT
D
97 87
LVDS_CONN_A_DATA_N<2>
1% 1/20W MF 201
R9240 357
2
3
IN
357
SN74LV4066A
97 87
R9237
3
2
BRANCH
PAGE
92 OF 132 SHEET
83 OF 101
1
A
6
5
4
3 8
IN
C9300
DP_EXTA_ML_C_P<0>
1
97 78
IN
C9301
DP_EXTA_ML_C_N<0>
1
IN
C9302
DP_EXTA_ML_C_P<1>
IN
C9303
DP_EXTA_ML_C_N<1>
1
D
IN
C9304
DP_EXTA_ML_C_P<2>
1
IN
C9305
DP_EXTA_ML_C_N<2>
IN
DP_EXTA_ML_C_P<3>
C9306
97 78
IN
DP_EXTA_ML_C_N<3>
C9307
1
1
BI
C9308
BI
C9309
DP_EXTA_AUXCH_C_N
0.47UF
C9371 1
IN
DP_EXTA_ML_N<2>
L9372
95 33 6
IN
T29_R2D_C_N<0> T29_R2D_C_P<0>
1
84
16V 402
2
10% X5R
1
1
DP_EXTA_ML_N<3>
84
95 33 6
16V 402
R9309
1
(C9372.2)
10% X5R
8
DP_EXTA_AUXCH_N
10% 0.1uF X5R If GPU uses common pins for AUX_CH and DDC, alias nets together at GPU.
16V 402
R9308
1
IN
95 33 6
IN
5% MF-LF
0.47UF
1
1.0NH+/-0.1NH
L9383
1
R9308/R9309 maintain bias on C9308/C9309 to prevent spikes when U9310 AUXDDC_OFF transitions from high to low.
R9354 5% MF
30
1
(C9383.2)
2 0201-1 2 0201-1
8
1
A1 0 0 1 1
A0 0 1 0 1
20% 2 10V CERM 402
1
1 1
95 95
C9312 0.1UF
20% 10V 2 CERM 402
R9351 5% MF
30
1
84
Note: Other Parade devices use 96/B6, so only 94/B4 are used for this part.
84
84 84
84
NO STUFF 1
R9311 1K
5% 1/16W MF-LF 402 2
84
1
R9310 1K
5% 1/16W MF-LF 2 402
83
IN
83
BI 84 84
1
R9312
83
1K
OUT
5% 1/16W MF-LF 2 402
IN
47
BI
B 23 16
IN
2
R9318 0
5% 1/16W MF-LF 402 1
1
R9319 4.99K
1% 1/16W MF-LF 2 402
9 IN_D3P 10 IN_D3N
OUT_D3P OUT_D3N
23 22
14 IN_SCL 13 IN_SDA
AC_AUXP AC_AUXN
20 19
DP_EXTA_ML_P<3> DP_EXTA_ML_N<3> DP_EXTA_DDC_CLK DP_EXTA_DDC_DATA
R9352
95
C9363
DP_SDRVA_ML_C_P<1> DP_SDRVA_ML_C_N<1> DP_SDRVA_ML_C_P<2> DP_SDRVA_ML_C_N<2>
95 95
95 95
1
0.1uF
C9362
1
0.1uF
C9367
DP_SDRVA_ML_C_P<3> DP_SDRVA_ML_C_N<3>
1
0.1uF
C9366
DP_SDRVA_AUXCH_C_P DP_SDRVA_AUXCH_C_N
1
0.1uF
2 10% X5R 2 10% X5R 2 10% X5R 2 10% X5R
16V 402
CEXT
11
DPSDRVA_CEXT
1
DP_AUXCH_ISOL
39 AUXDDC_OFF (IPD)
1
0.1uF
C9368
84 87
1
0.1uF
2 10% X5R 2 10% X5R
OUT
33
OUT
OUT
T29_MCU_INT_L
85 85 84
use PCIe WAKE# PCIE_WAKE_L OMIT
OUT
R93301
18
IN OUT
20% 2 10V CERM 402
10 11 12 13 14 15
C9331
10K
20% 10V 2 CERM 402
5% 1/16W MF-LF 402 2
SWCLK
0 5% 1/16W MF-LF 402 2
IN
85
IN
85
1K
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 1 402
84 85 84
1
10K
DP_SDRVA_ML_N<1> DP_SDRVA_ML_P<1>
27 26
DIN1_1+ DIN1_1-
DP_SDRVA_AUXCH_P DP_SDRVA_AUXCH_N
19 18
AUX1+ AUX1-
DP_SDRVA_HPD
17
HPD_1
5
5% MF 5% MF
1/20W 201 1/20W 201
1
2
PLACE_NEAR=C9361.1:2mm
1
R9362
8
DP_A_BIAS2 VOLTAGE=3.3V
2
1
DP_A_BIAS0
VOLTAGE=3.3V
1
R9363
51
C
5% 1/20W MF 2 201
51
5% 1/20W MF 201 2
T29_D2R1_BIASP T29_D2R1_BIASN
15 14
AUX2+ AUX2-
13
HPD_2
10 32 11
GPU_SEL AUX_SEL NC
DP_A_PWRDWN T29_A_BIAS
45 83 84
T29_A_HV_EN
2
OUT
35 85
P2R = Plug to Receptacle R2P = Receptacle to Plug IN
R9336 10K
R9339
U9390 CBTL04DP081 HVQFN DOUT_0+ 1 DOUT_0- 2
402
T29DPA_ML_N<3> T29DPA_ML_P<3> T29: Unused
OUT
6 85 95 6 85 95
BI
T29DPA_ML_N<1> BI 6 85 95 T29DPA_ML_P<1> OUT 6 85 95 T29: LSX_A_R2P/P2R (P/N)
AUX+ 6 AUX- 7
DP_A_EXT_AUXCH_P BI DP_A_EXT_AUXCH_N BI T29: RX_1 Bias Sink
HPD_IN 8
DP_A_EXT_HPD
IN
B
85 95 85 95
45 83 84
1
OMIT_TABLE
R9398 100K
5% 1/16W MF-LF 2 402
LO=Port A HI=Port B
THMPAD GND
SIGNAL_MODEL=T29DP_MUX
Note: U9390 ML/HPD defaults to T29 mode so that DP/T29 Display can detect host T29 support using I2C pull-ups on ML<3>. U9390 AUX defaults to DP mode because 100-ohm pull-downs would defeat DP Sink’s detection of DP Source. SYNC_MASTER=T29_REF
SYNC_DATE=10/16/2010
PAGE TITLE
DRAWING NUMBER
1M 5% 1/16W MF-LF 2 402
Apple Inc.
SIZE
D REVISION
R
5% 1/16W MF-LF 2 402
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
4
20%
DisplayPort/T29 A MUXing
33
1
C9391
10V 2 CERM
5% 1/16W MF-LF 2 402
DIN2_0+ DIN2_0DIN2_1+ DIN2_1-
1
0.1UF
20% 10V 2 CERM 402
100K
VDD
DOUT_1+ 4 DOUT_1- 5
23 22
C9390 0.1UF
CRITICAL
(T29_A_LSX_P2R) (T29_A_LSX_R2P)
5% 1/16W MF-LF 402
84
T29_A_UC_ADDR R9330 provides pads for programming/debug of MCU, please make accessible. If project has space for 10-pin programming header it should be used.
6
DIN1_0+ DIN1_0-
NC
1K
SWDIO
7
1/20W 201
8
R9399
DP_SDRVA_ML_N<3> DP_SDRVA_ML_P<3>
R9397
84
8
1.5K
31 30
2
1
R9335
85 95
PP3V3_SW_DPAPWR 85 84 Must be 3.3V DP A port power
R9334
I2C Addr: 0x26/0x27 (Wr/Rd) 1
85 95
OUT
PLACE_NEAR=C9361.1:2mm
CBTL04DP081 (353S3151) and PI3vEDP212 (353S3055) are footprint-compatible parts with similar pinouts. NXP uses pin 10 for ML and HPD, Pericom uses pin 10 for ML and pin 11 for HPD.
R9338
0.1UF
T29_A_LSX_P2R T29_A_LSX_R2P T29_LSEO<1>
PIO0_6/SCK PIO1_6/RXD 23 PIO0_7/CTS# PIO1_7/TXD 24 PIO0_8/MISO/CT16B0_MAT0 PIO1_8/CT16B1_CAP0 6 PIO0_9/MOSI/CT16B0_MAT1 SWCLK/PIO0_10/SCK/CT16B0_MAT2 (OD) R/PIO0_11/AD0 (OD) THRM XTALIN 4 VSS PAD
OUT
DP/T29 A Low-Speed MUX
5% 1/16W MF-LF 2 402
1
T29DPA_CONFIG1_RC T29DPA_CONFIG2_RC T29_A_HV_EN_R T29_A_UC_ADDR DP_A_EXT_HPD
16 17 18 19 20
6 85 95
DP_A_BIAS
4
51
1K
22
HVQFN25 1 RESET#/PIO0_0 R/PIO1_0/AD1 2 PIO0_1/CLKOUT R/PIO1_1/AD2 7 PIO0_2/SSEL/CT16B0_CAP0 R/PIO1_2/AD3 (IPU) SWDIO/PIO1_3/AD4 8 PIO0_4/SCL (OD) PIO1_4/AD5/WAKEUP 9 PIO0_5/SDA (OD)
3
31 25 17 6
BI
2
R9393
5% 1/16W MF-LF 402 1
OMIT_TABLE
6 85 95
IN
R9384 R9385
5% MF
U9359 74LVC1G04DBDCK
1
Must be 3.3V DP A port power
VDD
1.5K
CRITICAL 5
95
R9396
25
33
I2C_T29_SCL I2C_T29_SDA T29DPA_HPD T29_A_BIAS T29_LSOE<0> T29_LSOE<1>
95 47 33
=T29_WAKE_L:
T29_LSEO<0>
1
16V 402
2
21
A
IN
R9365 R9364
95
5% 1/16W MF-LF 402 2
0.1UF
2
DP Path Biasing R9361 1.5K 1 2 5% 1/20W 201 R9360 1.5K 1 2 MF
CKPLUS_WAIVE=NdifPr_badTerm 25 T29_A_RSVD_N 24 T29_A_RSVD_P
U9330
IN
95 6
1
C9330
1
IN
GND_VOID=TRUE (D9382/D9383) GND_VOID=TRUE (D9361.2) GND_VOID=TRUE 1.5K 1 2 GND_VOID=TRUE 5% 1/20W 201 1.5K 1 2 MF 5% 1/20W MF 201
(D9382/D9383)
6.3V 0201
95
1
TSLP-2-7
SIGNAL_MODEL=T29PIN
DP_SDRVA_ML_P<2> DP_SDRVA_ML_N<2>
95
1
2
1/20W 201 1/20W 201
(D9360/D9361) 95 6
16V 402
LPC1112A 33
6.3V 0201
D 5% MF 5% MF
SIGNAL_MODEL=EMPTY
95
51
CRITICAL
95 47 33
2 20% X5R 2 20% X5R
2
TSLP-2-7 BAR90-02LRH CRITICAL (All 4 D’s)
6.3V 0201
95
THMPAD
PP3V3_SW_DPAPWR
D9361
85 95
(D9360.2)
1
R93921 GND
5
85 84
DP_A_PWRDWN
95 6
TSLP-2-7
1
85 95
OUT
2
T29: TX_1 T29DPA_ML_C_P<2> T29DPA_ML_C_N<2>
2
BAR90-02LRH
DP_SDRVA_ML_P<0> DP_SDRVA_ML_N<0>
DP_A_PWRDWN
Port A MCU
84
95 6
TSLP-2-7
1
D9383
5% 1/20W MF 201
GND_VOID=TRUE
1
34 PD (IPD)
PS8301 has internal ~150K pull-down on PD pin. Okay to drive this pin even when VCC=0V per Parade (pin is 5V-tolerant).
DP_A_CA_DET
6.3V 0201
20% 6.3V CERM 2 402-LF
12 REXT
87 84
2 20% X5R 2 20% X5R
2.2UF
DPSDRVA_REXT
D9382
BAR90-02LRH
GND_VOID=TRUE
PLACE_NEAR=U9310.11:2 mm
C9319
R9383 1 2
2
BAR90-02LRH
OUT
GND_VOID=TRUE
R9374 1.5K 1 GND_VOID=TRUE R9375 1.5K 1
16V 402
C9369
IN
1.5K
IC supports input high while Vcc = 0V.
(DP_SDRVA_HPD) DP_A_CA_DET
95 6
1
6 85 95
SC70
31 32
R9382 1 2
T29_R2D_P<1> T29_R2D_N<1>
95 6
3
(IPD) OUT_HPD
I2C_DPSDRVA_SCL I2C_DPSDRVA_SDA
10% 6.3V CERM-X5R 402 2
PP3V3_S0
84
3 IN_HPD
38 SCL_CTL 37 SDA_CTL
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
16V 402
(DP_SDRVA_AUXCH_P) (DP_SDRVA_AUXCH_N)
CA_DET
1.5K
D9360
5% 1/20W MF 201
2
16V 402
18 17
36 I2C_ADDR0 (IPD) 35 I2C_ADDR1 (IPD)
C9361
2
6 85 95
IN
(D9372/D9373) (D9365.2)
T29_D2R_C_P<1> T29_D2R_C_N<1> GND_VOID=TRUE
10% 16V X5R 2 402
OUT_AUXP_SCL OUT_AUXN_SDA
DPSDRVA_I2C_ADDR0 DPSDRVA_I2C_ADDR1
1
0.22UF
1
GND_VOID=TRUE GND_VOID=TRUE
D9372/D9373: SIGNAL_MODEL=T29PIN D9364/D9365: SIGNAL_MODEL=EMPTY
0.1UF
16 IN_AUXP 15 IN_AUXN
26 I2C_CTL_EN (IPU)
1
TSLP-2-7
20% 4V CERM-X5R-1 2 201
DP_SDRVA_ML_C_P<0> DP_SDRVA_ML_C_N<0> 95
BAR90-02LRH
2
C9359
AUXCH Snoop Port, used by PS8301 during training.
DP_EXTA_HPD
DP_A_PWRDWN_R SDRV_PD
28 27 25 24
7 IN_D2P 8 IN_D2N
DP_EXTA_AUXCH_P DP_EXTA_AUXCH_N
OUT_D1P OUT_D1N OUT_D2P OUT_D2N
DP_EXTA_ML_P<2> DP_EXTA_ML_N<2>
DPSDRVA_I2C_CTL_EN
47
4 IN_D1P 5 IN_D1N
DP_EXTA_ML_P<1> DP_EXTA_ML_N<1>
30 29
C9360
1
5% 1/20W MF 2 201
OUT_D0P OUT_D0N
C9365
DP_SDRVA_ML_R_P<2> DP_SDRVA_ML_R_N<2>
270
CRITICAL
1
0.22UF
2
TSLP-2-7 BAR90-02LRH CRITICAL (All 4 D’s)
T29 Path Biasing
10% 6.3V CERM-X5R GND_VOID=TRUE 402
C9364
DP_SDRVA_ML_R_P<0> DP_SDRVA_ML_R_N<0>
TSLP-2-7
IN
(D9364.2)
T29: TX_0 T29DPA_ML_C_P<0> T29DPA_ML_C_N<0>
2
1
D9365
GND_VOID=TRUE TSLP-2-7
1
D9373
5% 1/20W MF 201
GND_VOID=TRUE
0.47UF
0.22UF
VDD
1 IN_D0P 2 IN_D0N
DP_EXTA_ML_P<0> DP_EXTA_ML_N<0>
D9372
T29_A_BIAS_R2D_N1
IN
2
1/20W 201
QFN
84
1
0.22UF
1/20W 201
PS8301TQFN40GTR-A2 84
95
2 MF 201 2
U9310
Addr (W/R) 0x96/0x97 0xB6/0xB7 0x94/0x95 0xB4/0xB5
95
41
C
PS8301 I2C Addresses:
C9311 0.1UF
20% 6.3V 2 CERM 402-LF
5% 1/20W MF 201 2
R9355 30 5% 1/20W R9350 30
21 40
1
2.2UF
C9383
R9353
5% MF
C9310
1
0.47UF
(C9383.2)
2
R9373 1 2
2
BAR90-02LRH
1
DP A Super-Driver
PP3V3_S0
6 33
82 51 39 22 6 17 28 47 61 88
95
1.5K
20% 4V CERM-X5R-1 201 GND_VOID=TRUE
C9382
T29_R2D_C_F_N<1> T29_R2D_C_F_P<1>
1/20W 201
270
87 84 83 60 56 53 45 41 40 26 25 23 16 12 7 20 19 18 36 35 32 50 49 48 79 72 71 98 89
95
95 6
1
BAR90-02LRH
T29_R2D_P<0> T29_R2D_N<0>
95 6
0.47UF
(Both L’s)
L9382
1.0NH+/-0.1NH
1/16W 402
C9380 1 C9381 1
T29_R2D_C_N<1> T29_R2D_C_P<1>
D9364
5% 1/20W MF 201
2
T29_A_BIAS_R2D_P1
IN
OVERSIZE_PAD=0.875 mm^2
84
2
1M
95 33 6
1
1.5K R9372 1 2
T29_A_BIAS_R2D_N0
IN
8
T29_D2R_N<1> T29_D2R_P<1>
1/16W 402
16V 402
2
OUT
GND_VOID=TRUE
20% 4V CERM-X5R-1 201 GND_VOID=TRUE
C9372
2
(C9380/C9381)
95 33 6 OUT 88 89 98 48 49 50 51 53 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 56 60 61 71 72 79 82 83 84 87
PP3V3_S0
2
5% 1M MF-LF DP_EXTA_AUXCH_P 84
2
1
84
16V 402
2
10% X5R
DP_EXTA_ML_P<3>
T29_D2R_C_P<0> T29_D2R_C_N<0>
20% 4V CERM-X5R-1 2 201
10% 6.3V 1.0NH+/-0.1NH 0201-1 95 T29_R2D_C_F_N<0> 0.47UF CERM-X5R 95 T29_R2D_C_F_P<0> 402 2 1 2 C9373 L9373 1 10% 6.3V 1.0NH+/-0.1NH 0201-1 0.47UF CERM-X5R Inductor values TBD (C9373.2) GND_VOID=TRUE 402
GND_VOID=TRUE 1
T29 A High-Speed Signals
2
0.47UF
T29 signals are P/N-swapped after AC caps to improve layout.
84
16V 402
2
0.1uF 97 83
DP_EXTA_ML_P<2>
10% X5R
84
95 33 6
16V 402
2
0.1uF DP_EXTA_AUXCH_C_P
OUT
84
16V 402
DP_EXTA_ML_N<1>
10% X5R
0.1uF
97 83
DP_EXTA_ML_P<1>
10% X5R
0.1uF 97 78
95 33 6
C9370 1
(C9370/C9371)
T29_D2R_N<0> T29_D2R_P<0> OVERSIZE_PAD=0.875 mm^2
2
0.1uF 97 78
84
OUT
16V 402
2
10% X5R
0.1uF 97 78
DP_EXTA_ML_N<0>
95 33 6
(Both L’s)
0.1uF 97 78
GND_VOID=TRUE 84
16V 402
2
10% X5R
0.1uF 97 78
DP_EXTA_ML_P<0>
2
10% X5R
0.1uF
1
29 20 16 12 9 3
97 78
2
T29_A_BIAS_R2D_P0
IN
28 21
7
33
8
3
2
BRANCH
PAGE
93 OF 132 SHEET
84 OF 101
1
A
8
6
5
4
470K
1
0.1UF
5% 1/16W MF-LF 402 2
VOUT
0.1UF
QFN
DPAPWRSW_CT OMIT_TABLE
9 CT GND 5 13 14
85 84
IN
0.1UF
IN
1
2
10% 6.3V X5R 201 PLACE_NEAR=C9490.1:2mm
OUT
95 84 6
OUT
R9490
1K
T29_A_BIAS_R VOLTAGE=3.3V
B
8
8
IN IN
OUT
5% 1/20W MF 201 2
8
SIGNAL_MODEL=EMPTY
95 84 6
T29_A_BIAS_D2R_P1
95 84 6
T29_A_BIAS_D2R_N1
2.2K 5% 1/20W MF 201 2
C9400 1
S
GND_VOID=TRUE 95 84 6 95 84 6
OUT OUT
5% 1/20W MF 2 201
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V
D
2 3
DPAPWRSW_HV_DET
2
5% 1/16W MF-LF 402
GND_DPACONN_1
DP Dir
CRITICAL
R9403 GND_VOID=TRUE 1
12
2
2
GND_DPACONN_8
DP Dir
6 8 10 12 14
R9404 GND_VOID=TRUE 1
1
12
2
GND_DPACONN_14
18
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V
5% 1/16W MF-LF 402
GND_VOID=TRUE
16
20
J9400 DSPLYPRT-M97-1
95 6
BOT ROW
TOP ROW
TH PINS
SM PINS
95 84
BI BI
95 6 95 6
2
T29DPA_HPD
OUT
T29DPA_CONFIG1_RC
84
OUT
T29DPA_CONFIG2_RC
R94521
1
DP_A_EXT_AUXCH_P DP_A_EXT_AUXCH_N
1M
5% 1/16W MF-LF 402 2
7
R9451 C9494 1 1M
3
5% 1/16W MF-LF 2 402
330PF
10% 50V CERM 2 402
1
1
1
12
2
30PF
5% 50V 2 CERM 402
C9495
10% 50V 2 CERM 402
2
C9402 0.01UF
10% 50V 2 X7R 402
1
C
5
12
C9471
12
IN
84 95
IN
84 95
T29DPA_ML_P<1> T29DPA_ML_N<1>
IN
6 84 95
T29DPA_ML_C_P<2> T29DPA_ML_C_N<2>
IN
84 95
IN
84 95
GND_VOID=TRUE
1
1
R9470
R9471 470K
5% 1/20W MF 2 201
5% 1/20W MF 2 201
11
BI
B
6 84 95
13
T29: LSX_R2P/P2R (P/N)
15 17 19
GND_VOID=TRUE
GND_DPACONN_13
R9407 1
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V
GND_DPACONN_19
12
2
GND_VOID=TRUE
(Both C’s)
5% 1/20W MF 201
C9472 C9473 1
2 0603
2
20% 4V CERM-X5R-1 201 2
1
20% 4V CERM-X5R-1 201
0.47UF GND_VOID=TRUE
1
1
0.47UF
T29DPA_ML_P<2> T29DPA_ML_N<2>
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V
2
T29DPA_ML_C_P<0> T29DPA_ML_C_N<0>
20% 4V CERM-X5R-1 201
0.47UF
9
21
R9401
2
20% 4V CERM-X5R-1 201 2
1
470K
2
5% 1/20W MF 201
7
1
0.47UF
GND_VOID=TRUE
L9408
1
1% 1/16W MF-LF 402 2
(Both C’s)
FERR-120-OHM-3A
C9401
R9472 470K
5% 1/20W MF 2 201
GND_VOID=TRUE 1
R9473 470K
5% 1/20W MF 2 201
R9408
5% 1/16W MF-LF 402
1
12
2
5% 1/20W MF 201
0.01UF
10% 2 50V X7R 402
470k R’s for ESD protection on AC-coupled signals.
SYNC_MASTER=T29_REF 1
SYNC_DATE=10/16/2010
PAGE TITLE
R9441
DisplayPort/T29 A Connector
100K 5% 1/16W MF-LF 2 402
PART NUMBER 116S0004
Sink HPD range: High: 2.0 - 5.0V Low: 0 - 0.8V
6
1% 1/16W MF-LF 402 2
GND_VOID=TRUE
C9470
T29: TX_1
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V 1
1
T29DPA_HPD_R
5% 1/16W MF-LF 402
C9499
DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a). 330PF
12
5% 1/20W MF 201
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V
R9402
DPACONN_20_RC
1
100K
DPAPWR_FB_DIV
T29DPA_ML_P<0> T29DPA_ML_N<0>
GND_DPACONN_7
95 6
GND_VOID=TRUE SIGNAL_MODEL=EMPTY
1
5% 1/16W MF-LF 2 402
GND_VOID=TRUE R9406
95 6
0603
5% 50V CERM 2 402
OUT
T29DPA_D2R1_AUXCH_P T29DPA_D2R1_AUXCH_N CRITICAL
L9499
30PF
84
22
650NH-5%-0.430MA-0.052OHM
C9498 1
84
5% 1/16W MF-LF 402 2
OMIT_TABLE
SHIELD PINS
SIGNAL_MODEL=EMPTY
(Both L’s) 95 84
1
T29 Dir 95 6
HOT_PLUG_DETECT GND CONFIG1 ML_LANE0P CONFIG2 ML_LANE0N GND GND ML_LANE3P ML_LANE1P ML_LANE3N ML_LANE1N GND GND AUX_CHP ML_LANE2P AUX_CHN ML_LANE2N DP_PWR RETURN
4
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V
5% 1/16W MF-LF 402
SIGNAL_MODEL=EMPTY
2
10K
R94351
R9405
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V
0603
1
R9432
220
T29: TX_0
2
D9499
1
F-RT-THSM
L9498
BAR90-02LRH
T29_2V9_ENABLE
82 5% 1/16W MF-LF 402 2
Circuit threshold range: 2.877-2.941V (2.903V nominal) OMIT_TABLE
For J9400 T29 SMT pads (3, 5, 17 & 19): GND_VOID=TRUE
5% 1/20W MF 2 201
2 TSLP-2-7
85 35 84
R94361
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V
0603
10% 50V 2 X7R 402
1
1K
GND_VOID=TRUE SIGNAL_MODEL=T29PIN
8
1K
GND_VOID=TRUE
T29DPA_ML_P<3> T29DPA_ML_N<3> BI T29: Unused
1
G 2
1 S
PP3V3RHV_SW_DPAPWR
R9495
TSLP-2-7 BAR90-02LRH CRITICAL
A
2
BI
D9498
S 4
T29_A_HV_EN
R9433
0.01UF
650NH-5%-0.430MA-0.052OHM
GND_VOID=TRUE
T29_D2R_C_P<1> T29_D2R_C_N<1>
1
GND_VOID=TRUE
2.2K
ZXRE060A
DisplayPort/T29 A Connector
L9400
FERR-120-OHM-3A PP3V3RHV_SW_DPAPWR_UF
1
0.1UF
SOT353 4 FB PGND GND 1 2
10% 10V 2 X5R 402
R94371
1
R9499
SOT563
C9435
20% 10V 2 CERM 402
24.9K
Q9419
CRITICAL
R94981
SSM6N37FEAPE
DPAPWRSW_NPN_E
1
DMB53D0UV
R94941
5% 1/20W MF 2 201
1
3 IN
6 D
GND_VOID=TRUE
51
5 OUT
1UF
22
T29_D2R_C_P<0> T29_D2R_C_N<0>
1
T29_A_BIAS
DPAPWRSW_ON_C
5% 1/16W MF-LF 402 2
ZXRE060A REF range: 0.595-0.605V (0.600V nominal) Circuit threshold range: 3.363-3.439V (3.395V nominal)
T29 Dir 95 84 6
85 84
R94241
DPAPWR_BLDR_B
Note: Bleeder active when DPAPWRSW_HV_DET is HIGH and T29_A_HV_EN is LOW.
0.1UF
20% 2 6.3V POLY-TANT CASE-B2-SM
Q9430
SOT563
R9418
2 G
C9490
C9429
6 D
SSM6N37FEAPE
5 G
DMB53D0UV
MIN_LINE_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MM
T29_A_HV_EN
T29_A_BIAS
1
D 3
SOT363
DPAPWRSW_HV_DET_L NO STUFF 20% 10V 2 CERM 402
SOT-563 85 84 35
S
4
GND 2
1
FB 4 PGND 1
Q9430
1
4
20% 2 6.3V X5R-CERM-1 603
CRITICAL
Q9426
SOT-563
5
100UF
MMDT3946XG DPAPWRSW_ON_L_C
Q9419
2.5V / 249 ohm = 10mA R9419 P = ~27mW 249 1 2 DPAPWR_BLDR_E 1% 1/16W MF-LF 402
SOT353
D
C9487
U9435
10% 6.3V CERM-X5R 2 402
5% 1/16W MF-LF 2 402
20% 10V CERM 2 402
Bleeder Resistor
S 2
4.7K
U9426
0.1UF
3
1
DPAPWRSW_P3V3_ON
1 R9429 C9424 0.47UF
ZXRE060A
C9426
20% 10V CERM 2 402
20% 2 10V CERM 402
CRITICAL
C9480 22UF
4
200k / RFLT = 885mA 201k / RLIM = 935mA CCT * 38900 CCT * 100000
1
5% 1/16W MF-LF 2 402
3
G
= = = =
20% 6.3V 2 X5R 603
1
0.1UF
4.7K
5% 1/16W MF-LF 2 402
1
SOD-VESM-HF
1
C9481
0.1UF
R9430
1K
6
D 3
1% 1/16W MF-LF 2 402
44 45 72
1
R9426
1
3 CRITICAL IN OUT 5
1% 1/16W MF-LF 402 2
210K
5% 1/16W MF-LF 402 2
Q9415
R9411
100K
C9485
C9436 1
21.5K
1
R9410
3.3V Always 1
1
10UF
DPAPWRSW_P3V3_ON_L DPAPWRSW_HV_DET_R_L
R94281 1
45 55 65 70 71 6 7 17 19 20 22 23 24 25 29 39 72 82 89 98
SMC_S4_WAKESRC_EN IN
EN 4
CRITICAL
C9486 1
BGA
Blocking FET, off when Source >3.4V or HV_EN high.
DPAPWRSW_VREF
DPAPWRSW_IFLT
10% 2 6.3V CERM-X5R 402
IFLT ILIM TFLT TSD
5% 1/16W MF-LF 402 2
4.7K
DPAPWRSW_ILIM
IFLT 8 THRM PAD
Q9425
SI8409DB
5
0.47UF
R94251
1% 1/16W MF-LF 402 2
100K
3 OC*
PP3V3_S5 IN 5
GND 2
2
C9412
R94271
TP_DPAPWRSW_FLT_L
16 EN* FLT* 15 (IPU-Weak!) 6 RTRY* ILIM 7
T29_A_HV_EN
85 84 35
2
STPS2L30AF
10% 2 50V X7R 603-1
SN1010017
DPAPWRSW_HVEN_L_R
1
C9411
DFLS1100
CRITICAL
3.3V/HV MUXed
SM
1
U9410
10% 50V 2 X7R 603-1
1
VIN
10 11 12
TPS2051B SOT23
1 OUT
G
C9410
1 2 3 4
D9425
-30V +/-12V -1.4V 65mOhm @ 2.5V Vgs 3.7A @ 70C
DP_PWR must be S4 to support wake from T29 devices.
U9480
POWERDI-123 2 1
SI8409DB: Vds(max): Vgs(max): Vgs(th): Rds(on): Id(max):
Min Max IFLT 876mA 894mA (*) ILIM 925mA 944mA (*) TFLT 13.4ms 26.7ms TSD 235ms 724ms CRITICAL PPHV_SW_DPAPWR D9410
17
R94161
C
Port A 3.3V Power Switch
CRITICAL
Nominal 885mA 935mA 18.3ms 470ms
CRITICAL
PP15V_T29 20V Max
SSM3K15FV
1
CRITICAL
(*) U9410 tolerance unknown
35 8 7
2
3.3V/HV Power MUX
PP3V3_SW_DPAPWR MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V
Port A HV Power Switch D
3
1
84
7
QTY 1
DESCRIPTION RES,0 OHM,5,1/16W,0402,SMD,LF
REFERENCE DES
CRITICAL
DRAWING NUMBER
BOM OPTION
Apple Inc.
C9412
SIZE
D REVISION
R
5
132S0121
1
CAP,CER,0.1UF,10%,6.3V,X5R,0201,SMD
R9405
132S0121
1
CAP,CER,0.1UF,10%,6.3V,X5R,0201,SMD
R9406
4
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
3
2
BRANCH
PAGE
94 OF 132 SHEET
85 OF 101
1
A
8
7
6
5
4
3
2
1
D
D
81 49 7
PPVIN_S5_HS_GPU_ISNS CRITICAL
C9540
1
1
68UF 20% 16V POLY-TANT CASE-D2E-SM
2
2
C9545
1
C9546
1UF
1000PF
10% 25V X5R 603-1
5% 25V NP0-C0G 402
2
CRITICAL
C9590 4.7
2
1
1
2
2
1
20% 16V POLY-TANT CASE-D2E-SM
PVIN_S0GPU_P1V0
1
C9595
C9596
1UF
68UF
R9500
1000PF
10% 25V X5R 603-1
5% 25V
2 NP0-C0G 402
5% 1/16W MF-LF 402
7
CRITICAL
3
2
CRITICAL
Q9510
C9500
SIZ700DT 1
10% 25V X5R 805
P1V0GPU_DRVH MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE
8
DIDT=TRUE
6
C
PP5V_S0
1
10UF
POWERPAIR-6X3.7
C9501 2
6 7 8 22 41 46 51 53 64 67 68 69 71 72 88 101
1
1UF 10% 10V X5R 402-1
2
(Internal 10-ohm path from PVCC to VCC) PP5V_S0GPU_P1V0P1V5_VCC
PCMB065T-SM
XW9515
C9516
SM
1000PF 2
CRITICAL
C9515
2
5% 25V NP0-C0G 402
1
1
CRITICAL
6 2
P1V0GPU_VBST
17
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
15
DIDT=TRUE
P1V0GPU_LL
16
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM SWITCH_NODE=TRUE
18
DIDT=TRUE
10
C9510
14
330UF 2
20% 2 2.0V POLY-TANT B2-SM
9
P1V0GPU_VFB P1V0GPU_TRIP
1
10UF 20% 6.3V X5R 603
11 12 29
PLACE_NEAR=L9510.1:3mm 4
2
20 2
VIN BOOT1 UGATE1 PHASE1 LGATE1 OUT1 EN1 BYP FB1 ILIM1 SKIP* EN_LDO SECFB TON
5
CRITICAL LDO LDOREFIN BOOT2 U9500 UGATE2 QFN2 PHASE2 LGATE2 OUT2 EN2 REFIN2 ILIM2 REF POK1 POK2
8.66K
2
1% 1/16W MF-LF 402
1 R9521
21
33
P1V0S0_VSNS
7
1
P1V5FB_VBST
2
R9535
(=PP1V5FB_S0_REG)
27
2
1
PP2V_S0GPU_P1V5_REF
13
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=2V
28
1% 1/16W MF-LF 402 2
1
XW9500 SM 1
2
C9565
1
10UF 2
20% 6.3V X5R 603
C9566 1000PF 5%
2 25V NP0-C0G 402
S
C9580
1
2
C9585 0.1UF
2
20% 10V CERM 402
10% 50V X7R 603-1
P1V5FB_LL
R9563
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM SWITCH_NODE=TRUE
P1V5_GPU_VSNS
1
XW9565 SM
DIDT=TRUE
2
11.8K 1% 1/16W MF-LF 402
R9564 1 1% 1/16W MF-LF 402 2
1
PLACE_NEAR=L9560.2:3mm
2
Vout = 2(Req/(Ra+Req))
GPIO7
FBVDDQ
1 0
1.35V 1.503V
B
R9562 78.7K
1
35.7K
Vout = 0.7V * (1 + Ra / Rb) (Rb should be between 10K and 100K)
3
0.1UF
GPU_P1V5_REFIN P1V5FB_TRIP
130K
1% 1/16W MF-LF 2 402
CRITICAL 1
DIDT=TRUE
R9585 1
75K
20% 2.5V 2 POLY-TANT CASE-B2-SM2
PWRPK-12128
G
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE
1
220UF
SIS426DN
4
P1V5FB_DRVL
PGND
353S2312
C9560
Q9561
C9561 0.001UF
2
10% 50V CERM 402
1% 1/16W MF-LF 402 2
CRITICAL
GPUFB_VID_L
Q9565 3
D
20.0K
2
CRITICAL
25
1
1
2 PCMB065T-SM
CRITICAL
23
7 100
Vout = 1.503V 8A MAX OUTPUT F = 500 KHZ
D
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
31
L9560
3
5
26
32
2
1.0UH-13A-5.6MOHM
1
100PF 5% 50V CERM 402
1
24
30
PP1V5_GPU_REG
CRITICAL
DIDT=TRUE
(SGND)
NO STUFF
C9520
S
NC
8
PWRPK-12128
G
2
1
THRM_PAD GND
1 R9520
10% 10V X5R 402-1
2
22
f = 400 kHz
1
10% 50V X7R 603-1
L9510 1
1
0.1UF
2.2UH-8.0A
(Q9510 limit?)
B
10% 10V X5R 402-1
1
C
SIS426DN
4
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE
1UF
1
1UF
ISL6236
C9530 CRITICAL
C9503
C9504
3
19
4
PVCC VCC VREF3
3.5A MAX OUTPUT
P1V5FB_DRVH
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V
PP1V0_S0GPU
Vout = 1.003V
Q9560
PP5V_S0GPU_VREF
DIDT=TRUE
100 7
CRITICAL
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V
P1V0GPU_DRVL MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE
5
5
D
SSM3K15FV SOD-VESM-HF
1% 1/16W MF-LF 402
GND_P1V0P1V5_SGND 89 87
IN
89 87 86 81 73 8
OUT
89 87 86 81 73 8
OUT
89
IN
P1V0GPU_EN PM_ALL_GPU_PGOOD PM_ALL_GPU_PGOOD P1V5FB_EN
2
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V
S
G
1
FBVDD_ALTVO
A
IN
78 79
SYNC_MASTER=K91_ERIC
SYNC_DATE=10/08/2010
PAGE TITLE
1V0 GPU / 1V5 FB Power Supply DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
95 OF 132 SHEET
86 OF 101
1
A
8 88 87 84 61 60 56 47 45 41 28 26 25 17 16 12 7 22 20 19 39 36 35 51 50 49 82 79 72 98
83 53 40 23 6 18 32 48 71 89
7
6
5
R9600 PP3V3_S0
0
1
C9610
1
0.1UF
C9621
20% 10V 2 CERM 402
D
70 25 14 7 6 22 20 17 71
PP1V8_S0
1
C9622
1
1
0.1UF
C9623 0.1UF
20% 10V 2 CERM 402
20% 2 10V CERM 402
1
C9624 0.1UF
20% 2 10V CERM 402
1
C9625
1
0.1UF
C9626
1
0.1UF
20% 10V 2 CERM 402
C9627
1
0.1UF
C9628 0.1UF
20% 2 10V CERM 402
20% 10V 2 CERM 402
1
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.09 mm VOLTAGE=3.3V
C9629
92 87 18
0.1UF
92 87 18
20% 10V 2 CERM 402
20% 2 10V CERM 402
92 87 18 92 87 18
L9621
92 87 18
FERR-220-OHM
PP1V8_S0_GMUX_R
2
5% 1/16W MF-LF 402
C9611
1
1
0.1UF
C9612 0.1UF
20% 10V 2 CERM 402
20% 10V 2 CERM 402
1
C9613 0.1UF
20% 10V 2 CERM 402
1
C9614
1
0.1UF
C9615
1
0.1UF
20% 10V 2 CERM 402
C9616
1
0.1UF
20% 10V 2 CERM 402
PP3V3_S0_GMUX_ULC_VCCPLL
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.09 mm VOLTAGE=1.8V
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.09 mm VOLTAGE=3.3V
C9617
2
92 87 18
97 87 78
20% 10V 2 CERM 402
20% 10V 2 CERM 402
97 87 78 97 87 78 97 87 78
L9620 PP3V3_S0_GMUX_LRC_VCCPLL MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.09 mm VOLTAGE=3.3V
PP1V2_S0 1
0.1UF
20% 4V 2 X5R-1 402
1
C9605
20% 10V 2 CERM 402
C9606
1
0.1UF
0.1UF
20% 10V 2 CERM 402
20% 10V 2 CERM 402
1
C9607 0.1UF
1
C9608 0.1UF
20% 10V 2 CERM 402
20% 10V 2 CERM 402
2
97 87 78 97 87 78
LVDS_EG_A_CLK_P LVDS_EG_A_DATA_P<0> LVDS_EG_A_DATA_P<1> LVDS_EG_A_DATA_P<2> LVDS_EG_B_DATA_P<0> LVDS_EG_B_DATA_P<1> LVDS_EG_B_DATA_P<2>
1
2
1
2
1
2
1
2
100 100 100
1
2
1
2
1
2
R9660 R9661 R9662 R9663 R9664 R9665 R9666
100 100 100 100
1
100 100 100
C9630
20% 10V 2 CERM 402
PLACE_NEAR=U9600.H3:5mm
1% 1%
2 2 2
1
2 2
1
2
GMUX_CFG0
87
EG_PWRSEQ_EN
R9684
1K
1
2
87
JTAG_GMUX_TDI
R9685
10K
1
2
87
JTAG_GMUX_TDO
R9686
10K
1
2
87
GMUX_DEBUG_RESET_L
R9680
1K
1
2
OUT
87 83
OUT
87 83
OUT
83
OUT
87 83
OUT
CRITICAL
J9600
B
JTAG_ISP_TCK
OUT
16 8
OUT
79
OUT
87 82
OUT
93 46 44 16 6
BI
93 46 44 16 6
BI
6 48 49 50 51 53 56 60 61 71 72 46 44 16 93 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 93 46 25 6 79 82 83 84 87 88 89 98
BI
IN OUT
18 87
8
NO STUFF
R96471 10K
1% 1/20W MF 201 2
PB26A PB26B
K12
A4 P11 ULC_VCCPLL LRC_VCCPLL
VCCIO7
VCCIO6
VCCIO5
VCCIO4
VCCIO3
VCCIO2
VCCIO1
PT9B
PB27A PB27B PB28A
PT14A PT14B PT15A PT15B PT16A PT16B PT17A PT17B PT18A PT18B PT19A PT19B PT20A PT20B PT28A PT28B
PB28B
PL2A PL2B
PR2A PR2B
PL6A
PR6A
PL6B
PR6B
PL7A PL7B
PR7A PR7B
PL8A
PR8A
PL8B PL9A PL9B
PR8B PR9A PR9B
PL10A PL10B PL11A PL11B PL12A PL12B PL14A PL14B PL15A PL15B PL25A PL25B
(Tie/strap low if EGPU doesn’t provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU)
J1
GND
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 88 87 84 83 82 79 72
B5 B7 A12 C14 F13 M12 M9 M3 N5 M1 C3 F2
PT9A
BANK6
89
B1 B2 C2 D3 D1 E1 D2 E3 F1 G1 F3 G2 H2 G3 H1 H3 L1 L3 K3 L2 N1 P1
IN
PT8A PT8B
BANK7
LVDS_IG_B_DATA_P<2> LVDS_IG_B_DATA_N<2> 92 87 18 IN GMUX_PL6A TP_GMUX_PL6B 6 LVDS_IG_A_DATA_P<0> 92 87 18 IN LVDS_IG_A_DATA_N<0> 92 87 18 IN LVDS_IG_A_DATA_P<1> 92 87 18 IN LVDS_IG_A_DATA_N<1> 92 87 18 IN LVDS_IG_A_DATA_P<2> 92 87 18 IN LVDS_IG_A_DATA_N<2> 92 87 18 IN LVDS_IG_B_DATA_P<0> 92 87 18 IN LVDS_IG_B_DATA_N<0> 92 87 18 IN LVDS_IG_B_DATA_P<1> 92 87 18 IN LVDS_IG_B_DATA_N<1> 92 87 18 IN LVDS_IG_A_CLK_P 92 87 18 IN LVDS_IG_A_CLK_N 92 87 18 IN TP_LVDS_MUX_SEL_EG 8 OUT TP_GMUX_PL14B GMUX_RESET_L 25 IN GMUX_VSYNC 88 87 8 PM_ALL_GPU_PGOOD 86 81 73 8 IN PEX_CLKREQ_L 79 8 IN 92 87 18
8 19 23 33 87
IN
25 19
87
5 6
OUT
89 87
PT7B
PB14A PB14B PB15A (OD) PB15B PB16A PB16B PB17A PB17B PB18A PB18B (OD) PB19A PB19B PB20A PB20B
BANK4
4
89 87 86
BI
7
3
OUT
93 46 44 16 6
GMUX_JTAG_CONN 2
OUT
89 87 81
BI
M-RT-SM
PP3V3_S0 JTAG_GMUX_TDO JTAG_GMUX_TDI JTAG_GMUX_TMS
89 87 71
93 46 44 16 6
1909782
1
OUT
PB7B
BANK5
87 73 8
PT7A
CSBGA
PP3V3_S0
PR10A PR10B PR11A PR11B PR12A PR12B PR14A PR14B PR24A PR24B
A2 A3 A1 B3 C5 A5 B6 C7 A6 A7 C8 C9 A8 B9 A9 C10 B10 A10 A11 B12 B13 A13
LVDS_B_DATA_P<0> LVDS_B_DATA_N<0> LVDS_B_DATA_P<1> LVDS_B_DATA_N<1> LVDS_B_DATA_P<2> LVDS_B_DATA_N<2> EG_PWRSEQ_EN GMUX_DEBUG_RESET_L LVDS_A_CLK_P LVDS_A_CLK_N LVDS_B_CLK_P LVDS_B_CLK_N LVDS_A_DATA_P<0> LVDS_A_DATA_N<0> LVDS_A_DATA_P<1> LVDS_A_DATA_N<1> LVDS_A_DATA_P<2> LVDS_A_DATA_N<2> GND GND GND GND
A14 B14 D12 D13 D14 E14 E12 F12 F14 G14 G12 G13 H13 H12 H14 J12 L14 M13 N14 N13
DP_A_CA_DET DP_HOTPLUG_DET LVDS_EG_A_DATA_P<0> LVDS_EG_A_DATA_N<0> LVDS_EG_A_DATA_P<1> LVDS_EG_A_DATA_N<1> LVDS_EG_A_DATA_P<2> LVDS_EG_A_DATA_N<2> LVDS_EG_B_DATA_P<0> LVDS_EG_B_DATA_N<0> LVDS_EG_B_DATA_P<1> LVDS_EG_B_DATA_N<1> LVDS_EG_B_DATA_P<2> LVDS_EG_B_DATA_N<2> LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N LVDS_IG_PANEL_PWR EG_LCD_PWR_EN LVDS_IG_BKL_ON EG_BKLT_EN
72 71 54 53 18 8 7 6 49 48 47 32 31 30 29 25 24 19
OUT
83 97
OUT
83 97
OUT
83 97
OUT
83 97
OUT
83 97
OUT
JTAG_GMUX_TDI
10K
IN IN
87
OUT
Q9605 GMUX_VSYNC
OUT
83 97
OUT
83 97
OUT
83 97
OUT
83 97
OUT
83 97
OUT
83 97
OUT
83 97
OUT
83 97
OUT
83 97
201
MF
201
1/20W
MF
201
LVDS_IG_B_DATA_N<0> LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_N<2>
LVDS_EG_A_CLK_N PLACE_NEAR=U9600.D13:5mm LVDS_EG_A_DATA_N<0> 1% 1/20W MF 201 PLACE_NEAR=U9600.E14:5mm LVDS_EG_A_DATA_N<1> 1% 1/20W MF 201 PLACE_NEAR=U9600.F12:5mm LVDS_EG_A_DATA_N<2> PLACE_NEAR=U9600.J12:5mm
1%
1/20W
MF
1/20W
201
MF
201
LVDS_EG_B_DATA_N<0> PLACE_NEAR=U9600.G13:5mm LVDS_EG_B_DATA_N<1> 1% 1/20W MF 201 PLACE_NEAR=U9600.H12:5mm LVDS_EG_B_DATA_N<2> PLACE_NEAR=U9600.G14:5mm
1%
1/20W
MF
201
1%
1/20W
MF
201
18 87 92 18 87 92
D
18 87 92
78 87 97 78 87 97 78 87 97 78 87 97
78 87 97 78 87 97 78 87 97
PP3V3_S0
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
C
87 83
DP_MUX_SEL_EG
R9681
10K
1
2
87 83
LVDS_DDC_SEL_IG
R9682
10K
1
2
87 83
LVDS_DDC_SEL_EG
R9683
10K
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
(Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rail’s source is valid)
NO STUFF
87 73 8
EG_RESET_L
R9691
100K
1
2
88 87 6
LCD_BKLT_PWM
R9693
100K
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
P1V5FB1V8GPU_R_EN
89 87 86
P1V0GPU_EN
89 87 81
GPUVCORE_EN
1
R9674
IN
84
IN
83
IN
78 87 97
IN
78 87 97
IN
78 87 97
IN
78 87 97
IN
78 87 97
IN
78 87 97
IN
78 87 97
IN
78 87 97
IN
89 87 71
87 82
78 87 97
IN
78 87 97
IN
78 87 97
IN
78 87 97
IN
78 87 97
IN
8 18
IN
78 79
IN
8 18
IN
78 79
5% 1/20W MF 2 201
R9673
P3V3GPU_EN
B
4.7K 5% 1/20W MF 2 201
1
R9672
LCD_PWR_EN
4.7K 5% 1/20W MF 2 201
1
R9671
78 87 97
IN
R9676
4.7K 1
1
R9678 4.7K 5% 1/20W MF 201
4.7K 5% 1/20W MF 2 201
2
GMUX_S3_PD_GND
Q9607 1
10K
1% 1/16W MF-LF 402 2
Required Pulldowns
89 87
D 3
NO STUFF 1
SSM6N15FEAPE
R9675
SOT563
0
100K 5% 1/20W MF 2201
5 G
JTAG_GMUX_TDO
87
5% 1/16W MF-LF
2402
S 4
SYNC_MASTER=K91_MARY 87
D 6
Q9605
SSM6N15FEAPE
SSM6N15FEAPE
SOT563
SOT563
8 87 88
2
R9605 1K
2
5% 1/20W MF 201
S 1
5
G
Graphics MUX (GMUX)
SOT563
DRAWING NUMBER
Apple Inc. S 4
89 72 44 23
IN
S 1
JTAG_ISP_TDI
33 19 8
NOTICE OF PROPRIETARY PROPERTY:
ALL_SYS_PWRGD
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
JTAG_ISP_TDO
6
5
4
SIZE
D REVISION
R
T29_JTAG_FET 33 19 8
7
G
SYNC_DATE=08/03/2010
PAGE TITLE
D 6
SSM6N15FEAPE
D 3
2 G
8
MF
1/20W
83 97
Q9607
1% 1/20W MF 2 201
1
1/20W
PLACE_NEAR=U9600.B2:5mm
18 87 92
GMUX_S3_PD_EN
R9670
PP3V3_T29
201
83 97 87
PP3V3_S3
NO STUFF 1
35 34 33 25 19 16 7
MF
R9679
U9600
BANK0
2
88 87 6
PB7A
BANK1
1% 1/20W MF 201
CFG0
P2 N2 P4 N4 N3 M4 P5 M5 P6 M6 P7 M7 N7 N8 P9 N9 P10 M10 P12 P13 N12 P14
BANK2
10K
1% 1/20W MF 201 2
K1
1/20W
18 87 92
18 87 92
1
XP25-5
LCD_BKLT_EN LCD_BKLT_PWM LVDS_DDC_SEL_EG LVDS_DDC_SEL_IG DP_MUX_EN DP_MUX_SEL_EG EG_RESET_L P3V3GPU_EN GPUVCORE_EN P1V0GPU_EN P1V5FB1V8GPU_R_EN PEG_CLKREQ_L DP_CA_DET_EG LCD_PWR_EN LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L LPCPLUS_RESET_L LPC_CLK33M_GMUX GMUX_INT
BANK3
1
OUT
ULC_GNDPLL LRC_GNDPLL
10K
R9641
88 8
201
18 87 92
NO STUFF
B4 M11
R96461
NO STUFF
MF
LVDS_IG_A_CLK_N LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_N<2>
Required Pullups
SILK_PART=GMUX_RST
GNDIO7
NO STUFF
VCCJ
OMIT CRITICAL
GNDIO6
87 18
VCCAUX
TCK TDI TDO TMS TOE
GNDIO5
87
2
VCCIO0
87
K14 L13 K13 L12 K2
GNDIO3 GNDIO4
1% 1/20W MF 201
JTAG_ISP_TCK JTAG_GMUX_TDI JTAG_GMUX_TDO JTAG_GMUX_TMS GMUX_TOE
GNDIO2
87 33 23 19 8
GNDIO1
1% 1/20W MF 201 2
C11 J2 J14 M8
VCC 1
10K
1/20W
PLACE_NEAR=U9600.G3:5mm
1%
1%
1
201
PLACE_NEAR=U9600.G2:5mm
1%
2
1
201
MF
PLACE_NEAR=U9600.G1:5mm
1%
1
MF
1/20W
PLACE_NEAR=U9600.E3:5mm
1%
1
1/20W
PLACE_NEAR=U9600.E1:5mm
1%
SIGNAL_MODEL=EMPTY
20% 10V 2 CERM 402
0.1UF
GNDIO0
R9640
10K
A
100 100 100 100
0.1UF
C9609
1
LVDS_IG_B_DATA_P<0> LVDS_IG_B_DATA_P<1> LVDS_IG_B_DATA_P<2>
R9650 R9651 R9652 R9653 R9654 R9655 R9656
PP3V3_S0
R96451
C
C9604
1
B8 C6 C12 C13 E13 M14 N10 N6 P3 M2 C1 E2
88 72 51 41 28 19 6 16 23 36 48 60 83
4.7UF
B11 C4 J3 J13 N11 P8
98 89 82 79 56 53 47 45 35 32 22 20 12 7 18 17 26 25 40 39 50 49 71 61 87 84
C9600
1
97 87 78
0402
1
LVDS_IG_A_CLK_P LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_P<2>
0402
C9631 0.1UF
0.1UF
20% 10V 2 CERM 402
1
1
92 87 18
FERR-220-OHM
70 7 6
1
LVDS Receiver Termination
R9610 0
2
PP3V3_S0_GMUX_R
0.1UF
20% 10V 2 CERM 402
3
GMUX CPLD
2
5% 1/16W MF-LF 402
1
4
3
2
BRANCH
PAGE
96 OF 132 SHEET
87 OF 101
1
A
8
7
6
5
4
3
2
1
PPBUS S0 LCDBkLT FET
CRITICAL
Q9706
MOSFET
FDC638APZ
CHANNEL
P-TYPE
RDS(ON)
43 mOhm @4.5V
LOADING
0.715 A (EDP)
FDC638APZ_SBMS001 SSOT6-HF
2 5
PPBUS_S0_LCDBKLT_FUSED MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
603-HF
BOTTOM
1
PPBUS_G3H
C9782 1
1
R9788
0.1UF
301K
10% 16V X5R 2 402
1% 1/16W MF-LF 2 402
3
39 35 8 7 6 63 62 49 48
2
4
D
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
6
F9700 3AMP-32V-467 1
PPBUS_SW_LCDBKLT_PWR
72 71 69 68 67 64 53 51 46 41 22 8 7 6 101 86
LCDBKLT_EN_DIV 100 7
88 100
THERE IS A SENSE RESISTOR BETWEEN PPBUS_SW_LCDBKLT_PWR AND PPBUS_SW_BKL ON THE SENSOR PAGE
PLACE_NEAR=L9701.2:3mm
PP5V_S0 PPBUS_SW_BKL CRITICAL
1 C9712 10UF
1
R9789 147K
1
10% 25V X5R 2 805
1% 1/16W MF-LF 2 402
D
*C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS *PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE. *LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
CRITICAL CRITICAL L9701 D9701 33UH-1.8A-110MOHM SOD-123 1 2 1 2 PPBUS_SW_LCDBKLT_PWR_SW MIN_LINE_WIDTH=0.5 MM 1217AS-2SM MIN_NECK_WIDTH=0.2 MM VOLTAGE=50V RB160M-60G SWITCH_NODE=TRUE
C9713 0.1UF
DIDT=TRUE
10% 2 25V X5R 402
PLACE_NEAR=L9701.1:3mm
PLACE_NEAR=U9701.A5:3mm
PLACE_NEAR=U9701.D1:5mm
1 C9710 1UF
D 3
10% 25V 2 X5R 603-1
SOT563
5 G 87 8
IN
LCD_BKLT_EN
71 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 98 89 87 84 83 82 79 72
S 4
Q9707
PLACE_NEAR=U9701.D1:3mm
1
C9714 0.01UF
10% 16V 2 CERM 402
XW9720 SM PPVOUT_SW_LCDBKLT_FB
PP3V3_S0
VOLTAGE=50V
PLACE_NEAR=U9701.C4:4mm
LCDBKLT_DISABLE
10% 2 50V X5R 1210-1
PLACE_NEAR=D9701.2:5mm PLACE_NEAR=D9701.2:3mm
LCDBKLT_EN_L
Q9707
6 8 82 100
CRITICAL MIN_NECK_WIDTH=0.375 MM
VOLTAGE=50V 1 C9797 1 C9799 C9796 220PF 10UF 10UF
10% 10% 50V 2 X7R-CERM 2 50V X5R 402 1210-1
PLACE_NEAR=L9701.1:3mm
SSM6N15FEAPE
PPVOUT_S0_LCDBKLT MIN_LINE_WIDTH=0.5 MM
CRITICAL
1
1
2
PLACE_NEAR=C9797.1:5mm
1 C9711 0.1UF 10% 16V X5R 2 402
D 6
SSM6N15FEAPE SOT563
C
C 2 G 25
IN
BKL_VSYNC_R
S 1
BKLT_PLT_RST_L
MIN_NECK_WIDTH=0.075 mm
NO STUFF
1 R9754 R9755 0 10K
1
GMUX_VSYNC
R9757 2
5% 1/16W MF-LF 402
5% Addr: 0x58(Wr)/0x59(Rd)1/16W MF-LF 402
100 88
PPBUS_SW_LCDBKLT_PWR
B
R9704 33
87 6
IN
LCD_BKLT_PWM
1
1/16W MF-LF 402
2
5% 1/16W MF-LF 402
1
C1
LP8550
1 0 SMBUS_PCH_DATA
2
1/16W MF-LF 1402
C9704 33PF
5% 50V 2 CERM 402
1 R9716 90.9K
1% Fpwm=9.62kHz 1/16W MF-LF see spec for others 4022
B1 B2
BKLT:PROD
R9717 0
PLACE_NEAR=U9701.E5:10mm 1 2 MIN_LINE_WIDTH=0.5 mm 5% MIN_NECK_WIDTH=0.20 mm 1/16W BOTTOM MF-LF
A5
BKL_ISEN1 BKL_ISEN2 BKL_ISEN3
6 82
LED_RETURN_2
6 82
BKLT:PROD
R9718 0
PLACE_NEAR=U9701.D5:10mm 1 2 MIN_LINE_WIDTH=0.5 mm 5% MIN_NECK_WIDTH=0.20 mm 1/16W BOTTOM MF-LF
BKL_ISEN4
BKL_ISEN5 BKL_ISEN6
MIN_LINE_WIDTH=0.5 mm OUT MIN_NECK_WIDTH=0.20 mm
402
BKLT:PROD
R9719 0
PLACE_NEAR=U9701.C5:10mm 1 2 MIN_LINE_WIDTH=0.5 mm 5% MIN_NECK_WIDTH=0.20 mm 1/16W BOTTOM MF-LF
B LED_RETURN_3 MIN_LINE_WIDTH=0.5 mm
OUT
6 82
MIN_LINE_WIDTH=0.5 mm OUT MIN_NECK_WIDTH=0.20 mm
LED_RETURN_4
6 82
LED_RETURN_5
6 82
LED_RETURN_6
6 82
MIN_NECK_WIDTH=0.20 mm
402
I_LED=22.7mA
BKLT:PROD
R9714 16.2K
R9720 0
1
1% 1/16W MF-LF 2402
LED_RETURN_1
MIN_LINE_WIDTH=0.5 mm OUT MIN_NECK_WIDTH=0.20 mm
402
E5 D5 C5 E3 E2 E1
GND_SW GND_SW
BI
SW_0
GND_L
93 61 47 41 30 28 26 23 16
1
VSYNC
A1 A2
SMBUS_PCH_CLK
D2
B5
IN
VIN
U9701 25-BUMP-MICRO
SW_1 C2 FILTER BKL_FLTR R9741 1 10K 2 MIN_NECK_WIDTH=0.075 mm BKL_ISETB3 ISET FB 5% MIN_NECK_WIDTH=0.075 mm 1/16W BKL_FSETB4 FSET MF-LF MIN_NECK_WIDTH=0.075 mm 402 BKL_SCL D3 SCLK MIN_NECK_WIDTH=0.075 mm OUT1 BKL_SDA D4 SDA MIN_NECK_WIDTH=0.075 mm OUT2 BKL_PWM A4 PWM OUT3 1 2 BKL_EN A3 EN OUT4 OUT5 C3 FAULT TP_BKL_FAULT R9731 2 PLACE_SIDE=BOTTOM R9715 301K CRITICALOUT6 100K 1% 1%
R9753 0
93 61 47 41 30 28 26 23 16
VDDIO VLDO
1% 1/16W MF-LF 402
20% 6.3V X5R 603
D1
2
E4
IN
1
10% NO STUFF 6.3V NO STUFF C9740 X5R 402 R9740 10UF 47.0K 1 2 1 2 BKL_FLTR_R
GND_S
87 8
NO STUFF
C9741 1UF
5% 1/16W MF-LF 2402
C4
5% 1/16W MF-LF 2402
PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)
GND_BKL_SGND
XW9710 SM 1
PLACE_NEAR=U9701.E3:10mm 1 2 MIN_LINE_WIDTH=0.5 mm 5% MIN_NECK_WIDTH=0.20 mm 1/16W BOTTOM MF-LF
402
2
BKLT:PROD
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V
R9721 0
PLACE_NEAR=U9701.E2:10mm 1 2 MIN_LINE_WIDTH=0.5 mm 5% MIN_NECK_WIDTH=0.20 mm 1/16W BOTTOM MF-LF
I_LED=369/Riset (EEPROM should set EN_I_RES=1)
MIN_LINE_WIDTH=0.5 mm OUT MIN_NECK_WIDTH=0.20 mm
402
BKLT:PROD
R9722 0
PLACE_NEAR=U9701.E1:10mm 1 2 MIN_LINE_WIDTH=0.5 mm 5% MIN_NECK_WIDTH=0.20 mm 1/16W BOTTOM MF-LF
MIN_LINE_WIDTH=0.5 mm OUT MIN_NECK_WIDTH=0.20 mm
402
A
PART NUMBER
103S0198 103S0198
QTY
3 R 3ES,THIN
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
BKLT:ENG BKLT:ENG
RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM R9717,R9718,R9719 FLIM,1/16W,10.2 OHM,0.1,0402,SM R9720,R9721,R9722
10.2 ohm resistors for current measurement on LED strings.
SYNC_MASTER=K90I_KIRAN SYNC_DATE=06/25/2010 PAGE TITLE
LCD Backlight Driver DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
97 OF 132 SHEET
88 OF 101
1
A
8
7
6
5
4
3
GPU Rail Sequencing
89 87 71
P3V3GPU_EN
89 87 71
GPUVCORE_EN
89 87 81
P1V0GPU_EN
89 87 86
P3V3GPU_EN
29 25 24 23 22 20 19 17 7 6 98 85 82 72 71 70 65 55 45 39 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 61 60 56 53 51 50 49 48 47 89 88 87 84 83 82 79 72 71 98
P3V3GPU_EN
GPUVCORE_EN
GPUVCORE_EN
MAKE_BASE=TRUE 89 87 86
P1V0GPU_EN
OUT
71 87 89
OUT
81 87 89
OUT
86 87 89
P1V0GPU_EN
MAKE_BASE=TRUE
P1V5FB1V8GPU_R_EN 89 87
P1V5FB1V8GPU_R_EN
1
MAKE_BASE=TRUE
87 72 44 23
0
2
P1V5FB_EN
P1V5FB_EN
MAKE_BASE=TRUE
5% 1/16W MF-LF 402
R9932 1
89 86
2
89 71
P1V8GPU_EN 1
0.47UF
67
86 89
IN
P1V8GPU_EN OUT
2
0.1UF
20% 10V 2 CERM 402
8 74LVC2G08GT
ALL_SYS_PWRGD
1
SOT833
A
U9950Y 7 2
CPUIMVP_PGOOD
B
PM_S0_PGOOD
08
8 74LVC2G08GT 5
U9950Y 3 6
71 89
R9962
SOT833
A
B
C9931
SYS_PWROK_R
1
1K
PM_PCH_SYS_PWROK
2
OUT
17 23
5% 1/16W MF-LF 402
08
4
0.47UF
10% 6.3V CERM-X5R 402
2
OUT
IN
0
5% 1/16W MF-LF 402
C9950
4
C9932
1
PLACE_NEAR=U7880.2:7mm
1
R99501
PLACE_NEAR=U1800.p12:7mm MAKE_BASE=TRUE
5% 1/16W MF-LF 402
1
1K
R9931 0
R9963
PP3V3_S5 PP3V3_S0
5% 1/16W MF-LF 402 2
PLACE_NEAR=U9500.27:7mm 89 87
D
NO STUFF
MAKE_BASE=TRUE 89 87 81
1
PCH S0 PWRGD
Whistler GPU requires rails to come up in the following order: 1) GPU_3.3V 2) GPUVcore 3) GPU_1.0V 4) GPU_1.8V;GDDR5 1.5/1.35V
D
2
2
NO STUFF
10% 6.3V CERM-X5R 402
SMC_DELAYED_PWRGD
NO STUFF
44 35
PLACE_NEAR=U1800.L22:5.54mm
NO STUFF
1
R9961 0
5% 1/16W MF-LF 2 402
C
C
PM_PCH_PWROK MAKE_BASE=TRUE
R9960 1
0
OUT
PM_PCH_PWROK
2
17 19 89
17 19 89
5% 1/16W MF-LF 402
EXT GPU PWRGD Pullup
Unused PGOOD signal
PP3V3_S0
98 89 88 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 87 84 83 82 79 72 71 61 60
B
B
R99901 100K
98 61 60 56 53 51 50 49 48 47 23 22 20 19 18 17 16 12 7 6 45 41 40 39 36 35 32 28 26 25 89 88 87 84 83 82 79 72 71
5% 1/16W MF-LF 4022
PP3V3_S0
NO STUFF
PLACE_NEAR=U8000.AH16:7mm
R99911 10K
89 87 86 81 73 8
IN
PM_ALL_GPU_PGOOD
89 87 86 81 73 8
IN
PM_ALL_GPU_PGOOD
89 87 86 81 73 8
IN
PM_ALL_GPU_PGOOD
5% 1/16W MF-LF 402 2 OUT
CPUIMVP_AXG_PGOOD
IN
TP_DDRREG_PGOOD
IN
66 89
TP_P1V5S3RS0_RAMP_DONE
IN
71 89
8 73 81 86 87 89 89 66
PM_ALL_GPU_PGOOD
TP_DDRREG_PGOOD MAKE_BASE=TRUE
MAKE_BASE=TRUE
89 71
TP_P1V5S3RS0_RAMP_DONE MAKE_BASE=TRUE
A
67
SYNC_MASTER=K91_MARY
SYNC_DATE=08/03/2010
PAGE TITLE
Power Sequencing EG/PCH S0 DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
99 OF 132 SHEET
89 OF 101
1
A
8
7
6
5
CPU Signal Constraints
4
3
2
1
CPU Net Properties TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
CPU_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
CPU_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
NET_TYPE PHYSICAL SPACING
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
CPU_27P4S
*
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
7 MIL
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance. TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=STANDARD
?
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=2x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
D
CPU_AGTL
* *
PCIE PCIE PCIE PCIE
DMI_S2N_P<3:0> DMI_S2N_N<3:0> DMI_N2S_P<3:0> DMI_N2S_N<3:0>
FDI_DATA FDI_DATA
PCIE_85D PCIE_85D CPU_50S CPU_50S
PCIE PCIE CPU_AGTL CPU_AGTL
FDI_DATA_P<7:0> FDI_DATA_N<7:0> FDI_FSYNC<1..0> FDI_LSYNC<1..0>
TOP,BOTTOM
CLK_PCIE_90D CLK_PCIE_90D
CLK_PCIE CLK_PCIE
DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N
CPU_VID
*
?
0.457 MM
I125
CPU_PECI PM_SYNC PM_MEM_PWRGD
CPU_50S CPU_50S CPU_50S CPU_50S
CPU_AGTL PCIE CPU_AGTL CPU_AGTL
FDI_INT CPU_PECI PM_SYNC PM_MEM_PWRGD
XDP_CPU_PWRGOOD XDP_BDRESET_L XDP_PRDY_L XDP_PREQ_l
CPU_50S CPU_50S CPU_50S CPU_50S
CPU_ITP CPU_ITP CPU_ITP CPU_ITP
XDP_CPU_PWRGD XDP_DBRESET_L XDP_CPU_PRDY_L XDP_CPU_PREQ_L
CPU_SM_RCOMP CPU_SM_RCOMP CPU_SM_RCOMP CPU_CFG CPU_CFG CPU_CATERR_L
CPU_27P4S CPU_27P4S CPU_27P4S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S
CPU_COMP CPU_COMP CPU_COMP CPU_ITP CPU_ITP CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_8MIL
CPU_SM_RCOMP0 CPU_SM_RCOMP1 CPU_SM_RCOMP2 CPU_CFG<11..0> CPU_CFG<17..16> CPU_CATERR_L CPU_PROC_SEL_L TP_CPU_VTT_SELECT CPU_PROCHOT_L CPU_PWRGD PM_THRMTRIP_L
CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CPU_55S CPU_50S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S
CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CPU_8MIL CPU_AGTL CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP
ITPCPU_CLK100M_P ITPCPU_CLK100M_N ITPXDP_CLK100M_P ITPXDP_CLK100M_N XDP_CPU_CLK100M_P XDP_CPU_CLK100M_N CPU_PSI_L PM_DPRSLPVR CPU_PEG_COMP CPU_PEG_RBIAS CPU_COMP3 CPU_COMP2 CPU_COMP1 CPU_COMP0
CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S
CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP
XDP_CPU_TDI XDP_CPU_TDO XDP_CPU_TMS XDP_CPU_TCK XDP_CPU_TRST_L XDP_BPM_L<3..0> XDP_BPM_L<7..4> XDP_CPURST_L
CPU_55S CPU_50S
CPU_8MIL CPU_AGTL
CPU_VID<6..0> CPUIMVP_IMON
CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE
CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S
CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE
CPU_VCCSENSE_P CPU_VCCSENSE_N CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N
CPU_VCCSENSE CPU_VCCSENSE
CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S
CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE
CPU_AXG_SENSE_P CPU_AXG_SENSE_N CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N
DMI_CLK100M
TABLE_SPACING_RULE_ITEM
CPU_COMP
*
20 MIL
?
CPU_ITP
*
=2:1_SPACING
?
CPU_VCCSENSE
*
25 MIL
?
6 9 17 6 9 17 9 17 9 17
6 9 17 6 9 17 6 9 17
D
6 9 17
TABLE_SPACING_RULE_ITEM
?
8 MIL
PCIE_85D PCIE_85D PCIE_85D PCIE_85D
TABLE_SPACING_RULE_ITEM
CPU_AGTL TABLE_SPACING_RULE_ITEM
CPU_8MIL
DMI_S2N DMI_S2N DMI_N2S DMI_N2S
I126
10 16 10 16
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
Most CPU signals with impedance requirements are 50-ohm single-ended. Some signals require 27.4-ohm single-ended impedance. SOURCE: Calpella SFF DG (DG-407364_v1.5), Section 2.8
PCI-Express TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
6 9 17 10 19 44 10 17 10 17 29
23 10 23 25 10 23 10 23
TABLE_PHYSICAL_RULE_ITEM
PCIE_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
CLK_PCIE_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
=3X_DIELECTRIC
?
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4X_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
PCIE
*
I124
TABLE_SPACING_RULE_ITEM
PCIE
TOP,BOTTOM
TABLE_SPACING_RULE_ITEM
CLK_PCIE
*
20 MIL
I115
?
CPU_PROCHOT_L CPU_PWRGD PM_THRMTRIP_L
C XDP_CLK_CPU XDP_CLK_CPU XDP_CLK_PCH XDP_CLK_PCH XDP_CLK_ITP XDP_CLK_ITP PM_DPRSLPVR
CPU_COMP CPU_COMP CPU_COMP CPU_COMP XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM XDP_BPM_L
(FSB_CPURST_L)
9 23 9 23 10 10 17 8 10 45 67 10 19 23 10 19
C 10 16 10 16 16 23 16 23 23 23
9
10 23 10 23 10 23 10 23 10 23 10 23 10 23 23
8
B
B
I120 I121 I122 I123
PM_DPRSLPVR
PEG_R2D PEG_D2R
A
CPU_55S CPU_50S CPU_50S CPU_50S
CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL
GFX_VID<6..0> GFX_DPRSLPVR GFX_VR_EN GFXIMVP_IMON
PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D CPU_50S CPU_50S CPU_50S
PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE CPU_VID CPU_VID CPU_VID
PEG_R2D_P<7..0> PEG_R2D_N<7..0> PEG_R2D_C_P<7..0> PEG_R2D_C_N<7..0> PEG_D2R_P<7..0> PEG_D2R_N<7..0> PEG_D2R_C_P<7..0> PEG_D2R_C_N<7..0> CPU_VIDSOUT CPU_VIDSCLK CPU_VIDALERT_L
12 67 12 67 12 69 12 69
12 67 12 67 12 12 12 12
8
73 73 8 73 8 73 8 73 8 73 73 73 12 67 12 67
SYNC_MASTER=K92_MLB
SYNC_DATE=08/09/2010
PAGE TITLE
CPU Constraints
12 67
DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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90 OF 101
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8
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Memory Bus Constraints
4
3
2
1
Memory Net Properties TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MEM_37S
*
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=STANDARD
=STANDARD
MEM_40S
*
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
NET_TYPE PHYSICAL SPACING
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MEM_A_CLK MEM_A_CLK
MEM_72D MEM_72D
MEM_CLK MEM_CLK
MEM_A_CLK_P<5..0> MEM_A_CLK_N<5..0>
MEM_A_CNTL MEM_A_CNTL MEM_A_CNTL
MEM_37S MEM_37S MEM_37S
MEM_CTRL MEM_CTRL MEM_CTRL
MEM_A_CKE<3..0> MEM_A_CS_L<3..0> MEM_A_ODT<3..0>
MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD
MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S
MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD
MEM_A_A<15..0> MEM_A_BA<2..0> MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L
MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7
MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S
MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA
MEM_A_DQ<7..0> MEM_A_DQ<15..8> MEM_A_DQ<23..16> MEM_A_DQ<31..24> MEM_A_DQ<39..32> MEM_A_DQ<47..40> MEM_A_DQ<55..48> MEM_A_DQ<63..56>
MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7
MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D
MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS
MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7>
MEM_B_CLK MEM_B_CLK
MEM_72D MEM_72D
MEM_CLK MEM_CLK
MEM_B_CLK_P<5..0> MEM_B_CLK_N<5..0>
MEM_B_CNTL MEM_B_CNTL MEM_B_CNTL
MEM_37S MEM_37S MEM_37S
MEM_CTRL MEM_CTRL MEM_CTRL
MEM_B_CKE<3..0> MEM_B_CS_L<3..0> MEM_B_ODT<3..0>
MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD
MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S
MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD
MEM_B_A<15..0> MEM_B_BA<2..0> MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L
MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7
MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S
MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA
MEM_B_DQ<7..0> MEM_B_DQ<15..8> MEM_B_DQ<23..16> MEM_B_DQ<31..24> MEM_B_DQ<39..32> MEM_B_DQ<47..40> MEM_B_DQ<55..48> MEM_B_DQ<63..56>
MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7
MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D
MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS
MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7>
6 11 26 6 11 26
TABLE_PHYSICAL_RULE_ITEM
MEM_72D
*
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
MEM_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
6 11 26 6 11 26 6 11 26
TABLE_PHYSICAL_RULE_ITEM
D
MEM_85D
*
SPACING_RULE_SET
LAYER
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT TABLE_SPACING_RULE_ITEM
MEM_CLK2MEM
*
?
=4:1_SPACING
6 11 26 6 11 26
D
6 11 26 6 11 26 6 11 26
TABLE_SPACING_RULE_ITEM
MEM_CTRL2CTRL
*
=3:1_SPACING
?
MEM_CTRL2MEM
*
=2.5:1_SPACING
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MEM_CMD2CMD
*
=1.5:1_SPACING
? TABLE_SPACING_RULE_ITEM
MEM_CMD2MEM
*
?
=3:1_SPACING
TABLE_SPACING_RULE_ITEM
MEM_DATA2DATA
*
=1.5:1_SPACING
?
MEM_DATA2MEM
*
=3:1_SPACING
?
TABLE_SPACING_RULE_ITEM
6 11 27 6 11 27 6 11 27 6 11 27 6 11 26 27 6 11 27 6 11 27 6 11 27
TABLE_SPACING_RULE_ITEM
MEM_DQS2MEM
*
=3:1_SPACING
?
MEM_2OTHER
*
25 MILS
?
TABLE_SPACING_RULE_ITEM
Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CMD
MEM_CLK
*
MEM_CMD2MEM
MEM_CMD
MEM_CTRL
*
MEM_CMD2MEM
MEM_CMD
MEM_CMD
*
MEM_CMD2CMD
MEM_CMD
MEM_DATA
*
MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CLK
*
MEM_CLK2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CTRL
*
MEM_CLK2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CMD
*
MEM_CLK2MEM
MEM_CLK
MEM_DATA
*
MEM_CLK2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_DQS
*
MEM_CLK2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
C
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
MEM_DQS
*
MEM_CMD2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_CLK
*
MEM_CTRL2MEM
MEM_CTRL
MEM_CTRL
*
MEM_CTRL2CTRL
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
MEM_CLK
*
MEM_DATA2MEM
MEM_DATA
MEM_CTRL
*
MEM_DATA2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_CMD
*
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
MEM_CMD
*
MEM_DATA2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_DATA
*
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
MEM_DATA
*
MEM_DATA2DATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_DQS
*
MEM_CTRL2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DQS
MEM_CLK
*
MEM_DQS2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
MEM_DQS
*
MEM_DATA2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
*
MEM_DQS2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_CMD
*
MEM_DQS2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_DATA
*
MEM_DQS2MEM
MEM_DQS
MEM_DQS
*
MEM_DQS2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
*
*
MEM_2OTHER
MEM_DQS
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
Need to support MEM_*-style wildcards!
DDR3:
B
6 11 27 6 11 27 6 11 27 6 11 27 6 11 27
C
6 11 27 6 11 27 6 11 27 6 11 27 6 11 27 6 11 27 6 11 26 27 6 11 26 27 6 11 27 6 11 27
6 11 28 6 11 28
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
6 11 27
DQ/DM signals should be matched within 0.508mm of associated DQS pair. DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement. DQS to clock matching should be within [CLK-12.7mm] and [CLK+25.4mm]. CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm. CONTROL signals should be matched within [CLK-12.7mm] to [CLK+0.0mm] of CLK pairs. A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs. DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric. Maximum length of any signal from die pad to SODIMM pad is 139.7mm, from procesor ball to SODIMM pad is 114.3mm.
6 11 28 6 11 28 6 11 28
6 11 28 6 11 28 6 11 28 6 11 28 6 11 28
6 11 27 6 11 27 6 11 27 6 11 27
B
6 11 27 28 6 11 27 6 11 27 6 11 27
SOURCE: Calpella SFF Platform DG, Rev 1.5 (#407364), Section 2.2
A
6 11 27 6 11 27 6 11 27 6 11 27 6 11 27 6 11 27 6 11 27 6 11 27 6 11 27 6 11 27 6 11 27 6 11 27 6 11 27 28 6 11 27 28 6 11 27
SYNC_MASTER=K18_MLB
SYNC_DATE=04/27/2010
PAGE TITLE
Memory Constraints
6 11 27
DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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Digital Video Signal Constraints LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
ELECTRICAL_CONSTRAINT_SET
TABLE_PHYSICAL_RULE_ITEM
DP_85D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
LVDS_85D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
3
2
1
PCH Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
4 NET_TYPE PHYSICAL SPACING
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
DISPLAYPORT
ISL3,ISL4,ISL9,ISL10
=4:1_SPACING
?
LVDS
ISL3,ISL4,ISL9,ISL10
=4:1_SPACING
?
DISPLAYPORT
TOP,BOTTOM
=4:1_SPACING
?
LVDS
TOP,BOTTOM
=4:1_SPACING
?
TABLE_SPACING_RULE_ITEM
D
DP_AUX_CH DP_AUX_CH
DP_85D DP_85D
DISPLAYPORT DISPLAYPORT
DP_IG_AUX_CH_P DP_IG_AUX_CH_N
LVDS_IG_A_CLK LVDS_IG_A_CLK LVDS_IG_A_DATA LVDS_IG_A_DATA LVDS_IG_A_DATA3 LVDS_IG_A_DATA3
LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D
LVDS LVDS LVDS LVDS LVDS LVDS
LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P<2..0> LVDS_IG_A_DATA_N<2..0> NC_LVDS_IG_A_DATAP<3> NC_LVDS_IG_A_DATAN<3>
LVDS_IG_B_DATA LVDS_IG_B_DATA SATA_HDD_R2D
LVDS_85D LVDS_85D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D
LVDS LVDS SATA SATA SATA SATA SATA SATA
LVDS_IG_B_DATA_P<2..0> LVDS_IG_B_DATA_N<2..0> SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_R2D_UF_P SATA_HDD_R2D_UF_N
SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D
SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA
SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N
TABLE_SPACING_RULE_ITEM
SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193
SATA Interface Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SATA_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
SATA_HDD_R2D
TABLE_PHYSICAL_RULE_ITEM
SATA_37SE
*
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
SATA_50SE
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
I218
TABLE_PHYSICAL_RULE_ITEM
SATA_HDD_R2D
I219
SATA_HDD_D2R TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
SATA
ISL3,ISL4,ISL9,ISL10
=5:1_SPACING
?
*
15 MIL
?
SATA_HDD_D2R
WEIGHT
TABLE_SPACING_RULE_ITEM
SATA_ICOMP
8 17 83 8 17 83
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
SATA
TOP,BOTTOM
?
=5:1_SPACING
SATA_ODD_R2D
TABLE_SPACING_RULE_ITEM
SATA_ODD_R2D
SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193
SATA_ODD_D2R SATA_ODD_D2R
18 87 18 87 18 87
D
18 87 8 18 8 18
18 87 18 87 16 41 16 41 6 41 6 41 41 41
16 41 16 41 6 41 6 41 16 41 16 41 6 41 6 41 16 41 16 41 6 41 6 41
C
C USB 2.0 Interface Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
PCH_USB_RBIAS
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
USB_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
I213
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LINE-TO-LINE SPACING
WEIGHT
USB
ISL3,ISL4,ISL9,ISL10
LAYER
=4:1_SPACING
?
USB_RBIAS
*
15 MIL
?
PCH_SATA3_ICOMP PCH_SATA_ICOMP USB_HUB1_UP
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4:1_SPACING
?
TABLE_SPACING_RULE_ITEM
USB_HUB2_UP
TABLE_SPACING_RULE_ITEM
USB
TOP,BOTTOM
USB_EXTA
TABLE_SPACING_RULE_ITEM
USB_EXTB USB_EXTC
SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193
USB_CAMERA USB_BT USB_TPAD USB_IR
B I214
PCH_USB_RBIAS USB_T29A
I215
SATA_50SE SATA_37SE USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D PCH_USB_RBIAS USB_85D USB_85D
SATA_ICOMP SATA_ICOMP USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB_RBIAS USB USB
PCH_SATA3COMP PCH_SATAICOMP USB_HUB1_UP_P USB_HUB1_UP_N USB_HUB2_UP_P USB_HUB2_UP_N USB_EXTA_P USB_EXTA_N USB_EXTB_P USB_EXTB_N USB_EXTC_P USB_EXTC_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N USB_BT_P USB_BT_N USB_TPAD_P USB_TPAD_N USB_IR_P USB_IR_N PCH_USB_RBIAS USB_T29A_P USB_T29A_N
A
16 16 18 24 18 24 18 24 18 24 24 42 24 42 24 42 24 42 8 24 8 24 6 31 6 31 24 31 24 31 24 52 24 52 24 43 24 43
B
18 8 24 8 24
SYNC_MASTER=K92_MLB
SYNC_DATE=08/09/2010
PAGE TITLE
PCH Constraints 1 DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
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102 OF 132 SHEET
92 OF 101
1
A
8
7
6
5
LPC Bus Constraints LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
ELECTRICAL_CONSTRAINT_SET
TABLE_PHYSICAL_RULE_ITEM
LPC_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
CLK_LPC_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
3
2
1
PCH Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
4 NET_TYPE PHYSICAL SPACING
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
6 MIL
?
TABLE_SPACING_RULE_ITEM
LPC
*
LPC_AD LPC_FRAME_L LPC_RESET_L
LPC_50S LPC_50S LPC_50S
LPC LPC LPC
LPC_AD<3..0> LPC_FRAME_L LPCPLUS_RESET_L
PCH_LPC_CLK0
CLK_LPC_50S CLK_LPC_50S CLK_LPC_50S
CLK_LPC CLK_LPC CLK_LPC
LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS
SMBUS_PCH_CLK SMBUS_PCH_DATA SMBUS_PCH_0_CLK SMBUS_PCH_0_DATA SMBUS_PCH_1_CLK SMBUS_PCH_1_DATA
SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S
SMB SMB SMB SMB SMB SMB
SMBUS_PCH_CLK SMBUS_PCH_DATA SML_PCH_0_CLK SML_PCH_0_DATA SML_PCH_1_CLK SML_PCH_1_DATA
HDA_BIT_CLK
HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S
HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA
HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 AUD_SDI_R HDA_SDOUT HDA_SDOUT_R
SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S
SPI SPI SPI SPI SPI SPI SPI
SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_CS0_R_L SPI_CS0_L
PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D
PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE
PCIE_ENET_R2D_P PCIE_ENET_R2D_N PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N PCIE_ENET_D2R_C_P PCIE_ENET_D2R_C_N
PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D
PCIE PCIE PCIE PCIE PCIE PCIE
PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_AP_D2R_P PCIE_AP_D2R_N
PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D
PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE
PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N
CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CPU_50S CPU_50S
CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE
PCIE_CLK100M_PCH_P PCIE_CLK100M_PCH_N PCIE_CLK100M_T29_P PCIE_CLK100M_T29_N PCH_CLK96M_DOT_P PCH_CLK96M_DOT_N PCH_CLK100M_SATA_P PCH_CLK100M_SATA_N PCH_CLK14P3M_REFCLK PCH_CLK33M_PCIIN
CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D
CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE
PEG_CLK100M_P 16 PEG_CLK100M_N 16 PCIE_CLK100M_ENET_P 16 PCIE_CLK100M_ENET_N 16 PCIE_CLK100M_AP_P 16 PCIE_CLK100M_AP_N 16 PCIE_CLK100M_FW_P 16 PCIE_CLK100M_FW_N 16 NC_PCIE_CLK100M_EXCARD_P NC_PCIE_CLK100M_EXCARD_N
PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D
PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE
PCIE_T29_R2D_C_P<3..0> PCIE_T29_R2D_C_N<3..0> PCIE_T29_R2D_P<3..0> PCIE_T29_R2D_N<3..0> PCIE_T29_D2R_P<3..0> PCIE_T29_D2R_N<3..0> PCIE_T29_D2R_C_P<3..0> PCIE_T29_D2R_C_N<3..0>
TABLE_SPACING_RULE_ITEM
CLK_LPC
D
*
?
8 MIL
SMBus Interface Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
SMB_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
HDA_SYNC
TABLE_SPACING_RULE_ITEM
SMB
*
=2x_DIELECTRIC
?
HDA_RST_L
HD Audio Interface Constraints
HDA_SDIN0 TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
HDA_SDOUT
TABLE_PHYSICAL_RULE_ITEM
HDA_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
6 16 44 46 87 6 16 44 46 87 6 25 46 87
18 25 25 44 6 25 46
D
16 23 26 28 30 41 47 61 88 16 23 26 28 30 41 47 61 88 16 47 16 47 16 47 16 47
16 56 16 16 56 16 16 16 56 16 56 56 16 56 16
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=2x_DIELECTRIC
?
SPI_CLK
TABLE_SPACING_RULE_ITEM
HDA
*
SPI_MOSI
SIO Signal Constraints
SPI_MISO SPI_CS0 TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
16 46 46 16 46 46 16 46 16 46 46
TABLE_PHYSICAL_RULE_ITEM
C
CLK_SLOW_55S
*
SPACING_RULE_SET
LAYER
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD PCIE_ENET_R2D
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT TABLE_SPACING_RULE_ITEM
CLK_SLOW
*
?
8 MIL
PCIE_ENET_D2R
SPI Interface Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SPI_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
PCIE_AP_R2D PCIE_AP_D2R
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
36
C
36 16 36 16 36 16 36 16 36 36 36
6 31 6 31 16 31 16 31 6 16 31 6 16 31
TABLE_SPACING_RULE_ITEM
SPI
*
8 MIL
?
PCIE_FW_R2D PCIE_FW_D2R
I253
B
I254 I262
PCIE_CLK100M_T29_
I261 I255 I257 I256 I259 I258 I260
PCIE_CLK100M PCIE_CLK100M_ENET PCIE_CLK100M_AP PCIE_CLK100M_FW PCIE_CLK100M_EXCARD
I263 I264 I265 I267
A
I266 I268 I270 I269
PCIE_T29_R2D PCIE_T29_R2D PCIE_T29_R2D PCIE_T29_R2D PCIE_T29_D2R PCIE_T29_D2R PCIE_T29_D2R PCIE_T29_D2R
38 38 16 38 16 38 16 38 16 38 38 38
16
B
16 16 33 16 33 16 16 16 16 16 16 25
73 73 36 36 31 31 38 38 8 16 8 16
8 9 33 8 9 33 33 33 8 9 33 8 9 33
SYNC_MASTER=K92_MLB
SYNC_DATE=08/09/2010
PAGE TITLE
PCH Constraints 2
33 33
DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
103 OF 132 SHEET
93 OF 101
1
A
8
7
6
5
CAESAR IV (Ethernet) Constraints
4
3
2
1
Ethernet Net Properties TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
ENET_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
NET_TYPE ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
ENET_50S
ENET_3X
ENET_50S
ENET_3X
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=3:1_SPACING
?
ENET_50S
ENET_3X
ENET_100D
ENET_MDI
ENET_100D
ENET_MDI
CR_DATA_A0
ENET_50S
ENET_CR
I167
CR_DATA_A0
ENET_50S
ENET_CR
I168
CR_CLK
ENET_50S
ENET_CR
I169
CR_DATA_A0
ENET_50S
ENET_CR
I170
CR_DATA_A0
ENET_50S
ENET_CR
I171
CR_CLK
ENET_50S
ENET_CR
I172
CR_CLK
ENET_50S
ENET_CR
BCM5764_CLK25M_XTALI BCM5764_CLK25M_XTALO ENET_RESET_L
32 36
TABLE_SPACING_RULE_ITEM
ENET_3X
*
ENET_MDI
ENET_MDI_P<3..0> ENET_MDI_N<3..0>
36 37 36 37
SOURCE: Broadcom 5764-DS04-RDS Page 38 I166
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
D
LAYER
LINE-TO-LINE SPACING
WEIGHT
=3X_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
*
ENET_CR
SOURCE: Attila Farkas Email - 8/2/10
CAESAR IV (Ethernet PHY) Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
ENET_100D
*
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SDCONN_DATA_R<7..0> SDCONN_CMD_R SDCONN_CLK_R SDCONN_DATA<7..0> SDCONN_CMD SDCONN_CLK SDCONN_CLK_R_L 32
32
D
32 32 36 32 36 32 36
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
0.6 MM
?
TABLE_SPACING_RULE_ITEM
ENET_MDI
*
SOURCE: Broadcom 5764-DS04-RDS Page 38
C
FireWire Interface Constraints
C
FireWire Net Properties TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
FW_110D
*
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
NET_TYPE ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
I158
FW_P0_TPA
FW_110D
FW_TP
I159
FW_P0_TPA
FW_110D
FW_TP
I160
FW_P0_TPB
FW_110D
FW_TP
I161
FW_P0_TPB
FW_110D
FW_TP
I162
FW_P1_TPA
FW_110D
FW_TP
I163
FW_P1_TPA
FW_110D
FW_TP
I164
FW_P1_TPB
FW_110D
FW_TP
I165
FW_P1_TPB
FW_110D
FW_TP
TABLE_SPACING_RULE_ITEM
FW_TP
*
=3:1_SPACING
?
NC_FW0_TPAP NC_FW0_TPAN NC_FW0_TPBP NC_FW0_TPBN FW_PORT1_TPA_P FW_PORT1_TPA_N FW_PORT1_TPB_P FW_PORT1_TPB_N
6 38 40 38 40 6 38 40 6 38 40 38 40 38 40 38 40 38 40
Port 2 Not Used
B
B
A
SYNC_MASTER=K91_ERIC
SYNC_DATE=08/03/2010
PAGE TITLE
Ethernet/FW Constraints DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
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4
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94 OF 101
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8
7
6
5
DisplayPort Signal Constraints
4 ELECTRICAL_CONSTRAINT_SET
T29 I2C Signal Constraints
T29_R2D0 T29_R2D0 T29_R2D1 T29_R2D1
TABLE_PHYSICAL_RULE_HEAD
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
T29_I2C_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=55_OHM_SE
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
T29_D2R0 T29_D2R0 T29_D2R1 T29_D2R1
TABLE_SPACING_RULE_ITEM
T29_I2C
*
?
=2x_DIELECTRIC
2
1
T29/DP Net Properties
NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.
PHYSICAL_RULE_SET
3
D T29 SPI Signal Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
T29_SPI_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
NET_TYPE PHYSICAL SPACING T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP_100D
T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP
T29_R2D_P<0> T29_R2D_N<0> T29_R2D_P<1> T29_R2D_N<1> T29_R2D_C_F_P<1..0> T29_R2D_C_F_N<1..0> T29_D2R_C_P<0> T29_D2R_C_N<0> T29_D2R_C_P<1> T29_D2R_C_N<1> T29DPA_D2R1_AUXCH_P T29DPA_D2R1_AUXCH_N
T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D
T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP
DP_SDRVA_ML_C_P<3..0> DP_SDRVA_ML_C_N<3..0> DP_SDRVA_ML_R_P<3..0> DP_SDRVA_ML_R_N<3..0> DP_SDRVA_ML_P<2..0:2> DP_SDRVA_ML_N<2..0:2> DP_SDRVA_ML_P<3..1:2> DP_SDRVA_ML_N<3..1:2> DP_SDRVA_AUXCH_P DP_SDRVA_AUXCH_N DP_SDRVA_AUXCH_C_P DP_SDRVA_AUXCH_C_N
T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D
T29DP T29DP T29DP T29DP T29DP T29DP
T29DPA_ML_P<3..0> T29DPA_ML_N<3..0> T29DPA_ML_C_P<3..0> T29DPA_ML_C_N<3..0> DP_A_EXT_AUXCH_P DP_A_EXT_AUXCH_N
T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP_100D
T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP
T29_R2D_P<2> T29_R2D_N<2> T29_R2D_P<3> T29_R2D_N<3> T29_R2D_C_F_P<3..2> T29_R2D_C_F_N<3..2> T29_D2R_C_P<2> T29_D2R_C_N<2> T29_D2R_C_P<3> T29_D2R_C_N<3> T29DPB_D2R3_AUXCH_P T29DPB_D2R3_AUXCH_N
T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D
T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP
DP_SDRVB_ML_C_P<3..0> DP_SDRVB_ML_C_N<3..0> DP_SDRVB_ML_R_P<3..0> DP_SDRVB_ML_R_N<3..0> DP_SDRVB_ML_P<2..0:2> DP_SDRVB_ML_N<2..0:2> DP_SDRVB_ML_P<3..1:2> DP_SDRVB_ML_N<3..1:2> DP_SDRVB_AUXCH_P DP_SDRVB_AUXCH_N DP_SDRVB_AUXCH_C_P DP_SDRVB_AUXCH_C_N
T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D
T29DP T29DP T29DP T29DP T29DP T29DP
T29DPB_ML_P<3..0> T29DPB_ML_N<3..0> T29DPB_ML_C_P<3..0> T29DPB_ML_C_N<3..0> DP_B_EXT_AUXCH_P DP_B_EXT_AUXCH_N
6 84 6 84 6 84 6 84 84 84 6 84 85 6 84 85
D
6 84 85 6 84 85 6 85 6 85
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT TABLE_SPACING_RULE_ITEM
T29_SPI
*
?
=2x_DIELECTRIC
DP_SDRVA_ML_EVEN DP_SDRVA_ML_EVEN DP_SDRVA_ML_ODD DP_SDRVA_ML_ODD DP_SDRVA_AUXCH DP_SDRVA_AUXCH
T29/DP Connector Signal Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
T29DP_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
T29DP_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=5x_DIELECTRIC
?
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=7x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
T29DP
*
TABLE_SPACING_RULE_ITEM
T29DP
TOP,BOTTOM
SOURCE: Bill Cornelius’s T29 Routing Notes
T29_R2D2 T29_R2D2 T29_R2D3 T29_R2D3
C
T29_D2R2 T29_D2R2 T29_D2R3 T29_D2R3
DP_SDRVB_ML_EVEN DP_SDRVB_ML_EVEN DP_SDRVB_ML_ODD DP_SDRVB_ML_ODD DP_SDRVB_AUXCH DP_SDRVB_AUXCH
B T29 IC Net Properties ELECTRICAL_CONSTRAINT_SET
DP_T29SNK0_ML DP_T29SNK0_ML
DP_T29SNK0_AUXCH DP_T29SNK0_AUXCH
DP_T29SNK1_ML DP_T29SNK1_ML
DP_T29SNK1_AUXCH DP_T29SNK1_AUXCH
A T29_SPI_CLK T29_SPI_MOSI T29_SPI_MISO T29_SPI_CS_L
8
NET_TYPE PHYSICAL SPACING DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D
DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT
DP_T29SNK0_ML_C_P<3..0> DP_T29SNK0_ML_C_N<3..0> DP_T29SNK0_ML_P<3..0> DP_T29SNK0_ML_N<3..0> DP_T29SNK0_AUXCH_C_P DP_T29SNK0_AUXCH_C_N DP_T29SNK0_AUXCH_P DP_T29SNK0_AUXCH_N
DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D
DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT
DP_T29SNK1_ML_C_P<3..0> DP_T29SNK1_ML_C_N<3..0> DP_T29SNK1_ML_P<3..0> DP_T29SNK1_ML_N<3..0> DP_T29SNK1_AUXCH_C_P DP_T29SNK1_AUXCH_C_N DP_T29SNK1_AUXCH_P DP_T29SNK1_AUXCH_N
DP_85D DP_85D DP_85D DP_85D
DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT
DP_T29SRC_ML_C_P<3..0> DP_T29SRC_ML_C_N<3..0> DP_T29SRC_AUXCH_C_P DP_T29SRC_AUXCH_C_N
T29_I2C_55S T29_I2C_55S
T29_I2C T29_I2C
I2C_T29_SCL I2C_T29_SDA
T29_SPI_55S T29_SPI_55S T29_SPI_55S T29_SPI_55S
T29_SPI T29_SPI T29_SPI T29_SPI
T29_SPI_CLK T29_SPI_MOSI T29_SPI_MISO T29_SPI_CS_L
T29DP_80D T29DP_80D T29DP_100D T29DP_100D
T29DP T29DP T29DP T29DP
T29_R2D_C_P<3..0> T29_R2D_C_N<3..0> T29_D2R_P<3..0> T29_D2R_N<3..0>
7
6 84 6 84 84 84 6 84 95 6 84 95 84 84 84 84 84 84
6 84 85 6 84 85 84 85 84 85 84 85 84 85
C
Only used on dual-port hosts. 95 95
B
6 33 78 6 33 78 6 33 6 33 6 33 78 6 33 78 6 33 6 33
6 33 78 6 33 78 6 33 6 33 6 33 78 6 33 78 6 33 6 33
Only used on hosts supporting T29 video-in
33 47 84
SYNC_MASTER=T29_REF
33 47 84
SYNC_DATE=10/16/2010
PAGE TITLE
T29 Constraints
33
DRAWING NUMBER
Apple Inc.
33 33
SIZE
D
33
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
6 8 33 84
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
6 8 33 84 6 8 33 84 6 8 33 84
6
5
4
3
2
PAGE
105 OF 132 SHEET
95 OF 101
1
A
8
7
6
5
4
3
2
1
SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
1TO1_DIFFPAIR
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
ELECTRICAL_CONSTRAINT_SET
NET_TYPE PHYSICAL SPACING
TABLE_PHYSICAL_RULE_ITEM
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
D
SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S
SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
6 31 44 47 53 54 6 31 44 47 53 54 44 47 50 44 47 50 6 31 44 47 50 79 6 31 44 47 50 79 6 44 47 62 63 6 44 47 62 63
D
44 47 100 44 47 100
SMBus Charger Net Properties ELECTRICAL_CONSTRAINT_SET
NET_TYPE PHYSICAL SPACING
CHGR_CSI
1TO1_DIFFPAIR 1TO1_DIFFPAIR
CHGR_CSI_P CHGR_CSI_N
CHGR_CSO
1TO1_DIFFPAIR 1TO1_DIFFPAIR
CHGR_CSO_P CHGR_CSO_N
63 63
63 63
C
C
B
B
A
SYNC_MASTER=K18_MLB
SYNC_DATE=04/27/2010
PAGE TITLE
SMC Constraints DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
106 OF 132 SHEET
96 OF 101
1
A
8
7
6
5
GDDR5 Frame Buffer Signal Constraints
4
3
GDDR5 FB A Net Properties
2
1
GDDR5 FB B Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
GDDR5_45R50SE
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
12.7 MM
=STANDARD
=STANDARD
GDDR5_45SE
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
GDDR5_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
GDDR5_CLK
*
=5x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
D
GDDR5_CMD
*
=2x_DIELECTRIC
? TABLE_SPACING_RULE_ITEM
GDDR5_DATA
*
=3x_DIELECTRIC
? TABLE_SPACING_RULE_ITEM
GDDR5_EDC
*
=7x_DIELECTRIC
?
Digital Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
DP_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
LVDS_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
DISPLAYPORT
*
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
DISPLAYPORT
TOP,BOTTOM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LVDS
*
=3x_DIELECTRIC
I293 I294 I295
TABLE_SPACING_RULE_ITEM
?
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
?
I296 I297
LVDS intra-pair matching should be 0.127 mm. Pairs should be within 0.508mm of entire channel. DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. DIsplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm. Max length of LVDS/DisplayPort/TMDS traces: 13 inches. SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.
I298
Max Length 241.3mm.
I299 I300 I301 I302 I303 I304
C
FB_A0_CLK FB_A0_CLK FB_A1_CLK FB_A1_CLK FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_EDC0 FB_A0_EDC1 FB_A0_EDC2 FB_A0_EDC3 FB_A1_EDC0 FB_A1_EDC1 FB_A1_EDC2 FB_A1_EDC3 FB_A0_DBI_L0 FB_A0_DBI_L1 FB_A0_DBI_L2 FB_A0_DBI_L3 FB_A1_DBI_L0 FB_A1_DBI_L1 FB_A1_DBI_L2 FB_A1_DBI_L3 FB_A0_WCLK0 FB_A0_WCLK0 FB_A0_WCLK1 FB_A0_WCLK1 FB_A1_WCLK0 FB_A1_WCLK0 FB_A1_WCLK1 FB_A1_WCLK1 FB_A0_DQ_BYTE0 FB_A0_DQ_BYTE1 FB_A0_DQ_BYTE2 FB_A0_DQ_BYTE3 FB_A1_DQ_BYTE0 FB_A1_DQ_BYTE1 FB_A1_DQ_BYTE2 FB_A1_DQ_BYTE3 FB_AB_RESET
PHYSICAL
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
SPACING
GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45R50SE
GDDR5_CLK GDDR5_CLK GDDR5_CLK GDDR5_CLK GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_CMD
FB_A0_CLK_P FB_A0_CLK_N FB_A1_CLK_P FB_A1_CLK_N FB_A0_A<8..0> FB_A1_A<8..0> FB_A0_ABI_L FB_A1_ABI_L FB_A0_RAS_L FB_A1_RAS_L FB_A0_CAS_L FB_A1_CAS_L FB_A0_WE_L FB_A1_WE_L FB_A0_CKE_L FB_A1_CKE_L FB_A0_CS_L FB_A1_CS_L FB_A0_EDC<0> FB_A0_EDC<1> FB_A0_EDC<2> FB_A0_EDC<3> FB_A1_EDC<0> FB_A1_EDC<1> FB_A1_EDC<2> FB_A1_EDC<3> FB_A0_DBI_L<0> FB_A0_DBI_L<1> FB_A0_DBI_L<2> FB_A0_DBI_L<3> FB_A1_DBI_L<0> FB_A1_DBI_L<1> FB_A1_DBI_L<2> FB_A1_DBI_L<3> FB_A0_WCLK_P<0> FB_A0_WCLK_N<0> FB_A0_WCLK_P<1> FB_A0_WCLK_N<1> FB_A1_WCLK_P<0> FB_A1_WCLK_N<0> FB_A1_WCLK_P<1> FB_A1_WCLK_N<1> FB_A0_DQ<7..0> FB_A0_DQ<15..8> FB_A0_DQ<23..16> FB_A0_DQ<31..24> FB_A1_DQ<7..0> FB_A1_DQ<15..8> FB_A1_DQ<23..16> FB_A1_DQ<31..24> FB_RESET_L
75 76 75 76 75 76 75 76 6 75 76 6 75 76 6 75 76 6 75 76 75 76 75 76 75 76 75 76 75 76 75 76 75 76 75 76 75 76 75 76 6 75 76 6 75 76
I305
6 75 76
I306
6 75 76
I307
6 75 76
I310
6 75 76
I309
6 75 76
I308
6 75 76 6 75 76 6 75 76
I311
6 75 76
I312
6 75 76
I313
6 75 76
I316
6 75 76
I315
6 75 76
I314
6 75 76 6 75 76 6 75 76 6 75 76 6 75 76 6 75 76 6 75 76 6 75 76 6 75 76 6 75 76 6 75 76 6 75 76 6 75 76 6 75 76 6 75 76 6 75 76 6 75 76
FB_B0_CLK FB_B0_CLK FB_B1_CLK FB_B1_CLK FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_EDC0 FB_B0_EDC1 FB_B0_EDC2 FB_B0_EDC3 FB_B1_EDC0 FB_B1_EDC1 FB_B1_EDC2 FB_B1_EDC3 FB_B0_DBI_L0 FB_B0_DBI_L1 FB_B0_DBI_L2 FB_B0_DBI_L3 FB_B1_DBI_L0 FB_B1_DBI_L1 FB_B1_DBI_L2 FB_B1_DBI_L3 FB_B0_WCLK0 FB_B0_WCLK0 FB_B0_WCLK1 FB_B0_WCLK1 FB_B1_WCLK0 FB_B1_WCLK0 FB_B1_WCLK1 FB_B1_WCLK1 FB_B0_DQ_BYTE0 FB_B0_DQ_BYTE1 FB_B0_DQ_BYTE2 FB_B0_DQ_BYTE3 FB_B1_DQ_BYTE0 FB_B1_DQ_BYTE1 FB_B1_DQ_BYTE2 FB_B1_DQ_BYTE3
PHYSICAL
GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE
LVDS_A_CLK LVDS_A_CLK LVDS_A_DATA LVDS_A_DATA LVDS_B_CLK LVDS_B_CLK LVDS_B_DATA LVDS_B_DATA
75 77 75 77 75 77 75 77 6 75 77 6 75 77 6 75 77 6 75 77
D
75 77 75 77 75 77 75 77 75 77 75 77 75 77 75 77 75 77 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77
C
6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77 6 75 77
Whistler Net Properties NET_TYPE
B
FB_B0_CLK_P FB_B0_CLK_N FB_B1_CLK_P FB_B1_CLK_N FB_B0_A<8..0> FB_B1_A<8..0> FB_B0_ABI_L FB_B1_ABI_L FB_B0_RAS_L FB_B1_RAS_L FB_B0_CAS_L FB_B1_CAS_L FB_B0_WE_L FB_B1_WE_L FB_B0_CKE_L FB_B1_CKE_L FB_B0_CS_L FB_B1_CS_L FB_B0_EDC<0> FB_B0_EDC<1> FB_B0_EDC<2> FB_B0_EDC<3> FB_B1_EDC<0> FB_B1_EDC<1> FB_B1_EDC<2> FB_B1_EDC<3> FB_B0_DBI_L<0> FB_B0_DBI_L<1> FB_B0_DBI_L<2> FB_B0_DBI_L<3> FB_B1_DBI_L<0> FB_B1_DBI_L<1> FB_B1_DBI_L<2> FB_B1_DBI_L<3> FB_B0_WCLK_P<0> FB_B0_WCLK_N<0> FB_B0_WCLK_P<1> FB_B0_WCLK_N<1> FB_B1_WCLK_P<0> FB_B1_WCLK_N<0> FB_B1_WCLK_P<1> FB_B1_WCLK_N<1> FB_B0_DQ<7..0> FB_B0_DQ<15..8> FB_B0_DQ<23..16> FB_B0_DQ<31..24> FB_B1_DQ<7..0> FB_B1_DQ<15..8> FB_B1_DQ<23..16> FB_B1_DQ<31..24>
75 76 77
MUXGFX Net Properties ELECTRICAL_CONSTRAINT_SET
SPACING
GDDR5_CLK GDDR5_CLK GDDR5_CLK GDDR5_CLK GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA
PHYSICAL
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
SPACING
LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D
LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS
LVDS_A_CLK_P LVDS_A_CLK_N LVDS_A_DATA_P<2..0> LVDS_A_DATA_N<2..0> LVDS_B_CLK_P LVDS_B_CLK_N LVDS_B_DATA_P<2..0> LVDS_B_DATA_N<2..0>
LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D
LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS
LVDS_CONN_A_CLK_F_P LVDS_CONN_A_CLK_F_N LVDS_CONN_B_CLK_F_P LVDS_CONN_B_CLK_F_N LVDS_CONN_A_CLK_P LVDS_CONN_A_CLK_N LVDS_CONN_A_DATA_P<2..0> LVDS_CONN_A_DATA_N<2..0> LVDS_CONN_B_CLK_P LVDS_CONN_B_CLK_N LVDS_CONN_B_DATA_P<2..0> LVDS_CONN_B_DATA_N<2..0>
83 87 83 87 83 87 83 87 83 87 83 87 83 87 83 87
6 82 6 82 6 82
PHYSICAL
GPU_CLK27M GPU_CLK100M LVDS_EG_A_CLK LVDS_EG_A_CLK LVDS_EG_A_DATA LVDS_EG_A_DATA LVDS_EG_A_DATA3 LVDS_EG_A_DATA3 LVDS_EG_B_DATA LVDS_EG_B_DATA LVDS_EG_B_DATA3 LVDS_EG_B_DATA3
CLK_SLOW_55S CLK_SLOW_55S LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D
DP_ML
DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D
B
SPACING
CLK_SLOW CLK_SLOW LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS
GPU_CLK27M GPU_CLK100M LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N LVDS_EG_A_DATA_P<2..0> LVDS_EG_A_DATA_N<2..0> NC_LVDS_EG_A_DATA_P<3> NC_LVDS_EG_A_DATA_N<3> LVDS_EG_B_DATA_P<2..0> LVDS_EG_B_DATA_N<2..0> NC_LVDS_EG_B_DATA_P<3> NC_LVDS_EG_B_DATA_N<3>
78 79 78 79 78 87 78 87 78 87 78 87 78 79 78 79 78 87 78 87 78 79 78 79
6 82 82 83 82 83 6 82 83
DP_AUX_CH
6 82 83 82 83
DP_AUX_CH
82 83
DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT
DP_EXTA_ML_C_P<3..0> DP_EXTA_ML_C_N<3..0> DP_EXTA_AUXCH_C_P DP_EXTA_AUXCH_C_N DP_EG_AUXCH_P DP_EG_AUXCH_N
78 84 78 84 83 84 83 84 8 78 83 8 78 83
6 82 83 6 82 83
A
SYNC_MASTER=K92_MLB
SYNC_DATE=08/09/2010
PAGE TITLE
GPU (Whistler) CONSTRAINTS DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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8
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5 TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
4
3
K91 Specific Net Properties
2
1
K91 Specific Net Properties
NET_TYPE
NET_TYPE
TABLE_PHYSICAL_RULE_ITEM
SENSE_1TO1_55S
*
=55_OHM_SE
=1:1_DIFFPAIR
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
ELECTRICAL_CONSTRAINT_SET
TABLE_PHYSICAL_RULE_ITEM
THERM_1TO1_55S
*
=55_OHM_SE
=1:1_DIFFPAIR
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
PHYSICAL
SPACING
ENET_100D
ENETCONN
ENET_100D
ENETCONN
=1:1_DIFFPAIR
ELECTRICAL_CONSTRAINT_SET
ENETCONN_P<3..0> ENETCONN_N<3..0>
PHYSICAL
SPACING
37 37
TABLE_PHYSICAL_RULE_ITEM
DIFFPAIR
*
=1:1_DIFFPAIR
AUDIODIFF
*
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
10 MM
0.1 MM
0.1 MM
SENSE_DIFFPAIR
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
TABLE_PHYSICAL_RULE_ITEM
0.1 MM
0.1 MM
I287
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
I288
WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM
CPU_COMP
TABLE_SPACING_RULE_ITEM
D
SENSE
*
=2:1_SPACING
?
THERM
*
=2:1_SPACING
?
GND
*
SENSE_DIFFPAIR
SENSE_DIFFPAIR
GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM
CPU_VCCSENSE
TABLE_SPACING_RULE_ITEM
GND
*
GND_P2MM
SENSE_DIFFPAIR
TABLE_SPACING_RULE_ITEM
AUDIO
*
?
=2:1_SPACING
SENSE_DIFFPAIR
SENSE_DIFFPAIR TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
25 MILS
?
SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
TABLE_SPACING_RULE_ITEM
ENETCONN
*
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM
ENET_MDI
GND
*
SENSE_DIFFPAIR
GND_P2MM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
SENSE_DIFFPAIR
TABLE_SPACING_RULE_ITEM
GND
*
=STANDARD
TABLE_SPACING_ASSIGNMENT_HEAD
?
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CLK_PCIE
GND
*
GND_P2MM
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE
GND
*
GND_P2MM
SATA
GND
*
GND_P2MM
SENSE_DIFFPAIR
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
0.20 MM
1000
TABLE_SPACING_ASSIGNMENT_ITEM
SENSE_DIFFPAIR
TABLE_SPACING_RULE_ITEM
GND_P2MM
*
TABLE_SPACING_ASSIGNMENT_ITEM
USB
GND
*
GND_P2MM
TABLE_SPACING_RULE_ITEM
PWR_P2MM
*
0.20 MM
1000
I249
TABLE_SPACING_ASSIGNMENT_ITEM
CLK_PCIE
SB_POWER
*
PWR_P2MM
I250
TABLE_SPACING_ASSIGNMENT_ITEM
SATA
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SB_POWER
*
I252
PWR_P2MM
SPACING_RULE_SET USB
MEM_CLK
GND
*
GND_P2MM
MEM_CMD
GND
*
GND_P2MM
SB_POWER
*
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
I251
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
SENSE_DIFFPAIR
PWR_P2MM
I256 I255
TABLE_SPACING_ASSIGNMENT_ITEM
I281
TABLE_SPACING_ASSIGNMENT_ITEM
C
MEM_CTRL
GND
*
GND_P2MM
MEM_DATA
GND
*
GND_P2MM
I282 I283
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
I284
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
GND
*
GND_P2MM
I285
TABLE_SPACING_ASSIGNMENT_ITEM
LVDS
GND
*
GND_P2MM
SENSE_DIFFPAIR
I286 SENSE_DIFFPAIR TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
I292
SENSE_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM
MEM_40S
*
OVERRIDE
OVERRIDE
0.09 MM OVERRIDE
OVERRIDE
I291
100 MIL
OVERRIDE
OVERRIDE
OVERRIDE
I299
OVERRIDE
SENSE_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM
MEM_72D
*
OVERRIDE
OVERRIDE
PCIE_85D
*
OVERRIDE
OVERRIDE
I300
0.09 MM
100 MIL
OVERRIDE
OVERRIDE
0.09 MM
10 mm
I302
OVERRIDE
I303
OVERRIDE
I301
OVERRIDE
SENSE_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
SENSE_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM
USB_85D
TOP
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
I304
OVERRIDE
I305
OVERRIDE
SENSE_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM
CPU_27P4S
BOTTOM
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.23 MM
100 MIL
OVERRIDE
OVERRIDE
I306
OVERRIDE
OVERRIDE
I308
SENSE_DIFFPAIR
I307 I329
SENSE_DIFFPAIR
I330 I337
SENSE_DIFFPAIR
I338 I331
SENSE_DIFFPAIR
I332 I333 I334
B
I335 I336 I342
SENSE_DIFFPAIR
I341
CPUTHMSNS_D2_P CPUTHMSNS_D2_N
CPU_THERMD_P CPU_THERMD_N GPUTHMSNS_D_P GPUTHMSNS_D_N GPU_TDIODE_P GPU_TDIODE_N VCCSAS0_CS_P VCCSAS0_CS_N VCCSAISNS_R_P VCCSAISNS_R_N ISNS_1V5_S3_R_P ISNS_1V5_S3_R_N CPUVCCIOS0_CS_P CPUVCCIOS0_CS_N CPUVCCIOISNS_R_P CPUVCCIOISNS_R_N GPUISENS_N GPUISENS_P ISNS_1V5_S3_N ISNS_1V5_S3_P ISNS_AIRPORT_N ISNS_AIRPORT_N ISNS_AIRPORT_P ISNS_AIRPORT_P ISNS_AIRPORT_R_N ISNS_AIRPORT_R_P ISNS_HDD_N ISNS_HDD_P ISNS_HDD_R_N ISNS_HDD_R_P ISNS_LCDBKLT_N ISNS_LCDBKLT_P ISNS_ODD_N ISNS_ODD_P ISNS_ODD_R_N ISNS_ODD_R_P ISNS_PP1V0_S0GPU_P ISNS_PP1V0_S0GPU_N ISNS_PP1V0_S0GPU_R_P ISNS_PP1V0_S0GPU_R_N PP1V8_S0GPU_P PP1V8_S0GPU_N PP1V8_S0GPU_R_P PP1V8_S0GPU_R_N PP1V5_S0GPU_P PP1V5_S0GPU_N PP1V5_S0GPU_R_P PP1V5_S0GPU_R_N CPUIMVP_ISNS1G_P CPUIMVP_ISNS1G_N CPUIMVP_ISNS1G_R_P CPUIMVP_ISNS1G_R_N ISNS_HS_OTHER_P ISNS_HS_OTHER_N ISNS_HS_GPU_P ISNS_HS_GPU_N ISNS_HS_COMPUTING_P ISNS_HS_COMPUTING_N CPUIMVP_ISNS_P CPUIMVP_ISNS_N
50 50
CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR
PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N CHGR_CSI_R_P CHGR_CSI_R_N CHGR_CSO_R_P CHGR_CSO_R_N
USB_85D
USB
USB_85D
USB
USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N
USB_85D
USB
USB_85D
USB
48
USB_85D
USB
48
USB_85D
USB
PCIE_CLK100M_AP
9 50 9 50 50 50 50 78 50 78
(USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTA)
48 64 48 64 48 48
6 31 6 31 63
D
63 49 63 49 63 42 42
USB2_LT1_P USB2_LT1_N
6 42 6 42
48 48 48 69 48 69
48
USB_85D
USB
48
USB_85D
USB
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
CONN_USB2_BT_P CONN_USB2_BT_N
6 6
USB_LT2_P USB_LT2_N
6 42 6 42
48 66 48 66 98 98
I324
AUDIO_DIFFPAIR
98
I323 98
I326
AUDIO_DIFFPAIR
100
I325 100
I328
AUDIO_DIFFPAIR
I327
SSM2375L_P SSM2375L_N SSM2375R_P SSM2375R_N SSM2375S_P SSM2375S_N
59 59 59 59 59 59
100 100
C SPK_OUT SPK_OUT
100 100
SPK_OUT
DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR
AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO
SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N SPKRCONN_S_OUT_P SPKRCONN_S_OUT_N
6 59 60 6 59 60 6 59 60 6 59 60 6 59 60 6 59 60
100 100
100 100
USB_85D
USB
USB_85D
USB
USB_TPAD_R_P USB_TPAD_R_N
52 52
100 100 49 68 49 68
SB_POWER
49
SB_POWER
49
SB_POWER
GND
49
45 55 65 70 71 72 82 85 89 6 7 17 19 20 22 23 24 25 29 39 48 49 50 51 53 56 60 61 71 72 6 7 12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 6
PP3V3_S5 PP3V3_S0 PP1V5_S3RS0
GND
49 49 49
B
49 49 49 49
Graphics ,SATA Constraint Relaxations Alternate diffpair width/gap through BGA fanout areas (95-ohm diff) TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
LVDS_85D
BGA
LVDS_85D
DP_85D
BGA
100_DIFF_BGA
SATA_90D
BGA
100_DIFF_BGA
CLK_PCIE_90D
BGA
100_DIFF_BGA
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
I312
AUDIO_DIFFPAIR
I311 I314
A Memory Constraint Relaxations
AUDIO_DIFFPAIR
I313 I316
AUDIO_DIFFPAIR
I315
Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.
I317
AUDIO_DIFFPAIR
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
MEM_72D
BOTTOM
0.127 MM
6.35 MM
I318 I319 I320
TABLE_PHYSICAL_RULE_ITEM
MEM_85D
TOP
0.1 MM
AUDIO_DIFFPAIR
I321
6.35 MM
AUDIO_DIFFPAIR
I322
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUD_LO1_R_P AUD_LO1_R_N AUD_LO2_L_P AUD_LO2_L_N AUD_LO2_R_P AUD_LO2_R_N AUD_SPKRAMP_LIN_P AUD_SPKRAMP_LIN_N AUD_SPKRAMP_RIN_P AUD_SPKRAMP_RIN_N AUD_SPKRAMP_SUBIN_P AUD_SPKRAMP_SUBIN_N
56 59 56 59 56 59 56 59 56 59
SYNC_MASTER=K18_MLB
56 59
SYNC_DATE=04/27/2010
PAGE TITLE
Project Specific Constraints
59 59
DRAWING NUMBER
Apple Inc.
59 59
7
6
5
4
REVISION
R
59
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
SIZE
D
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98 OF 101
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K91 Board-Specific Spacing & Physical Constraints TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS (MIL or MM)
ALLEGRO VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA
MM
15.5.1
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
0.1 MM
?
TABLE_PHYSICAL_RULE_ITEM
DEFAULT
*
Y
=50_OHM_SE
=50_OHM_SE
10 MM
0 MM
0 MM
TABLE_SPACING_RULE_ITEM
DEFAULT
*
STANDARD
*
=DEFAULT
?
BGA_P1MM
*
=DEFAULT
?
BGA_P2MM
*
=DEFAULT
?
TABLE_PHYSICAL_RULE_ITEM
STANDARD
*
Y
=DEFAULT
=DEFAULT
10 MM
=DEFAULT
=DEFAULT
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
D
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
55_OHM_SE
TOP,BOTTOM
Y
0.090 MM
0.090 MM
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
*
*
BGA
P072_SPACE
DIFFPAIR NECK GAP
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
D
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
55_OHM_SE
*
Y
0.076 MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
P072_SPACE
*
0.071 MM
?
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
2X_DIELECTRIC
LAYER
*
0.140 MM
?
3X_DIELECTRIC
*
0.210 MM
?
4X_DIELECTRIC
*
0.280 MM
?
5X_DIELECTRIC
*
0.350 MM
?
7X_DIELECTRIC
*
0.490 MM
?
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
50_OHM_SE
TOP,BOTTOM
Y
0.110 MM
0.095 MM
50_OHM_SE
*
Y
0.090 MM
0.090 MM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
0.15 MM
?
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
=STANDARD
=STANDARD
TABLE_SPACING_RULE_ITEM
1.5:1_SPACING
*
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
2:1_SPACING
*
0.2 MM
?
2.5:1_SPACING
*
0.25 MM
?
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
TABLE_SPACING_RULE_ITEM
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
45_OHM_SE
TOP,BOTTOM
Y
0.13 MM
0.13 MM
45_OHM_SE
*
Y
0.099 MM
0.099 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
40_OHM_SE
TOP,BOTTOM
Y
0.165 MM
0.095 MM
40_OHM_SE
*
Y
0.135 MM
0.090 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
37_OHM_SE
TOP,BOTTOM
Y
0.185 MM
0.095 MM
37_OHM_SE
*
Y
0.155 MM
0.090 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
27P4_OHM_SE
TOP,BOTTOM
Y
0.310 MM
0.095 MM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
3:1_SPACING
*
0.3 MM
?
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
4:1_SPACING
*
0.4 MM
?
5:1_SPACING
*
0.5 MM
?
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
C
C
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
27P4_OHM_SE
*
Y
0.250 MM
0.1 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
72_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
72_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.154 MM
0.154 MM
0.200 MM
0.200 MM
72_OHM_DIFF
ISL2,ISL11
Y
0.154 MM
0.154 MM
0.200 MM
0.200 MM
72_OHM_DIFF
TOP,BOTTOM
Y
0.175 MM
0.175 MM
0.200 MM
0.200 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
80_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
80_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.105 MM
0.105 MM
0.120 MM
0.120 MM
80_OHM_DIFF
ISL2,ISL11
Y
0.105 MM
0.105 MM
0.120 MM
0.120 MM
80_OHM_DIFF
TOP,BOTTOM
Y
0.135 MM
0.135 MM
0.160 MM
0.160 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
85_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
85_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.110 MM
0.090 MM
0.180 MM
0.180 MM
85_OHM_DIFF
ISL2,ISL11
Y
0.110 MM
0.090 MM
0.180 MM
0.180 MM
85_OHM_DIFF
TOP,BOTTOM
Y
0.125 MM
0.090 MM
0.190 MM
0.190 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
1:1_DIFFPAIR
*
Y
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
B
B
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
MAXIMUM NECK LENGTH
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
100_DIFF_BGA
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
100_DIFF_BGA
ISL3,ISL4
Y
0.075 MM
0.075 MM
0.125 MM
0.125 MM
100_DIFF_BGA
ISL9,ISL10
Y
0.075 MM
0.075 MM
0.125 MM
0.125 MM
TABLE_PHYSICAL_RULE_ITEM
90_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
90_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.102 MM
0.090 MM
0.220 MM
0.220 MM
90_OHM_DIFF
ISL2,ISL11
Y
0.102 MM
0.090 MM
0.220 MM
0.220 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
90_OHM_DIFF
TOP,BOTTOM
Y
0.115 MM
0.090 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
100_OHM_DIFF
*
N
=STANDARD
=STANDARD
100_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.080 MM
100_OHM_DIFF
ISL2,ISL11
Y
100_OHM_DIFF
TOP,BOTTOM
PHYSICAL_RULE_SET
NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.
0.230 MM
0.230 MM
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=STANDARD
=STANDARD
=STANDARD
0.080 MM
0.200 MM
0.200 MM
0.080 MM
0.080 MM
0.200 MM
0.200 MM
Y
0.089 MM
0.089 MM
0.220 MM
0.220 MM
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
110_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
110_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.065 MM
0.065 MM
0.2 MM
0.2 MM
110_OHM_DIFF
ISL2,ISL11
Y
0.065 MM
0.065 MM
0.2 MM
0.2 MM
110_OHM_DIFF
TOP,BOTTOM
Y
0.075 MM
0.075 MM
0.330 MM
0.330 MM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
A
SYNC_MASTER=K18_MLB
TABLE_PHYSICAL_RULE_ITEM
SYNC_DATE=04/27/2010
PAGE TITLE
PCB Rule Definitions
TABLE_PHYSICAL_RULE_ITEM
DRAWING NUMBER
TABLE_PHYSICAL_RULE_ITEM
Apple Inc.
TABLE_PHYSICAL_RULE_ITEM
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
PAGE
109 OF 132 SHEET
99 OF 101
1
A
8
7
6
5
4
3
2
1
DEBUG_ADC
RD103
VOUT_S0_LCDBKLT_XW
1
0.1UF
3
2
DEBUG_ADC 1
V+
PPBUS_SW_BKL
OUT
TP_ISNS_LCDBKLT_N
XWD159 SM
D
PLACE_NEAR=UD100.22:5mm
DEBUG_ADC
UD120
1
TP_ISNS_LCDBKLT_P
2
5 IN-
RD150
INA214 SC70
6 LCDBKLT_IOUT
OUT
4 IN+
2
4.53K 1
ADC_CH0
2
REF 1
1% 1/16W MF-LF 402
1
DEBUG_ADC
2
0.22UF 20% 6.3V X5R 402
GAIN: 100X 2
2
1
CD101
1
10UF
0.1UF
20% 10V CERM 402
20% 6.3V X5R 603
20% 10V CERM 402
2
226K 2 1% 1/16W MF-LF 402
2
RD157
AVDD ADC_CH7
100
CD152 2.2UF
1% 1/16W MF-LF 402
10% 6.3V X5R 402
2
1
101
PLACE_NEAR=UD100.22:5mm PLACE_NEAR=UD100.5:5mm
DIVIDER: ~ 1/22
100
22
100
23
ADC_CH0 ADC_CH1 100 ADC_CH2 100 ADC_CH3 100 ADC_CH4 100 ADC_CH5 100 ADC_CH6 100 ADC_CH7
5
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
6
COM
24 1 2 3 4
DVDD
6 7 29 31 41 42 43 45 65 66 71 81 100
10UF
RD101
QFN
DEBUG_ADC
11
9
10
AD0 AD1
14
SDA SCL
17
33
1
15
SMBUS_SMC_MGMT_SDA
RD102
7
ADC_VREF
REFCOMP
8
ADC_REFCOMP DEBUG_ADC
DEBUG_ADC
CD104
1
0.1UF 2
SMBUS_SMC_MGMT_SCL
2
IN
44 47 96
5% 1/16W MF-LF 402
VREF
LSB: 0.001V
44 47 96
PLACE_NEAR=U4900.E4:10mm
33 1
1
BI
DEBUG_ADC
ADC_SDA ADC_SCL
16
D
PLACE_NEAR=U4900.F1:10mm
2
5% 1/16W MF-LF 402
THRM PAD
GND
ADC RANGE: 0V TO 4.096V
20% 6.3V X5R 603
DEBUG_ADC
LTC2309
I2C ADDRESS: 0X10 / 0X11
CD103
2
UD100
DEBUG_ADC 1
DEBUG_ADC
CD102
0.1UF
RD158 1
46.4K
CD145
CD100
DEBUG_ADC
DEBUG_ADC
DEBUG_ADC
1
PPBUS_SW_LCDBKLT_PWR
IN
PLACE_NEAR=UD100.5:5mm
VOUT_S0_LCDBKLT_DIV
100
1% 1/16W MF-LF 402
GND 88
2
1M
EDP Current: 0.715A 88 7
RD156
DEBUG_ADC
12
DEBUG_ADC
20% 10V CERM 402
PP5V_S3
21
2
88 82 8 6
DEBUG_ADC
2
5% 1/16W MF-LF 402
MIN_NECK_WIDTH=0.25MM VOLTAGE=5V
25
CD144
SM
1
MIN_LINE_WIDTH=0.3MM
20
1
PPVOUT_S0_LCDBKLT 1
5% 1/16W MF-LF 402
10
PP5V_S5_DEBUG_ADC_DVDD_FILT
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V
19
DEBUG_ADC
PP5V_S5_DEBUG_ADC_AVDD_FILT
2
13
1
XWD150
PP5V_S3
100 81 71 66 65 45 43 42 41 31 29 7 6
RD104
10
PP5V_S3 100 81 71 66 65 45 43 42 41 31 29 7 6
18
LCD BKLT Voltage Sense
LCD BKLT Current Sense
DEBUG_ADC
DEBUG_ADC
CD105
1
CD106
10UF
20% 10V CERM 402
2
2.2UF
20% 6.3V X5R 603
2
20% 6.3V CERM 402-LF
AIRPORT Current Sense PP5V_S3
100 81 71 66 65 45 43 42 41 31 29 7 6
100 81 71 66 65 45 43 42 41 31 29 7 6
DEBUG_ADC 1
CD130
2
RD130
EDP Current: 1.06A
TP_ISNS_AIRPORT_P
IN
C
2.61K 1
2
98
ISNS_AIRPORT_R_P 8
THRM
2.61K 2
1
98
ISNS_AIRPORT_R_N
1
2
ADC_CH2
1% 1/16W MF-LF 402
4
1
TP_ISNS_ODD_N
IN
1
2.2UF 2
GAIN: 383X
DEBUG_ADC
ISNS_ODD_R_N
98
2
RD155 1
226K
ISNS_ODD_IOUT
1
4
1% 1/16W MF-LF 402
GAIN: 226X
9
NOSTUFF
RD153
RD154 1M 1
1% 1/16W MF-LF 2 402
1% 1/16W MF-LF 402
10% 6.3V X5R 402
2
DEBUG_ADC
DEBUG_ADC 1
SIGNAL_MODEL=EMPTY
CD150
1
PLACE_NEAR=UD100.1:5mm
PLACE_NEAR=UD100.24:5mm
100 101
2.2UF
1% 1/16W MF-LF 402
10% 6.3V X5R 402
ADC_CH3
2
VTHRM
2
1M
1M
1
1% 1/16W MF-LF 402
V+
2
C
NOSTUFF
OPA2333 DFN
3
RD133
1M
2
CD131
PLACE_NEAR=UD100.1:5mm
UD140
RD152 4.42K
20% 10V CERM 402
DEBUG_ADC 8
DEBUG_ADC
100
DEBUG_ADC
1% 1/16W MF-LF 402
RD132
ISNS_ODD_R_P
98
226K
ISNS_AIRPORT_IOUT
1
2
1% 1/16W MF-LF 402
9
DEBUG_ADC 1
4.42K
RD134
V-
2
1
DEBUG_ADC
DFN
RD131
TP_ISNS_ODD_P
IN
PLACE_NEAR=UD100.1:5mm
OPA2333
3
DEBUG_ADC
TP_ISNS_AIRPORT_N
RD151
UD130
V+
IN
2
DEBUG_ADC
1% 1/16W MF-LF 402
CD151 0.1UF
DEBUG_ADC
EDP Current: 1.8A
20% 10V CERM 402
DEBUG_ADC
DEBUG_ADC 1
Sense Resistor 0.005 Ohm
0.1UF Sense Resistor 0.005 Ohm
PP5V_S3
ODD Current Sense
SIGNAL_MODEL=EMPTY
2 1% 1/16W MF-LF 402
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
GPU 1.0V Current Sense HDD Current Sense EDP Current: 2.846A 86 7
DEBUG_ADC
IN PP1V0_S0GPU
UD130
RD140
XWD145
2
1
TP_ISNS_PP1V0_S0GPU_P
4.22K
V+
6 THRM
RD141 80 78 74 73 7
OUT PP1V0_S0GPU_ISNS
1
4.22K
2
1% 1/16W MF-LF 402
7
1V0_GPU_IOUT
1
V-
DEBUG_ADC
1
RD144
DFN
5
1% 1/16W MF-LF 402
TP_ISNS_PP1V0_S0GPU_N
B
ISNS_PP1V0_S0GPU_R_P
Sense Resistor 0.005 Ohm EDP Current: 1.2A
226K 1% 1/16W MF-LF 402
4
ADC_CH4 1
2.94K
TP_ISNS_HDD_P
IN
2
1
CD142
PLACE_NEAR=UD100.2:8mm
TP_ISNS_HDD_N
IN
1
RD143 1M
1
1% 1/16W MF-LF
2
2.94K
V+
98
RD164 7
ISNS_HDD_IOUT
1
VTHRM
2
DEBUG_ADC
OPA2333 DFN
6
ISNS_HDD_R_N
4
GAIN: 340X
9
226K
2
ADC_CH5
1% 1/16W MF-LF 402
1
10% 6.3V X5R 402
DEBUG_ADC
SIGNAL_MODEL=EMPTY
DEBUG_ADC 1
RD162
RD163
1M
1M 1
1% 1/16W MF-LF 2 402
GAIN: 237X
CD140 2.2UF
2
SIGNAL_MODEL=EMPTY
B
100
DEBUG_ADC
PLACE_NEAR=UD100.3:5mm
1% 1/16W MF-LF 402
2 402
PLACE_NEAR=UD100.3:5mm
UD140 8 5
1% 1/16W MF-LF 402
DEBUG_ADC
1M
ISNS_HDD_R_P
RD161
402
RD142
98
DEBUG_ADC
2 X5R
ISNS_PP1V0_S0GPU_R_N
2 1% 1/16W MF-LF 402
100
2.2UF 10% 6.3V DEBUG_ADC
9
DEBUG_ADC 1
RD160
DEBUG_ADC
OPA2333
8
2 98
SM
DEBUG_ADC
PLACE_NEAR=UD100.2:8mm
2
SIGNAL_MODEL=EMPTY
1% 1/16W MF-LF 402
SIGNAL_MODEL=EMPTY
GPU 1.8V Current Sense 100 81 71 66 65 45 43 42 41 31 29 7 6
PP5V_S3 1
EDP Current: 2.4065A 71 7 6
IN
PP1V8_GPUIFPX DEBUG_ADC
UD180
RD187 1
TP_PP1V8_S0GPU_P
1
XWD186 SM
A
11.8K
8 2
98
PP1V8_S0GPU_R_P 5
1% 1/16W MF-LF 402
2
80 78 74 7
OUT PP1V8_S0GPU_ISNS
TP_PP1V8_S0GPU_N
1
OPA2333
2
6
1.5V FB Current Sense
20% 10V
EDP Current: 7.8A
CERM
PLACE_NEAR=UD.23:5mm
402
7
P1V8_S0GPU_IOUT
V-
1
4.53K
2
98
ADC_CH1
MF-LF
4
PP1V5_GPU_REG
20% 6.3V
RD189
DEBUG_ADC
2
1% 1/16W MF-LF 402
SIGNAL_MODEL=EMPTY
1M
2
98
PP1V5_S0GPU_R_P
OUT
PP1V5_S0GPU_ISNS
TP_PP1V5_S0GPU_N
7
4.53K P1V5_S0GPU_IOUT
ADC_CH6
2
OUT
100
SYNC_MASTER=K91_DINESH
1
402
98
Gain: 130x
DEBUG_ADC
DRAWING NUMBER
Apple Inc.
X5R 402
RD183
2
1% 1/16W MF-LF 402
NOTICE OF PROPRIETARY PROPERTY:
DEBUG_ADC RD184
1M
DEBUG_ADC
1M 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIGNAL_MODEL=EMPTY
2 1% 1/16W MF-LF 402
3
SIZE
D REVISION
R
PLACE_NEAR=UD100.4:5mm 1
4
20% 6.3V 2
DEBUG SENSORS AND ADC
CD181 0.22UF
DEBUG_ADC
PP1V5_S0GPU_R_N
SYNC_DATE=08/06/2010
PAGE TITLE
1% MF-LF
9 2
SIGNAL_MODEL=EMPTY
5
1
1/16W
4
1% 1/16W DEBUG_ADCMF-LF 402
1% 1/16W MF-LF 402
6
RD185 1
VTHRM
SIGNAL_MODEL=EMPTY
8
V+ 2
7.68K 1
PLACE_NEAR=UD100.4:5mm
OPA2333 DFN
3
RD182 77 76 75 74 7
RD190 1
2 1% 1/16W MF-LF 402
X5R
DEBUG_ADC
1M
DEBUG_ADC
UD180 8
7.68K 1
2
402
1
TP_PP1V5_S0GPU_P
XWD180 SM
0.22UF
2 PLACE_NEAR=UD.23:5mm
DEBUG_ADC
DEBUG_ADC 1
100
1 CD182
402
DEBUG_ADC
1% 1/16W MF-LF 402
OUT
1%
9
PP1V8_S0GPU_R_N
IN
RD181 2
1/16W
THRM
86 7
RD191
DFN
V+
RD188 11.8K
CD180 0.1UF DEBUG_ADC
DEBUG_ADC
2
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100 OF 101
1
A
8
7
6
5
4
3
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D
D
CPURIPPLE_ENG
LD300
FERR-120-OHM-0.3A PP5V_S0
1
68 67 64 53 51 46 41 22 8 7 6 88 86 72 71 69
PP5V_S0_RMC_FLT
2
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V
0402
CPURIPPLE_ENG PLACE_NEAR=RD305.1:5MM
PLACE_NEAR=CD310.1:2MM
CD310
XWD300 SM 68 48 14 12 7 6
IN
PPVCORE_S0_CPU
2
1
1
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.1V
2
1
CD300 10UF
1UF PPVCORE_S0_RMC
CPURIPPLE_ENG
CPU_VCORE_C
20% 2 6.3V CERM-X5R 0402
CPURIPPLE_ENG
RD306
10% 16V X5R 402
CPURIPPLE_ENG
1
10.2 2 0.1% 1/16W TF 402
RD300
PP1V05_S0
22 20 17 16 14 13 12 10 9 7 6 72 69 67 44 39 35 23
1
100
5% 1/16W MF-LF 402
2
PP1V05_S0_RMC_R
CPURIPPLE_ENG
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
DD300 SOD-523 1
C
2
C
BAT54XV2T1 CPURIPPLE_ENG
CPURIPPLE_ENG CPURIPPLE_ENG
1 CD304 1 RD301 11K
10UF
20% 6.3V CERM-X5R 2 0402
0.1% 1/16W MF 402 2
CPURIPPLE_ENG
1
1
RD303
CD301 0.1UF
1.0K
10% 16V 2 X5R 402-1
0.1% 1/16W TF 2 402
CPURIPPLE_ENG
UD300 1V05_S0_RMC_DIV CPURIPPLE_ENG
8
3
NO_TEST=TRUE
V+
1
RD305 10.2 2 1
CPURIPPLE_ENG CPURIPPLE_ENG
RD3021 CPURIPPLE_ENG
CD305
1
0.1UF
11K 0.1% 1/16W MF 402 2
1
RD304
0.1% 1/16W TF 402
CPURIPPLE_ENG
OPA2365
CPURIPPLE_ENG
DD301 SOD-523
SO-8
COMP_CPU_VCORE_RMC
1
UD300 CPU_VCORE_RMC_P
2
8
5
NO_TEST=TRUE
CPU_VCORE_RMC_DIV
V-
2
NO_TEST=TRUE
OPA2365 7
BAT54XV2T1
VSNS_CPU_VCORE_RMC_OUT NO_TEST=TRUE
4
CPU_VCORE_RMC_N
V-
6
NO_TEST=TRUE
CPURIPPLE_ENG
SO-8
V+
4
1.0K
RD320 4.53K2
ADC_CH3
1
1% 1/16W MF-LF 402
OUT
100
CPURIPPLE_ENG 1
CD320 0.22UF
0.1% 1/16W TF 2 402
10% 10V 2 CERM 402
10% 16V 2 X5R 402-1
CPURIPPLE_ENG PLACE_NEAR=RD305.1:5MM
CPURIPPLE_ENG
RD308
RD307 1
10
1
1K
2
2 1% 1/16W MF-LF 402
5% 1/16W MF-LF 402
B
B
A
SYNC_MASTER=K91_DINESH
SYNC_DATE=08/18/2010
PAGE TITLE
Power Supplies BIST DRAWING NUMBER
Apple Inc.
SIZE
D REVISION
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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7
6
5
4
3
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