Latch-Up in CMOS

MUTHU KUMAR G University VOC College Of Engineering Thoothukudi https://astonishingengineering.blogspot.in/

Latch up-Definition • Latch is the generation of a low-impedance path in CMOS chips between the power supply and the ground rails due to interaction of parasitic pnp and npn bipolar transistors. These BJTs for a siliconcontrolled rectifier with positive feedback and virtually short circuit the power and the ground rail. • This causes excessive current flows and potential permanent damage to the devices. https://astonishingengineering.blogspot.in/

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Equivalent circuit of CMOS latch-up

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Parasitic PNP transistor-Q1 • CMOS transistor consisting of an NMOS and a PMOS device. • Q1 and Q2 are parasitic transistor elements residing inside it. • Q1 is double emitter vertical pnp transistor whose base is formed by n well substrate of PMOS, two emitters are formed by source and drain terminal of PMOS and collector is formed by substrate(p type) of NMOS. https://astonishingengineering.blogspot.in/

Parasitic NPN transistor-Q2 • Q2 is double emitter lateral npn transistor whose base is formed by substrate(p type)., two emitters are formed by source and drain terminal of NMOS and collector is formed by n well substrate of PMOS.

• Rwell represents the parasitic resistance in the n-well structure whose value ranges from 1KW to 20kW. • The substrate resistance Rsub depends on the substrate structure https://astonishingengineering.blogspot.in/

• The collector current of both transistors consists of reverse leakage current. But if collector current of one of BJT is temporarily increased by disturbance, resulting positive feedback loop causes current perturbation to be multiplied by β1β2. • Because collector current of one transistor Q1 is fed as input base current to another transistor Q2, collector current of Q2, Ic2 = β2 * Ib2 and this collector current Ic2 is fed as input base current Ib1 to another transistor Q1. In this way both transistors feedback each other and the collector currenthttps://astonishingengineering.blogspot.in/ of each goes on multiplying.

Latch-up Analysis • The cross coupled transistors form a bistable siliconcontrolled rectifier. Ordinarily, both parasitic bipolar transistors are OFF. • Latch up can be triggered when transient currents flow through the substrate during chip power-up or when external voltages outside the normal operating range are applied. https://astonishingengineering.blogspot.in/

Latch-up Analysis • If substantial current flows in the substrate, Vsub will rise, turning ON the NPN transistor. This pulls current through the well resistor, bringing down Vwell and turning ON the PNP transistor.

• The PNP transistor current in turn rises Vsub, initiating a positive feedback loop with a large current flowing between VDD and GND that persists until the power supply is turned off or the power wires melt. https://astonishingengineering.blogspot.in/

How to avoid Latch-up? • By reducing the gain of parasitic transistors. • By reducing Rwell and Rsub . • Use Guard rings around well. Internal latch up prevention: • Well must have a substrate contact of the appropriate type. • The substrate contact should be connected to metal directly to a supply pad. • Place substrate and well contacts as close as possible to the source connections of the MOS transistors to reduce the values of Rw and Rsub. https://astonishingengineering.blogspot.in/ • Place substrate contact for every 5-10 transistors.

How to avoid Latch-up? • Use p+ guard band rings connected to ground around nMOS transistors and n+ guard rings connected to VDD around pMOS transistors to reduce Rwell and Rsub and to capture injected minority carriers before they reach the base of the parasitic BJT. • Use technologies SOI or TWINTUB

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