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RAJEEV GANDHI MEMORIAL COLLEGE OF ENGINEERING AND TECHNOLOGY::NANDYAL
LINEAR IC APPLICATIONS LAB MANUAL III – B.Tech, II-SEM EIE REGULATION: R09
DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING
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Electronics and Instrumentation Engineering (9A04505) LINEAR & DIGITAL IC APPLICATIONS LAB (Common to E Con E, EIE) B.Tech. III-II Sem. (E.I.E.) T P C 0 3 2 Minimum Twelve Experiments to be conducted: Part A (IC Application Lab): 1. OP AMP Applications – Adder, Subtractor, Comparator Circuits. 2. Active Filter Applications – LPF, HPF (first order). 3. Function Generator using OP AMPs. 4. IC 555 Timer – Monostable and Astable Operation Circuit. 5. IC 566 – VCO Applications. 6. Voltage Regulator using IC 723. 7. 4 bit DAC using OP AMP. Part B (ECAD Lab): Simulate the internal structure of the following Digital IC’s using VHDL / VERILOG and verify the operations of the Digital IC’s (Hardware) in the Laboratory 1. Logic Gates- 74XX. 2. Half Adder, Half Subtractor, Full Adder, Full Subtractor & Ripple Carry Adder. 3. 3-8 Decoder -74138 & 8-3 Encoder- 74X148. 4. 8 x 1 Multiplexer -74X151 and 2x4 Demultiplexer-74X155. 5. 4 bit Comparator-74X85. 6. D Flip-Flop 74X74. 7. JK Flip-Flop 74X109. 8. Decade counter-74X90. 9. Universal shift register -74X194. Equipment required for Laboratories: 1. RPS 2. CRO 3. Function Generator 4. Multi Meters 5. IC Trainer Kits (Optional) 6. Bread Boards 7. Components: IC741, IC555, IC566, 7805, 7809, 7912 and other essential components. 8. Analog IC Tester For Software Simulation 1. Computer Systems 2. LAN Connections (Optional) 3. Operating Systems 4. VHDL/ VERILOG 5. FPGAS/CPLDS (Download Tools)
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1. APPALICATIONS OF IC 741 ADDER, SUBTRACTOR, COMPARATOR AIM: To study the applications of IC 741 as adder, sub tractor, comparator. APPARATUS: 1. IC 741 2. Resistors (1KΩ)—4 3. Function generator 4. Regulated power supply 5. IC bread board trainer 6. CRO 7. Patch cards and CRO probes CIRCUIT DIAGRAM: Adder:
Subtractor:
4 Comparator:
THEORY: ADDER: Op-Amp may be used to design a circuit whose output is the sum of several input signals such as circuit is called a summing amplifier or summer. We can obtain either inverting or non inverting summer. The circuit diagrams shows a two input inverting summing amplifier. It has two input voltages V1and V2, two input resistors R1 ,R2 and a feedback resistor Rf. Assuming that op-amp is in ideal conditions and input bias current is assumed to be zero, there is no voltage drop across the resistor Rcomp and hence the non inverting input terminal is at ground potential. By taking nodal equations. V1/R1 +V2/R2 +V0/Rf =0 V0 = - [(Rf/R1) V1 +(Rf/R2) V2] And here R1 = R2 = Rf = 1KΩ V0 = -(V1 +V2) Thus output is inverted and sum of input.
5 SUBTRACTOR: A basic differential amplifier can be used as a sub tractor. It has two input signals V1 and V2 and two input resistances R1 and R2 and a feedback resistor Rf. The input signals scaled to the desired values by selecting appropriate values for the external resistors. From the figure, the output voltage of the differential amplifier with a gain of ‘1’ is V0 = -R/Rf(V2-V1) V0 = V1-V2. Also R1 =R2 = Rf =1KΩ. Thus, the output voltage V0 is equal to the voltage V1 applied to the non inverting terminal minus voltage V2 applied to inverting terminal. Hence the circuit is sub tractor. COMPARATOR: A comparator is a circuit which compares a signal voltage applied at one input of an op-amp with a known reference voltage at the other input . It is basically an open loop op-amp with output ±Vsat as in the ideal transfer characteristics. It is clear that the change in the output state takes place with an increment in input Vi of only 2mv. This is the uncertainty region where output cannot be directly defined There are basically 2 types of comparators. 1. Non inverting comparator and. 2. Inverting comparator. The applications of comparator are zero crossing detector , window detector, time marker generator and phase meter. OBSERVATIONS: ADDER: V1(volts)
V2(volts)
Theoretical V0 = -(V1+V2)
Practical V0 = -(V1+V2)
6 SUBTRACTOR: V1(volts)
V2(volts)
Theoretical V0 = (V1-V2)
Practical V0 = (V1-V2)
COMPARATOR: Voltage input
Vref
Observed square wave amplitude
MODEL GRAPH:
PROCEDURE: ADDER: 1. connections are made as per the circuit diagram. 2. Apply input voltage 1) V1= 5v,V2=2v 2) V1= 5v,V2=5v 3) V1= 5v,V2=7v. 3. Using Millimeter measure the dc output voltage at the output terminal. 4. For different values of V1 and V2 measure the output voltage.
7 SUBTRACTOR: 1. Connections are made as per the circuit diagram. 2. Apply input voltage 1) V1= 5v,V2=2v 2) V1= 5v,V2=5v 3) V1= 5v,V2=7v. 3. Using multi meter measure the dc output voltage at the output terminal. 4. For different values of V1 and V2 measure the output voltage. COMPARATOR: 1. Connections are made as per the circuit diagram. 2. Select the sine wave of 10V peak to peak , 1K Hz frequency. 3. Apply the reference voltage 2V and trace the input and output wave forms. 4. Superimpose input and output waveforms and measure sine wave amplitude with reference to Vref. 5. Repeat steps 3 and 4 with reference voltages as 2V, 4V, -2V, -4V and observe the waveforms. 6. Replace sine wave input with 5V dc voltage and Vref= 0V. 7. Observe dc voltage at output using CRO. 8. Slowly increase Vref voltage and observe the change in saturation voltage. PRECAUTIONS: 1. Make null adjustment before applying the input signal. 2. Maintain proper Vcc levels. RESULT: The operation of IC 741 Op-Amp as adder, sub tractor and comparator is studied and values are noted.
VIVA QUESTIONS: 1. What is an op-amp? 2. What are ideal characteristics of op amp? 3. What is the function of adder? 4. What is meant by comparator?
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2. ACTIVE FILTER APPLICATIONS-LPF, HPF [ FIRST ORDER ] AIM: To study Op-Amp as firs order LPF and first order HPF and to obtain frequency response. APPARATUS: 1. 2. 3. 4. 5. 6. 7. 8.
IC 741. Resistors (10KΩ--2, 560Ω, 330Ω Capacitors(0.1Ω) Bread board trainer CRO Function generator connecting wires Patch cards.
CIRCUIT DIAGRAM: (a)
LPF
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(a) HPF
THEORY: LOWPASS FILTER: The first order low pass butter worth filter uses an Rc network for filtering. The op-amp is used in the non inverting configuration, hence it does not load down the RC network. Resistor R1 and R2 determine the gain of the filter. V0/Vin = Af/(1+ jf/fh) Af = 1 + Rf/R1 = pass band gain of filter . F = frequency of the input signal. Fh = 1/2ΠRC =High cutt off frequency of filter . V0/Vin = Gain of the filter as afunction of frequency The gain magnitude and phase angle equations of the LPF the can be obtained by converting V0/Vin into its equivalent polar form as follows |V0/Vin| = Af/(√1 +(f/fl)2) Φ = - tan-1(f/fh) Where Φ is the phase angle in degrees . The operation of the LPF can be verified from the gain magnitude equation.
10 1. At very low frequencies i.e f
fh , |V0/Vin|
Connections are made as per the circuit diagram. Apply sine wave of amplitude 4Vp-p to the non inverting input terminal. Values the input signal frequency. Note down the corresponding output voltage. Calculate gain in db. Tabulate the values. Plot a graph between frequency and gain. Identify stop band and pass band from the graph.
11 OBSERVATIONS: Low Pass Filter Frequency(Hz)
V0(V)
Gain in 20log(V0/Vi)
db=
V0(V)
Gain in 20log(V0/Vi)
db=
High Pass Filter Frequency(Hz)
MODEL GRAPH: High Pass Filter
12 Low Pass Filter
PRECAUTIONS: 1. Make null adjustment before applying the input signal. 2. Maintain proper Vcc levels. RESULT: The frequency response of LPF and HPF is plotted using IC741 Op-Amp.
VIVA QUESTIONS: 1. What is the function of the filter? 2. What are the different types of filters? 3. Define pass band and stop band of filters? 4. Define cut off frequency? 5. what is the difference between HPF&LPF?
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3. FUNCTION GENERATOR USING IC 741 AIM: To generate triangular and square wave forms and to determine the time period of the waveforms. APPARATUS: 1. Op-Amp IC 741 –2 Nos 2. Bread board IC trainer 3. Capacitor 0.1µF 4. Zener diodes (6.2V)—2 Nos 5. Resistors—10KΩ, 150KΩ1.5KΩ, 1MΩ, 8.2KΩCRO 6. Patch cards 7. Connecting wires CIRCUIT DIAGRAM:
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THEORY: The function generator consists of a comparator U1 and an integrator A2.The comparator U2 compares the voltage at point P continuously with the inverting input i.e., at zero volts. When voltage at P goes slightly below or above zero volts, the output of U1 is at the negative or positive saturation level, respectively. To illustrate the circuit operation let us set the output of U1 at positive saturation +Vsat (approximately +Vcc). This +Vsat is an input to the integrator U2. The output of U2, therefore will be a negative going ramp. Thus, one end of the voltage divider R2-R3 is the positive saturation voltage +Vast of U1 and the other is the negative going ramp of U2. When the negative going ramp attains a certain value –Vramp, point p is slightly below zero valts; hence the output of U1 will switch from positive saturation to negative saturation –Vsat (approximately – Vcc). This means that the output of U2 will now stop going negatively and will begin to go positively. The output of U2 will continue to increase until it reaches +Vramp. At this time the point P is slightly above zero volts. The sequence then repeats. The frequencies of the square are a function of the d.c supply voltage. Desired amplitude can be obtained by using approximate zeners at the output of U1. THEORETICAL VALUES: Time period, T= 4R5C (R3+R4)/ (R1+R2) = 0.492 msec. Positive peak ramp = VzR5/ (R1+R2) = 0.05 volts. PRACTICAL VALUES: Time periods of triangular wave= Time periods of square wave= Positive peak ramp= Voltage of square wave=
PROCEDURE: 1. The circuit is connected as shown in the figure. 2. The output of the comparator U1 is connected to the CRO through chennal1, to generate a square wave. 3. The output of the comparator U2 is connected to the CRO through chennal2, to generate a triangular wave. 4. The time periods of the square wave and triangular waves are noted and they are found to be equal.
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MODEL GRAPH:
PRECAUTIONS: 1. Make null adjustment before applying the input signal. 2. Maintain proper Vcc levels. RESULT: The theoretical and practical values of time periods are found to be equal. VIVA QUESTIONS: 1. 2. 3. 4.
Define function generator? Write some applications of function generator? What is the function of function generator? Draw the block diagram of function generator?
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4.a. IC 555 TIMER MONOSTABLE MULTIVIBRATOR
AIM: To construct and study the operation of a monostable multivibrator using 555 IC timer. APPARATUS: 1. 2. 3. 4. 5. 6.
555 IC timer Capacitors (0.1µF, 0.01µF) Resistors 10KΩ Bread board IC trainer CRO Connecting wires and Patch cards
THEORY: Monostable multivibrator is also known as triangular wave generator. It has one stable and one quasi stable state. The circuit is useful for generating single output pulse of time duration in response to a triggering signal. The width of the output pulse depends only on external components connected to the opamp. The diode gives a negative triggering pulse. When the output is +Vsat, a diode clamps the capacitor voltage to 0.7V. then, a negative going triggering impulse magnitude Vi passing through RC and the negative triggering pulse is applied to the positive terminal. Let us assume that the circuit is instable state. The output V0i is at +Vsat. The diode D1 conducts and Vc the voltage across the capacitor ‘C’ gets clamped to 0.7V. the voltage at the positive input terminal through R1R2 potentiometer divider is +ßVsat. Now, if a negative trigger of magnitude Vi is applied to the positive terminal so that the effective signal is less than 0.7V.the output of the Op-Amp will switch from +Vsat to –Vsat. The diode will now get reverse biased and the capacitor starts charging exponentially to –Vsat. When the capacitor charge Vc becomes slightly more negative than –ßVsat, the output of the op-amp switches back to +Vsat. The capacitor ‘C’ now starts charging to +Vsat through R until Vc is 0.7V. − t / RC V0 = Vf +(Vi-Vf) е . ß = R2/(R1+R2) If Vsat >> Vp and R1=R2 and ß = 0.5, Then, T = 0.69RC.
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CIRCUIT DIAGRAM:
PROCEDURE: 1. 2. 3. 4.
Connections are made as per the circuit diagram. Negative triggering is applied at the terminal 2. The output voltage is measured by connecting the channel-1 at pin3. The output voltage across capacitor is measured by connecting the channel-2 at the point ‘P’. 5. Theoretically the time period is calculated by T= 1.1R1C1 where R1 = 10KΩ C1 =0.1µF. 6. Practically the charging and discharging timers are measured and theoretical value of time period is measured with practical value
18 MODELGRAPH:
PRECAUTIONS: 1. Make the null adjustment before applying the input signal. 2. Maintain proper vcc levels.
RESULT: Operation of monostable multivibrator using 555 IC trainers is studied and wave forms are noted. VIVA QUESTIONS: 1. What is another name for mono stable multi? 2. What is the purpose of pin reset? 3. Define duty cycle? 4. What are the various applications of one shot? 5. How many external triggers are necessary in one shot?
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4.b. ASTABLE MULTIVIBRATOR USING IC 555 TIMER AIM: To construct and study the operation of astable multivibrator using 555 timer APPARATUS: 1. IC 555 Timer 2. Resistors (10 KΩ, 4.7 KΩ) 3. Diode (IN 4007) 4. Capacitors (0.1µF, 0.01µF) 5. CRO 6. Patch cards 7. CRO Probes 8. Connecting wires CIRCUIT DIAGRAM:
20 THEORY: A simple OP_AMP astable multivibrator is also called square wave generator and free running oscillator .The principle for the generation of square wave output is to force an OP_AMP to operate in the saturation region β=R2/(R1+R2) of the output is feedback to input. The output is also feedback to the negative input terminal after integrating by means of a RC LPF whenever the negative input just exceeds Vref, switching takes place resulting in a square wave output. In astable multivibrator both states are quasi stable states. When the output is +Vsat, the capacitor is now starts charging towards +Vsat through resistance R the voltage is held at +βVsat. This condition continuous until the charge on C just exceed βVsat.Then the capacitor begins to discharge towards –Vsat.Then the capacitor charges more and more negatively until its voltage just –βVsat.The frequency is determined by the time it takes the capacitor to charge from –βVsat and +βVsat Vc (t) =Vf+(Vi-Vf)e-t/RC Vc (t)=Vsat-Vsat(1+β)e-t/RC We get T1=RC ln((1+β)/(1-β)) T=2T1=2 RC ln ((1+β)/(1-β)),Vo(p-p)=2Vsat PROCEDURE: 1. Connections are made as per the circuit diagram. 2. Pins 4 and 8 are shorted and connected to power supply Vcc (+5V) 3. Between pins 8 and 7 resistor R1 of 10KΩ is connected and between 7 and 6 resistor R2 of 4.7KΩ is connected. Pins 2 and 6 short circuited. 4. In between pins 1 and 5 a Capacitor of 0.01µF is connected. 5. The out put is connected across the pin 3 and GND. 6. In between pins 6 and GND a Capacitor of 0.1μF is connected. 7. Theoretically with out diode charging time Tc is given by Tc=0.69(R1+R2) C1, Discharging time Td is given by Td= 0.69R2C1 The frequency f is given by f= 1.45/(R1+2R2)C1 %of Duty cycle is (Tc/(Tc+Td))*100 8. Practically Td and Tc are measured and wave forms are noted and theoretical Values are verified with practical values 9. Connect diode between pins 7 and 2. 10. Theoretically with diode connected charging time is given by Tc=0.69R1C1 Discharging time is given by Td=0.69R2C1 11. Practically Td and Tc are noted and verified with theoretical values.
21 OBSERVATIONS: With diode Theoretical Practical
MODEL GRAPH:
Theoretical
without diode Practical
22 PRECAUTIONS: 1. Make null adjustment before applying the input signal. 2. Maintain proper Vcc levels.
RESULT: The Operation of astable multivibrator using IC 555 timer is studied. VIVA QUESTIONS: 1. 2. 3. 4. 5.
Define astable multi? Explain the pulse width of the astable multi? What is the other name for astable multi? Write one application of free running oscillator? How many external triggers are necessary for astable?
23 5. IC 565 - PHASE LOCKED LOOP AIM: To study and design the Phase locked loop. APPARATUS: 1. 2. 3. 4. 5. BLOCK DIAGRAM:
Phase Locked Loop trainer kit Function generator. C.R.O. Connecting wires Probs and patch cards
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-V
THEORY: The phase locked principle has been used in applications such as FM,stereo de coders, motor speed control ,FM de modulators ,FSK decoders and generation of local oscillator frequencies in TV and FM tuners. The phase locked loop is having three basic blocks with feed back system. One is a phase comparator, a low pass filter and a voltage- controlled oscillator. The block diagram is as shown. Phase detector: The function of phase detector is to compare the I/p signal f in with the feed back signal fout. There fore the o/p of phase detector is proportional to the phase difference between fin and fout. But the o/p voltage of the phase detector is D.C voltage and is often referred as the error voltage. Low pass filter: The o/p signal of phase detector is fed to the i/p of low pass filter. The function of the low pass filter is to remove the high frequencies and it allows only the low frequency signals. It produces a D.C level. V.C.O: The o/p of low pass filter is fed to the vco is a sine or square wave oscillator having a free running frequency that can be determined by an external RC time constant. the vco frequency is compared with the I/p frequencies and adjusted until it is equal to the I/p frequencies. In other words the PLL goes through three states 1. Free - running state 2. Capture and 3. Phase lock. If no signal is applied then PLLis in free- running state. Once the I/p frequency is applied the vco frequency starts to change and the PLL is said to be in the capture mode. The vco frequency continues to change until it equals the I/p frequency and the PLL is said to be in phase locked state. fIN
FOUT
PHASE DETECTOR
LOW PASS FILTER FEED BACK PATH
Relation ship between Fout,FL and Fc: Lock range fL Capture range fc F out
V.C.O
25 1.5k
2.433k2.5k
2.566k
3.5k
PROCEDURE: (FREE RUNNING FREQUENCY) 1. Switch on the trainer and measure the output of the regulated power supplies i.e., +12V and ±5V 2. Observe the output of the square wave generator-using oscilloscope and measure the frequency range. The frequency range should be around 1KHz to 10KHz. 3. Calculate the free running frequency range of the circuit for different values of timing capacitor and Rt. 4. Connect 0.1µF capacitor (CC) to the circuit and open the loop by removing short between pin 4 and 5 . Measure the minimum and maximum free running frequencies obtainable at the output of the PLL (Pin 4)by varying the pot. Compare your results with your calculation from step 3 (theoretical value). Simultaneously you can observe the output signal using CRO. Table 1: 1 FREE RUNNING FREQUENCY
LOCK RANGE: 5. Calculate the lock range of the circuit for a 5KHz free running frequency and record in table 1.2. 6. Connect pins 4,5 with the help of springs and adjust potentiometer to get a free running frequency of 5KHz . Connect square wave generator output to the input of PLL circuit. Provide a 5KHz square signal of 1 Vpp approximately (make this input frequency as close to the Vcc frequency as possible). 7. Observe the input & Output of the PLL. 8. Observe the input and output frequencies while slowly increasing the frequency of the square wave at the input. For some range output and input are equal (This is known as lock Range and PLL is said to be in lock with the input signal). Record the frequency at which the PLL breaks lock. (Output frequency of
26 the PLL will be around VCO frequency and in oscilloscope you will see a jittery waveform when it breaks lock instead of clean square wave). This frequency is called as upper end of the lock range and records this as F2. 9. Beginning at 5KHz, slowly decrease the frequency of the input and determine the frequency at which the PLL breaks lock on the low end record it as F1 10. Find the lock range from F2 – F1 and compare with the theoretical values from step5.
LOCK RANGE TABLE 1.2:
CAPTURE RANGE: 11. Calculate the capture range of the circuit for a 5KHz free-running frequency (consider filter capacitor (CC) is 0.1µF). 12. With the oscilloscope and counter still on pin 4, slowly increase the input frequency from minimum (say 1KHz), Record frequency (as F3) at which the input and output frequencies of the PLL are equal, this is known as lower end of the capture range. 13. Now keep input frequency at maximum possible (say 10KHz) and slowly reduce and record the frequency (as F4) at which the input and output frequencies of PLL are equal. This is known as upper end of the capture range. 14. Find capture range from F4 – F3 and compare it with the theoretical value (from step11) 15. Repeat the steps from 11 to 14 with CC value 0.2µF CAPTURE RANGE:
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OBSERVATIONS: Theoritical values Fin FL Fout=1.2/4R1C1
Practical values FL (lock-range) Fc (capture range)
PRECAUTIONS: 1. Connection must be tight. 2. Note the output wave forms carefully. VIVA QUESTIONS: 1. What are the applications of PLL? 2. What is a PLL? 3. What is a VCO? 4. Define the lock range of a PLL? 5. Define the capture range of PLL? 6. Give the expression for free running frequency f0 of a PLL? 7. What is meant by the free running frequency of a PLL? 8. Give the formulae for the lock range and capture range of the PLL? The lock range and capture range is measured for the given 1. RESULT: fin by using Phase Locked
28 6. VOLTAGE REGULATOR USING IC 723 AIM: To plot the regulation characteristics of the given IC LM 723.
APPARATUS: 1. 2. 3. 4. 5. 6. 7. 8.
Bread board IC LM 723 Resistors(7.8KΩ ,3.9KΩ ) RPS DRB Capacitors 100µF Patch cards Connecting wires
CIRCUIT DIAGRAM:
29 THEORY: A voltage regulator is a circuit that supplies constant voltage regardless of changes in load currents. Except for the switching regulators, all other types of regulators are called linear regulators. IC LM 723 is general purpose regulator. The input voltage of this 723 IC is 40 V maximum. Output voltage adjustable from 2V to 30 V. 150mA output current external pass transistor. Out put currents in excess of 10Ampere possible by adding external transistors. It can be used as either a linear or a switching regulator. The variation of DC output voltage as a function of DC load current is called regulation. % Regulation =[(Vnl-Vfl)/Vfl]*100 PROCEDURE: (1).LINE REGULATION 1. Connections are made as per the circuit diagram 2. Power supply is connected to 12 and 7 terminals 3. Volt meter is connected to 10 and 7 terminals 4. By increasing the input voltage corresponding volt meter reading is noted. (2).LOAD REGULATION 1. Connect the load to the terminals 10 and GND. 2. Keep the input voltage constant at which line regulation is obtained 3. The maximum load value is calculated from IC ratings. 4. Now, we decrease the load resistance and note down the corresponding value Of the output in volt meter. 5. Plot the graph for load verses load regulation.
OBSERVATIONS: (1).LINE REGULATION: Vnl= Line voltage (V)
Output voltage(V)
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(2).LOAD REGULATION: Regulated output(V)
Load current(mA)
Load resistance(KΩ)
Load regulation
% REGULATION=[(Vnl-Vfl)/Vfl]*100
MODEL GRAPH:
PRECAUTIONS: 1. While taking the readings of regulated output voltage load regulation , keep the input voltage constant at 15V. 2. Do not increase the input voltage more than 30 V while taking the reading for no load condition?
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RESULT: The regulation characteristics of the given IC LM 723 are successfully plotted.
VIVA QUESTIONS: 1. What is regulator? 2. What is meant by line regulation? 3. What is meant by load regulation? 4. Formula for % REGULATION? 5. What is full load in voltage regulation?
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7. DIGITAL TO ANALOG CONVERTER AIM: To construct and study digital to analog converter circuit. APPARATUS: IC 741 Multi meters Patch cards Connecting wires Resistors 1k, 2k, 8k IC bread board trainer
CIRCUIT DIAGRAM: (a) Weighted resistor DAC:
(b)R-2R ladder DAC
33 THEORY: A digital to analog converter is used when a binary output from a digital system must be converted to equivalent analog voltage or current . A DAC converter uses an op amp and binary weighted resistors or R-2r ladder resistors. Weighted resistor DAC: It has n electronic switches –d1, d2, d3……….dn controlled by binary input Word. These switches are single pole double throw type. If the binary input to a particular switch is 1,it connects resistance to the reference voltage (-vr).And if the input is 0,the switch connects the resistor to the ground. The output current I0 for an ideal op amp can be written as I0=I1+I2+…………..In Vr/2Rd1+Vr/4Rd2+…….+Vr/2nRdn=V0=I0Rf=VrRf/R(d1,2….n) The weighted resistor DAC circuit uses a negative reference voltage .The analog output voltage is positive stair case .For a 3bit weighted resistor DAC (1) if the op amp is connected in non inverting mode, it can be connected in non inverting mode also .(2)The op amp is working as current to voltage converter.(3) The polarity of reference voltage is in accordance with type of switch used. R-2R ladder DAC: In binary weighted resistors method are used. This can be avoided by using R-2R ladder type DAC where only 2 values of resistors are required .The binary inputs are simulated by switches B0-B3 and output is proportional to the binary inputs. Binary inputs can be high (+5V) or low(0V).
PROCEDURE: 1. Connections are made as per circuit diagram. 2. Pin2 is connected to resistor 1MΩand ground. 3. +Vcc are available at Pin7 and –Vcc is applied at Pin4. 4. Output is taken between pin6 and ground 5. Voltage at each bit (Vr) is found at bits b0, b1, b2, b3. 6. Pin3 of op amp is connected to resistor 1kΩ and is given to b3 (msb). 7. A resistor of 2kΩ is connected between pin2 and pin 6 of op amp.
34 OBSERVATIONS: D3
D2 D1 D0 Binary weighted R-2R ladder DAC (v)_________________________ resistor(v) Theoretical practical Theoretical practical
RESULT: Thus digital to analog converter is constructed and studied. VIVA QUESTIONS: 1. What is meant by resolution of DAC? 2. What is meant by linearity of DAC? 3. What is meant by accuracy of DAC? 4. What is meant by DAC? 5. What is disadvantage of weighted resistor DAC? 6. What is the value of resistor required in weighted resistor DAC if LSB resistor value is 12KΩ for 4 bit DAC? 7. What are the applications of DAC?
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1. VHDL code for Gates -----------------------------------------------------------------------------------------------------------
Dataflow VHDL code for AND gate -----------------------------------------------------------------------------------------------------------Library IEEE; Use IEEE.std_logic_1164.all; Entity and1 is Port ( a: in STD_LOGIC; b: in std_logic; y: out STD_LOGIC ); end and1; Architecture and1d of and1 is begin y<= a and b ; end and1d; ------------------------------------------------------------------------------------------------------------
Dataflow VHDL code for AND gate using WITH-SELECT -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity and2we is port(a,b:in std_logic; c:out std_logic); end and2we; architecture and2we of and2we is signal d:std_logic_vector(1 downto 0); begin d<=(a&b); with d select c<='0' when "00", '0' when "01", '0' when "10", '1' when "11", 'U' when others; end and2we;
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Sequential VHDL code for AND gate using IF statements -----------------------------------------------------------------------------------------------------------Library ieee; Use ieee.std_logic_1164.all; entity and2if is port( a,b:in std_logic; c:out std_logic ); end and2if; architecture and2if of and2if is begin process(a,b) begin if a='1' and b='1' then c<='1'; else c<='0'; end if; end process; end and2if;
Sequential VHDL code for AND gate using CASE statements -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity andc is port (a: in std_logic_vector(1 downto 0); c: out std_logic ); end andc; architecture andcc of andc is begin process(a) begin case a is when "00"=>c<='0'; when "01"=>c<='0'; when "10"=>c<='0'; when "11"=>c<='1'; when others=>c<='U'; end case; end process; end andcc;
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Dataflow VHDL code for NOT gate -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity inv1 is port (a: in std_logic;y: out std_logic ); end inv1; architecture inv of inv1 is begin y<= not a ; end inv; -----------------------------------------------------------------------------------------------------------
Dataflow VHDL code for NOT gate using WITH-SELECT statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity inv is port(a:in std_logic; c:out std_logic); end inv; architecture inv of inv is begin with a select c<='1' when '0', '0' when '1', 'U' when others; end inv;
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Sequential VHDL code for NOT gate using CASE statement -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity invc is port (a: instd_logic; c: out std_logic); end invc; architecture invcc of invc is begin process(a) begin case a is when '0'=>c<='1'; when '1'=>c<='0'; when others=>c<='U'; end case; end process; end invcc; -----------------------------------------------------------------------------------------------------------
Sequential VHDL code for NOT gate using IF statements -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity invif is port (a: in std_logic; c: out std_logic ); end invif; architecture invcc of invif is begin process(a) begin if a='0'then c<='1'; else c<='0'; end if; end process; end invcc; -----------------------------------------------------------------------------------------------------------
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Dataflow VHDL code for NAND gate statements -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity nand1 is port ( a: in std_logic; b:in std_logic; y: out std_logic ); end nand1;
architecture nand1d of nand1 is begin y<= a nand b ; end nand1d;
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Dataflow VHDL code for NAND gate using WITH-SELECT statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity nand2we is port(a,b:in std_logic; c:out std_logic); end nand2we; architecture nand2we of nand2we is signal d:std_logic_vector(1 downto 0); begin d<=(a&b); with d select c<='1' when "00", '1' when "01", '1' when "10", '0' when "11", 'U' when others; end nand2we;
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Sequential VHDL code for NAND gate using CASE statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity nand2 is port(a,b:in std_logic; c:out std_logic); end nand2; architecture nand2 of nand2 is begin process (a,b) variable d:std_logic_vector(0 to 1); begin d:=(a&b); case d is when "00" => c<='1'; when "01" => c<='1'; when "10" => c<='1'; when "11" => c<='0'; when others=>c<='U'; end case; end process; end nand2; -----------------------------------------------------------------------------------------------------------
Sequential VHDL code for NAND gate using IF statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity nand2if is port(a,b:in std_logic; c:out std_logic); end nand2if; architecture nand2if of nand2if is begin process(a,b) begin if a=b then c<='0'; else c<='1'; end if; end process; end nand2if; -----------------------------------------------------------------------------------------------------------
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Dataflow VHDL code for NOR gate -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity nor1 is port ( a: in std_logic; b:in std_logic; y: out std_logic ); end nor1; architecture nor1d of nor1 is begin y<= a nor b ; end nor1d;
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Dataflow VHDL code for NOR gate using WITH-SELECT statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity norws is port(a,b:in std_logic; c:out std_logic); end norws; architecture nor2ws of norws is signal d:std_logic_vector(1 downto 0); begin d<=(a&b); with d select c<= 1' when "00", 0' when "01", 0' when "10", 0' when "11", 'U' when others; end nor2ws;
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Sequential VHDL code for NOR gate using IF statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity nor2if is port(a,b:in std_logic; c:out std_logic); end nor2if; architecture nord2if of nor2if is begin process(a,b) begin if a='0' and b='0' then c<='1'; else c<='0'; end if; end process; end nord2if; -----------------------------------------------------------------------------------------------------------
Sequential VHDL code for NOR gate using CASE statements -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity norc is port (a: in std_logic_vector(1 downto 0); c: out std_logic ); end norc; architecture norcc of norc is begin process(a) begin case a is when "00"=>c<='1'; when "01"=>c<='0'; when "10"=>c<='0'; when "11"=>c<='0'; when others=>c<='U'; end case; end process; end norcc;
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Dataflow VHDL code for OR gate -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity or1 is port ( a: in std_logic;b:in std_logic; y: out std_logic); end or1; architecture or1d of or1 is begin y<= a or b ; end or1d;
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Dataflow VHDL code for OR gate using WITH-SELECT statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity orws is port(a,b:in std_logic; c:out std_logic); end orws; architecture or2ws of orws is signal d:std_logic_vector(1 downto 0); begin d<=(a&b); with d select c<='0' when "00", '1' when "01", '1' when "10", '1' when "11", 'U' when others; end or2ws;
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Sequential VHDL code for OR gate using IF statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity or2if is port(a,b:in std_logic; c:out std_logic); end or2if; architecture ord2if of or2if is begin process(a,b) begin if a='0' and b='0' then c<='0'; else c<='1'; end if; end process; end ord2if; -----------------------------------------------------------------------------------------------------------
Sequential VHDL code for OR gate using CASE statements -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity ors is port ( a: in std_logic_vector(1 downto 0); c: out std_logic ); end ors; architecture ors of ors is begin process(a) begin case a is when "00"=>c<='0'; when "01"=>c<='1'; when "10"=>c<='1'; when "11"=>c<='1'; when others=>c<='u'; end case; end process; end ors; -----------------------------------------------------------------------------------------------------------
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Dataflow VHDL code for XNOR gate -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity xnor1 is port ( a: in std_logic; b: in std_logic; y: out std_logic ); end xnor1; architecture xnord of xnor1 is begin y<=a xnor b; end xnord;
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Dataflow VHDL code for XNOR gate using WITH-SELECT statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity xnorws is port(a,b:in std_logic; c:out std_logic); end xnorws; architecture xnor2ws of xnorws is signal d:std_logic_vector(1 downto 0); begin d<=(a&b); with d select c<='1' when "00", '0' when "01", '0' when "10", '1' when "11", 'U' when others; end xnor2ws;
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Sequential VHDL code for XNOR gate using IF statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity xnor2if is port(a,b:in std_logic; c:out std_logic); end xnor2if; architecture xnord2if of xnor2if is begin process(a,b) begin if a=b then c<='1'; else c<='0'; end if; end process; end xnord2if; -----------------------------------------------------------------------------------------------------------
Sequential VHDL code for XNOR gate using CASE statements -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity xnorc is port (a: in std_logic_vector(1 downto 0); c: out std_logic ); end xnorc; architecture xnorcc of xnorc is begin process(a) begin case a is when "00"=>c<='1'; when "01"=>c<='0'; when "10"=>c<='0'; when "11"=>c<='1'; when others=>c<='U'; end case; end process; end xnorcc; -----------------------------------------------------------------------------------------------------------
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Dataflow VHDL code for XOR gate -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity xor1 is port ( a: in std_logic;b:in std_logic; y: out std_logic ); end xor1; architecture xor1d of xor1 is begin y<= a xor b ; end xor1d; -----------------------------------------------------------------------------------------------------------
Dataflow VHDL code for XOR gate using WITH-SELECT statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity xorws is port(a,b:in std_logic; c:out std_logic); end xorws; architecture xor2ws of xorws is signal d:std_logic_vector(1 downto 0); begin d<=(a&b); with d select c<='0' when "00", '1' when "01", '1' when "10", '0' when "11", 'U' when others; end xor2ws;
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Sequential VHDL code for XOR gate using IF statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity xor2if is port(a,b:in std_logic; c:out std_logic); end xor2if; architecture xord2if of xor2if is begin process(a,b) begin if a=b then c<='0'; else c<='1'; end if; end process; end xord2if; -----------------------------------------------------------------------------------------------------------
Sequential VHDL code for XOR gate using CASE statements -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity xorc is port (a: in std_logic_vector(1 downto 0); c: out std_logic ) ; end xorc; architecture xorcc of xorc is begin process(a) begin case a is when "00"=>c<='0'; when "01"=>c<='1'; when "10"=>c<='1'; when "11"=>c<='0'; when others=>c<='U'; end case; end process; end xorcc; -----------------------------------------------------------------------------------------------------------
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Dataflow VHDL code for LOGIC gates -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity logicgates is port(a:in std_logic; b:in std_logic; y_and:out std_logic; y_not:out std_logic; y_or:out std_logic; y_nor:out std_logic; y_nand:out std_logic; y_xor:out std_logic ); end logicgates; architecture logicgates_arch of logicgates is begin y_not <= not a; y_and <= a and b; y_nand <= a nand b; y_or <=a or b; y_nor <= a nor b; y_xor <= a xor b; end logicgates_arch; -----------------------------------------------------------------------------------------------------------1) What is the mean by ENTITY? 2) What are the dataflow elements? 3) What are the standard available ICs for AND gate? 4) What is the syntax for SIGNAL declaration? 5) What are the standard available ICs for NAND gate? 6) What is the syntax for ENTITY? 7) What are the standard available ICs for OR gate? 8) What are the standard available ICs for NOR gate? 9) What is the syntax for ARCHITECTURE? 10) What is the syntax for VARIABLE declaration? 11) What are the standard available ICs for XOR gate? 12) What are the Universal gates? 13) What are the structural elements? 14) What is VHDL?
2.VHDL code for D- Flipflop 74x74.
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Sequential VHDL code for 74x74 using IF statements ----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity vdff7474 is port ( D: in std_logic; CLK: in std_logic; PR_L: in std_logic; CLR_L: in std_logic; Q: out std_logic; QN: out std_logic ); end vdff7474; architecture vdff7474 of vdff7474 is signal PR,CLR:std_logic; begin process(CLR_L,CLR,CLK,PR,PR_L) begin PR<=Not PR_L; CLR<=Not CLR_L; if(CLR and PR)='0'then Q<='0';QN<='0'; elsif(CLR='0')then Q<='0';QN<='1'; elsif(PR='0')then Q<='1';QN<='0'; elsif(CLK'event and CLK='1')then Q<=D;QN<=not D; end if; end process; end vdff7474;
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Dataflow VHDL code for 74x74 ----------------------------------------------------------------------------------------------------------Library ieee; use ieee.std_logic_1164.all; entity DFF7474 is port(pr_l,clr_l,clk,d:in std_logic; q,qn:inout std_logic); end DFF7474; Architecture DFF7474d of DFF7474 is signal s1,s2,s3,s4:std_logic; begin s1<= (pr_l nand s2) nand s4; s2<= (clr_l nand clk) nand s1; s3<= (s2 nand clk) nand s4; s4<= (d nand s3) nand clr_l; q<= (pr_l nand s2) nand qn; qn<= (q nand clr_l) nand s3; end dff7474d; -----------------------------------------------------------------------------------------------------------
Structural VHDL code for 74x74 -----------------------------------------------------------------------------------------------------------Library ieee; use ieee.std_logic_1164.all; entity DFF7474 is port(pr_l,clr_l,clk,d:in std_logic; q,qn:inout std_logic); end DFF7474; Architecture DFF7474s of DFF7474 is component NAND1 port(i0,i1,i2 :in std_logic; O:out std_logic); end component; signal s1,s2,s3,s4:std_logic; begin u1:nand1 port map (pr_l,s2,s4,s1); u2:nand1 port map (clr_l,clk,s1,s2); u3:nand1 port map (s2,clk,s4,s3); u4:nand1 port map (d,s3,clr_l,s4); u5:nand1 port map (pr_l,s2,qn,q); u6:nand1 port map (q,clr_l,s3,qn); end DFF7474s; -----------------------------------------------------------------------------------------------------------
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Sequential VHDL code for D-flipflop using IF statements ----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity syndff is port(d,c,clk,clr,pre:in std_logic;q,q0:out std_logic); end syndff; architecture syndff of syndff is begin process(d,c,clk,clr,pre) begin if(clk'event and clk='1') then elsif clk<='0' then q<='1'; q0<='0'; elsif (pre='0') then q<='1'; q0<='0'; end if; end process; end syndff;
3.VHDL code for JK- Flipflop -----------------------------------------------------------------------------------------------------------
Dataflow VHDL code for JK-flipflop using WHEN-ELSE statements ----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity jkff is port ( j: in std_logic; k: in std_logic; pr_l: in std_logic; clr_l: in std_logic; clk: in std_logic; q :buffer std_logic; qn: buffer std_logic); end jkff; architecture jkffd of jkff is begin q<=
'0'when (clr_l='0') else '1'when (pr_l='0') else
53 q when (clk' event and clk='1'and j='0' and k='0') else '0'when(clk'event and clk='1' and j='0' and k='1')else '1'when(clk'event and clk='1' and j='1' and k='0')else not q when(clk'event and clk='1' and j='1' and k='1')else 'U'; qn<=not q; end jkffd; ---------------------------------------------------------------------------------------------------------
Dataflow VHDL code for JK-flipflop using WITH-SELECT statements ----------------------------------------------------------------------------------------------------------Library IEEE; use IEEE.std_logic_1164.all; entity jkff is port ( j: in std_logic; k: in std_logic; pr_l: in std_logic; clr_l: in std_logic; clk: in std_logic; q :buffer std_logic; qn: buffer std_logic ); end jkff; architecture jkffd1 of jkff is signal s:std_logic_vector(0 to 4); begin s<=(j&k&pr_l&clr_l&clk ); with s select q <= ‘0' when "--100", '1' when "--010", q when "00111", '0' when "01111", '1'when "10111", not q when "11111", 'U' when others; end jkffd1;
4). Decade counter – 7490.
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Sequential VHDL code for 74x 90 using IF statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity counter_7490 is port(clk:in std_logic; rst:in std_logic; tc:out std_logic; count:out std_logic_vector(3 downto 0)); end counter_7490; architecture counter_7490_arch of counter_7490 is signal count_int:std_logic_vector(3 downto 0); begin process(clk,rst) begin if rst='1'or count_int="1001" then count_int <="0000"; elsif rising_edge(clk)then count_int <=count_int+1; end if; count <=count_int; if count_int="1001"then tc<='1'; else tc<='0'; end if; end process; end counter_7490_arch;
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Structural VHDL code for 74x90 -----------------------------------------------------------------------------------------------------------Library ieee; use ieee.std_logic_1164.all; entity v7490 is port(a,b,ro1,ro2,rq1,rq2,clk: in std_logic; q:out std_logic_vector(3 downto 0)); end v7490; architecture v7490s of v7490 is component mod5 port(clk,clr,prl:in std_logic; q:out std_logic_vector(3 downto 0)); end component; component jkff port(j,k,clk,clr,prl:in std_logic; q:out std_logic); end component; component NAND2 port(i0,i1 :in std_logic; O:out std_logic); end component; component AND2 port(i0,i1 :in std_logic; O:out std_logic); end component; signal s1,s2,s3,qn:std_logic; begin u1:nand2 port map (ro1,ro2,s1); u2:nand2 port map (rq1,rq2,s2); u3:nand2 port map (s1,s2,s3); u4:jkff port map ('1','1',clk,s1,s2,q(0)); u5:mod5 port map (b,s3,s1,q(3 downto 0)); end v7490s;
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COUNTERS 1) What are the different types counters? 2) What is mean by decade counter? 3) What are the standard available ICs for counters? 4) What are the different control signals of 74x? 5) What is the function of RCO? 6) What are the standard logic levels in VHDL? 7) How to declare temporary signals? 8) What is mean by Positional mapping? 9) What is the difference between Signal and Variable assignment?
5). 4-Bit counter –7493 -----------------------------------------------------------------------------------------------------
Sequential VHDL code for 74x93 using IF-CASE statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity counter is port(clk,clr,ld,enp,ent:in std_logic; d:in unsigned(3 downto 0); q:out unsigned (3 downto 0); rco:out std_logic); end counter; architecture counter_4bit of counter is signal iq:unsigned(3downto 0):="0000"; begin process(clk,ent,iq) begin if(clk'event and clk='1')then if clr='0'then iq<=(others=>'0'); elsif ld<='0'then iq<=d; elsif (ent and ent)='1'then iq<=iq+1; end if; end if; if(iq=15)and (ent='1')then rco<='1'; else rco<='0'; end if; q<=iq; end process; end counter_4bit;
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Sequential VHDL code for 74x93 using IF statements -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port ( clock: in std_logic; clear: in std_logic; en: in std_logic; q: out std_logic_vector (3 downto 0) ); end counter; architecture counter of counter is signal s:std_logic_vector(3 downto 0); begin process(clock,clear) begin if clear='0' then s <="0000"; elsif(clock'event and clock='1') then if en='1' then s<=s+1; else s<=s; end if; end if; end process; q<=s; end counter;
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Structural VHDL code for 74x93 -----------------------------------------------------------------------------------------------------------Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity v74x93 is port(a,clk:in std_logic; b:inout std_logic; ro1:in std_logic; ro2:in std_logic; q:buffer std_logic_vector(3 downto 0)); end v74x93; Architecture v74x93s of v74x93 is signal clr:std_logic; component jkff port(j:in std_logic; k:in std_logic; clk:in std_logic; clr:in std_logic; q:out std_logic); end component; begin clr <= ro1 nand ro2; U1:jkff port map ('1','1',clk,clr,q(0)); U2:jkff port map ('1','1',q(0),clr,q(1)); U3:jkff port map ('1','1',q(1),clr,q(2)); U4:jkff port map ('1','1',q(2),clr,q(3)); end v74x93s;
6). Shift registers- 7495.
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Sequential VHDL code for 74x95 -----------------------------------------------------------------------------------------------------------Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity v74x95 is port(modc:in std_logic; ser:in std_logic; clk1,clk2:in std_logic; a,b,c,d:in std_logic; qa,qb,qc,qd:inout std_logic); end v74x95; Architecture v74x95s of v74x95 is begin Process(modc,clk1,clk2,A,B,C,D) begin if nodc ='1' then QA<= A; QB<= B; QC<= C; QD<= D; elsif modc ='0' then QA<= SER; QB<= QA; QC<= QB; QD<= QC; end if; end if; end process; end v74x95s;
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Structural VHDL code for 74x95 -----------------------------------------------------------------------------------------------------------Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity v74x95 is port(modc:in std_logic; ser:in std_logic; clk1,clk2:in std_logic; a,b,c,d:in std_logic; qa,qb,qc,qd:inout std_logic); end v74x95; Architecture v74x95s of v74x95 is component dff is port(d :in std_logic;clk:in std_logic;q:out std_logic); end component; component andor is port(i0,i1,i2,i3 :in std_logic;o:out std_logic); end component; signal modcn,s1,s2,s3,s4,s5:std_logic;
begin modcn<= not modc; U1:andor port map (ser,modcn,modc,a,s1); U2:andor port map (qa,modcn,modc,b,s2); U3:andor port map (qb,modcn,modc,c,s3); U4:andor port map (qc,modcn,modc,s4); U5:andor port map (clk1,modcn,clk2,modc,s5); U6:dff port map (s1,s5,qa); U7:dff port map (s2,s5,qb); U8:dff port map (s3,s5,qc); U9:dff port map (s4,s5,qd); end v74x95s;
SHIFT REGISTER
61 1) 2) 3) 4) 5) 6) 7) 8)
What is mean by register? What are the different types of shift Registers? What are the standard available ICs for SISO? What are the standard available ICs for PISO? What are the logic operators of VHDL? What are the modes in VHDL? What are the sequential statements? What is the syntax for IF-ELSIF statements?
7). Universal shift registers- 74194/195 ------------------------------------------------------------------------------------------------------------
Sequential VHDL code for 74x 194 using IF-CASE statements -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity reg194 is port ( d: in std_logic_vector (3 downto 0); lin: in std_logic; in: in std_logic; clr: in std_logic;clk: in std_logic; s: in std_logic_vector (1 downto 0); q: out std_logic_vector (3 downto 0) ); end reg194; architecture reg194 of reg194 is begin process(d,lin,rin,clk,clr) variable qt:std_logic_vector(3 downto 0); begin qt:=d; if(clk'event and clk='1')then if(clr='0')then qt:="0000"; else case s is when "00"=>qt:=qt(3 downto 0); when"01"=>qt:=qt(2downto 0)&lin; when "10"=>qt:=rin&qt(2 downto 0); when "11"=>qt:=d; when others=>qt:=d; end case; end if; end if; q<=qt; end process; end reg194; -----------------------------------------------------------------------------------------------------------
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Structural VHDL code for 74x194 -----------------------------------------------------------------------------------------------------------Library ieee; use ieee.std_logic_1164.all; entity v74x194 is port(clk,clr:in std_logic; s:in std_logic_vector(1 downto 0); LIN,RIN:in std_logic; ld:in std_logic_vector(3 downto 0); q:buffer std_logic_vector(3 downto 0 )); end v74x194; Architecture v74x194s of v74x194 is signal q1: std_logic_vector(3 downto 0); component DFF is port(clr,clk,d:in std_logic; q:out std_logic); end component; component and3 is port(i0,i1,i2:in std_logic; o:out std_logic); end component; component or4 is port(i0,i1,i2,i3:in std_logic; o:out std_logic); end component; signal s1:std_logic_vector(0 to 15); signal s2:std_logic_vector(0 to 3); signal ns:std_logic_vector(1 downto 0); signal clkn:std_logic; begin ns(1)<= not s(1);
63 ns(0)<= not s(0); clkn<= not clk; U1:and3 port map (ns(1),ns(0),q(3),s1(0)); U2:and3 port map (ns(1),s(0),q(2),s1(1)); U3:and3 port map (s(1),ns(0),LIN,s1(2)); U4:and3 port map (s(1),s(0),ld(3),s1(3)); U5:and3 port map (ns(1),ns(0),q(2),s1(4)); U6:and3 port map (ns(1),s(0),q(1),s1(5)); U7:and3 port map (s(1),ns(0),q(3),s1(6)); U8:and3 port map (s(1),s(0),ld(2),s1(7)); U9:and3 port map (ns(1),ns(0),q(1),s1(8)); U10:and3 port map (ns(1),s(0),q(0),s1(9)); U11:and3 port map (s(1),ns(0),q(2),s1(10)); U12:and3 port map (s(1),s(0),ld(1),s1(11)); U13:and3 port map (ns(1),ns(0),q(0),s1(12)); U14:and3 port map (ns(1),s(0),rin,s1(13)); U15:and3 port map (s(1),ns(0),q(1),s1(14)); U16:and3 port map (s(1),s(0),ld(0),s1(15)); U17:or4 port map (s1(0),s1(1),s1(2),s1(3),s2(0)); U18:or4 port map (s1(4),s1(5),s1(6),s1(7),s2(1)); U19:or4 port map (s1(8),s1(9),s1(10),s1(11),s2(2)); U20:or4 port map (s1(12),s1(13),s1(14),s1(15),s2(3)); U21:dff port map (clkn,clr,s2(0),q(3)); U22:dff port map (clkn,clr,s2(1),q(2)); U23:dff port map (clkn,clr,s2(2),q(1)); U24:dff port map (clkn,clr,s2(3),q(0)); end v74x194s;
UNIVERSAL SHIFT REGISTERS 1) What is mean by Logical shift? 2) What is mean by CIRCULAR shift? 3) What is mean by Logical shift? 4) What is the syntax for WHEN-ELSE statements? 5) What are the control signals for 74x194? 6) What are the functions of 74x194?
8). 3 – 8 Decoder – 74138.
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Dataflow VHDL code for 74x138 using WITH-SELECT statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity dec138 is port(a:in std_logic_vector(2 downto 0); g,gb_l,gc_l:in std_logic; y_l:out std_logic_vector(7 downto 0)); end dec138; architecture dec138 of dec138 is signal y_t:std_logic_vector(7 downto 0); begin with a select y_t<= "11111110" when "000", "11111101" when "001", "11111011" when "010", "11110111" when "011", "11101111" when "100", "11011111" when "101", "10111111" when "110", "01111111" when "111", "11111111" when others; y_l<= y_t when((g and (not gb_l) and (not gc_l))='1')else "11111111"; end dec138;
65 -----------------------------------------------------------------------------------------------------
Sequential VHDL code for 74x138 using IF-CASE statements -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity dec138 is port ( a: in std_logic_vector(2 downto 0); GA: in std_logic; G1B_L: in std_logic; G2B_L: in std_logic; Y_L: out std_logic_vector(7 downto 0)); end dec138; architecture dec138 of dec138 is begin process(a,GA,G1B_L,G2B_L) variable y_t:std_logic_vector(7 downto 0); begin case a is when "000"=>y_t:="11111110"; when "001"=>y_t:="11111101"; when "010"=>y_t:="11111011"; when "011"=>y_t:="11110111"; when "100"=>y_t:="11101111"; when "101"=>y_t:="11011111"; when "110"=>y_t:="10111111"; when "111"=>y_t:="01111111"; when others=>y_t:="11111111"; end case; if(GA='1'and G1B_L='0'and G2B_L='0')then Y_L<=y_t; else Y_L<="11111111"; end if; end process; end dec138;
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Structural VHDL code for 74x138 -----------------------------------------------------------------------------------------------------------Library ieee; use ieee.std_logic_1164.all; entity v74x138 is port(G1,G2A_L,G2B_L:in std_logic; A:in std_logic_vector(2 downto 0); y_l:out std_logic_vector(0 to 7)); end v74x138; Architecture v74x138s of v74x138 is signal s0,s1,s2,s3,s4,s5,s6,s7: std_logic; component NAND4 port(i0,i1,i2,i3 :in std_logic;O:out std_logic); end component; component NAND3 port(i0,i1,i2 :in std_logic;O:out std_logic); end component; component INV port(i:in std_logic;O:out std_logic); end component; begin U1:INV port map (G1,s0); U2:NAND3 port map (s0,G2A_L,G2B_L,s1); U3:INV port map (A(0),s2); U4:INV port map (A(1),s3); U5:INV port map (A(2),s4); U6:INV port map (s2,s5); U7:INV port map (s3,s6); U8:INV port map (s4,s7); U9:NAND4 port map (s2,s3,s4,s1,Y_L(0)); U10:NAND4 port map (s5,s3,s4,s1,Y_L(1)); U11:NAND4 port map (s2,s6,s4,s1,Y_L(2)); U12:NAND4 port map (s5,s6,s4,s1,Y_L(3)); U13:NAND4 port map (s2,s3,s7,s1,Y_L(4)); U14:NAND4 port map (s5,s3,s7,s1,Y_L(5)); U15:NAND4 port map (s2,s6,s7,s1,Y_L(6)); U16:NAND4 port map (s3,s6,s7,s1,Y_L(7)); end V74x138s;
9). 2- 4 Decoder 74x139
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Dataflow VHDL code for 74x139 using WHEN-ELSE statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity dec139 is port(a:in std_logic_vector (0 to 1); g_l:in std_logic;y_l:out std_logic_vector (0 to 3)); end dec139; architecture dec139 of dec139 is signal x_l:std_logic_vector (0 to 3); begin x_l<= "0111"when a="00"else "1011"when a="01"else "1101"when a="10"else "1110"when a="11"else "1111"; y_l<= x_l when g_l='0'else "1111"; end dec139; -----------------------------------------------------------------------------------------------------------
Dataflow VHDL code for 74x139 using WITH-SELECT statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity dec139 is port(a:in std_logic_vector(0 to 1); g_l:in std_logic; y_l:out std_logic_vector(0 to 3)); end dec139; architecture dec139 of dec139 is signal x_l:std_logic_vector(0 to 3); begin with a select x_l<= "0111" when "00", "1011" when "01", "1101" when "10", "1110" when "11", "1111" when others; y_l<= x_l when g_l='0' else "1111"; end dec139; -----------------------------------------------------------------------------------------------------------
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Sequential VHDL code for 74x139 using IF-CASE statement -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity dec139 is port(a:in std_logic_vector(0 to 1); g_l:in std_logic; y_l:out std_logic_vector(0 to 3)); end dec139; architecture dec139 of dec139 is begin process(a,g_l) begin if(g_l='0') then case a is when "00" => y_l<="0111"; when "01" => y_l<="1011"; when "10" => y_l<="1101"; when "11" => y_l<="1110"; when others => y_l<="1111"; end case; else y_l<="1111"; end if; end process; end dec139;
10). Priority encoder – 74x148
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Dataflow VHDL code for 74x148 using WHEN-ELSE statements -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity prien148 is port ( I: in std_logic_vector(0 to 7); EI_L: in std_logic; GS_L: out std_logic; A:out std_logic_vector(2 downto 0); EO_L: out std_logic ); end prien148; architecture prien148 of prien148 is signal y_t:std_logic_vector(4 downto 0); begin y_t<= "11111" when(EI_L='0')else "00001" when(I(7)='0')else "00101" when(I(6)='0')else "01001" when(I(5)='0')else "01101" when(I(4)='0')else "10001" when(I(3)='0')else "10101" when(I(2)='0')else "11001" when(I(1)='0')else "11101" when(I(0)='0')else "11110"; GS_L<=y_t(1); A<=y_t(4 downto 2); EO_L<=y_t(0); end prien148; DECODERS 1) What are the standard available ICs for Decoder? 2) What are the control signals for 3x8 decoder? 3) What is mean by DECODER? 4) What are the applications of the Decoder? 5) Is process statements is sequential or concurrent? 6) What is the logic value of the outputs of 3X8 Decoder? 7) What is the syntax for CASE statement? 8) How many decoders required for 5X32 decoder? 9) VARIABLE is local to which statement? 10) What are the logic levels of the control signal of 74X138?
11). Bit Comparator – 7485
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Dataflow VHDL code for 74x85 using WHEN-ELSE statements -----------------------------------------------------------------------------------------------------------Library ieee; use ieee.std_logic_1164.all; entity v74x85d is port(a:in std_logic_vector (3 downto 0); b:in std_logic_vector(3 downto 0); altbin:in std_logic; aeqbin:in std_logic; agtbin:in std_logic; altbout,aeqbout,agtbout:out std_logic); end v74x85d; Architecture v74x85d of v74x85d is signal eq,lt,gt:std_logic; begin eq<= '1'when a=b else '0'; lt<= '1'when ab else '0'; agtbout<= gt or (eq and agtbin); aeqbout<= eq and aeqbin; altbout<= eq or (eq and altbin); end v74x85d;
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Sequential VHDL code for 74x 85 using IF statements -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity comparator is port ( a: in std_logic_vector (3 downto 0); b: in std_logic_vector (3 downto 0); agtb: out std_logic; altb: out std_logic; aeqb: out std_logic ); end comparator; architecture comparator of comparator is begin process(a,b) begin if(a=b)then aeqb<='1'; else aeqb<='0'; end if; if(ab)then agtb<='1'; else agtb<='0'; end if; end process; end comparator;
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Structural VHDL code for 74x85 -----------------------------------------------------------------------------------------------------------Library ieee; use ieee.std_logic_1164.all; entity v74x85 is port(a:in std_logic_vector(3 downto 0); b:in std_logic_vector(3 downto 0); altbin:in std_logic; aeqbin:in std_logic; agtbin:in std_logic; altbout,aeqbout,agtbout:out std_logic); end v74x85; Architecture v74x85s of v74x85 is component xnor1 is port(i0,i1:in std_logic; o:out std_logic); end component; component and5 is port(i0,i1,i2,i3,i4:in std_logic; o:out std_logic); end component; component or4 is port(i0,i1,i2,i3:in std_logic; o:out std_logic); end component; component and3 is port(i0,i1,i2:in std_logic; o:out std_logic); end component; component and4 is port(i0,i1,i2,i3:in std_logic; o:out std_logic); end component; signal x3,x2,x1,x0: std_logic; signal eq,gt,lt: std_logic; signal s: std_logic_vector(0 to 7); signal an,bn: std_logic_vector(3 downto 0);
73 begin an<= not a; bn<= not b; U1:xnor1 port map (a(3),b(3),x3); U2:xnor1 port map (a(2),b(2),x2); U3:xnor1 port map (a(3),b(3),x1); U4:xnor1 port map (a(0),b(0),x0); U5:and4 port map (x3,x2,x1,x0,eq); s(0)<=a(3) and bn(3); U6:and3 port map (x3,a(2),bn(2),s(1)); U7:and4 port map (x3,x2,a(1),bn(1),s(2)); U8:and5 port map (x3,x2,x1,a(0),bn(0),s(3)); U9:or4 port map (s(0),s(1),s(2),s(3),gt); s(4)<= an(3) and b(3); U10:and3 port map (x3,an(2),b(2),s(5)); U11:and4 port map (x3,x2,an(1),b(1),s(6)); U12:and5 port map (x3,x2,x1,an(0),b(0),s(7)); U13:and4 port map (s(4),s(5),s(6),s(7),lt); altbout <=lt or (eq and altbin); aeqbout <= eq and aeqbin; agtbout <= gt or (eq and agtbin); end v74x85s;
COMPARATOR
1) What is mean by COMPARATOR? 2) What is mean by magnitude COMPARATOR? 3) What are the standard available comparator ICs? 4) What are the comparator control signals? 5) What are the cascade signal of comparator? 6) What is the syntax for PROCESS statements? 7) How the higher comparator is designed with stadard available ICs? 8) What is the syntax for VARIABLE declaration? 9) Design the two bit comparator using fundamental gates? 10) How many logic levels are there in VHDL? 11) What are the Arithmetic operators in VHDL?
12). 8 x 1 Multiplexer – 74150.
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Dataflow VHDL code for 74x150 using WITH-SELECT -----------------------------------------------------------------------------------------------------------library ieee; use ieee. std_logic_1164.all; entity mux_150 is port (en:in std_logic; s:in std_logic_vector(3 downto 0); d:in std_logic_vector(15 downto 0 ); y0:out std_logic); end mux_150; architecture mux_150_d of mux_150 is signal y0l:std_logic; begin with s select y0l<='d(0)'when"0000", 'd(1)'when "0001", 'd(2)'when "0010", 'd(3)'when "0011", 'd(4)'when "0100", 'd(5)'when "0101", 'd(6)'when "0110", 'd(7)'when "0111", 'd(8)'when "1000", 'd(9)'when "1001", 'd(10)'when "1010", 'd(11)'when "1011", 'd(12)'when "1100", 'd(13)'when "1101", 'd(14)'when "1110", 'd(15)'when "1111", 'U'when others ; end mux_150_d;
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Sequential VHDL code for 74x150 using IF-CASE statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity mux150 is port( e_l:in std_logic; s:in std_logic_vector(3 downto 0); d: in std_logic_vector (15 downto 0);3 y,y_l:out std_logic); end mux150; architecture mux150_b of mux150 is begin process(s) variable y_t:std_logic; begin case s is when "0000"=>y_t:=d(0); when "0001"=>y_t:=d(1); when "0010"=>y_t:=d(2); when "0011"=>y_t:=d(3); when "0100"=>y_t:=d(4); when "0101"=>y_t:=d(5); when "0110"=>y_t:=d(6); when "0111"=>y_t:=d(7); when "1000"=>y_t:=d(8); when "1001"=>y_t:=d(9); when "1010"=>y_t:=d(10); when "1011"=>y_t:=d(11); when "1100"=>y_t:=d(12); when "1101"=>y_t:=d(13); when "1110"=>y_t:=d(14); when "1111"=>y_t:=d(15); when others=>y_t:='U'; end case; if(e_l='0')then y<=y_t; y_l<=not y_t; else y<='0'; y_l<='1'; end if; end process; end mux150_b ; -----------------------------------------------------------------------------------------------------------
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Sequential VHDL code for 74x150 using IF statements -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity mux150 is port ( D: in std_logic_vector(15 downto 0); A: in std_logic_vector(3 downto 0); Y: out std_logic; Y_L: out std_logic; G_L: in std_logic ); end mux150; architecture mux150 of mux150 is begin process(A,G_L,D) begin if(G_L='0')then if(A="0000")then Y<=D(0);Y_L<=not D(0); elsif(A="0001")then Y<=D(1);Y_L<=not D(1); elsif(A="0010")then Y<=D(2);Y_L<=not D(2); elsif(A="0011")then Y<=D(3);Y_L<=not D(3); elsif(A="0100")then Y<=D(4);Y_L<=not D(4); elsif(A="0101")then Y<=D(5);Y_L<=not D(5); elsif(A="0110")then Y<=D(6);Y_L<=not D(6); elsif(A="0111")then Y<=D(7);Y_L<=not D(7); elsif(A="1000")then Y<=D(8);Y_L<=not D(8); elsif(A="1001")then Y<=D(9);Y_L<=not D(9); elsif(A="1010")then Y<=D(10);Y_L<=not D(10); elsif(A="1011")then Y<=D(11);Y_L<=not D(11); elsif(A="1100")then Y<=D(12);Y_L<=not D(12); elsif(A="1101")then Y<=D(13);Y_L<=not D(13); elsif(A="1110")then Y<=D(14);Y_L<=not D(14); elsif(A="1111")then Y<=D(15);Y_L<=not D(15); else Y<='U';Y_L<='U'; end if; else Y<='U'; Y_L<='1'; end if; end process;
end mux150; -----------------------------------------------------------------------------------------------------------
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Structural VHDL code for 74x150 -----------------------------------------------------------------------------------------------------------library ieee; use ieee. std_logic_1164.all; entity mux_150 is port (enl:in std_logic; d:in std_logic_vector(15 downto 0); y0:out std_logic); end mux_150; architecture mux_150_s of mux_150 is begin signal s0,s1,s2,s3,s1l,s2,s3,s0l:std_logic; signal q:std_logic_vector(15 downto 0); component not1 port(i:in std_logic; o:out std_logic); end component ; component and6 port(i:in std_logic_vector(5downto 0 ); o:out std_logic); end component ; component or16 port (i:in std_logic_vector(15downto 0); end component; begin u1:not1 port map(so,s0l); u2:not1 port map(s1,s1l); u3:not1 port map(s2,s2l); u4:not1 port map(s3,s3l); u5:and6 port map(enl,s0l,s1l,s2l,s3l,do,q0); u6:and6 port map(enl,s0,s1l,s2l,s3l,d1,q1); u7:and6 port map(enl,s0l,s1,s2l,s3l,d2,q2); u8:and6 port map(enl,s0,s1,s2l,s3l,d3,q3); u9:and6 port map(enl,s0l,s1l,s2,s3l,d4,q4); u10:and6 port map(enl,s0,s1l,s2,s3l,d5,q5); u11:and6 port map(enl,s0l,s1,s2,s3l,d6,q6); u12:and6 port map(enl,s0l,s1,s2,s3l,d7,q7); u13:and6 port map(enl,s0,s1,s2,s3l,d8,q8); u14:and6 port map(enl,s0,s1l,s2l,s3,d9,q9); u15:and6 port map(enl,s0l,s1,s2l,s3,d1o,q10); u16:and6 port map(enl,s0,s1,s2l,s3,d11,q11); u17:and6 port map(enl,s0l,s1l,s2,s3,d12,q12); u18:and6 port map(enl,s0,s1l,s2,s3,d13,q13); u19:and6 port map(enl,s0l,s1,s2,s3,d14,q14); u20:and6 port map(enl,s0,s1,s2,s3,d15,q15); u21:and16 port map(q0,q1,q2,q3,q4,q5,q6,q7,q8,q9,q10,q11,q12,q13,q14,q15,y0); end mux_150_s;
13). 16 x 1 Multiplexer – 74151
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Dataflow VHDL code for 74x151 using WITH-SELECT -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity mux151 is port ( D: in std_logic_vector(0 to 7); A: in std_logic_vector(0 to 2); Y: out std_logic; Y_L: out std_logic; G_L: in std_logic ); end mux151; architecture mux151d of mux151 is signal y1:std_logic; begin with a select y1 <= d(0)when"000", d(1)when "001", d(2)when "010", d(3)when "011", d(4)when "100", d(5)when "101", d(6)when "110", d(7)when "111", 'U'when others ; y<= y1 when g_l='0' else '0'; y_l<= not y1 when g_l='0' else '0'; end mux151d;
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Sequential VHDL code for 74x151 using IF-CASE statements -----------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity mux151 is port(s:in std_logic_vector(2 downto 0); d: in std_logic_vector (2 downto 0); e_l:in std_logic; y,y_l:out std_logic); end mux151; architecture mux151_b of mux151 is begin process(s) begin variable y_t:std-logic; case s is when "000"=>y_t:=d(0); when "001"=>y_t:=d(1); when "010"=>y_t:=d(2); when "011"=>y_t:=d(3); when "100"=>y_t:=d(4); when "101"=>y_t:=d(5); when "110"=>y_t:=d(6); when "111"=>y_t:=d(7); when others=>y_t:='U'; end case; if(e_l='0') then y<=y_t; y_l<=not y_t; else y<='0'; y_l<='1'; end if; end process; end mux151_b;
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Sequential VHDL code for 74x151 using IF statements -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity mux151 is port ( D: in std_logic_vector(7 downto 0); A: in std_logic_vector(2 downto 0); Y: out std_logic; Y_L: out std_logic; G_L: in std_logic ); end mux151; architecture mux151 of mux151 is begin process(A,G_L,D) begin if(G_L='0')then if(A="000")then Y<=D(0);Y_L<=not D(0); elsif(A="001")then Y<=D(1);Y_L<=not D(1); elsif(A="010")then Y<=D(2);Y_L<=not D(2); elsif(A="011")then Y<=D(3);Y_L<=not D(3); elsif(A="100")then Y<=D(4);Y_L<=not D(4); elsif(A="101")then Y<=D(5);Y_L<=not D(5); elsif(A="110")then Y<=D(6);Y_L<=not D(6); elsif(A="111")then Y<=D(7);Y_L<=not D(7); else Y<='U'; Y_L<='U'; end if; else Y<='U'; Y_L<='1'; end if; end process; end mux151;
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Structural VHDL code for 74x151 -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity mux151 is port ( D: in std_logic_vector(0 to 7); A: in std_logic_vector(0 to 2); Y: inout std_logic; Y_L: out std_logic; G_L: in std_logic ); end mux151; architecture mux151d of mux151 is signal enh,a0n,a1n,a2n :std_logic; signal s:std_logic_vector(0 to 7); component nor8 port(s:in std_logic_vector(0 to 7); o:out std_logic); end component ; component and5 port(i0,i1,i2,i3,i4:in std_logic; o:out std_logic); end component ; component or16 port (i:in std_logic_vector(15downto 0); o:out std_logic); end component ; component inv port(i:in std_logic; o:out std_logic); end component ; begin enh <= not g_l; a0n <=not a(0);a1n<=not a(1);a2n<= not a(2); u1:and5 port map(a0n,a1n,a2n,enh,s(0)); u2:and5 port map(a(0),a1n,a2n,enh,s(1)); u3:and5 port map(a0n,a(1),a2n,enh,s(2)); u4:and5 port map(a(0),a(1),a2n,enh,s(3)); u5:and5 port map(a0n,a1n,a(2),enh,s(4)); u6:and5 port map(a(0),a1n,a(2),enh,s(5)); u7:and5 port map(a0n,a(1),a(2),enh,s(6)); u8:and5 port map(a(0),a(1),a(2),enh,s(7)); u9:nor8 port map(s,y); u10:inv port map(y,y_l); end mux151d;
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MULTIPLEXERS 1) What are the standard available ICs for MULTIPLEXERS? 2) What are the control signals for 74X150? 3) What is mean by MULTIPLEXER? 4) What are the applications of the MULTIPLEXER? 5) What is 74X151? 6) What is 74X153? 7) Write the syntax for WITH-SELECT statement? 8) Design 32X1 multiplexer using standard available Multiplexers? 9) What are the concurrent statements? 10) What is the syntax for COMPONENT declaration?
