Lenovo G470_G570_Compal_LA-6751P_LA ...

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Compal Confidential 2

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G470/G570 DIS+UMA+Muxless M/B Schematics Document Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH ATI Robson/PX3.0,PX4.0

2010-10-22 LA-6751P / LA-6753P

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REV:0.3 www.masteram.su 4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

Cover Page Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet E

1

of

59

A

B

C

D

E

Compal confidential

For 14"(Page 4x) LS6753P PWR/B LS6751P CardReader/B

File Name : G470/G570 WĂŐĞϮϯͲϯϬ

AMD Robson XT

Intel Sandy Bridge

1

VRAM 64*16 DDR3*4

BANK 0, 1, 2, 3

WĂŐĞϱͲϭϭ

100MHz 2.7GT/s

WĂŐĞϯϮ

CRT Connector

FDI *8

Up to 8GB Dual Channel DDR3 1066MHz(1.5V) DDR3 1333MHz(1.5V)

2

Audio Jacks

WĂŐĞϯϵ

PCI-E x1 *6

USB2.0 *14

Camera Conn. BlueTooth Conn. WĂŐĞϰϮ

SATA *6 WĂŐĞϭϰͲϮϮ

WĂŐĞϯϲ RJ-45 Connector

PCI Express

Mini Card Slot *1 WĂŐĞϯϰ

SPIROM BIOS

Card Reader Reltek

LPC BUS PCI-E(WLAN)

WĂŐĞϰϬ

EC

Mini Card Slot *1

RTS5139 SDXC/MMC/MS/xD

ENE KB930 ENE KB9012

USB(WiMAX)

WLAN WiMAX

Int. MIC

CX20671

AR8151-B(GLAN) AR8152-B(10/100)

3

2 channel speaker

Audio Codec Conexant

AZALIA

FCBGA 989 25mm*25mm

WĂŐĞϯϱ

WĂŐĞϭϮͲϭϯ

DMI *4

Intel Cougar Point

LVDS WĂŐĞϯϭ Connector LAN Athros

DDR3 SO-DIMM *2

Socket-rPGA988B 37.5mm*37.5mm

HDMI Connector

2

1

PCI-E x16

WĂŐĞϯϯ

For 15"(Page 4x+1) LS6753P PWR/B LS6751P CardReader/B LS6754P LED/B LS6755P ODD/B

3

USB2.0 *1(Right)

WĂŐĞϯϰ

Touch Pad Thermal Sensor EMC1403

USB2.0 *2(Left)

Int. KBD

WĂŐĞϯϳ

SPI ROM WĂŐĞϰϭ

eSATA+USB(Left) WĂŐĞϰϮ SATA3 HDD SATA ODD

WĂŐĞϯϴ

(Port 0/Port 1 support SATA3)

WĂŐĞϯϴ

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

Block Diagram Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet E

2

of

59

A

B

C

D

Voltage Rails

SIGNAL

STATE

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

+VALW

+V

+VS

Clock

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

ON

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

Full ON +5VS

E

+3VS power plane

+1.5VS +VCCP

1

+1.5V

+5VALW

1

+CPU_CORE

+B

+VGA_CORE +3VALW

+GFX_CORE

BOARD ID Table

+1.8VS State

Board ID / SKU ID Table for AD channel

+0.75VS

Board ID 0 1 2 3 4 5 6 7

+1.05VS

S0

O

O

O

O

S3

O

O

O

X

O

O

X

X

O

X

X

X

X

X

X

PCB Revision 0.1

Vcc Ra/Rc/Re Board ID

0 1 2 3 4 5 6 7

3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC

V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V

V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V

V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V

EVT DVT PVT MP

2

2

S5 S4/AC

USB Port Table

S5 S4/ Battery only S5 S4/AC & Battery don't exist

X

USB 2.0 USB 1.1 Port

EC SM Bus2 address

Device Smart Battery

0001 011X b

UHCI1

Address

Device Thermal Sensor EMC1403-2

1001_101xb

Thermal Sensor EMC1402-1

100_1100 b

0 1 2 3 4 5 6 7 8 9 10 11 12 13

UHCI0

Address

EC SM Bus1 address

BOM Structure Table

EHCI1 UHCI2 UHCI3

PCH SM Bus address 3

UHCI4

Device

Address

DDR DIMM0

1001 000Xb

DDR DIMM2

1001 010Xb

EHCI2

UHCI5 UHCI6

BTO Item UMA and PX bus Discrete Only

BOM Structure PX@ DIS@ PX3.0 only, not for BACO PX3@ BACO BACO@ COMMON HDMI HDMI@ UMA HDMI UMA_HDMI@ Discrete HDMI VGA_HDMI@ eSATA ESATA@ Blue Tooth BT@ Connector ME@ 45 LEVEL 45@ 10/100 LAN 8152@ GIGA LAN GIGA@ Cameara CMOS@

3 External USB Port USB/B (Right Side) USB Port (Left Side) USB Port (Left Side) USB Port (Left Side) Camera

Mini Card(WLAN)

Card Reader Blue Tooth

SMBUS Control Table SOURCE SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 SMBCLK SMBDATA SML0CLK SML0DATA 4

SML1CLK SML1DATA

KB930 +3VALW KB930 +3VALW PCH +3VALW PCH +3VALW PCH +3VALW

VGA

WLAN WWAN

Thermal Sensor

BATT

KE930

SODIMM

V

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

V

X

X

+3VS

+3VALW

Unpop

X V

+3VS

+3VS

V

X

X

X

X

X

X

X

V

X

X

V

X

+3VS

+3VS

4

2010/07/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

@

PCH

+3VS

V

3

C

D

Title

Notes List Size B Date:

Document Number

Rev 0.2

LA-6751P Friday, November 26, 2010

Sheet E

3

of

59

5

4

3

Power-Up/Down Sequence

KŽƉƚŝŽŶ͗ Wͺ'W/KϬ͗,ŝŐŚͲхEŽƌŵĂůŽƉĞƌĂƚŝŽŶ;Ě'WhŝƐŶŽƚƌĞƐĞƚŽŶKŵŽĚĞͿ Wͺ'W/Kϭ͗>ŽǁͲхĚ'WhWŽǁĞƌK&&͖,ŝŐŚͲхĚ'WhWŽǁĞƌKE;ĂůǁĂǇƐ,ŝŐŚͿ

2. VDDR3 should ramp-up before or simultaneously with VDDC. 3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. 4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and VDD_CT have ramped up. 5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to ramp-up (or vice versa).)

VDDR3(3.3VGS)

Note: Do not drive any IOs before VDDR3 is ramped up.

PCIE_VDDC(1.0V) C

1

Wͺ'W/KϬ͗>ŽǁͲхZĞƐĞƚĚ'Wh͖,ŝŐŚͲхEŽƌŵĂůŽƉĞƌĂƚŝŽŶ Wͺ'W/Kϭ͗>ŽǁͲхĚ'WhWŽǁĞƌK&&͖,ŝŐŚͲхĚ'WhWŽǁĞƌKE

1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred.

D

2

tŝƚŚŽƵƚKŽƉƚŝŽŶ͗

VDDR1(1.5VGS)

Ě'WhWŽǁĞƌWŝŶƐ

sŽůƚĂŐĞ

Wyϯ͘Ϭ

KDŽĚĞ DĂǆĐƵƌƌĞŶƚ

W/ͺWs͕W/ͺsZ͕d^s͕sZϰ͕sͺd͕ WͺWs͕W΀&͗΁ͺsϭϴ͕W΀͗΁ͺWs͕ W΀͗΁ͺsϭϴ͕s͕sϭ/͕ϮsY͕sϮ/͕ W>>ͺWs͕DWsϭϴ͕ĂŶĚ^Wsϭϴ

ϭ͘ϴs

K&&

KE

ϭϲϳϵŵ

W΀&͗΁ͺsϭϬ͕W΀͗΁ͺsϭϬ͕W>>ͺs͕ĂŶĚ ^WsϭϬ

ϭ͘Ϭs

K&&

KE

ϱϳϱŵ

W/ͺs

ϭ͘Ϭs

K&&

KE

Ϯ

sZϯ͕ĂŶĚϮs

ϯ͘ϯs

K&&

KE

ϭϵϬŵ

/&ͺs;ĐƵƌƌĞŶƚĐŽŶƐƵŵƉƚŝŽŶсϱϱŵΛϭ͘Ϭs͕ŝŶ KŵŽĚĞͿ

^ĂŵĞĂƐ s

K&&

KE ^ĂŵĞĂƐ W/ͺs

ϳϬŵ

sZϭ

ϭ͘ϱs

K&&

K&&

Ϯ͘ϴ

sͬs/

ϭ͘ϭϮs

K&&

K&&

ϭϮ͘ϵ

D

C

VDDC/VDDCI(1.12V) VDD_CT(1.8V)

ŝ'Wh

PE_GPIO0

PE_EN

Ě'Wh

PERSTb

K^ǁŝƚĐŚ

BIF_VDDC PE_GPIO1

REFCLK

PX_mode

нϯ͘ϯs>t

B

Straps Reset

нϭ͘Ϭs

Straps Valid

MOS

Regulator

ϭ Ϯ

нϯ͘ϯs'^

нϭ͘Ϭs'^

B

нϭ͘ϱs

SI4800

ϯ

Regulator

ϰ

нϭ͘ϱs'^

Global ASIC Reset нϭ͘ϴs

SI4800

T4+16clock

ϱ

н

нϭ͘ϴs'^

нs'ͺKZ

PWRGOOD

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/07/12

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

dGPU Block Diagram Size B Date:

Document Number

Rev 0.2

LA-6751P Friday, November 26, 2010

Sheet 1

4

of

59

5

4

3

2

D

1 R1 24.9_0402_1%

1K_0402_5% 2 DIS@

1 R2

FDI_FSYNC0

1K_0402_5% 2 DIS@

1 R3

FDI_FSYNC1

1K_0402_5% 2 DIS@

1 R4

FDI_INT

1K_0402_5% 2 DIS@

1 R5

FDI_LSYNC0

1K_0402_5% 2 DIS@

1 R6

FDI_LSYNC1

+1.05VS

DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3]

<16> <16> <16> <16>

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

B28 B26 A24 B23

DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3]

<16> <16> <16> <16>

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

G21 E22 F21 D21

DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3]

<16> <16> <16> <16>

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

G22 D22 F20 C21

DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]

<16> <16> <16> <16> <16> <16> <16> <16>

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

A21 H19 E19 F18 B21 C20 D18 E17

<16> <16> <16> <16> <16> <16> <16> <16>

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

A22 G19 E20 G18 B20 C19 D19 F17

<16> FDI_FSYNC0 <16> FDI_FSYNC1 FDI_INT

1

<16>

<16> FDI_LSYNC0 <16> FDI_LSYNC1

R7 24.9_0402_1%

J18 J17

FDI_INT

H20

FDI_LSYNC0 FDI_LSYNC1

J19 H17

FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC

2

B

FDI_FSYNC0 FDI_FSYNC1

FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3]

DMI

B27 B25 A25 B24

eDP_HPD

A18 A17 B16 C15 D15 C17 F16 C16 G15 C18 E16 D16 F15

eDP_COMPIO eDP_ICOMPO eDP_HPD eDP_AUX eDP_AUX# eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3]

eDP

EDP_COMP

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms

eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3]

PCI EXPRESS* - GRAPHICS

DISCRETE ONLY

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

Intel(R) FDI

C

<16> <16> <16> <16>

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

J22 J21 H22

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

D

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils - typical impedance = 14.5 mohms

+1.05VS

2

JCPU1A

1

PEG_COMP

PCIE_CRX_GTX_N[0..15] <23>

PCIE_CRX_GTX_N15 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_N10 PCIE_CRX_GTX_N9 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N0

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # socket pin map definition

CFG2

*

definition matches

0:Lane Reversed C

PCIE_CRX_GTX_P[0..15] <23>

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

PCIE_CRX_GTX_P15 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P0

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

PCIE_CTX_GRX_C_N15 PCIE_CTX_GRX_C_N14 PCIE_CTX_GRX_C_N13 PCIE_CTX_GRX_C_N12 PCIE_CTX_GRX_C_N11 PCIE_CTX_GRX_C_N10 PCIE_CTX_GRX_C_N9 PCIE_CTX_GRX_C_N8 PCIE_CTX_GRX_C_N7 PCIE_CTX_GRX_C_N6 PCIE_CTX_GRX_C_N5 PCIE_CTX_GRX_C_N4 PCIE_CTX_GRX_C_N3 PCIE_CTX_GRX_C_N2 PCIE_CTX_GRX_C_N1 PCIE_CTX_GRX_C_N0

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

PCIE_CTX_GRX_N15 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N0

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PCIE_CTX_GRX_C_P15 PCIE_CTX_GRX_C_P14 PCIE_CTX_GRX_C_P13 PCIE_CTX_GRX_C_P12 PCIE_CTX_GRX_C_P11 PCIE_CTX_GRX_C_P10 PCIE_CTX_GRX_C_P9 PCIE_CTX_GRX_C_P8 PCIE_CTX_GRX_C_P7 PCIE_CTX_GRX_C_P6 PCIE_CTX_GRX_C_P5 PCIE_CTX_GRX_C_P4 PCIE_CTX_GRX_C_P3 PCIE_CTX_GRX_C_P2 PCIE_CTX_GRX_C_P1 PCIE_CTX_GRX_C_P0

C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

PCIE_CTX_GRX_P15 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P0

PCIE_CTX_GRX_N[0..15] <23>

B

PCIE_CTX_GRX_P[0..15] <23>

Sandy Bridge_rPGA_Rev1p0 ME@

A

A

Compal Secret Data

Security Classification Issued Date

2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet 1

5

of

59

5

4

3

2

1

JCPU1B D

D

AN34

PROC_SELECT# SKTOCC#

+1.05VS

R15 56_0402_5% 1 2

H_PROCHOT#

<40> H_PROCHOT#

<19> H_THRMTRIP#

AL33

H_PECI

AN33

PECI

H_PROCHOT#_R

AL32

PROCHOT#

H_THRMTRIP#

AN32

AM34

H_CPUPWRGD_R 2

2

AP33

R29 1 2 PM_DRAM_PWRGD_R 130_0402_5%

PM_SYNC

V8

UNCOREPWRGOOD

SM_DRAMPWROK

1

R27 10K_0402_5%

BUF_CPU_RST#

AR33

RESET#

+3VALW

C33 0.1U_0402_16V4Z

1

2 2

1 1K_0402_5% 1 1K_0402_5%

DG1.0

SM_DRAMRST#

R8

H_DRAMRST#

AK1 A5 A4

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

AP29 AP27

XDP_PRDY# XDP_PREQ#

AR26 AR27 AP30

XDP_TCK XDP_TMS XDP_TRST#

XDP_TMS XDP_TDI XDP_TDO

AR28 AP26

XDP_TDI XDP_TDO

XDP_TCK R24 XDP_TRST# R25

+1.05VS

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

H_DRAMRST# <7>

R16 R17 R18

1 140_0402_1% 1 25.5_0402_1% 1 200_0402_1%

2 2 2

DDR3 Compensation Signals

THERMTRIP#

R26 0_0402_5%1

<19> H_CPUPWRGD

R12 R13

A16 A15

TCK TMS TRST#

JTAG & BPM

H_PM_SYNC_R

CLK_CPU_DMI <15> CLK_CPU_DMI# <15>

CATERR#

PWR MANAGEMENT

R22 0_0402_5% 1 2

<16> H_PM_SYNC

DG1.0

DPLL_REF_CLK DPLL_REF_CLK#

PRDY# PREQ# C

R11

0_0402_5% 1 2 1 2 0_0402_5%

DDR3 MISC

2

<19,40> H_PECI

H_CATERR#

THERMAL

1

closs to EC 250~750mils

R9 62_0402_5%

BCLK BCLK#

CLOCKS

C26

<18> H_SNB_IVB#

MISC

R10 CLK_CPU_DMI_R CLK_CPU_DMII#_R

A28 A27

TDI TDO

DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

AL35 XDP_DBRESET#

+1.05VS

R28

R20 R21 R23

2 2 2

1 51_0402_5% 1 51_0402_5% 1 51_0402_5%

C

PU/PD for JTAG signals

1 51_0402_5% 1 51_0402_5%

2 2

1 1K_0402_5%

2

@

+3VS

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

Sandy Bridge_rPGA_Rev1p0 ME@

2

Buffered reset to CPU

10/12 reserve R880 / R882 +1.5V_CPU_VDDQ

B

1

+1.05VS

O 3

A

4

1

PM_SYS_PWRGD_BUF

74AHC1G09GW_TSSOP5

D

S

2 G

R34 43_0402_1% 1 2 1

BUF_CPU_RST#

U2 BUFO_CPU_RST# 4

SN74LVC1G07DCKR_SC70-5

NC

Y A

3V

1 2

PLT_RST#

PLT_RST# <18>

3

1 2 SUSP

3

@ R33 39_0402_5%

<10,44,51> SUSP

2

R32 75_0402_5%

5

B

1

P

2

C34 0.1U_0402_16V4Z

2

1

G

U1

R161 100K_0402_5% 1 2

<16> PM_DRAM_PWRGD

R30 200_0402_5%

@ Q1 2N7002H_SOT23-3 Change footprint 20100814

R35 @ 0_0402_5% 2

R880 @ 2

2

0_0402_5% 1

+3VS

1

+3VS

R882 @ 2

5

<16> SYS_PWROK

0_0402_5% 1

P

<16,40> PCH_POK

G

B

A

A

Compal Secret Data

Security Classification Issued Date

2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet 1

6

of

59

5

4

3

2

JCPU1D

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

D

C

<12> DDR_A_BS0 <12> DDR_A_BS1 <12> DDR_A_BS2

B

<12> DDR_A_CAS# <12> DDR_A_RAS# <12> DDR_A_WE#

C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

AE10 AF10 V6

SA_BS[0] SA_BS[1] SA_BS[2]

AE8 AD9 AF9

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

<12> DDR_A_D[0..63]

SA_CLK[0] SA_CLK#[0] SA_CKE[0]

AB6 AA6 V9

M_CLK_DDR0 <12> <13> DDR_B_D[0..63] M_CLK_DDR#0 <12> DDR_CKE0_DIMMA <12>

SA_CLK[1] SA_CLK#[1] SA_CKE[1]

AA5 AB5 V10

M_CLK_DDR1 <12> M_CLK_DDR#1 <12> DDR_CKE1_DIMMA <12>

RSVD_TP[1] RSVD_TP[2] RSVD_TP[3]

AB4 AA4 W9

RSVD_TP[4] RSVD_TP[5] RSVD_TP[6]

AB3 AA3 W10

SA_CS#[0] SA_CS#[1] RSVD_TP[7] RSVD_TP[8]

AK3 AL3 AG1 AH1

DDR_CS0_DIMMA# <12> DDR_CS1_DIMMA# <12>

SA_ODT[0] SA_ODT[1] RSVD_TP[9] RSVD_TP[10]

AH3 AG3 AG2 AH2

M_ODT0 <12> M_ODT1 <12>

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

C4 G6 J3 M6 AL6 AM8 AR12 AM15

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS#[0..7]

D4 F6 K3 N6 AL5 AM9 AR11 AM14

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_DQS[0..7]

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

<12>

<12>

DDR_A_MA[0..15] <12>

<13> DDR_B_BS0 <13> DDR_B_BS1 <13> DDR_B_BS2

<13> DDR_B_CAS# <13> DDR_B_RAS# <13> DDR_B_WE#

Sandy Bridge_rPGA_Rev1p0 ME@

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

AA9 AA7 R6

SB_BS[0] SB_BS[1] SB_BS[2]

AA10 AB8 AB9

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

JCPU1C

1

SB_CLK[0] SB_CLK#[0] SB_CKE[0]

AE2 AD2 R9

M_CLK_DDR2 <13> M_CLK_DDR#2 <13> DDR_CKE2_DIMMB <13>

SB_CLK[1] SB_CLK#[1] SB_CKE[1]

AE1 AD1 R10

M_CLK_DDR3 <13> M_CLK_DDR#3 <13> DDR_CKE3_DIMMB <13>

RSVD_TP[11] RSVD_TP[12] RSVD_TP[13]

AB2 AA2 T9

RSVD_TP[14] RSVD_TP[15] RSVD_TP[16]

AA1 AB1 T10

SB_CS#[0] SB_CS#[1] RSVD_TP[17] RSVD_TP[18]

AD3 AE3 AD6 AE6

DDR_CS2_DIMMB# <13> DDR_CS3_DIMMB# <13>

SB_ODT[0] SB_ODT[1] RSVD_TP[19] RSVD_TP[20]

AE4 AD4 AD5 AE5

M_ODT2 <13> M_ODT3 <13>

D7 F3 K6 N3 AN5 AP9 AK12 AP15

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS#[0..7]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

C7 G3 J6 M3 AN6 AP8 AK11 AP14

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_DQS[0..7]

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

D

<13>

C

<13>

DDR_B_MA[0..15] <13>

B

Sandy Bridge_rPGA_Rev1p0 ME@

R37 1K_0402_5% R38 1K_0402_5% 2

2

@ R36 0_0402_5% 1 2

1

+1.5V

D

S

H_DRAMRST#

3

1

2

<6> H_DRAMRST#

1

DDR3_DRAMRST# <12,13>

Q2 BSS138_NL_SOT23-3

1

2

G

R39 4.99K_0402_1%

DDR3_DRAMRST#_R

A

R40 0_0402_5% 1 2

<15> DRAMRST_CNTRL_PCH

A

DRAMRST_CNTRL

1

2

C35 0.047U_0402_16V4Z

Eiffel used 0.01u Module design used 0.047u

Compal Secret Data

Security Classification Issued Date

2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. PROCESSOR(3/7) DDRIII

Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet 1

7

of

59

5

4

3

2

1

CFG Straps for Processor

1

CFG2

2

R41 1K_0402_1% D

JCPU1E

RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35

AT26 AM33 AJ27

R353 1K_0402_1% 2

R64 1K_0402_1% 2

RSVD6 RSVD7

1

1

B4 D1

2

VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE RSVD5

8/5 Check

B

F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 J20 B18 A19 J15

RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23

R42 1K_0402_1%

RSVD37 RSVD38 RSVD39 RSVD40

T8 J16 H16 G16

RSVD41 RSVD42 RSVD43 RSVD44 RSVD45

AR35 AT34 AT33 AP35 AR34

RSVD46 RSVD47 RSVD48 RSVD49 RSVD50

B34 A33 A34 B35 C35

RSVD51 RSVD52

AJ32 AK32

RSVD24 RSVD25 VCCIO_SEL

*

CFG4

VCC_DIE_SENSE

C

1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG6 CFG5 1

AJ26

0:Lane Reversed CFG4

@ R43 1K_0402_1%

@ R44 1K_0402_1% 2

AJ31 AH31 AJ33 AH33

definition matches

Display Port Presence Strap

RESERVED

PAD PAD PAD PAD

*

@

C

T9 T10 T11 T12

1: Normal Operation; Lane # socket pin map definition

CFG2

1

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17]

1

CFG4 CFG5 CFG6 CFG7

PEG Static Lane Reversal - CFG2 is for the 16x L7 AG7 AE7 AK2 W8

PAD

AH27

2

CFG2

AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29

D

T13

PCIE Port Bifurcation Straps RSVD54 RSVD55

AN35 AM35

11: (Default) x16 - Device 1 functions 1 and 2 disabled

CFG[6:5] RSVD56 RSVD57 RSVD58

*10: x8, x8 - Device 1 function 1 enabled ; function 2

B

disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

AT2 AT1 AR1

RSVD27 B1

CFG7 1

KEY

@R45 @ R45 1K_0402_1% 2

Sandy Bridge_rPGA_Rev1p0 ME@

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training

A

Compal Secret Data

Security Classification Issued Date

2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

A

Compal Electronics, Inc. PROCESSOR(4/7) RSVD,CFG

Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet 1

8

of

59

5

4

3

JCPU1F

Cap quantity follow HR_PDDG_Rev07

@

2

1

+

+

C69 220U_6.3V_M

2

D

1 C72 220U_6.3V_M

2

+

@

2

OSCAN (220uF_6.3V_4.2L_ESR17m)*2=(SF000002Y00)

C73 330U_D2_2.5VY_R9M

PEG AND DDR

2

2

C47 22U_0805_6.3V6M

1

1

@

1

C65 22U_0805_6.3V6M

2

2

C56 22U_0805_6.3V6M

2

1

@

C64 22U_0805_6.3V6M

1

@

2

1

C55 22U_0805_6.3V6M

2

2

1

C63 22U_0805_6.3V6M

1

@

1

C46 22U_0805_6.3V6M

2

2

C62 22U_0805_6.3V6M

2

1

@

C45 22U_0805_6.3V6M

A

C

1

+1.05VS

SVID

2

R46 75_0402_5%

VIDALERT# VIDSCLK VIDSOUT

AJ29 AJ30 AJ28

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

R47 R48 R49

1 1 1

2 43_0402_5% 2 0_0402_5% 2 0_0402_5%

R50

2

1 130_0402_5%

VR_SVID_CLK series-resistors close to VR VR_SVID_ALRT# <53> VR_SVID_CLK <53> VR_SVID_DAT <53>

+1.05VS B

VCC_SENCE 100ohm +-1% pull-up to VCC near processor

1

+CPU_CORE

AJ35 VCCSENSE_R AJ34 VSSSENSE_R

R52 R53

1 1

0_0402_5% 0_0402_5%

2 2

VCCSENSE <53> VSSSENSE <53> 1

VCC_SENSE VSS_SENSE

2

R51 100_0402_1%

VCCIO_SENSE VSSIO_SENSE

B10 A10

1

2 R74 0_0402_5% @

R54 100_0402_1%

VCCIO_SENSE <51> VSSIO_SENSE

1

2

2

+ 2

1

@

2

1

C61 22U_0805_6.3V6M

10/21 modify

1

2

1

2

1

C54 22U_0805_6.3V6M

+ 2

C400

J23

2

1

2

1

C60 22U_0805_6.3V6M

@

1

VCCIO40

1

2

1

C44 22U_0805_6.3V6M

+ 2

C397

330U_X_2VM_R6M

@

1

330U_X_2VM_R6M

+ 2

C394

330U_X_2VM_R6M

@

+ 2

1

C91 330U_X_2VM_R6M

+ 2

1

C90 330U_X_2VM_R6M

2

1

C89 330U_X_2VM_R6M

+

(330uF)*4

C88 330U_X_2VM_R6M

1

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

2

1

C59 22U_0805_6.3V6M

B

VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

+1.05VS 1

C43 22U_0805_6.3V6M

+CPU_CORE

AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12

C58 22U_0805_6.3V6M

2

C87 22U_0805_6.3V6M

1

C83 22U_0805_6.3V6M

2

C78 22U_0805_6.3V6M

2

1

@

C86 22U_0805_6.3V6M

1

2

C71 22U_0805_6.3V6M

2

1

C82 22U_0805_6.3V6M

1 @

2

C77 22U_0805_6.3V6M

2

2

1

C70 22U_0805_6.3V6M

1

1

C85 22U_0805_6.3V6M

2

2

C84 22U_0805_6.3V6M

1

1

C81 22U_0805_6.3V6M

2

2

2

C76 22U_0805_6.3V6M

1

1

C80 22U_0805_6.3V6M

2

C79 22U_0805_6.3V6M

1

2

2

C75 22U_0805_6.3V6M

2

1

C74 22U_0805_6.3V6M

1

C

2

1

C68 22U_0805_6.3V6M

2

1

C67 22U_0805_6.3V6M

@

1

C66 22U_0805_6.3V6M

1

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

C42 22U_0805_6.3V6M

(22uF_0805_6.3V)*16

+CPU_CORE

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100

+1.05VS

OSCAN(22uF_0805_6.3V)*13

C57 22U_0805_6.3V6M

2

22uF*7 NO-STUFF

18A AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26

C41 22U_0805_6.3V6M

C53 10U_0603_6.3V6M

@

2

1

C52 10U_0603_6.3V6M

2

1

C51 10U_0603_6.3V6M

1

2

C40 10U_0805_6.3V6M

2

1

C39 10U_0805_6.3V6M

2

C50 10U_0603_6.3V6M

1

1

C38 10U_0805_6.3V6M

2

2

C49 10U_0603_6.3V6M

1

1

C37 10U_0805_6.3V6M

2

2

C48 10U_0603_6.3V6M

1

C36 10U_0805_6.3V6M

2

D

1

QC=94A DC=53A

SENSE LINES

(6/16 change 10uF_0603_6.3V)*5 1

1

POWER

CORE SUPPLY

+CPU_CORE

2

R75 0_0402_5% @

VSS_SENCE 100ohm +-1% pull-down to GND near processor 8/12 Modify, need follow diffential routing R74 close CPU,R75 close PWR

Sandy Bridge_rPGA_Rev1p0 Security Classification ME@

Issued Date

Compal Secret Data 2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. PROCESSOR(5/7) PWR,BYPASS

Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet 1

9

of

59

A

4

3

+1.5V

<6,44,51> SUSP

2

1 1

15K_0402_1%

2

+1.5V_CPU_VDDQ

1

2

1

2

1

2

D

2

2

@

1

4

R667 100K_0402_5%

2 G S

@ C396 0.1U_0402_10V6K

R56

@ RUN_ON_CPU1.5VS3#

C129 0.1U_0402_10V6K

8/27 change to @

2 D

Q3 2N7002H_SOT23-3 Change footprint 20100814

DMN3030LSS-13_SOP8L-8 8 1 7 2 6 3 5

C96 0.1U_0402_10V6K

+VSB

C92 0.1U_0402_10V6K C95 0.1U_0402_10V6K

U3

D

@

R55 220_0402_5%

+3VALW

+1.5V

1

1

PAD-OPEN 4x4m

2 R668

12

1 0_0402_5%

1

+1.5V_CPU_VDDQ

@ J1 1

8/27 change to stuff

2

3

5

1

1

Q4 2N7002H_SOT23-3

2 G Change footprint 20100814

S

@ 1 2 0_0402_5% R59

S

Change footprint 20100814

PX@

10/21 Change

SENSE LINES MISC

2 1

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

1 2 2

10/5 change to 1K

+1.5V_CPU_VDDQ VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

1 R63 1K_0402_1%

2 RUN_ON_CPU1.5VS3

1 1

2

1

2

1

1

2

2

1

2

1

2

+

C123 330U_2.5V_M

2

B

+VCCSA VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

VCCSA_SENSE

+VCCSA

M27 M26 L26 J26 J25 J24 H26 H25

@ 1

2

1

2

1

1

2

2

R65 1 +

2 R66

VCCSA_SENSE

H23

C128 330U_D2_2.5VY_R9M

1.8V RAIL

Q5 @ AP2302GN-HF_SOT23-3

C122 10U_0603_6.3V6M

2

VCCPLL1 VCCPLL2 VCCPLL3

+V_SM_VREF

1

100K_0402_5% R666 @

C121 10U_0603_6.3V6M

2

2

B6 A6 A2

1

C127 10U_0805_6.3V6M

1

1

C132 1U_0402_6.3V6K

@

1

C131 1U_0402_6.3V6K

2

C130 10U_0805_6.3V6M

@

C345 22U_0805_6.3V6M

C154 22U_0805_6.3V6M

2

1

3

C114 0.1U_0402_16V4Z

C126 10U_0805_6.3V6M

+1.8VS_VCCPLL 1

+V_SM_VREF_CNT

C125 10U_0805_6.3V6M

R67 0_0805_5% 1 2

AL1

C124 10U_0805_6.3V6M

+1.8VS

SM_VREF

2

Sandy Bridge_rPGA_Rev1p0 ME@

C

R62 1K_0402_1%

C120 10U_0603_6.3V6M

B

+1.5V_CPU_VDDQ R61 0_0402_5% 2 1

C119 10U_0603_6.3V6M

2

@

VCC_AXG_SENSE <53> VSS_AXG_SENSE <53>

C118 10U_0603_6.3V6M

2

+

AK35 AK34

C117 10U_0603_6.3V6M

PX@

1

C116 330U_D2_2.5VY_R9M

+

C115 330U_D2_2.5VY_R9M

1

VAXG_SENSE VSSAXG_SENSE

VREF

PX@

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54

DDR3 -1.5V RAILS

PX@

2

PX@

2

AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17

GRAPHICS

1

2

1

2

1

C107 22U_0805_6.3V6M

1

PX@

1

C106 22U_0805_6.3V6M

PX@

2

C105 22U_0805_6.3V6M

@

2

1

C113 22U_0805_6.3V6M

2

PX@

1

C104 22U_0805_6.3V6M

@

1

2

C112 22U_0805_6.3V6M

2

PX@

C111 22U_0805_6.3V6M

1

2

1

C103 22U_0805_6.3V6M

PX@

1

C102 22U_0805_6.3V6M

2

C110 22U_0805_6.3V6M

2

1

C101 22U_0805_6.3V6M

2

C100 22U_0805_6.3V6M

1

PX@

1

PX@

C109 22U_0805_6.3V6M

PX@

2

C99 22U_0805_6.3V6M

2

1

PX@

C108 22U_0805_6.3V6M

1

C98 22U_0805_6.3V6M

2 PX@

A

C97 0.1U_0603_25V7K

JCPU1G

1

2

2

POWER

+VGFX_CORE

C

1

R57 330K_0402_5% @

8/27 change to @

0_0402_5% R60 DIS@

2

0_0402_5%

2

1

Q7 2N7002H_SOT23-3

2 G

1

D

SA RAIL

<26,40,44,49,51,52> SUSP#

RUN_ON_CPU1.5VS3

D

3

@ 1 2 0_0402_5% R58

3

<40> CPU1.5V_S3_GATE

11/18 add for sequence

R885 RUN_ON_CPU1.5VS3#

@

1

2 0_0402_5%

1

2 0_0402_5%

VCCSA_SENSE

VCCSA_SENSE <50>

@ VSSSA_SENSE <50>

9/27 update C128 to D2 and @

@ FC_C22 VCCSA_VID1

R68

1

2 0_0402_5%

R69

1

2 10K_0402_5%

C22 H_FC_C22 C24

A

VCCSA_SEL <50>

6/9 change 330U to 22U X2 Compal Secret Data

Security Classification Issued Date

2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

PROCESSOR(6/7) PWR Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet 1

10

of

59

5

4

3

2

JCPU1H D

AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25

C

B

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

1

JCPU1I

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

D

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29

Sandy Bridge_rPGA_Rev1p0 ME@

VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

VSS

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

C

B

Sandy Bridge_rPGA_Rev1p0 ME@

A

A

Compal Secret Data

Security Classification Issued Date

2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. PROCESSOR(7/7) VSS

Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet 1

11

of

59

5

4

3

1 <7> DDR_A_DQS[0..7]

JDIMM1

DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27

C

<7> DDR_CKE0_DIMMA

DDR_CKE0_DIMMA

<7> DDR_A_BS2

DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1

<7> M_CLK_DDR0 <7> M_CLK_DDR#0

M_CLK_DDR0 M_CLK_DDR#0

<7> DDR_A_BS0

DDR_A_MA10 DDR_A_BS0

<7> DDR_A_WE# <7> DDR_A_CAS#

DDR_A_WE# DDR_A_CAS#

<7> DDR_CS1_DIMMA#

DDR_A_MA13 DDR_CS1_DIMMA#

2

C

DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR1 M_CLK_DDR#1 DDR_A_BS1 DDR_A_RAS#

OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)

M_CLK_DDR1 <7> M_CLK_DDR#1 <7> DDR_A_BS1 <7> DDR_A_RAS# <7>

DDR_CS0_DIMMA# M_ODT0 M_ODT1

DDR_CS0_DIMMA# M_ODT0 <7>

<7>

+VREF_CA

DDR_A_D44 DDR_A_D45

@

2

1

2

1

2

1

2

1

2

1

2

1

2

2

1

2

1

2

1

2

1 +

C149 220U_6.3V_M

B

2 @

DDR_A_DQS#5 DDR_A_DQS5

VDDQ(1.5V) =

DDR_A_D46 DDR_A_D47

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

DDR_A_D52 DDR_A_D53

6*0603 10uf (PER CONNECTOR)

DDR_A_DM6

Layout Note: Place near DIMM

VTT(0.75V) =

DDR_A_D54 DDR_A_D55

3*0805 10uf

7/28 Update connect GND directly

4*0402 1uf

VREF =

DDR_A_D60 DDR_A_D61

1*0402 0.1uf

DDR_A_DQS#7 DDR_A_DQS7

SMB_DATA_S3 SMB_CLK_S3

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

1*0402 2.2uf

VDDSPD (3.3V)= 1*0402 0.1uf

DDR_A_D62 DDR_A_D63

+0.75VS

1*0402 2.2uf

1

2

SMB_DATA_S3 <13,15,34> SMB_CLK_S3 <13,15,34>

1

2

@

+0.75VS

1

2

1

2

Layout Note: Place near DIMM

@

1/76BA1/86W

A

FOX_AS0A626-U4SN-7F ME@

Compal Secret Data

Security Classification Issued Date

2010/07/12

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

1

C148 0.1U_0402_10V6K

2

1

C147 0.1U_0402_10V6K

@

1

C146 0.1U_0402_10V6K

R73 1K_0402_1%

C144

2

C145 0.1U_0402_10V6K

1

+1.5V

C143

2

DDR_A_D38 DDR_A_D39

(0.1uF_402_10V)*4

10U_0603_6.3V6M

1

DDR_A_DM4

(10uF_0603_6.3V)*8

R72 1K_0402_1%

M_ODT1 <7>

DDR_A_D36 DDR_A_D37

Layout Note: Place near DIMM

+1.5V

10U_0603_6.3V6M

1

<7>

C142

2

DDR_CKE1_DIMMA

DDR_A_MA15 DDR_A_MA14

10U_0603_6.3V6M

206

DDR_CKE1_DIMMA

1U_0402_6.3V6K

G2

DDR_A_D30 DDR_A_D31

C153 1U_0402_6.3V6K

G1

DDR_A_DQS#3 DDR_A_DQS3

C152 1U_0402_6.3V6K

205

DDR_A_D28 DDR_A_D29

C151 1U_0402_6.3V6K

2

R83 10K_0402_5%

2

1

C156 0.1U_0402_10V6K

1

C155 2.2U_0603_6.3V4Z

+3VS A

DDR_A_D22 DDR_A_D23

C150

DDR_A_D58 DDR_A_D59 1 R81 2 10K_0402_5%

DDR_A_DM2

C141

DDR_A_DM7

DDR_A_D20 DDR_A_D21

10U_0603_6.3V6M

DDR_A_D56 DDR_A_D57

<7,13>

C140

DDR_A_D50 DDR_A_D51

DDR3_DRAMRST#

DDR_A_D14 DDR_A_D15

10U_0603_6.3V6M

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_DM1 DDR3_DRAMRST#

10U_0603_6.3V6M

DDR_A_D48 DDR_A_D49

D

C139

DDR_A_D42 DDR_A_D43

R71 1K_0402_1%

DDR_A_D12 DDR_A_D13

10U_0603_6.3V6M

DDR_A_DM5

DDR_A_D6 DDR_A_D7

C138

DDR_A_D40 DDR_A_D41

DDR_A_DQS#0 DDR_A_DQS0

C137

DDR_A_D34 DDR_A_D35

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

+VREF_DQ_DIMMA

10U_0603_6.3V6M

B

CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2

<7> DDR_A_MA[0..15]

C136 2.2U_0603_6.3V4Z

DDR_A_DQS#4 DDR_A_DQS4

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

R70 1K_0402_1%

<7> DDR_A_DQS#[0..7] DDR_A_D4 DDR_A_D5

C135 0.1U_0402_10V6K

DDR_A_D32 DDR_A_D33

73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

1

DDR_A_DM0

VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26

2

2

VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25

1

D

1

C134 2.2U_0603_6.3V4Z

2

C133 0.1U_0402_10V6K

1

DDR_A_D0 DDR_A_D1

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

1

<7> DDR_A_D[0..63]

2

4BA2/6W

DDR3 SO-DIMM A +VREF_DQ_DIMMA

2

+1.5V

+1.5V

1

+1.5V

2

+VREF_DQ_DIMMA

4

3

2

Title

Compal Electronics, Inc. DDRIII-SODIMM SLOT1

Size Document Number Custom Date:

Rev 0.2

LA-6751P Sheet

Friday, November 26, 2010 1

12

of

59

5

4

3

4BA2/6W +1.5V

DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11 DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D24 DDR_B_D25 DDR_B_DM3 DDR_B_D26 DDR_B_D27

<7> DDR_CKE2_DIMMB

DDR_CKE2_DIMMB

<7> DDR_B_BS2

DDR_B_BS2

C

DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 <7> M_CLK_DDR2 <7> M_CLK_DDR#2

M_CLK_DDR2 M_CLK_DDR#2

<7> DDR_B_BS0

DDR_B_MA10 DDR_B_BS0

<7> DDR_B_WE# <7> DDR_B_CAS#

DDR_B_WE# DDR_B_CAS#

<7> DDR_CS3_DIMMB#

DDR_B_MA13 DDR_CS3_DIMMB#

1 2

C

DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_DDR3 M_CLK_DDR#3 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB# M_ODT2 M_ODT3

M_CLK_DDR3 <7> M_CLK_DDR#3 <7> DDR_B_BS1 <7> DDR_B_RAS# <7> DDR_CS2_DIMMB# M_ODT2 <7>

+1.5V <7>

M_ODT3 <7>

+VREF_CB DDR_B_D36 DDR_B_D37

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

2

1

2

B

VDDQ(1.5V) = 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs) 6*0603 10uf (PER CONNECTOR)

DDR_B_D52 DDR_B_D53

Layout Note: Place near DIMM

VTT(0.75V) =

DDR_B_DM6

3*0805 10uf

DDR_B_D54 DDR_B_D55

4*0402 1uf 7/28 Update connect GND directly

DDR_B_D60 DDR_B_D61

1*0402 0.1uf

DDR_B_DQS#7 DDR_B_DQS7

+0.75VS

1*0402 2.2uf

VDDSPD (3.3V)= 1*0402 0.1uf

1*0402 2.2uf

DDR_B_D62 DDR_B_D63 SMB_DATA_S3 SMB_CLK_S3

1/76BA1/86W

1

2 SMB_DATA_S3 <12,15,34> SMB_CLK_S3 <12,15,34> +0.75VS

1

2

@

1

2

1

2

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

@ A

Layout Note: Place near DIMM

FOX_AS0A626-U8SN-7F ME@

Compal Secret Data

Security Classification Issued Date

2010/07/12

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

1

C172 0.1U_0402_10V6K

DDR_B_D46 DDR_B_D47

1

C171 0.1U_0402_10V6K

DDR_B_DQS#5 DDR_B_DQS5

2

@

C170 0.1U_0402_10V6K

DDR_B_D44 DDR_B_D45

1

C169 0.1U_0402_10V6K

@

C168

R87 1K_0402_1%

C167

2

+1.5V

10U_0603_6.3V6M

1

C166

2

DDR_B_D38 DDR_B_D39

(0.1uF_402_10V)*4

10U_0603_6.3V6M

DDR_B_DM4

(10uF_0603_6.3V)*8

10U_0603_6.3V6M

1

Layout Note: Place near DIMM

R86 1K_0402_1%

C165

206

<7>

1U_0402_6.3V6K

G2

DDR_CKE3_DIMMB

DDR_B_MA15 DDR_B_MA14

C176 1U_0402_6.3V6K

G1

DDR_CKE3_DIMMB

C175 1U_0402_6.3V6K

2

205

DDR_B_D30 DDR_B_D31

C174 1U_0402_6.3V6K

2

1

C178 0.1U_0402_10V6K

1

C177 2.2U_0603_6.3V4Z

+3VS A

DDR_B_DQS#3 DDR_B_DQS3

C173

DDR_B_D58 DDR_B_D59 1 R95 2 10K_0402_5% 1 2 R97 10K_0402_5%

DDR_B_D28 DDR_B_D29

10U_0603_6.3V6M

DDR_B_DM7

DDR_B_D22 DDR_B_D23

C164

DDR_B_D56 DDR_B_D57

For Arranale only +VREF_DQ_DIMMB supply from a external 1.5V voltage divide circuit. 07/17/2009

DDR_B_DM2

10U_0603_6.3V6M

DDR_B_D50 DDR_B_D51

DDR_B_D20 DDR_B_D21

10U_0603_6.3V6M

DDR_B_DQS#6 DDR_B_DQS6

<7,12>

C163

DDR_B_D48 DDR_B_D49

DDR3_DRAMRST#

DDR_B_D14 DDR_B_D15

10U_0603_6.3V6M

DDR_B_D42 DDR_B_D43

DDR_B_DM1 DDR3_DRAMRST#

R85 1K_0402_1%

C162

DDR_B_DM5

+VREF_DQ_DIMMB

D

DDR_B_D12 DDR_B_D13

C161

DDR_B_D40 DDR_B_D41

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

DDR_B_D6 DDR_B_D7

10U_0603_6.3V6M

DDR_B_D34 DDR_B_D35

CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2

R84 1K_0402_1%

DDR_B_DQS#0 DDR_B_DQS0

C160 2.2U_0603_6.3V4Z

DDR_B_DQS#4 DDR_B_DQS4 B

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

<7> DDR_B_MA[0..15]

C159 0.1U_0402_10V6K

DDR_B_D32 DDR_B_D33

73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

+1.5V

<7> DDR_B_DQS#[0..7] DDR_B_D4 DDR_B_D5

1

DDR_B_D8 DDR_B_D9

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

2

DDR_B_D2 DDR_B_D3

VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26

1

DDR_B_DM0

VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25

2

2

C157

C158

2

DDR_B_D0 DDR_B_D1

1

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

1

0.1U_0402_10V6K

2.2U_0603_6.3V4Z

D

1

1

<7> DDR_B_DQS[0..7]

JDIMM2 +VREF_DQ_DIMMB

2

<7> DDR_B_D[0..63]

+1.5V

2

+VREF_DQ_DIMMB

4

3

2

Title

Compal Electronics, Inc. DDRIII-SODIMM SLOT2

Size

Document Number

Rev 0.2

LA-6751P Date:

Sheet

Friday, November 26, 2010 1

13

of

59

5

4

W=20mils

W=20mils

+RTCVCC

+RTCBATT

1

3

2 10M_0402_5%

R98

PCH_RTCX2_OUT <40>

2

+3VS HDA_SPKR

2 1K_0402_5%

HIGH= Enable ( No Reboot ) LOW= Disable (Default)

<39> HDA_SPKR

+3VALW

C181 2

U4A PCH_RTCX1

A20

PCH_RTCX2

C20

PCH_RTCRST#

D20

RTCRST#

PCH_SRTCRST#

G22

SRTCRST#

SM_INTRUDER#

K22

PCH_INTVRMEN

C17

INTRUDER#

L34

HDA_SYNC

HDA_SPKR

T10

SPKR

HDA_RST#

K34 E34

Low = Disabled (Default) High = Enabled [Flash Descriptor Security Overide]

HDA_SYNC

1 1K_0402_5%

R107 1

HDA_RST# HDA_SDIN0 HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

2

HDA_SYNC_R

3

R878 1M_0402_5% HDA_SDOUT

R125 100_0402_1%

N32

PCH_JTAG_TCK

J3

PCH_JTAG_TMS

H7

PCH_JTAG_TDI

K5

PCH_JTAG_TDO

H1

SPI_CLK_PCH_R SPI_SB_CS0#

1

JTAG_TMS JTAG_TDI

T3 Y14

2 T1

@ R325 0_0402_5%

9/27 reserve R878 for DG1.5

SPI_SI

V4

SPI_SO_R

U3

SATA_ITX_C_DRX_N0 0.01U_0402_16V7K 2 SATA_ITX_C_DRX_P0 0.01U_0402_16V7K 2

1 C184 1 C185

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

AM10 AM8 AP11 AP10

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

AD7 AD5 AH5 AH4

SATA_ITX_C_DRX_N2 0.01U_0402_16V7K 2 SATA_ITX_C_DRX_P2 0.01U_0402_16V7K 2

1 C186 1 C187

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

AB8 AB10 AF3 AF1

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATAICOMPO SATAICOMPI

JTAG_TDO

SATA3RBIAS

Y7 Y5 AD3 AD1

SERIRQ

<40>

ESATA@ SATA_ITX_C_DRX_N4 0.01U_0402_16V7K 2 1 C188 SATA_ITX_C_DRX_P4 0.01U_0402_16V7K 2 1 C189 ESATA@

SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 SATA_ITX_DRX_N0 SATA_ITX_DRX_P0

SATA_DTX_C_IRX_N4 SATA_DTX_C_IRX_P4 SATA_ITX_DRX_N4 SATA_ITX_DRX_P4

Y3 Y1 AB3 AB1

SATA_COMP

SATA3_COMP

R113 49.9_0402_1% 1 2

AB12 AB13 AH1

HDD

C

SATA_DTX_C_IRX_N2 <56,57> SATA_DTX_C_IRX_P2 <56,57> SATA_ITX_DRX_N2_CONN <56,57> SATA_ITX_DRX_P2_CONN <56,57>

SATA_DTX_C_IRX_N4 <42> SATA_DTX_C_IRX_P4 <42> SATA_ITX_DRX_N4 <42> SATA_ITX_DRX_P4 <42>

ODD

ESATA

7/28 change from port 5 to port 4 R111 37.4_0402_1% +1.05VS_VCC_SATA 1 2

Y11 Y10

SATA_DTX_C_IRX_N0 <38> SATA_DTX_C_IRX_P0 <38> SATA_ITX_DRX_N0 <38> SATA_ITX_DRX_P0 <38>

SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 SATA_ITX_DRX_N2_CONN SATA_ITX_DRX_P2_CONN

RBIAS_SATA3 R115 1

+1.05VS_SATA3

2 750_0402_1% B

SPI_CS0# SPI_CS1#

R117 SATALED#

SPI_MOSI

SATA0GP / GPIO21

SPI_MISO

SATA1GP / GPIO19

1 10K_0402_5%

2

+3VS

P3

HDD_LED#

V14

PCH_GPIO21

2

R119 1 10K_0402_5%

+3VS

P1

PCH_GPIO19

2

R187 1 10K_0402_5%

+3VS

HDD_LED# <56,57>

@

COUGARPOINT_FCBGA989

4MB SPI ROM FOR ME & Non-share ROM.

SPI_CLK_PCH

8/16 reserved for MOW

R124 33_0402_5% @

+3VS

PCH_JTAG_TDI

1

2

1 10K_0402_5%

2

AM3 AM1 AP7 AP5

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SPI_CLK

LPC_FRAME# <34,40> +3VS

R104

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

HDA_DOCK_RST# / GPIO13

JTAG_TCK

EC and Mini card debug port

SERIRQ

R123 200_0402_5%

R127 1

2 SPI_WP# 3.3K_0402_5%

R129 1

2 SPI_HOLD# 3.3K_0402_5%

R128 100_0402_1% 2

R126 100_0402_1% 2

2

@

PCH_JTAG_TMS

1

2 1

PCH_JTAG_TDO

R122 200_0402_5% 2

R121 200_0402_5%

@

Kill_SW#

HDA_DOCK_EN# / GPIO33

<34,40> <34,40> <34,40> <34,40>

V5

SATA3COMPI

+3VALW 1

+3VALW 1

1

+3VALW

C36

LPC_FRAME#

E36 K36

SATA3RCOMPO

Q10 BSS138_NL_SOT23-3 HDA_SYNC 1

2

HDA_RST#

1

<39> HDA_SDOUT_AUDIO

HDA_BIT_CLK

D

<39> HDA_RST_AUDIO#

PCH_GPIO33

+3VS

S

<39> HDA_SYNC_AUDIO B

R110 51_0402_5% 2 1

G

<39> HDA_BITCLK_AUDIO

2 1K_0402_1%

<56,57> Kill_SW#

On Die PLL VR Select is supplied by 1.5V when smapled high 1.8V when sampled low Needs to be pulled High for Huron River platfrom R112 33_0402_5% 1 2 R114 33_0402_5% 1 2 R116 33_0402_5% 1 2 R118 33_0402_5% 1 2

@

HDA_SDOUT

1 2 0_0402_5%

D36

LDRQ0# LDRQ1# / GPIO23

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

2

2

This signal has a weak internal pull-down

*

ME_FLASH

<40> ME_FLASH

FWH4 / LFRAME#

SERIRQ

HDA_BCLK

R109 +3VALW

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

INTVRMEN

N34

G34

C38 A38 B37 C37

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

RTCX2

HDA_SYNC

HDA_SDIN0

<39> HDA_SDIN0

RTCX1

HDA_BIT_CLK

HDA_SDOUT

@ 1 1K_0402_5%

D

15P_0402_50V8J

1

1

C182 1U_0603_10V4Z

(INTVRMEN should always be pull high.)

R108

1

1

SATA 6G

INTVRMEN

2

CLRP3 SHORT PADS

C183 1U_0603_10V4Z 1 2 R103 20K_0402_5% 1 2 R100 20K_0402_5%

Integrated VRM enable ΚIntegrated * LHΚ VRM disable

*

2 R670 0_0402_5%

SPI

PCH_INTVRMEN

1

2 330K_0402_5%

2

R102 1

1

1

SM_INTRUDER#

2

2 1M_0402_5%

R106 2

@

SATA

+RTCVCC R101 1

CLRP2 SHORT PADS

+RTCVCC

C

PCH_RTCX2 1

RTC

2

CMOS

*

PCH_RTCX1_OUT <40>

IHDA

OSC NC

2 D

@

2 R663 0_0402_5%

JTAG

OSC

2

Y1

3

C180 15P_0402_50V8J

32.768KHZ_12.5PF_9H03200413

4

1 1

NC

1 CLRP1 SHORT PADS

2

C179 1U_0603_10V4Z

R105 1

@

6/24 Update R663,R670 must be close Y1

R99 1K_0402_5% 1 2 1

2

PCH_RTCX1 1

C190 22P_0402_50V8J @

+3VS C191 1 2

DPDG1.1

6/30 update R121, R122, R123

SPI_SB_CS0# SPI_SO_R

R130 0_0402_5% 1 2 1 2 33_0402_5% R131

A

0.1U_0402_16V4Z

U5 SPI_SO_L SPI_WP#

1 2 3 4

CS# SO WP# GND

VCC HOLD# SCLK SI

8 7 6 5

SPI_HOLD# 0_0402_5% R132 SPI_CLK_PCH 1 2 SPI_CLK_PCH_R SPI_SI_R 1 2 SPI_SI 33_0402_5% R133

S IC FL 32M W25Q32BVSSIG SOIC 8P

Compal Secret Data

Security Classification Issued Date

2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

A

Compal Electronics, Inc. PCH (1/8) SATA,HDA,SPI, LPC, XDP

Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet 1

14

of

59

3

2

10K_0402_5% 2 1

U4B

BF36 BE36 AY34 BB34

PERN4 PERP4 PETN4 PETP4

C

+3VALW

WLAN

<34> CLK_PCIE_WLAN1# <34> CLK_PCIE_WLAN1 <34> WLAN_CLKREQ1# +3VS

R147

2

PCH_GPIO73

1 10K_0402_5%

R149 R150

1 1

2 0_0402_5% CLK_PCIE_WLAN1#_R 2 0_0402_5% CLK_PCIE_WLAN1_R

R156 R158

1 2

2 0_0402_5% 1 10K_0402_5%

WLAN_CLKREQ1#_R

BJ38 BG38 AU36 AV36

PERN6 PERP6 PETN6 PETP6

BG40 BJ40 AY40 BB40

PERN7 PERP7 PETN7 PETP7

BE38 BC38 AW38 AY38

PERN8 PERP8 PETN8 PETP8

Y40 Y39 J2 AB49 AB47 M1 AA48 AA47

+3VS

LAN

<35> CLK_PCIE_LAN# <35> CLK_PCIE_LAN <35> CLKREQ_LAN# +3VALW

R301

2

1 10K_0402_5%

R153 R154

1 1

2 0_0402_5% 2 0_0402_5%

1 2

2 0_0402_5% 1 10K_0402_5%

R151 R152

V10 CLK_PCIE_LAN#_R CLK_PCIE_LAN_R PCH_GPIO25

Y37 Y36 A8 Y43 Y45

+3VALW

R165

2

1 10K_0402_5%

PCH_GPIO26

+3VALW

R168

2

1 10K_0402_5%

PCH_GPIO44

PERN5 PERP5 PETN5 PETP5

L12 V45 V46 L14

SML0ALERT# / GPIO60 SML0CLK SML0DATA

+3VALW

C8

PCH_SML0CLK

G12

PCH_SML0DATA

7/28 reserved PCH_GPIO74

SML1CLK / GPIO58

E14

PCH_SML1CLK

SML1DATA / GPIO75

M16

PCH_SML1DATA

CL_CLK1

M7

SMB_DATA_S3 <12,13,34>

8/14 change P/N to 2N7002KDW(SB00000EO10)

2

+3VALW Q61A 2N7002DW-T/R7_SOT363-6 EC_SMB_CK2 6 1

7/5 change to 1K +3VALW

2.2K_0402_5% R141 2 1

R140 +3VALW

EC_SMB_CK2 <24,37,40>

VGA EC thermal sensor

+3VS

1

2 R142 2.2K_0402_5%

EC_SMB_DA2

4

+3VALW

CL_RST1#

T11

EC_SMB_DA2 <24,37,40>

R143 10K_0402_5% @

P10

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

M10 PEG_CLKREQ#_R

PEG_CLKREQ# <24>

PCH_SML0CLK

10K_0402_5% R145 1 2

CLK_PCIE_VGA#_R CLK_PCIE_VGA_R

AB37 AB38

R544 2.2K_0402_5%

R144 0_0402_5% 1 2

R146 1 R148 1

R545 2.2K_0402_5%

PCH_SML0DATA CLK_PCIE_VGA# CLK_PCIE_VGA

2 0_0402_5% 2 0_0402_5%

7/28 reserved

CLK_PCIE_VGA# <23> CLK_PCIE_VGA <23>

C

@ CLKOUT_DMI_N CLKOUT_DMI_P

CLK_CPU_DMI# CLK_CPU_DMI

AV22 AU22

CLK_CPU_DMI# CLK_CPU_DMI

CLK_CPU_DMI# <6> CLK_CPU_DMI <6>

R349 1 R347 1

2 2

10K_0402_5% 10K_0402_5%

@

PCIECLKRQ1# / GPIO18 CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P CLKOUT_PCIE2N CLKOUT_PCIE2P CLKIN_DMI_N CLKIN_DMI_P

PCIECLKRQ2# / GPIO20 CLKOUT_PCIE3N CLKOUT_PCIE3P

CLKIN_DMI2_N CLKIN_DMI2_P

PCIECLKRQ3# / GPIO25 CLKIN_DOT_96N CLKIN_DOT_96P CLKOUT_PCIE4N CLKOUT_PCIE4P CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P

CLKOUT_PCIE5N CLKOUT_PCIE5P

REFCLK14IN

PCIECLKRQ5# / GPIO44

CLKIN_PCILOOPBACK

AM12 AM13

6/30 Update to @

BF18 BE18

CLK_BUF_CPU_DMI# CLK_BUF_CPU_DMI

R155 1 R157 1

2 2

10K_0402_5% 10K_0402_5%

BJ30 BG30

CLKIN_DMI2# CLKIN_DMI2

R159 1 R160 1

2 2

10K_0402_5% 10K_0402_5%

G24 E24

CLK_BUF_DREF_96M# CLK_BUF_DREF_96M

R162 1 R163 1

2 2

10K_0402_5% 10K_0402_5%

AK7 AK5

CLK_BUF_PCIE_SATA# R164 1 CLK_BUF_PCIE_SATA R166 1

2 2

10K_0402_5% 10K_0402_5%

K45

CLK_BUF_ICH_14M

2

10K_0402_5%

H45

CLK_PCI_LPBACK

V47 V49

XTAL25_IN XTAL25_OUT

Y47

XCLK_RCOMP

R167 1

CLK_PCI_LPBACK <18>

B

B

XTAL25_IN

+3VALW

R170

@ +3VALW <18> PE_GPIO0

PE_GPIO0

+3VALW <18,25,26,52> PE_GPIO1

R174

PE_GPIO1

2

PCH_GPIO56

1 10K_0402_5%

E6

1 R520

2 100K_0402_5%

V40 V42

2 R172

1 10K_0402_5% PCH_GPIO45

T13

1 @ R700 2 1 R701 @

2 0_0402_5%

V38 V37

1 10K_0402_5% PCH_GPIO46 2 0_0402_5%

PCIE_CLK_8N PCIE_CLK_8P

K12 AK14 AK13

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

XTAL25_IN XTAL25_OUT

PEG_B_CLKRQ# / GPIO56 XCLK_RCOMP

XTAL25_OUT R171 90.9_0402_1% 1 2

PCIECLKRQ7# / GPIO46

Y2

CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLKOUT_BCLK0_P / CLKOUT_PCIE8P

CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

1

25MHZ_20PF_7A25000012

C196 27P_0402_50V8J 2 CLKOUTFLEX0 / GPIO64

2 1M_0402_5%

2 1

PCIECLKRQ6# / GPIO45 CLKOUT_PCIE7N CLKOUT_PCIE7P

1 R169

+1.05VS_VCCDIFFCLKN

CLKOUT_PCIE6N CLKOUT_PCIE6P

FLEX CLOCKS

AB42 AB40

1

2

C197 27P_0402_50V8J

K43 F47

CLK_PCI_DB_R

R173 1 @

2 22_0402_5%

CLK_PCI_DB <34>

H47 K49 CLK_BUF_ICH_14M

COUGARPOINT_FCBGA989

6/23 for GPU

@ R175 33_0402_5% 2 1

@ C198 22P_0402_50V8J 1 2

Reserve for EMI please close to PCH

CLK_PCI_LPBACK A

@ R176 33_0402_5% 2 1

@ C199 22P_0402_50V8J 1 2

A

Reserve for EMI please close to PCH

Compal Secret Data

Security Classification Issued Date

2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

D

2N7002DW-T/R7_SOT363-6 Q61B

@

PCIECLKRQ4# / GPIO26

DIMM1 DIMM2 MINI CARD

+3VALW CL_DATA1

CLKOUT_PCIE0N CLKOUT_PCIE0P

CLKOUT_PCIE1N CLKOUT_PCIE1P

2 R139 1 1K_0402_5%

SMB_CLK_S3 <12,13,34>

2.2K_0402_5% 1 2 R137 +3VS 1 2 R138 2.2K_0402_5% 4 SMB_DATA_S3

2N7002DW-T/R7_SOT363-6 Q60B

3

PEG_A_CLKRQ# / GPIO47

PCIECLKRQ0# / GPIO73

DRAMRST_CNTRL_PCH <7>

10K_0402_5% 2 1

C13

SML1ALERT# / PCHHOT# / GPIO74

3

DRAMRST_CNTRL_PCH

A12

1 2 R135 2.2K_0402_5%

5

PCH_SMBDATA

2.2K_0402_5% R136 2 1

2

PERN3 PERP3 PETN3 PETP3

C9

SMBDATA

EC_LID_OUT# <40>

2

BG36 BJ36 AV34 AU34

BG37 BH37 AY36 BB36

Desktop Only

PERN2 PERP2 PETN2 PETP2

PCH_SMBCLK

1

D

BE34 BF34 BB32 AY32

H14

2

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

SMBCLK

2

2 0.1U_0402_10V7K 2 0.1U_0402_10V7K

EC_LID_OUT#

1

1 1

SMBUS

C194 C195

SMBALERT# / GPIO11

E12

Link

2 0.1U_0402_10V7K 2 0.1U_0402_10V7K

+3VALW

R134

PERN1 PERP1 PETN1 PETP1

Controller

<34> PCIE_PRX_DTX_N2 <34> PCIE_PRX_DTX_P2 <34> PCIE_PTX_C_DRX_N2 <34> PCIE_PTX_C_DRX_P2

1 1

BG34 BJ34 AV32 AU32

CLOCKS

WLAN

C192 C193

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCI-E*

LAN

<35> PCIE_PRX_DTX_N1 <35> PCIE_PRX_DTX_P1 <35> PCIE_PTX_C_DRX_N1 <35> PCIE_PTX_C_DRX_P1

1

Q60A 2N7002DW-T/R7_SOT363-6 6 1 SMB_CLK_S3

1

4

5

5

4

3

2

Title

Compal Electronics, Inc. PCH (2/8) PCIE, SMBUS, CLK

Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet 1

15

of

59

5

4

3

2

1

D

D

U4C

100K_0402_1% SYS_PWROK

1

R743 1 2 @ 0_0402_5%

PCH_POK_R

C

<5> <5> <5> <5>

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

<5> <5> <5> <5>

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

BE24 BC20 BJ18 BJ20

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

AW24 AW20 BB18 AV18

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

AY24 AY20 AY18 AU18

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

BJ24

DMI_ZCOMP

FDI_FSYNC0

DMI_IRCOMP

FDI_FSYNC1

DMI2RBIAS

FDI_LSYNC0 FDI_LSYNC1

BB10

FDI_LSYNC1

DSWVRMEN

A18

DSWODVREN 0_0402_5%

1 R181

2 @

E22

PCH_DPWROK_R 0_0402_5% R185 0_0402_5% WAKE# 1 2 1 2 10K_0402_5% R186 PM_CLKRUN# R189 2 1 8.2K_0402_5% SUS_STAT#

1 R182

2

DMI_IRCOMP 2 49.9_0402_1% RBIAS_CPY 2 750_0402_1%

1 R177 1 R178

R742 1 2 @ 0_0402_5%

<40> SYS_PWROK_EC

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

+1.05VS_PCH

SYS_PWROK

BG25 BH21

4mil width and place within 500mil of the PCH

7/22 modify

T72

R191 PCH_POK_R

1

APWROK

2

0_0402_5%

@

7/22 modify

R184

VGATE

R188 1

<6,40> PCH_POK

R190 1

2 0_0402_5%

R302 1

2 0_0402_5%

<53>

<40> PCH_APWROK

@

R194

2

1 200_0402_5%

PM_DRAM_PWRGD

2

1 10K_0402_5%

SUSWARN#

SYS_PWROK

P12

PCH_POK_R

L22

2 0_0402_5%

<6> PM_DRAM_PWRGD

APWROK

L10

1

2

PCH_RSMRST#_R 0_0402_5%

C21

1

2

SUSWARN#_R 0_0402_5%

K16

R193

<40> SUSWARN#

@ R192 B

K3

PM_DRAM_PWRGD B13

<40> EC_RSMRST#

+3VALW

C12

1 SYS_RST# 10K_0402_5%

2

+3VS

AEPWROK can be connect to PWROK if iAMT disable

SUSACK#

PAD

R196 1 R198

<40> PBTN_OUT#

PBTN_OUT#_R 2 0_0402_5%

E20

System Power Management

SUSACK# is only used on platform that support the Deep Sx state. SUSACK# SYS_RESET# SYS_PWROK PWROK APWROK DRAMPWROK RSMRST#

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_INT

AW16

FDI_INT

AV12

FDI_FSYNC0

BC10

FDI_FSYNC1

AV14

FDI_LSYNC0

DPWROK WAKE# CLKRUN# / GPIO32

N3

SUS_STAT# / GPIO61

G8

SUSCLK / GPIO62 SLP_S5# / GPIO63 SLP_S4#

SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# PWRBTN#

B9

SLP_A#

N14

SUSCLK

D10

SLP_S5#

H4

SLP_S4#

F4

SLP_S3#

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

<5> <5> <5> <5> <5> <5> <5> <5>

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

<5> <5> <5> <5> <5> <5> <5> <5>

FDI_INT <5> FDI_FSYNC0

+RTCVCC <5> 1

+3VS R180 2

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_FSYNC1

<5>

FDI_LSYNC0

<5>

FDI_LSYNC1

<5>

R179 330K_0402_5%

ACIN_R

2 1 200K_0402_1% 1 10K_0402_5%

2

PCH_RSMRST#_R

1

<24,40,47> ACIN

1 R199

@

+3VALW

ACIN_R 2 D29 CH751H-40PT_SOD323-2 2 0_0402_5% R200 2 PCH_GPIO72 1 8.2K_0402_5% R201 2 1 RI# 10K_0402_5%

H20 E10 A10

ACPRESENT / GPIO31 BATLOW# / GPIO72

SLP_SUS# PMSYNCH

RI#

SLP_LAN# / GPIO29

PAD

T73

*

+3VS

Κ Κ

DSWODVREN - On Die DSW VR Enable H Enable L Disable

SUSCLK <40> SLP_S5# <40> SLP_S4# <40> SLP_S3# <40>

G16

PM_SLP_SUS#

AP14

H_PM_SYNC @ T66

R183 330K_0402_5% @

PCH_DPWROK <40>

7/28 Update

Can be left NC when IAMT is not support on the platfrom

G10

K14

PCH_RSMRST#_R

PCIE_WAKE# <34,35> +3VALW

R195

R197

C

2

7/28 Defult use AND Gate

*

<5> <5> <5> <5>

SYS_PWROK <6>

U6

DMI0RXN DMI1RXN DMI2RXN DMI3RXN

1

SYS_PWROK

4

Y B

BC24 BE20 BG18 BG20

2

A

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

FDI

2

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI

PCH_POK

P

1

5

VGATE

G

3

MC74VHC1G08DFT2G SC70 5P

<5> <5> <5> <5>

PAD

T71

B

H_PM_SYNC <6>

Can be left NC if no use integrated LAN.

PAD

COUGARPOINT_FCBGA989

7/28 modify +3VS

R546

2

1 200_0402_5%

PM_DRAM_PWRGD

7/28 Modify follow CRB & ORB

A

A

Compal Secret Data

Security Classification Issued Date

2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. PCH (3/8) DMI,FDI,PM,

Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet 1

16

of

59

5

4

3

2

1

D

D

1 R523 2.2K_0402_5% PX@

U4D

R204 1 R205 1

+3VS

CTRL_CLK CTRL_DATA

2 2.2K_0402_5% 2 2.2K_0402_5% 2.37K_0402_1% R206 2 1 PX@

T40 K47 T45 P39

LVD_VREF

AE48 AE47

LVD_VREFH LVD_VREFL

<31> LVDS_ACLK# <31> LVDS_ACLK

AK39 AK40

LVDSA_CLK# LVDSA_CLK

<31> LVDS_A0# <31> LVDS_A1# <31> LVDS_A2#

AN48 AM47 AK47 AJ48

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

<31> LVDS_A0 <31> LVDS_A1 <31> LVDS_A2

AN47 AM49 AK49 AJ47

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

AF40 AF39

LVDSB_CLK# LVDSB_CLK

0_0402_5% 2 1 PX@

PX@ R209 2 PX@

<32> DAC_RED

R210 2

AH43 AH49 AF47 AF43

DAC_BLU 1 150_0402_1% DAC_GRN 1 150_0402_1% DAC_RED 1 150_0402_1%

N48 P49 T49

PX@ +3VS

Pull up R for Chipset SIDE

<32> CRT_DDC_CLK <32> CRT_DDC_DATA

CRT_DDC_CLK CRT_DDC_DATA

T39 M40

SDVO_INTN SDVO_INTP

AP39 AP40

SDVO_CTRLCLK SDVO_CTRLDATA

LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED CRT_DDC_CLK CRT_DDC_DATA

DDPB_AUXN DDPB_AUXP DDPB_HPD DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P DDPC_CTRLCLK DDPC_CTRLDATA DDPC_AUXN DDPC_AUXP DDPC_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P DDPD_CTRLCLK DDPD_CTRLDATA

1

1

CRT_IREF

2

2

M47 M49

<32> CRT_HSYNC <32> CRT_VSYNC

R559 2.2K_0402_5% PX@

T43 T42

CRT_HSYNC CRT_VSYNC DAC_IREF CRT_IRTN

1

CRT_DDC_CLK CRT_DDC_DATA

+3VS

1

AM42 AM40

1

SDVO_STALLN SDVO_STALLP

DDPD_AUXN DDPD_AUXP DDPD_HPD

B

R524 2.2K_0402_5% PX@

AP43 AP45

L_CTRL_CLK L_CTRL_DATA LVD_IBG LVD_VBG

R208 2

<32> DAC_GRN

L_DDC_CLK L_DDC_DATA

AF37 AF36

AH45 AH47 AF49 AF45

<32> DAC_BLU

L_BKLTCTL

LVDS_IBG

R207

C

EDID_CLK EDID_DATA

<31> EDID_CLK <31> EDID_DATA

SDVO_TVCLKINN SDVO_TVCLKINP

R202 2.2K_0402_5% UMA_HDMI@

R203 2.2K_0402_5% UMA_HDMI@

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

P38 M39

2

Pull up R for Chipset SIDE

P45

PCH_PWM

L_BKLTEN L_VDD_EN

2

<31>

J47 M45

Digital Display Interface

PCH_ENBKL PCH_ENVDD

<31> PCH_ENBKL <31> PCH_ENVDD

EDID_CLK EDID_DATA

LVDS

2

2

R234 2.2K_0402_5% PX@

CRT

1

+3VS

HDMICLK_NB HDMIDAT_NB

AT49 AT47 AT40

HDMICLK_NB <33> HDMIDAT_NB <33>

TMDS_B_HPD# <33>

AV42 TMDS_B_DATA2#_PCH AV40 TMDS_B_DATA2_PCH AV45 TMDS_B_DATA1#_PCH AV46 TMDS_B_DATA1_PCH AU48 TMDS_B_DATA0#_PCH AU47 TMDS_B_DATA0_PCH AV47 TMDS_B_CLK#_PCH AV49 TMDS_B_CLK_PCH

UMA_HDMI@ UMA_HDMI@ UMA_HDMI@ UMA_HDMI@ UMA_HDMI@ UMA_HDMI@ UMA_HDMI@ UMA_HDMI@

C200 C201 C202 C203 C204 C205 C206 C207

1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

HDMI_TX2-_CK <33> HDMI_TX2+_CK <33> HDMI_TX1-_CK <33> HDMI_TX1+_CK <33> HDMI_TX0-_CK <33> HDMI_TX0+_CK <33> HDMI_CLK-_CK <33> HDMI_CLK+_CK <33>

HDMI

C

UMA_HDMI@

P46 P42 AP47 AP49 AT38 AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 M43 M36 AT45 AT43 BH41

B

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

COUGARPOINT_FCBGA989

2

R211 1K_0402_1%

A

A

Compal Secret Data

Security Classification Issued Date

2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. PCH (4/9) LVDS,CRT,DP,HDMI

Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet 1

17

of

59

5

4

3

2

1

+3VS

R551

1

@

2 8.2K_0402_5%

PCH_GPIO53 U4E

RP1 PCH_GPIO2 PCH_GPIO54 PCH_GPIO4 PCH_GPIO3

1 2 3 4

8.2K_0804_8P4R_5% R225

1

2 8.2K_0402_5%

WL_OFF#

R212

1

2 8.2K_0402_5%

PCH_GPIO52

R213

1

2 8.2K_0402_5%

PCH_GPIO5

R214

1

2 8.2K_0402_5%

PCH_GPIO50

@

PCH_GPIO51

R221

1

@

WL_OFF#

GNT1#/ GPIO51

Boot BIOS Destination

0

1

Reserved

1

0

Reserved

1

1

0

0

*

SPI

R215

1

@

2 1K_0402_5%

A16 swap overide Strap/Top-Block Swap Override jumper

Boot BIOS Strap bit1 BBS1

C

TP21 TP22 TP23 TP24

BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

NV_DQS0 NV_DQS1

Low=A16 swap override/Top-Block PCI_GNT3# Swap Override enabled High=Default *

(Default)

LPC

10/5

change to PX@ PE_GPIO0

<15> PE_GPIO0

PE_GPIO1

<15,25,26,52> PE_GPIO1

PX@ 1 2 R553 0_0402_5% 1 2 R691 0_0402_5% PX@ <34> WL_OFF#

GPIO53=This Signal has a weak internal pull-up. NOTE: The internal pull-up is disabled after <40,56,57> PLTRST# deasserts.

ODD_DA#

B

<15> CLK_PCI_LPBACK <40> CLK_PCI_LPC

ODD_DA# 0_0402_5%

@ 1 R715

<40>

PCI_PME#

<6>

PLT_RST#

2

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

K40 K38 H38 G38

PCH_GPIO50 PCH_GPIO52 PCH_GPIO54

C46 C44 E40

NV_ALE NV_CLE

AV5 AY1

PCH_GPIO51 PCH_GPIO53 WL_OFF#

D47 E42 F46

PCH_GPIO2 PCH_GPIO3 PCH_GPIO4 PCH_GPIO5

G42 G40 C42 D44

R219 22_0402_5% 1 2 1 2 R220 22_0402_5%

AT8 AY5 BA2

GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5

USBRBIAS# USBRBIAS

K10 PLT_RST#

NV_RB#

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

D

NV_CLE

AV10

NV_RE#_WRB0 NV_RE#_WRB1 NV_WE#_CK0 NV_WE#_CK1

REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54

AT10 BC8 AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

NV_RCOMP

PIRQA# PIRQB# PIRQC# PIRQD#

AY7 AV7 AU3 BG4

NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15

GPIO55

2 1K_0402_5%

Bit11 Bit10

B21 M20 AY16 BG46

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

USB

8 7 6 5

D

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

NVRAM

8.2K_0804_8P4R_5%

BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45

DMI Termination Voltage Set to Vcc when HIGH NV_CLE Set to Vss when LOW

AT12 BF3

USB DEBUG=PORT1 AND PORT9 C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32 C33

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3

USB20_N5 USB20_P5

USB20_N5 <31> USB20_P5 <31>

USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11

+1.8VS

RIGHT USB

6/24 change to 1K

LEFT USB LEFT USB

NV_CLE

LEFT USB (COMBO)

PLTRST#

CLK_PCI_LPBACK_R H49 CLK_PCI_LPC_R H43 J48 K42 H40

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

1 4.7K_0402_5%

8/6 WLAN change WLAN to port 9

+3VALW RP3

USB20_N11 <43> USB20_P11 <43> USB20_N13 <42> USB20_P13 <42>

USB_OC0# USB_OC2# USB_OC7# USB_OC5#

CARD READER

4 3 2 1

5 6 7 8

10K_1206_8P4R_5%

Bluetooth

Within 500 mils 1 R218

2 22.6_0402_1%

RP4 USB_OC1# USB_OC4# USB_OC3# USB_OC6#

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#

H_SNB_IVB# <6>

USB Camera

B33 A14 K20 B17 C16 L16 A16 D14 C14

2 R217

PME#

C6

C

R216 1K_0402_5%

USB charger

CLOSE TO THE BRANCHING POINT

USB20_N9 <34> USB20_P9 <34>

USB20_N13 USB20_P13 USBRBIAS

<56,57> <56,57> <38> <38> <42> <42> <42> <42>

1

8/17 reserved

RSVD

1 2 3 4

PCI

8 7 6 5

PCI_PIRQA# PCI_PIRQD# PCI_PIRQC# PCI_PIRQB#

2

RP2

4 3 2 1

USB_OC0# <38,56,57> USB_OC1# <42>

5 6 7 8

B

10K_1206_8P4R_5%

COUGARPOINT_FCBGA989

7/12 For DIS only R690 2 DIS@ 0_0402_5%

PE_GPIO0

7/12 Reserve for BACO suggestion

1

B

Y A

NC7SZ08P5X_NL_SC70-5

4

VGA_RST#_R

PX@ R682 2 1 0_0402_5%

2

A

1U_0402_6.3V4Z C208 @

PE_GPIO0

R741 @ 2 1

10/5

VGA_RST#

0_0402_5%

Issued Date

4

U7

PLT_RST#

1 2

R223 100K_0402_5%

2

Compal Secret Data 2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

B

A

+3VS

change to PX@ Security Classification

7/12 Reserve for PX3.0

1

A

Y

VGA_RST# <23>

PX@ R684 100K_0402_5%

PX@

4

<34,35,40> BUF_PLT_RST#

G

2

P

PLT_RST#

0_0402_5%

5

5

3

MC74VHC1G08DFT2G SC70 5P @ U12

1

CH751H-40PT_SOD323-2

VGA_RST#

1

2

2 0_0402_5%

+3VGS

P

1

R693 @ 2 1

G

PE_GPIO0

1 R222

@

@

3

D27

+3VGS

2

1 R487 2 10K_0402_5%

1

3

2

Title

Compal Electronics, Inc. PCH (5/9) PCI, USB

Size Document Number Custom

Rev 0.1

LA-6751P

Date:

Friday, November 26, 2010

Sheet 1

18

of

59

5

4

3

2

1

+3VS

0

DIS

1

0

PX3.0

2 1

PCH_GPIO69

R704 2

0

0

R703

1

1

R702

UMA

10K_0402_5%

0

2

0

1

0

10K_0402_5%

PCH_GPIO70

10K_0402_5%

PCH_GPIO71

Function

PCH_GPIO69

PX@

@

PCH_GPIO70

7/22 update to reserve only

H ; Disable L ; Enable

*

+3VS

@ R235

2 1K_0402_5%

1

R227

1

2 10K_0402_5%

R228

1

2 10K_0402_5%

EC_SMI#

Weak internal pull-high +3VALW

R229

1

R230

1

@

T7 A42 PCH_GPIO6

H36

BMBUSY# / GPIO0

TACH4 / GPIO68

C40

PCH_GPIO68

TACH1 / GPIO1

TACH5 / GPIO69

B41

PCH_GPIO69

TACH2 / GPIO6

TACH6 / GPIO70

C41

PCH_GPIO70

+3VS

TACH7 / GPIO71

A40

PCH_GPIO71

<40> EC_SCI#

EC_SCI#

E38

TACH3 / GPIO7

<40> EC_SMI#

EC_SMI#

C10

GPIO8

2 10K_0402_5%

CPUSB#

C4

2 1K_0402_5%

PCH_GPIO15

G2

GPIO15

A20GATE

R240

@

1

2 1K_0402_5% PCH_GPIO28

<42> ESATA_DET# +3VS

R542 R232

1 1

+3VS

R238

7/22 update to used intel function

@

1

2 10K_0402_5%

PCH_GPIO16

2 0_0402_5% 2 10K_0402_1%

GPIO17

2 10K_0402_5%

PCH_GPIO22

T5

ODD_EN

E8

<38> ODD_EN

+3VALW

U2 D40

PCH_GPIO27 (Have internal Pull-High) VCCVRM VR Enable *High: Low: VCCVRM VR Disable

R243

+3VS R245

@

1

2 10K_0402_5%

PCH_GPIO27

+3VS

R244

R250 R547

@

1

2 10K_0402_5%

E16

GPIO27

P8

GPIO28

@ 1 R242 1

2 10K_0402_5%

BT_OFF#

K1

STP_PCI# / GPIO34

2 10K_0402_5%

PCH_GPIO35

K4

GPIO35

PCH_GPIO36

V8

2 10K_0402_5%

PCH_GPIO37

M5 N2

1

@

R246

1

2 10K_0402_5%

PCH_GPIO38

R247

1

2 10K_0402_5%

PCH_GPIO39

M3

R248

1

2 10K_0402_5%

PCH_GPIO48

V13

R249

1

2 10K_0402_5%

ESATA_DET#_R

2 10K_0402_5%

1

R251

1

8/5 update to pull down

1

10/8 update to

2 10K_0402_5%

RCIN# PROCPWRGD THRMTRIP#

NC_1

P4 AU16 P5

AY10

NC_5

@ T15

PAD

@ T16

PAD

D6

GPIO57

VSS_NCTF_17

BH3

@ T17

PAD

BH47

@ T18

PAD

BJ4

@ T20

PAD

BJ44

@ T22

PAD

BJ45

@ T24

PAD

BJ46

@ T26

PAD

BJ5

@ T28

PAD

BJ6

@ T30

PAD

C2

@ T32

PAD

C48

@ T34

PAD

D1

@ T36

PAD

D49

@ T38

PAD

E1

@ T40

PAD

E49

@ T42

PAD

F1

@ T44

PAD

F49

@ T46

PAD

T23 @

A45

PAD

T25 @

A46

PAD

T27 @

A5

PAD

T29 @

A6

PAD

T31 @

B3

PAD

T33 @

B47

PAD

T35 @

BD1

PAD

T37 @

BD49

PAD

T39 @

BE1

PAD

T41 @

BE49

PAD

T43 @

BF1

PAD

T45 @

BF49

2

2

2 10K_0402_5%

H_THRMTRIP# <6>

C

SDATAOUT0 / GPIO39

BG48

PAD

1

R226

SLOAD / GPIO38

BG2

A44

KB_RST#

Intel schematic reviwe recommand.

VSS_NCTF_16

T21 @

2 10K_0402_5%

P37

VSS_NCTF_15

PAD

H_THRMTRIP# 2 390_0402_5%

AK10

SATA5GP / GPIO49

A4

1

This signal has weak internal PU, can't pull low

SDATAOUT1 / GPIO48

T19 @

+3VS

PCH_GPIO68 R224

H_CPUPWRGD <6> PCH_THRMTRIP#_R 1 R239

V3

PAD

<6,40>

KB_RST# <40>

AH8

AH10

SATA3GP / GPIO37

KB_RST#

H_PECI

INIT3_3V

AK11

NC_4

@ 1 2 0_0402_5% R237

T14

NC_3 SATA2GP / GPIO36

GATEA20 <40> PCH_PECI_R

AY11

NC_2

VSS_NCTF_18

PCH_GPIO37

pull down for checklist Rev1.2

PECI

INIT3_3V#

2 10K_0402_5%

B

R881

GPIO24 / MEM_LED

PCH_GPIO28

PCH_GPIO36 +3VALW

SCLOCK / GPIO22

PCH_GPIO27

PCH_GPIO57 +3VS

TACH0 / GPIO17

2 10K_0402_5%

R241 <42> BT_OFF# +3VS

SATA4GP / GPIO16

1

C

CPU/MISC

voltage regulator enable ΚΚOn-Die On-Die PLL Voltage Regulator disable

1

GPIO

H L

R231

6/23 update for MB ID

LAN_PHY_PWR_CTRL / GPIO12

VSS_NCTF_1

VSS_NCTF_19

VSS_NCTF_2

VSS_NCTF_20

VSS_NCTF_3

VSS_NCTF_21

VSS_NCTF_4 VSS_NCTF_5

NCTF

*

+3VS

DIS@

R236 10K_0402_5%

GPIO28

On-Die PLL Voltage Regulator This signal has a weak internal pull up

@

1

U4F 2 R303

10K_0402_5%

1 0_0402_5%

R706

1

ICC_EN#

R705

1

PCH_GPIO0

@

Integrated Clock Chip Enable

R707

10K_0402_5%

2 10K_0402_5%

1

PCH_GPIO71

1

R233

ESATA_DET#

2

+3VS

D

PX4.0 *

0

1

2

1

10K_0402_5%

D

VSS_NCTF_22 VSS_NCTF_23

VSS_NCTF_6

VSS_NCTF_24

VSS_NCTF_7

VSS_NCTF_25

VSS_NCTF_8

VSS_NCTF_26

VSS_NCTF_9

VSS_NCTF_27

VSS_NCTF_10

VSS_NCTF_28

VSS_NCTF_11

VSS_NCTF_29

VSS_NCTF_12

VSS_NCTF_30

VSS_NCTF_13

VSS_NCTF_31

VSS_NCTF_14

VSS_NCTF_32

B

COUGARPOINT_FCBGA989

A

A

Compal Secret Data

Security Classification Issued Date

2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. PCH (6/9) GPIO, CPU, MISC

Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet 1

19

of

59

4

3

@ PJP1

+VCCAPLLEXP

T47 @

BJ22

This pin can be left as no connect in On-Die VR enabled mode (default).

AN16 AN17

1

VCCIO[17] VCCIO[18]

+1.05VS_VCC_EXP

2

2

1

2

VCCIO[20]

AP23

VCCIO[21] VCCIO[22]

AP26

VCCIO[23]

AT24

AN34 R260 0_0805_5% 1 2

+3VS_VCCA3GBG

BH29

VCCIO[24]

+VCCAFDI_VRM

AP16

1 @C229 @ C229 1U_0402_6.3V6K

2

BG6

+1.05VS_PCH R263 1 2 +1.05VS_VCCDPLL_FDI AP17 0_0805_5% AU20

+VCCP_VCCDMI

B

R252 0.022_0805_1% 1 2 PX@

60mA VCCTX_LVDS[3]

AP36

VCCTX_LVDS[4]

AP37

VCC3_3[6]

+VCCTX_LVDS 1

1

1

V34 2

AT16

VCCDMI[1]

AT20

VCCIO[1]

190mA VCCPNAND[2]

VCCVRM[2] VCCFDIPLL

R258

+VCCP_VCCDMI

1

AB36 +1.05VS_VCC_DMI_CCI 1

0_0805_5% 1 @

2

C917

1

2

VCCPNAND[3] VCCPNAND[4]

+VCCPNAND

2

2

C220 1U_0402_6.3V6K

+1.8VS R261 0_0805_5% 1 2

AJ16 1 AJ17

V1

Vcc3_3

3.3

0.266

VccADAC

3.3

0.001

VccADPLLA

1.05

0.08

VccADPLLB

1.05

0.08

VccCore

1.05

1.3

VccDMI

1.05

0.042

VccIO

1.05

2.925

VccASW

1.05

1.01

VccSPI

3.3

0.02

VccDSW

3.3

0.003

VccpNAND

1.8

0.19

VccRTC

3.3

6 uA

VccSus3_3

3.3

0.119

1 R399

COUGARPOINT_FCBGA989

2

2

3.3 / 1.5

0.01

VccVRM

1.8 / 1.5

0.16

1.05

0.02

VccSSC

1.05

0.095

VccDIFFCLKN

1.05

0.055

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.06

+3VS

0_0805_5%

1

VccSusHDA

VccCLKDMI

C228 0.1U_0402_10V7K

+3V_VCCPSPI

C

0_0805_5%

2

20mA VCCSPI

0.001

2

8/11 update for PDGD 1.2 8/27 update L75 symbol

AG16 AG17

@ 1 R259

+1.05VS

L75 10UH_LBR2012T100M_20% 1 2

10U_0603_6.3V6M

VCC3_3[3]

0.001

5

+VCCAFDI_VRM

C226 1U_0402_6.3V6K

VCCPNAND[1]

5

V5REF_Sus

C219 0.1U_0402_10V7K

+1.05VS_PCH

20mA

V5REF

0.1uH inductor, 200mA

1 VCC3_3[7]

0.001

D

DIS@ R255 0_0402_5%

PX@

S0 Iccmax Current (A)

@

+1.8VS L2 PX@ 0.1UH_MLF1608DR10KT_10%_1608 2 1

C216 C217 0.01U_0402_16V7K 0.01U_0402_16V7K 2 PX@ 2 PX@ 2 +3VS R256 0_0805_5% +3VS_VCC3_3_6 1 2

V33

2

+3VS

8/5 Reserved

2 AM38

C395 10U_0805_6.3V6M

2

1

CRT

VCC CORE

LVDS

AM37

VCCTX_LVDS[2]

VCCVRM[3]

VCCIO[26]

VCCDMI[2]

1

Voltage 1.05

V_PROC_IO C215 10U_0805_6.3V6M

DIS@ R253 0_0402_5%

VCCIO[25]

VCCIO[27]

2

1

+VCCP_VCCDMI

Place CH53 Near BG6 pin +1.05VS_VCCAPLL_FDI

VCCTX_LVDS[1]

2925mA

C227 0.1U_0402_10V7K

2 @ R262 0_0603_5% 2 1

AP24

AN33

1

+1.05VS_PCH

C225 1U_0402_6.3V6K

2

1

C224 1U_0402_6.3V6K

+3VS

2

1

C223 1U_0402_6.3V6K

2

1

C222 1U_0402_6.3V6K

1

C221 10U_0805_6.3V6M

R257 0_0805_5%

VCCIO[19]

AP21 @ 1

VCCIO[16]

FDI

C

VCCIO[15]

+VCCA_LVDS

1

AK37

VCCAPLLEXP

AN26 AN27

PAD-OPEN 4x4m +1.05VS_PCH

AK36

VCCIO[28]

AN21 @ J12

VSSALVDS

HVCMOS

PAD

U47 2

DMI

+1.05VS_VCCDPLLEXP AN19

1 0_0603_5%

2

VSSADAC

Voltage Rail

C218 22U_0805_6.3V6M

R254

VCCADAC

1mA VCCALVDS

NAND / SPI

+1.05VS_PCH

1mA

C214 0.1U_0402_10V7K

2

VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] VCCCORE[16] VCCCORE[17]

+VCCADAC 1

U48

C213 0.01U_0402_16V7K

2

1

C212 1U_0402_6.3V6K

1

C211 1U_0402_6.3V6K

2

C210 1U_0402_6.3V6K

C209 10U_0603_6.3V6M

2

D

1

AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31

VCCIO

+1.05VS_PCH

1 PAD-OPEN 4x4m 1

2

+3VS L1 MBK1608221YZF_2P 2 1

1300mA

2

1

PCH Power Rail Table

POWER

U4G

1

+1.05VS

2

2

5

C230 1U_0402_6.3V6K

B

6/30 update

+VCCAFDI_VRM +1.5VS R265

2

1

0_0603_5%

1

0_0603_5%

+VCCAFDI_VRM

+1.8VS R266

2

@

Intel recommand stuff R265 and unstuff R266

VCCVRM==>1.5V FOR MOBILE VCCVRM==>1.8V FOR DESKTOP

VCCVRM = 160mA detal waiting for newest spec

A

A

Compal Secret Data

Security Classification Issued Date

2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. PCH (7/9) PWR

Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet 1

20

of

59

5

4

3

2

1

Have internal VRM +1.05VS_PCH @ R268 0_0603_5% 2 1

T38

10U_0805_6.3V6M C237

@

R274

2 0_0603_5%

1

+VCCAPLL_CPY_PCH

BH23

+VCCDPLL_CPY

AL29

+VCCSUS1

2

AL24

1

2 +1.05VS_PCH R277 0_0805_5% 1 2

C

2

2

+1.05VS_VCCA_B_DPL

2

+1.05VS_PCH

2

VCCASW[6]

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

+VCCRTCEXT C256 1U_0402_6.3V6K

C258 0.1U_0402_10V7K

2

VCCASW[18]

N16

1 Y49

+1.05VS_VCCA_A_DPL C259 1U_0402_6.3V6K

BD47

+1.05VS_VCCA_B_DPL

BF47

+VCCDIFFCLK +1.05VS_VCCDIFFCLKN

AF17 AF33 AF34 AG34

+1.05VS_SSCVCC

AG33

+1.05VS_SSCVCC 1

2

D1 CH751H-40PT_SOD323-2

DCPSUS[4] VCCSUS3_3[1]

AN24

+3V_VCCPSUS

P34

+PCH_V5REF_RUN

N20

+3V_VCCPSUS

C243

2

1mA V5REF

VCCSUS3_3[3]

N22

VCCSUS3_3[4]

P20

VCCSUS3_3[5] VCC3_3[1] VCC3_3[8] VCC3_3[4]

VCCASW[19]

VCC3_3[2]

VCCASW[20]

1

1 +3VS_VCCPCORE

VCCVRM[4]

VCCIO[13]

R281 0_0805_5% 2 1

T34

+3VS_VCCPPCI

2 1

AJ2

R283 0_0603_5% 2 1

+VCC3_3_2

+3VS

+3VS

+PCH_V5REF_RUN

1

2

R282 0_0603_5% 1

C

D2 CH751H-40PT_SOD323-2

C248 1U_0603_10V6K

+3VS

C254 0.1U_0402_10V7K

+1.05VS_SATA3

C255 0.1U_0402_10V7K

+1.05VS_PCH R285 0_0805_5% 2 1

1

AH13 2

+1.05VS_SATA3

AH14

R279 100_0402_5%

2

1 AF13

+3VS

C249 0.1U_0402_10V7K

2

W16

+3VALW

C247 1U_0402_6.3V

2

2 DCPRTC

R278 0_0603_5% 2 1

P22 AA16

C240 0.1U_0603_25V7K

2 1U_0402_6.3V6K

1

+5VS

VCCSUS3_3[2]

+PCH_V5REF_SUS

1

+VCCA_USBSUS

VCCIO[12] +VCCAFDI_VRM

+3VALW

R275 100_0402_5%

+1.05VS_PCH R276 0_0603_5% 2 1

+1.05VS_VCCAUPLL +PCH_V5REF_SUS

VCCASW[16] VCCASW[17]

2

+5VALW

@

VCCASW[15]

W29

T26

2

+3VALW R272 0_0603_5% 2 1

C257 1U_0402_6.3V6K

2

+1.05VS_VCCDIFFCLKN

R288 0_0603_5% 2 1

VCCADPLLA VCCADPLLB

80mA

VCCIO[6]

80mA

VCCAPLLSATA VCCVRM[1]

VCCIO[7] VCCIO[8] 55mA VCCIO[9] VCCIO[11]

VCCIO[2] VCCIO[3]

C262 1U_0402_6.3V6K

VCCIO[10]

VCCIO[4]

95mA

+1.05VS_PCH L7 @ @ R287 10UH_LB2012T100MR_20% 0_0805_5% +VCCSATAPLL_R2 1 2 1

AF14 +VCCSATAPLL +VCCAFDI_VRM

AK1 AF11 AC16

1

+VCCAFDI_VRM +1.05VS_VCC_SATA R289 +1.05VS_PCH 0_0805_5% +1.05VS_VCC_SATA 2 1

AC17

1

AD17

2

B

@ C260 10U_0805_6.3V6M

Place CH80 Near AK1 pin

C261 1U_0402_6.3V6K

2

@ R290 0_0603_5% 2 1

+1.05VM_VCCSUS C263 0.1U_0402_10V7K

2

C264 1U_0402_6.3V6K

+VCCSST

V16

+1.05VM_VCCSUS

T17 V19

1

1 @

+1.05VS

2

R293 0_0603_5% 1 2

+V_CPU_IO

2

1

2

BJ8

+1.05VS_PCH

DCPSST DCPSUS[1] DCPSUS[2]

V_PROC_IO 1mA

VCCASW[22] VCCASW[23] VCCASW[21]

T21

+VCCME_22

R291

2

1 0_0603_5%

V21

+VCCME_23

R292

2

1 0_0603_5%

T19

+VCCME_21

R294

2

1 0_0603_5%

P32

+VCCSUSHDA

R295

2

1 0_0603_5%

+RTCVCC

+3VALW A22

2

1

2

C270 0.1U_0402_10V7K

2

1

C269 0.1U_0402_10V7K

1

C268 1U_0402_6.3V6K

@

C267 0.1U_0402_10V7K

1

C266 0.1U_0402_10V7K

2

C265 4.7U_0603_6.3V6K

1

A

VCCASW[14]

D

+3VALW R273 0_0603_5% +3V_VCCAUBG 2 1 1 C238 0.1U_0402_10V7K

AN23

+1.05VS_VCCDIFFCLKN

2

+1.05VS_PCH

VCCASW[13]

1

M26

VCCIO[5]

1

+1.05VS_PCH

VCCASW[12]

W26

W33

P24

1mA V5REF_SUS

VCCASW[7]

AC26

W31

V24

VCCSUS3_3[6] VCCIO[34]

+3V_VCCPUSB

V23

VCCSUS3_3[10]

1010mA

VCCASW[4] VCCASW[5]

W24

T24

VCCSUS3_3[9]

VCCASW[1]

AA29

W23

VCCSUS3_3[8]

SATA

B

2

1

+VCCDIFFCLK 1

R286 0_0603_5% 2 1

+

T23

MISC

+1.05VS_PCH

R284 0_0603_5% 2 1

2

1

DCPSUS[3]

AA27

W21 C253 1U_0402_6.3V6K

2

1

C252 220U_B2_2.5VM_R35

+

C251 1U_0402_6.3V6K

1

C250 220U_B2_2.5VM_R35

L6 10UH_LB2012T100MR_20%

VCCIO[14]

VCCASW[3]

AD31 1

T29

119mA VCCSUS3_3[7] VCCAPLLDMI2

AA24

AD29

+1.05VS_VCCA_A_DPL

VCCIO[33]

VCCASW[2]

AA31

VCCIO[32]

C233 1U_0402_6.3V6K

2

T27

VCC3_3[5]

AA21

AA26

C246 1U_0402_6.3V6K

L5 10UH_LB2012T100MR_20% +VCCA_DPLL_L 1 2

1

C245 1U_0402_6.3V6K

2 +1.05VS_PCH

1

C244 1U_0402_6.3V6K

1

2

C242 22U_0805_6.3V6M

2

AA19

+1.05VM_VCCASW 1

C241 22U_0805_6.3V6M

1

@ C239 1U_0402_6.3V6K

DCPSUSBYP

P28

2

+3VS_VCC_CLKF33

P26

2

V12

+1.05VS_PCH

1

+PCH_VCCDSW

USB

L4 10UH_LBR2012T100M_20% +VCCAPLL_CPY 1 2 +1.05VS_PCH

R270 0_0603_5% 2 1

+1.05VS_VCCUSBCORE 1

1

VCCIO[31]

@

1

VCCIO[30]

3mA

VCCDSW3_3

N26

1

T16

VCCIO[29]

2

C234 0.1U_0402_10V7K

2

C235 0.1U_0402_10V7K 2 1

VCCACLK

1

AD49

2

7/1 update to @ @

POWER

U4J +VCCPDSW 1

C236 0.1U_0402_10V7K

@ R271 0_0603_5% 1 2

2

R269 0_0603_5% 1 2

VCCRTC

COUGARPOINT_FCBGA989

HDA

+1.05VS_PCH

C232 1U_0402_6.3V6K

2 D

+3VALW

+3VS_VCC_CLKF33 1

C231 10U_0805_10V4Z

1

VCCDMI = 42mA detal waiting for newest spec

PCI/GPIO/LPC

L3 10UH_LBR2012T100M_20% 1 2

VCC3_3 = 266mA detal waiting for newest spec +VCCACLK

Clock and Miscellaneous

@ R267 0_0805_5% 2

CPU

1

RTC

+3VS

10mA VCCSUSHDA

1

C271 0.1U_0402_16V4Z

A

2

@

Compal Secret Data

Security Classification Issued Date

2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. PCH (8/9) PWR

Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet 1

21

of

59

5

4

3

2

1

U4I

D

AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3

U4H H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3

C

B

VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79]

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

COUGARPOINT_FCBGA989

VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258]

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]

D

C

B

A

A

COUGARPOINT_FCBGA989

Compal Secret Data

Security Classification Issued Date

2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. PCH (9/9) VSS

Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet 1

22

of

59

5

4

PCIE_CTX_GRX_P[15..0]

<5> PCIE_CTX_GRX_P[15..0]

3

PCIE_CRX_GTX_P[15..0]

U8A

PCIE_CTX_GRX_N[15..0]

<5> PCIE_CTX_GRX_N[15..0]

2

PCIE_CRX_GTX_P[15..0] <5>

PCIE_CRX_GTX_N[15..0]

1

U8F R296 1 2 10K_0402_5%

PCIE_CRX_GTX_N[15..0] <5> LVDS CONTROL

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0

AF30 AE31

PCIE_RX0P PCIE_RX0N

PCIE_TX0P PCIE_TX0N

AH30 PCIE_CRX_C_GTX_P0 AG31 PCIE_CRX_C_GTX_N0

0.1U_0402_10V7K C273 2 1 2 1 0.1U_0402_10V7K C272

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0

PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1

AE29 AD28

PCIE_RX1P PCIE_RX1N

PCIE_TX1P PCIE_TX1N

AG29 PCIE_CRX_C_GTX_P1 AF28 PCIE_CRX_C_GTX_N1

0.1U_0402_10V7K C274 2 1 2 1 0.1U_0402_10V7K C275

PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1

PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2

AD30 AC31

PCIE_RX2P PCIE_RX2N

PCIE_TX2P PCIE_TX2N

AF27 PCIE_CRX_C_GTX_P2 AF26 PCIE_CRX_C_GTX_N2

0.1U_0402_10V7K C276 2 1 2 1 0.1U_0402_10V7K C277

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3

AC29 AB28

PCIE_RX3P PCIE_RX3N

PCIE_TX3P PCIE_TX3N

AD27 PCIE_CRX_C_GTX_P3 AD26 PCIE_CRX_C_GTX_N3

0.1U_0402_10V7K C278 2 1 2 1 0.1U_0402_10V7K C279

PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3

PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4

AB30 AA31

PCIE_RX4P PCIE_RX4N

PCIE_TX4P PCIE_TX4N

AC25 PCIE_CRX_C_GTX_P4 AB25 PCIE_CRX_C_GTX_N4

0.1U_0402_10V7K C280 2 1 2 1 0.1U_0402_10V7K C281

PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4

PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5

AA29 Y28

PCIE_RX5P PCIE_RX5N

PCIE_TX5P PCIE_TX5N

Y23 Y24

PCIE_CRX_C_GTX_P5 PCIE_CRX_C_GTX_N5

0.1U_0402_10V7K C282 2 1 2 1 0.1U_0402_10V7K C283

PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5

PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6

Y30 W31

PCIE_RX6P PCIE_RX6N

PCIE_TX6P PCIE_TX6N

AB27 PCIE_CRX_C_GTX_P6 AB26 PCIE_CRX_C_GTX_N6

0.1U_0402_10V7K C284 2 1 2 1 0.1U_0402_10V7K C285

PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6

PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7

W29 V28

PCIE_RX7P PCIE_RX7N

PCIE_TX7P PCIE_TX7N

Y27 Y26

PCIE_CRX_C_GTX_P7 PCIE_CRX_C_GTX_N7

0.1U_0402_10V7K C286 2 1 2 1 0.1U_0402_10V7K C287

PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7

PCIE_CTX_GRX_P8 PCIE_CTX_GRX_N8

V30 U31

PCIE_RX8P PCIE_RX8N

PCIE_TX8P PCIE_TX8N

W24 PCIE_CRX_C_GTX_P8 W23 PCIE_CRX_C_GTX_N8

0.1U_0402_10V7K C288 2 1 2 1 0.1U_0402_10V7K C289

PCIE_CRX_GTX_P8 PCIE_CRX_GTX_N8

PCIE_CTX_GRX_P9 PCIE_CTX_GRX_N9

U29 T28

PCIE_RX9P PCIE_RX9N

PCIE_TX9P PCIE_TX9N

V27 PCIE_CRX_C_GTX_P9 U26 PCIE_CRX_C_GTX_N9

0.1U_0402_10V7K C290 2 1 2 1 0.1U_0402_10V7K C291

PCIE_CRX_GTX_P9 PCIE_CRX_GTX_N9

PCIE_CTX_GRX_P10 PCIE_CTX_GRX_N10

T30 R31

PCIE_RX10P PCIE_RX10N

PCIE_TX10P PCIE_TX10N

U24 PCIE_CRX_C_GTX_P10 U23 PCIE_CRX_C_GTX_N10

0.1U_0402_10V7K C292 2 1 2 1 0.1U_0402_10V7K C293

PCIE_CRX_GTX_P10 PCIE_CRX_GTX_N10

PCIE_CTX_GRX_P11 PCIE_CTX_GRX_N11

R29 P28

PCIE_RX11P PCIE_RX11N

PCIE_TX11P PCIE_TX11N

T26 T27

PCIE_CRX_C_GTX_P11 PCIE_CRX_C_GTX_N11

0.1U_0402_10V7K C294 2 1 2 1 0.1U_0402_10V7K C295

PCIE_CRX_GTX_P11 PCIE_CRX_GTX_N11

PCIE_CTX_GRX_P12 PCIE_CTX_GRX_N12

P30 N31

PCIE_RX12P PCIE_RX12N

PCIE_TX12P PCIE_TX12N

T24 T23

PCIE_CRX_C_GTX_P12 PCIE_CRX_C_GTX_N12

0.1U_0402_10V7K C296 2 1 2 1 0.1U_0402_10V7K C297

PCIE_CRX_GTX_P12 PCIE_CRX_GTX_N12

PCIE_CTX_GRX_P13 PCIE_CTX_GRX_N13

N29 M28

PCIE_RX13P PCIE_RX13N

PCIE_TX13P PCIE_TX13N

P27 P26

PCIE_CRX_C_GTX_P13 PCIE_CRX_C_GTX_N13

0.1U_0402_10V7K C298 2 1 2 1 0.1U_0402_10V7K C299

PCIE_CRX_GTX_P13 PCIE_CRX_GTX_N13

PCIE_CTX_GRX_P14 PCIE_CTX_GRX_N14

M30 L31

PCIE_RX14P PCIE_RX14N

PCIE_TX14P PCIE_TX14N

P24 P23

PCIE_CRX_C_GTX_P14 PCIE_CRX_C_GTX_N14

0.1U_0402_10V7K C300 2 1 2 1 0.1U_0402_10V7K C301

PCIE_CRX_GTX_P14 PCIE_CRX_GTX_N14

PCIE_CTX_GRX_P15 PCIE_CTX_GRX_N15

L29 K30

PCIE_RX15P PCIE_RX15N

PCIE_TX15P PCIE_TX15N

M27 PCIE_CRX_C_GTX_P15 N26 PCIE_CRX_C_GTX_N15

0.1U_0402_10V7K C302 2 1 2 1 0.1U_0402_10V7K C303

PCIE_CRX_GTX_P15 PCIE_CRX_GTX_N15

D

B

T48 PAD CLK_PCIE_VGA CLK_PCIE_VGA#

<15> CLK_PCIE_VGA <15> CLK_PCIE_VGA#

PCI EXPRESS INTERFACE

C

VARY_BL DIGON

AB11 AB12

VGA_ENVDD

VGA_ENVDD <31>

1

2 R297 10K_0402_5%

D

TXCLK_UP_DPF3P TXCLK_UN_DPF3N

AH20 AJ19

TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N

AL21 AK20

TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N

AH22 AJ21

TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N

AL23 AK22

TXOUT_U3P TXOUT_U3N

AK24 AJ23

TXCLK_LP_DPE3P TXCLK_LN_DPE3N

AL15 AK14

VGA_LVDS_ACLK <31> VGA_LVDS_ACLK# <31>

TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N

AH16 AJ15

VGA_LVDS_A0 <31> VGA_LVDS_A0# <31>

TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N

AL17 AK16

VGA_LVDS_A1 <31> VGA_LVDS_A1# <31>

TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N

AH18 AJ17

VGA_LVDS_A2 <31> VGA_LVDS_A2# <31>

TXOUT_L3P TXOUT_L3N

AL19 AK18

LVTMDP

C

216-0774207-A11ROB_FCBGA631

LVDS B

CLOCK AK30 AK32

PCIE_REFCLKP PCIE_REFCLKN

T49 PAD CALIBRATION VGA_PWRGD

<25> VGA_PWRGD

2 R299 1 10K_0402_5%

A

N10 AL27

<18> VGA_RST#

PWRGOOD

PCIE_CALRP

Y22 1.27K_0402_1% 1

2 R298

PCIE_CALRN

AA22

2K_0402_5% 1

2 R300

+1.0VGS

PERSTB

PCIE LANE 5

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 216-0774207-A11ROB_FCBGA631

A

2010/07/12

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3

2

RobsonXT-S3 PCIE/LVDS Size B Date:

Document Number Friday, November 26, 2010

Rev 0.1 Sheet 1

23

of

59

5

4

Transmitter Power Saving Enable GPIO0 0: 50% Tx output swing for mobile mode 1: full Tx output swing (Default setting for Desktop)

TX_DEEMPH_EN

PCI Express Transmitter De-emphasis Enable GPIO1 0: Tx de-emphasis diabled for mobile mode 1: Tx de-emphasis enabled (Defailt setting for desktop)

TX5P_DPB0P TX5M_DPB0N

+DPC_VDD10

AA5 AA6

C308 1U_0402_6.3V4Z

1

Change to 0 ohm P/N

C309 0.1U_0402_10V6K

110mA +DPC_VDD10 C307 10U_0603_6.3V6M

2 1 BLM15BD121SN1D_0402

1

2

1

2

GPIO2

RESERVED

0

AK6 AM5

RSVD

GPIO8

RESERVED

0

AJ7 AH6

BIF_VGA DIS

GPIO9

VGA ENABLED

0

AK8 AL7

RSVD

GPIO21

RESERVED

0

BIOS_ROM_EN

GPIO_22_ROMCSB

ENABLE EXTERNAL BIOS ROM

X

ROMIDCFG(2:0)

GPIO[13:11]

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

XXX

V2SYNC

IGNORE VIP DEVICE STRAPS

0

DPC

DPC_PVDD DPC_PVSS

TXCCP_DPC3P TXCCM_DPC3N

DPC_VDD18#1 DPC_VDD18#2

TX0P_DPC2P TX0M_DPC2N

DPC_VDD10#1 DPC_VDD10#2

TX1P_DPC1P TX1M_DPC1N

2

U1 W1 U3 Y6 AA1

RSVD

DPC_VSSR#1 DPC_VSSR#2 DPC_VSSR#3 DPC_VSSR#4 DPC_VSSR#5

TX2P_DPC0P TX2M_DPC0N DPC_CALR

V4 U5 W3 V2

VIP_DEVICE_STRAP_ENA

Y4 W5

RSVD

H2SYNC

AA3 Y2

RSVD

GENERICC

VGA_CRT_R

AUD[1]

HSYNC

VGA_CRT_G

AUD[0]

VSYNC

J8

1 R305 2 150_0402_1%

I2C

1 R662 2 10K_0402_5%

1

ACIN

VGA_ENBKL

<31> VGA_ENBKL

@

<52> GPU_VID0

<52> GPU_VID1 <15> PEG_CLKREQ#

+3VGS 1 1 1 1

R321 R322 R323 R324

10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2

GPIO24_TRSTB GPIO25_TDI GPIO27_TMS GPIO26_TCK

T64 2

+1.8VGS

U6 U10 T10 U8 @ U7 GPU_GPIO5 2 T9 T8 T7 GPU_GPIO8 P10 GPU_GPIO9 P4 P2 GPU_GPIO11 N6 GPU_GPIO12 N5 GPU_GPIO13 N3 Y9 GPU_VID0 N1 T63 M4 THM_ALERT# R6 W10 R319 1 10K_0402_5% 2 M2 GPU_VID1 P8 P7 N8 PEG_CLKREQ# N7

1 R326 10K_0402_5%

GPIO24_TRSTB L6 GPIO25_TDI L5 GPIO26_TCK L3 GPIO27_TMS L1 GPIO28_TDO K4 TEST_EN K7 T65 AF24 AB13 W8 W9 W7 AD10

+DPLL_PVDD +DPLL_PVDD

C324 1U_0402_6.3V4Z

C325 0.1U_0402_10V6K

75mA C323 10U_0603_6.3V6M

L14 2 1 BLM15BD121SN1D_0402

1

1

2

1

2

<33> HDMI_DETECT_VGA <25> PX_EN

+1.0VGS

+DPLL_VDDC

2

+1.8VGS

1

2

1

2

L17

1499_0402_1%

2 R331

1249_0402_1%

1

2

XTALOUT

+VREFG_GPU

GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4

R2 R2B G2 G2B B2 B2B C Y COMP H2SYNC V2SYNC VDD2DI VSS2DI

HPD1 PX_EN

A2VSSQ

AF14 AE14

+DPLL_VDDC

+DPLL_VDDC

AD14

XTALIN XTALOUT

XTALIN Voltage Swing: 1.8 V 2 R332 2 R333

10_0402_5% 10_0402_5%

AM28 AK28 AC22 AB22

1

DPLL_PVDD DPLL_PVSS

DDC1CLK DDC1DATA AUX1P AUX1N

DPLL_VDDC

DDC2CLK DDC2DATA

XTALIN XTALOUT

AUX2P AUX2N

XO_IN XO_IN2

DDCCLK_AUX3P DDCDATA_AUX3N DDCCLK_AUX5P DDCDATA_AUX5N

2

GPU_THERMAL_D+ GPU_THERMAL_D-

R337 XTALIN 1M_0603_5%

+3VGS +TSVDD

2.61K_0402_5% 1 +TSVDD

2

T4 T2 R5 AD17 AC17

VGA_CRT_G

AH24 AG25

VGA_CRT_B

AH26 AJ27

VGA_HSYNC VGA_VSYNC

AD22 AG24 AE22

VGA_CRT_R

<32>

VGA_CRT_G

<32>

VGA_CRT_B

<32>

VGA_HSYNC VGA_VSYNC

<32> <32>

+AVDD

1

2

DPLUS DMINUS

1

2

THERMAL

DDC6CLK DDC6DATA

2

AH12 AM10 AJ9

1

STRAPS

Change to 0 ohm P/N

2

2

1

AD19 +VDD2DI AC19

+VDD2DI

AE20 +A2VDD

+A2VDD

AE17 +A2VDDQ

+A2VDDQ

2

1

2

2 2 2 2

@ @

1 1 1 1

GPU_GPIO8 GPU_GPIO9

R313 R314

2 2

@ @

1 10K_0402_5% 1 10K_0402_5%

GPU_GPIO11 R315 GPU_GPIO12 R316 GPU_GPIO13 R317

2 2 2

@ @

1 10K_0402_5% 1 10K_0402_5% 1 10K_0402_5%

R548 R549

1 DIS@ 1 DIS@

Change to 0 ohm P/N

R714 R713 R712 R711 R621 R426

2 2 2 2 2 2

2

2 AG13 1 R330 715_0402_1%

B

+3VGS

2

R327 10K_0402_5% +3VGS

VGA_HDMI_SCL VGA_HDMI_SDA

VGA_HDMI_SCL VGA_HDMI_SDA

<33> <33>

VGA_LVDS_SCL VGA_LVDS_SDA

<31> <31>

2

AD2 AD4

L13 1 2 BLM15BD121SN1D_0402

VGA_SMB_CK2_R

Change to 0 ohm P/N

VGA_SMB_DA2_R

100mA 1

+3VGS R328 10K_0402_5%

8/14 change P/N to DMN66D0LDW-7_SOT363-6 (SB00000DH00)

1

2

1

6

Q64A 2N7002DW-T/R7_SOT363-6

1

4

EC_SMB_CK2

<15,37,40>

EC_SMB_DA2

<15,37,40>

Q64B 2N7002DW-T/R7_SOT363-6

2

+A2VDDQ

+1.8VGS

AD13 AD11

1

AD20 AC20

2

AE16 AD16 VGA_DDCCLK VGA_DDCDATA

L15

130mA +A2VDDQ 1

2

C329 0.1U_0402_16V4Z

1 2 BLM15BD121SN1D_0402

1

VGA Thermal Sensor EMC1402-1 Closed to

2

1

Change to 0 ohm P/N

1

2

VGA_DDCCLK <32> VGA_DDCDATA <32>

GPU_THERMAL_D+

2

1 2 C333 2200P_0402_50V7K GPU_THERMAL_D-

3

+3VGS

TS_FDO TSVDD TSVSS

GPU

U9

1 R335

4

VDD

SCLK

D+

SDATA

D-

ALERT#

THERM#

GND

8

VGA_SMB_CK2_R

7

VGA_SMB_DA2_R

6 THM_ALERT#

5

A

2 R336 1 4.7K_0402_5%

EMC1402-2-ACZL-TR MSOP 8P

2

+3VGS

4.7K_0402_5% EMC1412-A (SA00003YA00) Address 1111_100xb S IC EMC1412-A-ACZL-TR MSOP 8P SENSOR

@

216-0774207-A11ROB_FCBGA631

1

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

C338 18P_0402_50V8J

2010/07/12

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

RobsonXT-S3 Main Generic/MSIC Size C Date:

5

3

+3VGS VGA_LVDS_SCL VGA_LVDS_SDA

27MHZ_16PF_X5H027000FG1H C337 18P_0402_50V8J

DIS_HDMI@ 1 10K_0402_5% DIS_HDMI@ 1 10K_0402_5% DIS@ 1 10K_0402_5% DIS@ 1 10K_0402_5% DIS@ 1 10K_0402_5% DIS@ 1 10K_0402_5%

Change to 0 ohm P/N

Y3

SD013000080

2 10K_0402_5% 2 10K_0402_5%

+3VGS VGA_HDMI_SCL VGA_HDMI_SDA VGA_LVDS_SCL VGA_LVDS_SDA VGA_DDCCLK VGA_DDCDATA

1

+A2VDD

AE19

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

8/5 Add For DIS HDMI audio strap

+1.8VGS L12 1 2 BLM15BD121SN1D_0402

2mA

+VDD2DI

R309 R310 R311 R308

2

+VDD2DI

AL13 AJ13

+3VGS

GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 GPU_GPIO5

VGA_HSYNC VGA_VSYNC

L11 1 2 BLM15BD121SN1D_0402

1

C

GPIO8

1

110mA 1

AK10 AL9

AC1 AC3

GPIO2

+1.8VGS

+VDD1DI

AL11 AJ11

AC11 AC13

GENERICC

+VDD1DI

AM12 AK12

AE6 AE5

H2SYNC

+1.8VGS L10 1 2 BLM15BD121SN1D_0402

65mA

+AVDD

1 R312 2 499_0402_1% +AVDD +AVDD

AE23 +VDD1DI AD23

AMD RESERVED CONFIGURATION STRAPS

GPIO21

+A2VDD

VREFG

DDC/AUX +DPLL_PVDD

VGA_CRT_R

AL25 AJ25

DAC2

A2VDDQ

AC16

AM26 AK26

11

ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND NOT CONFLICT DURING RESET

+VDD1DI

R2SET

+DPLL_PVDD

R334

0_0603 5%

VDD1DI VSS1DI

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO TESTEN TESTEN_LEGACY

1 0.1U_0402_10V6K

@ C336 0.1U_0402_16V4Z

1

2 R329

+TSVDD

C335 @ 1U_0402_6.3V4Z

@ C334 10U_0603_6.3V6M

2 1 BLM18AG121SN1D_0603

RSET AVDD AVSSQ

PLL/CLOCK

+TSVDD

20mA

HSYNC VSYNC

A2VDD

2

@ L17

B BB

DAC1

0.60 V level, Please VREFG Divider ans cap close to ASIC

2 C322

C332 0.1U_0402_10V6K

1

C331 1U_0402_6.3V4Z

125mA +DPLL_VDDC C330 10U_0603_6.3V6M

2 1 BLM15BD121SN1D_0402

G GB

1 2 R613 4.7K_0402_5%

2

+1.8VGS

L16

AC14 AB16

PX_EN

GPIO_0 GPIO_1 GPIO_2 GPIO_3_SMBDATA GPIO_4_SMBCLK GPIO_5_AC_BATT GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16_SSIN GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21_BB_EN GPIO_22_ROMCSB GPIO_23_CLKREQB

0 AUD[1] AUD[0] 0 0 No audio function 0 1 Audio for DisplayPort and HDMI if dongle is detected 1 0 Audio for DisplayPort only 1 1 Audio for both DisplayPort and HDMI

2

D3

CH751H-40PT_SOD323-2 <16,40,47> VGA_ENBKL

GPU_GPIO0 GPU_GPIO1 GPU_GPIO2

C310 0.1U_0402_10V6K

8/13 update to @

A

R RB

GENERAL PURPOSE I/O

C

B

SCL SDA

C313 0.1U_0402_10V6K

R1 R3

C316 0.1U_0402_10V6K

VGA_SMB_CK2_R VGA_SMB_DA2_R

C319 0.1U_0402_10V6K

VGA_SMB_CK2_R 4.7K_0402_5% 2 4.7K_0402_5% VGA_SMB_DA2_R 2

1R306 1R307

C326 0.1U_0402_10V6K

@ @

R318 1 2 150_0402_1%

VGA_CRT_B +3VGS

D

0

1

AC6 AC5

+DPC_VDD10

+DPC_VDD10 L9

X

AK5 AM3

R541 1 2 150_0402_1%

+DPC_VDD18

+DPC_VDD18

W6 V6

PCIE TRANSMITTER DE-EMPHASIS ENABLED

C312 10U_0603_6.3V6M

+DPC_VDD18

X

GPIO1

C315 10U_0603_6.3V6M

+1.0VGS

+DPC_VDD18

PCIE FULL TX OUTPUT SWING

TX_DEEMPH_EN

5

TX4P_DPB1P TX4M_DPB1N

GPIO0

VGA_HDMI_TX2+ <33> VGA_HDMI_TX2- <33>

1

DPB

TX_PWRS_ENB

AK3 AK1

RECOMMENDED SETTINGS

2

TX3P_DPB2P TX3M_DPB2N

DESCRIPTION OF DEFAULT SETTINGS

2

TXCBP_DPB3P TXCBM_DPB3N

PIN

VGA_HDMI_TX1+ <33> VGA_HDMI_TX1- <33>

C318 10U_0603_6.3V6M

VRAM_ID2 VRAM_ID1 VRAM_ID0

TX2P_DPA0P TX2M_DPA0N

STRAPS

AH3 AH1

<33> <33>

C321 10U_0603_6.3V6M

<29> <29> <29>

2

TX1P_DPA1P TX1M_DPA1N

DVDATA_12 DVDATA_11 DVDATA_10 DVDATA_9 DVDATA_8 DVDATA_7 DVDATA_6 DVDATA_5 DVDATA_4 DVDATA_3 DVDATA_2 DVDATA_1 DVDATA_0

VGA_HDMI_TX0+ <33> VGA_HDMI_TX0- <33>

C328 10U_0603_6.3V6M

2

DPA

VGA_HDMI_CLK+ VGA_HDMI_CLK-

R320 1 2 150_0402_1%

2

1

AE8 AD9 AC10 AD7 AC8 AC7 AB9 AB8 AB7 AB4 AB2 Y8 Y7

DVO

TX0P_DPA2P TX0M_DPA2N

AF2 AF4

C311 1U_0402_6.3V4Z

1

RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE

AG3 AG5

C314 1U_0402_6.3V4Z

T50 T56 T57 T51 T58 T59 T60 T61 T62 T70 VRAM_ID2 VRAM_ID1 VRAM_ID0

TXCAP_DPA3P TXCAM_DPA3N DVCLK DVCNTL_0 DVCNTL_1 DVCNTL_2

C317 1U_0402_6.3V4Z

C306 0.1U_0402_10V6K

1

Change to 0 ohm P/N

Y11 AE9 L9 N9

C320 1U_0402_6.3V4Z

T52 T53 T54 T55

150mA +DPC_VDD18 C305 1U_0402_6.3V4Z

L8 2 1 BLM15BD121SN1D_0402

1

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

+DPC_VDD18

C304 10U_0603_6.3V6M

D

2

CONFIGURATION STRAPS

C327 1U_0402_6.3V4Z

+1.8VGS

3

U8B

TX_PWRS_ENB

4

3

2

Document Number

Rev 0.2

Friday, November 26, 2010

Sheet 1

24

of

59

5

4

3

@ 0_0402_5% 1 2 VGA_PWRGD R689

<52> VGA_CORE_PG

2

1

VGA_PWRGD <23>

+3VGS

VGA_CORE_PG

+5VS

+5VS D

+3VS @

2

2 PX_MODE

2

1

0_0402_5%

10K_0402_5%

B A

1

2 1

1

2

VDDC_ON# 1.0V_ON#

D 2N7002H_SOT23-3 Q66 Change footprint 20100814 BACO@

2 G

MC74VHC1G08DFT2G SC70 5P

S

D

2 G 3

1 R340

R692

@ 1

BACO@

U10 BACO@ Y 4

3

+3VGS

P

1 R612 2 10K_0402_5%

G

5

2

R338 10K_0402_5% BACO@

R339 10K_0402_5% BACO@

3

1

0.1U_0402_10V6K @

C339

1

D

S

2N7002H_SOT23-3 Q67 Change footprint 20100814

3

S

D

BACO@

Q71 AO3414_SOT23-3

Q72 AO3414_SOT23-3 S

D

P

3 BACO@

VDDC_ON#

2 G

G

G

1

BACO@

U40 SN74LVC1G07DCKR_SC70-5

2

B

2 R342 0_0402_5% DIS@

2

1

BACO@ 1 C732 1U_0603_10V4Z @

1

1

RUNPWROK

4

+VGA_CORE

3

2 G

1.0V_ON#

BACO@ MC74VHC1G08DFT2G SC70 5P

3 Y

3

1

BACO@

+VGA_CORE

NC A

1

PX_MODE <26,52>

5

1 2

PX_MODE

D

2

A

4

S

2

3 Y

C

+BIF_VDDC

G

PE_GPIO1 1 D28 CH751H-40PT_SOD323-2

@ 0.1U_0402_10V6K

B

Q70 AO3414_SOT23-3 D

1 C731 1 2

<15,18,26,52> PE_GPIO1

Q69 AO3414_SOT23-3 +1.0VGS S

2 +3VGS

@ 1

C386 0.1U_0402_10V6K @

U37

BACO@

BACO@ R872 20K_0402_5%

2

BACO@ C343 0.1U_0402_10V6K

0.1U_0402_10V6K @ 1 2

+3VGS

2

S

2

2 G

5

C

2 R341 0_0402_5% BACO@

P

1

PX_EN

3

<24>

C382

2N7002H_SOT23-3 Q68 Change footprint 20100814

G

1

BACO@ 1

D

Add when verify BACO 2 1 R873 0_0402_5% BACO@

9/28 modify to AO3414

B

D28 with leakage need to check

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/07/12

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

PARK-S3 Main Generic/MSIC Size B Date:

Document Number

Rev 0.1

LA-6751P Friday, November 26, 2010

Sheet 1

25

of

59

5

4

3

2

1

Short J2 for control sequence at PWM

+VGA_PCIE TO +1.0VGS +VGA_PCIE

+1.8VS

+1.0VGS @ 2

+1.8VGS

@

+1.8VS TO +1.8VGS

2

1

1 2MM

R664 470_0603_5%

2

C348 10U_0805_10V4Z

2

Change footprint 20100814

3

2

D

S

@

C350 1U_0603_10V4Z

R348 470_0603_5% @

D 2N7002H_SOT23-3 Q76 @

1

2N7002H_SOT23-3 1 C730 Q85 0.1U_0603_25V7K

2

S@

2

2 G Change footprint 20100814

S

330K_0402_5% R350

1

D

2 G

S

1 C349 10U_0805_10V4Z

+VSB 2 G Change footprint 20100814

3

PE_GPIO1#

1

20K_0402_5%

3

@

2N7002H_SOT23-3 Q75 @

0_0402_5% 2 R687 @

1

2

@

D R640

1

1 2

@ +VSB

C368

3

2

1

4

C375

1

1

1 1

4

2

10U_0805_10V4Z 1U_0603_10V4Z

DMN3030LSS-13_SOP8L-8 8 1 7 2 6 3 5

1 R352 2 0_0402_5% PE_GPIO1# PE_GPIO1#

2 G

R354 0_0402_5% @

Q78

Change footprint 20100814

PE_GPIO1#

2

C346 10U_0805_10V4Z

D

U13

U14 @ DMN3030LSS-13_SOP8L-8 8 1 7 2 6 3 5

1

J5

J2

1

2MM

1 2

D

1

C352 0.1U_0603_25V7K

2

2N7002H_SOT23-3

C

C

+1.5VS TO +1.5VGS +1.5V

+1.5VGS

2MM J3 @ U11 DMN3030LSS-13_SOP8L-8 8 1 7 2 1 6 3 C340 5 10U_0805_10V4Z 2

@

C376

1

C377

R686 470_0603_5% @

2

R688

20K_0402_5%

20K_0402_5%

S

DIS@ 1

0_0402_5% 2

PE_GPIO1

2 G Change footprint 20100814

Q86 S 2N7002H_SOT23-3

3

B

D

PE_GPIO1# C351 0.1U_0603_25V7K

PX_MODE#

1 R677 BACO@

2

1

0_0402_5% 2

D

2 G

R343 470_0603_5% @ D

R345 1 2 200K_0402_1%

S

S

@ R346 0_0402_5% @

Q74 3

1

R674

C342 1U_0603_10V4Z

2N7002H_SOT23-3 Q73 @

R344 20K_0402_5%

2 G Change footprint 20100814

1

2

+VSB

PE_GPIO1# 1

2

D

2N7002H_SOT23-3 Q77 @

R641

C341 10U_0805_10V4Z

1

2

2 Q65 AP2301GN-HF_SOT23-3

3

Change footprint 20100814

2

1

1

1 2

1

4

J4

3 +5VALW

10U_0805_10V4Z 1U_0603_10V4Z

1 2MM

1

2

3

+3VGS

2

+3VS

1

+3.3VS TO +3.3VGS

1

1

2

2

0_0402_5% 2

PE_GPIO1# 1

1 C344 0.1U_0603_25V7K

2 G Change footprint 20100814

R680 @ PX_MODE# 1

0_0402_5% 2

B

R681

2N7002H_SOT23-3

Add when verify BACO

Change footprint 20100814

DIS@

<10,40,44,49,51,52> SUSP#

0_0402_5% 1 2 R744

PE_GPIO1 +3VALW

1

1

+3VALW

R676 100K_0402_5% 2

2

R718 100K_0402_5%

2N7002H_SOT23-3 Q87 Change footprint 20100814

<15,18,25,52> PE_GPIO1

PE_GPIO1

2

IN

1

2

R719 100K_0402_5%

OUT

S

2 G

PE_GPIO1# Q121 DTC124EKAT146_SC59-3

GND

1 3

PX_MODE 1

<25,52> PX_MODE

PX_MODE# D

A

3

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

PARK-S3 Main Generic/MSIC Size Document Number Custom Date:

Rev 0.1

LA-6751P

Friday, November 26, 2010

Sheet 1

26

of

59

5

4

2

+DPEF_VDD18

1

U8G

2

DP E/F POWER

130mA AG15 AG16

DPE_VDD18#1 DPE_VDD18#2

+DPEF_VDD10

1

MBK1608121YZF_0603 Change to 0 ohm P/N

2

1

2

DPA_VDD18#1 DPA_VDD18#2

AE11 +DPAB_VDD18 AF11 +DPAB_VDD10

110mA

C361 0.1U_0402_10V6K

1

C360 1U_0402_6.3V4Z

2

total:240mA@LVDS total:220mA@DP C356 10U_0603_6.3V6M

L20

2

DP A/B POWER

1

2

AG20 AG21

DPE_VDD10#1 DPE_VDD10#2

DPA_VDD10#1 DPA_VDD10#2

AF6 AF7

AG14 AH14 AM14 AM16 AM18

DPE_VSSR#1 DPE_VSSR#2 DPE_VSSR#3 DPE_VSSR#4 DPE_VSSR#5

DPA_VSSR#1 DPA_VSSR#2 DPA_VSSR#3 DPA_VSSR#4 DPA_VSSR#5

AE1 AE3 AG1 AG6 AH5

AF16 AG17

DPF_VDD18#1 DPF_VDD18#2

DPB_VDD18#1 DPB_VDD18#2

1

2

2 1 1 MBK1608121YZF_0603

C359 10U_0603_6.3V6M

1

2

1

2

+DPEF_VDD18

D

Change to 0 ohm P/N +1.0VGS

total:220mA 1

2

C364 10U_0603_6.3V6M

2

+1.8VGS

C358 1U_0402_6.3V4Z

2

+1.0VGS

C357 0.1U_0402_10V6K

Change to 0 ohm P/N

1

C362 0.1U_0402_10V6K

1

MBK1608121YZF_0603

1

L19

total:300mA

C355 0.1U_0402_10V6K

1

D

C354 1U_0402_6.3V4Z

2

+DPAB_VDD18

total:440mA@LVDS total:300mA@DP C353 10U_0603_6.3V6M

L18

C363 1U_0402_6.3V4Z

+1.8VGS

3

L21 1

2

1

2

MBK1608121YZF_0603

Change to 0 ohm P/N

+DPAB_VDD18

130mA C

AE13 AF13

+DPAB_VDD18 C

+DPEF_VDD10

+DPAB_VDD10

110mA

R355 2 1 150_0402_1%

AF22 AG22

DPF_VDD10#1 DPF_VDD10#2

DPB_VDD10#1 DPB_VDD10#2

AF8 AF9

AF23 AG23 AM20 AM22 AM24

DPF_VSSR#1 DPF_VSSR#2 DPF_VSSR#3 DPF_VSSR#4 DPF_VSSR#5

DPB_VSSR#1 DPB_VSSR#2 DPB_VSSR#3 DPB_VSSR#4 DPB_VSSR#5

AF10 AG9 AH8 AM6 AM8

AF17

DPEF_CALR

DPAB_CALR

AE10

+DPEF_VDD18

1 R356 2 150_0402_1% +DPAB_VDD18

20mA +DPEF_VDD18

AG18 AF19

20mA DPE_PVDD DPE_PVSS

DP PLL POWER

DPA_PVDD DPA_PVSS

AG8 AG7

+DPEF_VDD18

B

+DPAB_VDD10

+DPAB_VDD18 +DPAB_VDD18

20mA +DPEF_VDD18

AG19 AF20

B

20mA DPF_PVDD DPF_PVSS

DPB_PVDD DPB_PVSS

AG10 AG11

+DPAB_VDD18

216-0774207-A11ROB_FCBGA631

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/07/12

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

RobsonXT-S3 DP PWR Size B Date:

Document Number Friday, November 26, 2010

Rev 0.1 Sheet 1

27

of

59

5

4

3

2

1

+1.5VGS

2

+PCIE_VDDR

L24 C430 0.1U_0402_10V6K C447 1U_0402_6.3V4Z

1

2

V11 U11

VDDR4#1 VDDR4#2 VDDR4#3 NC#1 NC#2 NC#3 NC#4

MEM CLK

2

C449 0.1U_0402_10V6K

AM30

1

2

75mA L8

+SPV18

75mA H7

+SPV10

120mAH8

+1.0VGS

J7 L28

1 2 BLM15BD121SN1D_0402

1

2

B

+MPV18

1

2

@

C380 10U_0603_6.3V6M

C388 1U_0402_6.3V4Z

C387 1U_0402_6.3V4Z 2

1

2

AA27 AB24 AB32 AC24 AC26 AC27 AD25 AD32 AE27 AF32 AG27 AH32 K28 K32 L27 M32 N25 N27 P25 P32 R27 T25 T32 U25 U27 V32 W25 W26 W27 Y25 Y32

1

2

C384 10U_0603_6.3V6M

1

C403 1U_0402_6.3V4Z

2

C399 1U_0402_6.3V4Z

C398 1U_0402_6.3V4Z

1920mA 1

1

2

+VGA_CORE

2

1

2

1

2

1

1

2

2

1

2

1

2

C426 22U_0805_6.3V6M

2

1

C425 22U_0805_6.3V6M

2

1

C424 10U_0603_6.3V6M

2

1

C423 10U_0603_6.3V6M

2

1

C420 1U_0402_6.3V4Z

1

C419 1U_0402_6.3V4Z

11.8A(RMS)/12.9A(Peak) 1

2

M6 N11 N12 N13 N16 N18 N21 P6 P9 R12 R15 R17 R20 T13 T16 T18 T21 T6 U15 U17 U20 U9 V13 V16 V18 Y10 Y15 Y17 Y20 R11 T11

7/22 modify

NC_VDDRHA +BIF_VDDC

NC_VSSRHA PLL

For Seymour, PCIE_PVDD is PCIE_VDDR.

C458 0.1U_0402_10V6K

2

1

L16

+1.8VGS

2

C457 1U_0402_6.3V4Z

1

2

L17

1

C456 10U_0603_6.3V6M

C453 10U_0603_6.3V6M

2

1

C455 0.1U_0402_10V6K

1

L26 1 2 BLM15BD121SN1D_0402

AA11 AA12

2

C454 1U_0402_6.3V4Z

L25 1 2 BLM15BD121SN1D_0402

V12 Y12 U12

1

POWER

C429 1U_0402_6.3V4Z

170mA

C446 10U_0603_6.3V6M

1 2 BLM15BD121SN1D_0402

Change to 0 ohm P/N

VDDR3#1 VDDR3#2 VDDR3#3 VDDR3#4

+

C418 1U_0402_6.3V4Z

AA17 AA18 AB17 AB18

1

C417 1U_0402_6.3V4Z

60mA

C

VDDC#1 VDDC#2 VDDC#3 VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8 VDDC#9 VDDC#10 VDDC#11 VDDC#12 VDDC#13 VDDC#14 VDDC#15 VDDC#16 VDDC#17 VDDC#18 VDDC#19 VDDC#20 VDDC#21 VDDC#22 VDDC#23

CORE

I/O

+VGA_CORE

2

C416 1U_0402_6.3V4Z

2

AA15 N15 N17 R13 R16 R18 Y21 T12 T15 T17 T20 U13 U16 U18 V21 V15 V17 V20 Y13 Y16 Y18 M11 M12

D

Change to 0 ohm P/N

1

PCIE_PVDD BIF_VDDC#1 BIF_VDDC#2

R21 U21

2

NC_MPV18 SPV18 SPV10 SPVSS

1

ISOLATED CORE I/O

VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4 VDDCI#5 VDDCI#6 VDDCI#7 VDDCI#8

M13 M15 M16 M17 M18 M20 M21 N20

2

+VDDCI

1

2

2

1

+VGA_CORE R745 0_0603_5% 1 2 1

2

1

2

C466 10U_0603_6.3V6M

@

VDD_CT#1 VDD_CT#2 VDD_CT#3 VDD_CT#4

2

U8E

MBK1608121YZF_0603

1

2

C414 1U_0402_6.3V4Z

2

AA20 AA21 AB20 AB21

2

1

1

+1.0VGS

C413 1U_0402_6.3V4Z

LEVEL TRANSLATION

17mA

1

L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22

2

C451 1U_0402_6.3V4Z

2

1

AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26

C459 1U_0402_6.3V4Z

1

C411 1U_0402_6.3V4Z

2

C410 1U_0402_6.3V4Z

2

PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8 PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12

+3VGS

1

C409 10U_0603_6.3V6M

2

1

C408 0.1U_0402_10V6K

1

Change to 0 ohm P/N

C405 1U_0402_6.3V4Z

110mA C404 10U_0603_6.3V6M

L23 1 2 BLM15BD121SN1D_0402

PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8

C460 1U_0402_6.3V4Z

+VDDC_CT

VDDR1#1 VDDR1#2 VDDR1#3 VDDR1#4 VDDR1#5 VDDR1#6 VDDR1#7 VDDR1#8 VDDR1#9 VDDR1#10 VDDR1#11 VDDR1#12 VDDR1#13 VDDR1#14 VDDR1#15 VDDR1#16 VDDR1#17

1

2

C736 220U_B2_2.5VM_R35

H13 H16 H19 J10 J23 J24 J9 K10 K23 K24 K9 L11 L12 L13 L20 L21 L22

C385 0.1U_0402_10V6K 1

PCIE

9/28 Reserved for VGA_CORE 10/8 change to B2 size

L22

+PCIE_VDDR MEM I/O

D

+1.8VGS

+1.8VGS

504mA U8D

C383 1U_0402_6.3V4Z

2

C415 1U_0402_6.3V4Z

2

1

C452 1U_0402_6.3V4Z

2

1

C461 1U_0402_6.3V4Z

2

1

C392 0.1U_0402_10V6K

2

1

C381 0.1U_0402_10V6K

2

1

C391 0.1U_0402_10V6K

2

1

C390 0.1U_0402_10V6K

2

1

C389 0.1U_0402_10V6K

2

1

C374 1U_0402_6.3V4Z

2

1

C373 1U_0402_6.3V4Z

1

C372 1U_0402_6.3V4Z

1

C371 1U_0402_6.3V4Z

2

C370 1U_0402_6.3V4Z

1

C369 10U_0603_6.3V6M

2

C366 22U_0805_6.3V6M

C365 22U_0805_6.3V6M

2.3A(RMS)/2.8A(Peak) 1

PCIE_VSS#1 PCIE_VSS#2 PCIE_VSS#3 PCIE_VSS#4 PCIE_VSS#5 PCIE_VSS#6 PCIE_VSS#7 PCIE_VSS#8 PCIE_VSS#9 PCIE_VSS#10 PCIE_VSS#11 PCIE_VSS#12 PCIE_VSS#13 PCIE_VSS#14 PCIE_VSS#15 PCIE_VSS#16 PCIE_VSS#17 PCIE_VSS#18 PCIE_VSS#19 PCIE_VSS#20 PCIE_VSS#21 PCIE_VSS#22 PCIE_VSS#23 PCIE_VSS#24 PCIE_VSS#25 PCIE_VSS#26 PCIE_VSS#27 PCIE_VSS#28 PCIE_VSS#29 PCIE_VSS#30 PCIE_VSS#31

GND#56 GND#57 GND#58 GND#59 GND#60 GND#61 GND#62 GND#63 GND#64 GND#65 GND#66 GND#67 GND#68 GND#69 GND#70 GND#71 GND#72 GND#73 GND#74 GND#75 GND#76 GND#77 GND#78 GND#79 GND#80 GND#81 GND#82 GND#83 GND#84 GND#85 GND#86

GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8 GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55

GND

VSS_MECH#1 VSS_MECH#2 VSS_MECH#3

A3 A30 AA13 AA16 AB10 AB15 AB6 AC9 AD6 AD8 AE7 AG12 AH10 AH28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B6 B8 C1 C32 E28 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6

C

A32 AM1 AM32

1

216-0774207-A11ROB_FCBGA631

2

B

216-0774207-A11ROB_FCBGA631

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/07/12

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

RobsonXT-S3 PWR/GND Size C Date:

5

4

3

2

Document Number

Rev 0.2 Sheet

Friday, November 26, 2010 1

28

of

59

5

4

3

2

M_DA[63..0]

<30> M_DA[63..0]

GDDR5/DDR3 M_DA0 M_DA1 M_DA2 M_DA3 M_DA4 M_DA5 M_DA6 M_DA7 M_DA8 M_DA9 M_DA10 M_DA11 M_DA12 M_DA13 M_DA14 M_DA15 M_DA16 M_DA17 M_DA18 M_DA19 M_DA20 M_DA21 M_DA22 M_DA23 M_DA24 M_DA25 M_DA26 M_DA27 M_DA28 M_DA29 M_DA30 M_DA31 M_DA32 M_DA33 M_DA34 M_DA35 M_DA36 M_DA37 M_DA38 M_DA39 M_DA40 M_DA41 M_DA42 M_DA43 M_DA44 M_DA45 M_DA46 M_DA47 M_DA48 M_DA49 M_DA50 M_DA51 M_DA52 M_DA53 M_DA54 M_DA55 M_DA56 M_DA57 M_DA58 M_DA59 M_DA60 M_DA61 M_DA62 M_DA63

M_DQM[7..0]

<30> M_DQM[7..0]

M_DQS[7..0]

<30> M_DQS[7..0]

M_DQS#[7..0]

<30> M_DQS#[7..0] D

C

+1.5VGS

1

1

+1.5VGS

R365 40.2_0402_1%

2

2

R363 40.2_0402_1%

R367 100_0402_1%

PARK SCL has different recommand

2

C468 0.1U_0402_16V4Z

2

9/28 change P/N to SD034100A80 R369 10_0402_1% 2 1

R366 <30> DRAM_RST#

1

1

C469 120P_0402_50V8J

DRAM_RST

1

49.9_0402_1% 1

R371 4.99K_0402_1%

2

+1.5VGS

2

B

C467 0.1U_0402_16V4Z

2

2

2

R364 100_0402_1%

1

MVREFSA

1

MVREFDA

K27 J29 H30 H32 G29 F28 F32 F30 C30 F27 A28 C28 E27 G26 D26 F25 A25 C25 E25 D24 E23 F23 D22 F21 E21 D20 F19 A19 D18 F17 A17 C17 E17 D16 F15 A15 D14 F13 A13 C13 E11 A11 C11 F11 A9 C9 F9 D8 E7 A7 C7 F7 A5 E5 C3 E1 G7 G6 G1 G3 J6 J1 J3 J5

MVREFDA MVREFSA R368 1 243_0402_1% 2 1 2 R370 243_0402_1%

GDDR5/DDR3

DQA0_0/DQA_0 DQA0_1/DQA_1 DQA0_2/DQA_2 DQA0_3/DQA_3 DQA0_4/DQA_4 DQA0_5/DQA_5 DQA0_6/DQA_6 DQA0_7/DQA_7 DQA0_8/DQA_8 DQA0_9/DQA_9 DQA0_10/DQA_10 DQA0_11/DQA_11 DQA0_12/DQA_12 DQA0_13/DQA_13 DQA0_14/DQA_14 DQA0_15/DQA_15 DQA0_16/DQA_16 DQA0_17/DQA_17 DQA0_18/DQA_18 DQA0_19/DQA_19 DQA0_20/DQA_20 DQA0_21/DQA_21 DQA0_22/DQA_22 DQA0_23/DQA_23 DQA0_24/DQA_24 DQA0_25/DQA_25 DQA0_26/DQA_26 DQA0_27/DQA_27 DQA0_28/DQA_28 DQA0_29/DQA_29 DQA0_30/DQA_30 DQA0_31/DQA_31 DQA1_0/DQA_32 DQA1_1/DQA_33 DQA1_2/DQA_34 DQA1_3/DQA_35 DQA1_4/DQA_36 DQA1_5/DQA_37 DQA1_6/DQA_38 DQA1_7/DQA_39 DQA1_8/DQA_40 DQA1_9/DQA_41 DQA1_10/DQA_42 DQA1_11/DQA_43 DQA1_12/DQA_44 DQA1_13/DQA_45 DQA1_14/DQA_46 DQA1_15/DQA_47 DQA1_16/DQA_48 DQA1_17/DQA_49 DQA1_18/DQA_50 DQA1_19/DQA_51 DQA1_20/DQA_52 DQA1_21/DQA_53 DQA1_22/DQA_54 DQA1_23/DQA_55 DQA1_24/DQA_56 DQA1_25/DQA_57 DQA1_26/DQA_58 DQA1_27/DQA_59 DQA1_28/DQA_60 DQA1_29/DQA_61 DQA1_30/DQA_62 DQA1_31/DQA_63

MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA0_6 MAA0_7/MAA0_7 MAA1_0/MAA_8 MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12 MAA1_5/MAA_13/BA2 MAA1_6/MAA_14/BA0 MAA1_7/MAA_15/BA1

K17 J20 H23 G23 G24 H24 J19 K19 J14 K14 J11 J13 H11 G11 J16 L15

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_BA2 M_BA0 M_BA1

WCKA0_0/DQMA_0 WCKA0B_0/DQMA_1 WCKA0_1/DQMA_2 WCKA0B_1/DQMA_3 WCKA1_0/DQMA_4 WCKA1B_0/DQMA_5 WCKA1_1/DQMA_6 WCKA1B_1/DQMA_7

E32 E30 A21 C21 E13 D12 E3 F4

M_DQM0 M_DQM1 M_DQM2 M_DQM3 M_DQM4 M_DQM5 M_DQM6 M_DQM7

EDCA0_0/RDQSA_0 EDCA0_1/RDQSA_1 EDCA0_2/RDQSA_2 EDCA0_3/RDQSA_3 EDCA1_0/RDQSA_4 EDCA1_1/RDQSA_5 EDCA1_2/RDQSA_6 EDCA1_3/RDQSA_7

H28 C27 A23 E19 E15 D10 D6 G5

M_DQS0 M_DQS1 M_DQS2 M_DQS3 M_DQS4 M_DQS5 M_DQS6 M_DQS7

DDBIA0_0/WDQSA_0 DDBIA0_1/WDQSA_1 DDBIA0_2/WDQSA_2 DDBIA0_3/WDQSA_3 DDBIA1_0/WDQSA_4 DDBIA1_1/WDQSA_5 DDBIA1_2/WDQSA_6 DDBIA1_3/WDQSA_7

H27 A27 C23 C19 C15 E9 C5 H4

M_DQS#0 M_DQS#1 M_DQS#2 M_DQS#3 M_DQS#4 M_DQS#5 M_DQS#6 M_DQS#7

ADBIA0/ODTA0 ADBIA1/ODTA1

L18 K16

VRAM_ODT0 VRAM_ODT1

CLKA0 CLKA0B

H26 H25

M_CLK0 M_CLK#0

CLKA1 CLKA1B

G9 H9

M_CLK1 M_CLK#1

RASA0B RASA1B

G22 G17

M_RAS#0 M_RAS#1

CASA0B CASA1B

G19 G16

M_CAS#0 M_CAS#1

CSA0B_0 CSA0B_1

H22 J22

M_CS#0

G13 K13

M_CS#1

MEMORY INTERFACE

M_MA[13..0]

<30> M_MA[13..0]

1

1

+1.8VGS

U8C

CSA1B_0 CSA1B_1

K26 J26

MVREFDA MVREFSA

CKEA0 CKEA1

K20 J17

M_CKE0 M_CKE1

J25 K25

MEM_CALRN0 MEM_CALRP0

WEA0B WEA1B

G25 H10

M_WE#0 M_WE#1

MAA1_8 MAA0_8

G14 G20

GDDR5

1R372@ 51.1_0402_1% 2 1 2 R373@ 51.1_0402_1%

DRAM_RST L10

DRAM_RST

K8 L7

CLKTESTA CLKTESTB

[email protected]_0402_16V4Z 1 2 C471@ 0.1U_0402_16V4Z

R357 R358 R359 R360 R361 R362

1 1 1 1 1 1

X76@ 2 X76@ 2 X76@ 2 X76@ 2 X76@ 2 X76@ 2

VRAM_ID0

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

VRAM_ID0 <24>

VRAM_ID1

VRAM_ID1 <24>

VRAM_ID2

VRAM_ID2 <24>

D

Vendor M_BA2 M_BA0 M_BA1

<30> <30> <30>

VRAM_ID0 VRAM_ID1 VRAM_ID2

Hynix 512MB PN:SA000032460

R357

R360

R362

Samsung 512MB PN:SA000035700

R358

R359

R362

Hynix 1GB PN:SA00003VS20

R357

R360

R361

Samsung 1GB PN:SA00003MQ20

R358

R359

R361

C

VRAM_ODT0 <30> VRAM_ODT1 <30> M_CLK0 <30> M_CLK#0 <30> M_CLK1 <30> M_CLK#1 <30> M_RAS#0 <30> M_RAS#1 <30>

B

M_CAS#0 <30> M_CAS#1 <30> M_CS#0

<30>

M_CS#1

<30>

M_CKE0 <30> M_CKE1 <30> M_WE#0 <30> M_WE#1 <30>

M_MA13

A

A

216-0774207-A11ROB_FCBGA631

Route 50ohms single-ended/100ohm diff and keep short debug only, for clock observation,if not need, DNI.

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/07/12

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

RobsonXT-S3 MEM Interface Size B Date:

Document Number Friday, November 26, 2010

Rev 0.2 Sheet 1

29

of

59

5

4

3

<29> M_DA[63..0]

1

M_MA[13..0]

<29> M_MA[13..0]

M_DQM[7..0]

<29> M_DQM[7..0]

M_DQS[7..0]

<29> M_DQS[7..0]

M_DQS#[7..0]

Hynix

Samsung

H1G@ X7624938L01

S1G@ X7624938L02

0706 update update X76 PN

ZZZ

N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

ZZZ

Hynix

M_BA0 M_BA1 M_BA2

M3 N9 M4

<29> <29> <29>

M_BA0 M_BA1 M_BA2

<29> <29> <29>

M_CLK0 M_CLK#0 M_CKE0

M_CLK0 J8 M_CLK#0 K8 M_CKE0 K10

<29> VRAM_ODT0 <29> M_CS#0 <29> M_RAS#0 <29> M_CAS#0 <29> M_WE#0

VRAM_ODT0K2 M_CS#0 L3 M_RAS#0 J4 M_CAS#0 K4 M_WE#0 L4

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

S512@ X7624938L04

C

M_DQS2 M_DQS0

F4 C8

M_DQM2 M_DQM0

E8 D4

M_DQS#2 M_DQS#0

G4 B8

VDD VDD VDD VDD VDD VDD VDD VDD VDD

CK CK CKE/CKE0 ODT/ODT0 CS RAS CAS WE

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

DQSL DQSU DML DMU

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

DQSL DQSU

T3

<29> DRAM_RST#

RESET

L9

M_DA22 M_DA20 M_DA19 M_DA18 M_DA21 M_DA17 M_DA23 M_DA16

D8 C4 C9 C3 A8 A3 B9 A4

M_DA3 M_DA1 M_DA0 M_DA5 M_DA6 M_DA7 M_DA2 M_DA4

VREFC_A2 VREFD_Q2 M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13

+1.5VGS

BA0 BA1 BA2

Samsung

H512@ X7624938L03

E4 F8 F3 F9 H4 H9 G3 H8

M_CLK0 M_CLK#0 M_CKE0

J8 K8 K10

A2 A9 C2 C10 D3 E10 F2 H3 H10

VRAM_ODT0 K2 M_CS#0 L3 M_RAS#0 J4 M_CAS#0 K4 M_WE#0 L4 M_DQS3 M_DQS1

F4 C8

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

M_DQM3 M_DQM1

E8 D4

M_DQS#3 M_DQS#1

G4 B8

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

CK CK CKE/CKE0 ODT/ODT0 CS RAS CAS WE

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

DQSL DQSU DML DMU

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

DQSL DQSU

DRAM_RST# T3

RESET

L9

E4 F8 F3 F9 H4 H9 G3 H8

M_DA25 M_DA28 M_DA27 M_DA31 M_DA24 M_DA29 M_DA26 M_DA30

D8 C4 C9 C3 A8 A3 B9 A4

M_DA14 M_DA10 M_DA15 M_DA11 M_DA12 M_DA8 M_DA13 M_DA9

VREFC_A3 VREFD_Q3 M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13

ZQ/ZQ0

M_BA0 M_BA1 M_BA2

B3 D10 G8 K3 K9 N2 N10 R2 R10 A2 A9 C2 C10 D3 E10 F2 H3 H10

<29> VRAM_ODT1 <29> M_CS#1 <29> M_RAS#1 <29> M_CAS#1 <29> M_WE#1

VRAM_ODT1K2 M_CS#1 L3 M_RAS#1 J4 M_CAS#1 K4 M_WE#1 L4

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A1 A11 T1 T11

NC NC NC NC

B2 B10 D2 D9 E3 E9 F10 G2 G10

M_DQS4 M_DQS5

F4 C8

M_DQM4 M_DQM5

E8 D4

M_DQS#4 M_DQS#5

G4 B8

J2 L2 J10 L10

R375 243_0402_1%

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

A1 A11 T1 T11

100-BALL SDRAM DDR3 64MX16 H5TQ1G63BFR-12C FBGA X76@

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

CK CK CKE/CKE0 ODT/ODT0 CS RAS CAS WE

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

DQSL DQSU DML DMU

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

DQSL DQSU

RESET

L9

E4 F8 F3 F9 H4 H9 G3 H8

M_DA35 M_DA34 M_DA36 M_DA37 M_DA32 M_DA38 M_DA33 M_DA39

D8 C4 C9 C3 A8 A3 B9 A4

M_DA47 M_DA42 M_DA45 M_DA41 M_DA43 M_DA40 M_DA46 M_DA44

VREFC_A4 VREFD_Q4

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

NC NC NC NC

B2 B10 D2 D9 E3 E9 F10 G2 G10

+1.5VGS

M9 H2

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13

+1.5VGS

BA0 BA1 BA2

DRAM_RST# T3

ZQ/ZQ0

J2 L2 J10 L10

R376 243_0402_1%

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

A1 A11 T1 T11

100-BALL SDRAM DDR3 64MX16 H5TQ1G63BFR-12C FBGA X76@

+1.5VGS

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

M3 N9 M4

M_CLK1 J8 M_CLK#1 K8 M_CKE1 K10

U21

VREFCA VREFDQ

N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8

M_CLK1 M_CLK#1 M_CKE1

<29> <29> <29>

+1.5VGS

1 NC/ODT1 NC/CS1 NC/CE1 NCZQ1

M9 H2

+1.5VGS

BA0 BA1 BA2

2

J2 L2 J10 L10

2

R374 243_0402_1%

M3 N9 M4

U18

VREFCA VREFDQ

N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8

M_BA0 M_BA1 M_BA2

+1.5VGS

1

ZQ/ZQ0

B3 D10 G8 K3 K9 N2 N10 R2 R10

M9 H2

B3 D10 G8 K3 K9 N2 N10 R2 R10

M_BA0 M_BA1 M_BA2

M3 N9 M4

M_CLK1 M_CLK#1 M_CKE1

J8 K8 K10

+1.5VGS

A2 A9 C2 C10 D3 E10 F2 H3 H10

VRAM_ODT1 K2 M_CS#1 L3 M_RAS#1 J4 M_CAS#1 K4 M_WE#1 L4 M_DQS6 M_DQS7

F4 C8

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

M_DQM6 M_DQM7

E8 D4

M_DQS#6 M_DQS#7

G4 B8

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

CK CK CKE/CKE0 ODT/ODT0 CS RAS CAS WE

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

DQSL DQSU DML DMU

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

DQSL DQSU

RESET

L9

M_DA52 M_DA48 M_DA54 M_DA50 M_DA53 M_DA49 M_DA55 M_DA51

E4 F8 F3 F9 H4 H9 G3 H8

D

M_DA60 M_DA58 M_DA56 M_DA61 M_DA63 M_DA62 M_DA57 M_DA59

D8 C4 C9 C3 A8 A3 B9 A4

+1.5VGS

BA0 BA1 BA2

DRAM_RST# T3

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

NC NC NC NC

B2 B10 D2 D9 E3 E9 F10 G2 G10

ZQ/ZQ0

J2 L2 J10 L10

R377 243_0402_1%

+1.5VGS

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

A1 A11 T1 T11

100-BALL SDRAM DDR3 64MX16 H5TQ1G63BFR-12C FBGA X76@

+1.5VGS

VREFCA VREFDQ

N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

2

ZZZ M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13

U20

VREFCA VREFDQ

1

ZZZ

M9 H2

B3 D10 G8 K3 K9 N2 N10 R2 R10

+1.5VGS

A2 A9 C2 C10 D3 E10 F2 H3 H10

C

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

1

U19 VREFC_A1 VREFD_Q1

2

<29> M_DQS#[7..0]

D

2

M_DA[63..0]

NC NC NC NC

B2 B10 D2 D9 E3 E9 F10 G2 G10

100-BALL SDRAM DDR3 64MX16 H5TQ1G63BFR-12C FBGA X76@

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS 1 2

4.99K_0402_1%

2

1

VREFD_Q4 C479

1

R392

R393 4.99K_0402_1%

1

2

2

C478

1

VREFC_A4

2

1

C477

1

2

2

C476

4.99K_0402_1%

2

2

2 1 2

C475

1

1

1

1 2 1 2

4.99K_0402_1%

1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1

1

1

1

1

1

1

C487

1

C505

@ 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z

1

C504

1

C503

1

C502

1

C486

1

C485

1

C484

1

C499

1

C498

1

C497

1

C501

1 1

C481

2 2 2 10U_0603_6.3V6M10U_0603_6.3V6M

C496

C491

C480 2

C495

C490

2 10U_0603_6.3V6M

C494

10U_0603_6.3V6M 1 1

C493

10U_0603_6.3V6M 1 1

C483

C489

1

C482

2 56_0402_1%

2

R391

1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z C492

1 R397

1

C500

10U_0603_6.3V6M 1

2

M_CLK#1

C474

1 2

C473

C472

1 2

2

+1.5VGS

C488

2 56_0402_1%

VREFD_Q3

+1.5VGS

C506 0.01U_0402_16V7K

2

1 R395

2

R390 4.99K_0402_1%

R385

+1.5VGS 1

M_CLK1

2

1

R389 4.99K_0402_1%

4.99K_0402_1%

0.1U_0402_10V6K

2 56_0402_1%

1

R384

4.99K_0402_1%

0.1U_0402_10V6K

1 R396

2

R388 4.99K_0402_1%

R383

VREFC_A3 0.1U_0402_10V6K

M_CLK#0

1

VREFD_Q2 0.1U_0402_10V6K

2 56_0402_1%

R387 4.99K_0402_1%

VREFC_A2 0.1U_0402_10V6K

1 R394

VREFC_A1 0.1U_0402_10V6K

M_CLK0

2

0.1U_0402_10V6K

1

R382 4.99K_0402_1%

0.1U_0402_10V6K

1

VREFD_Q1 R386 4.99K_0402_1%

R381 4.99K_0402_1% 2

R380 4.99K_0402_1% 2

R379 4.99K_0402_1% 2

R378 4.99K_0402_1%

1

1

B

1

B

2 2 2 2 2 2 2 2 @ 2 2 @ 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z

A

A

1

C507 0.01U_0402_16V7K

2

ref 139-02 recommand

VRAM P/N :

add off page

Hynix : SA000041S10 (S IC D3 64MX16 H5TQ1G63BFR-11C FBGA C38! )

Park SCL recommand pu 60.4 ohm to 1.5VGS 0619 update

Samsung : SA000041T10 (S IC D3 64MX16 K4W1G1646E-HC11 FBGA C38! ) update VRAM PN

Issued Date

0619 update

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/07/12

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

RobsonXT-S3 VRAM Size C Date:

5

4

3

2

Document Number

Rev 0.2 Sheet

Friday, November 26, 2010 1

30

of

59

5

4

3

2

1

INVPWM

LCD POWER CIRCUIT +LCDVDD

470P_0402_50V7K

470P_0402_50V7K

+LEDVDD

C509 1

2

+5VALW

0_0402_5%

1 DIS@

3

Q80

2

@ 680P_0402_50V7K C514

Change footprint 20100814

1

<40>

CE_EN 1 0_0402_5% DIS@ R402

<40> INVT_PWM

2 R404 R405

CONN_LVDS_SCL CONN_LVDS_SDA

2.2K_0402_5% 2.2K_0402_5% @

AP2301GN-HF_SOT23-3

C515

32

W=60mils

0.1U_0402_16V4Z +LCDVDD 1

Q81 DTC124EKAT146_SC59-3

Pull high at chipset/VGA side

C516 1

1

2

2

2

<24> VGA_LVDS_SCL <24> VGA_LVDS_SDA

0.1U_0402_16V4Z

<23> VGA_LVDS_A0 <23> VGA_LVDS_A0#

<23> VGA_LVDS_ACLK <23> VGA_LVDS_ACLK#

<17> EDID_CLK <17> EDID_DATA +3VS

5

U22

P

LVDS_A0 LVDS_A0#

<17> <17>

LVDS_A1 LVDS_A1#

<17> <17>

INVPWM

4

<17> <17>

LVDS_A2 LVDS_A2#

G 3 G

2

JLVDS1 1 1 3 3 5 5 7 7 9 9 11 11 13 13 15 15 17 17 19 19 21 21 23 23 25 25 27 27 29 29

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

USB20_N5 USB20_P5

USB20_N5 <18> USB20_P5 <18>

CMOS D

CONN_LVDS_A0# CONN_LVDS_A0 CONN_LVDS_A1# CONN_LVDS_A1 CONN_LVDS_A2# CONN_LVDS_A2 CONN_LVDS_ACLK# CONN_LVDS_ACLK

31

GNDGND

<17> LVDS_ACLK <17> LVDS_ACLK#

TC7SZ14FU_SSOP5 @

VGA_LVDS_SCL 0_0402_5% VGA_LVDS_SDA 0_0402_5%

2 DIS@ 2 DIS@

1 R409 1 R410

CONN_LVDS_SCL CONN_LVDS_SDA

VGA_LVDS_A0 0_0402_5% VGA_LVDS_A0# 0_0402_5%

2 DIS@ 2 DIS@

1 R411 1 R412

CONN_LVDS_A0 CONN_LVDS_A0#

VGA_LVDS_A1 0_0402_5% VGA_LVDS_A1# 0_0402_5%

2 DIS@ 2 DIS@

1 R413 1 R414

CONN_LVDS_A1 CONN_LVDS_A1#

VGA_LVDS_A2 0_0402_5% VGA_LVDS_A2# 0_0402_5%

2 DIS@ 2 DIS@

1 R415 1 R416

CONN_LVDS_A2 CONN_LVDS_A2#

VGA_LVDS_ACLK 0_0402_5% VGA_LVDS_ACLK#0_0402_5%

2 DIS@ 2 DIS@

1 R417 1 R418

CONN_LVDS_ACLK CONN_LVDS_ACLK#

EDID_CLK EDID_DATA

0_0402_5% 0_0402_5%

2 PX@ 2 PX@

1 R419 1 R420

CONN_LVDS_SCL CONN_LVDS_SDA

LVDS_A0 LVDS_A0#

0_0402_5% 0_0402_5%

2 PX@ 2 PX@

1 R421 1 R422

CONN_LVDS_A0 CONN_LVDS_A0#

LVDS_A1 LVDS_A1#

0_0402_5% 0_0402_5%

2 PX@ 2 PX@

1 R423 1 R424

CONN_LVDS_A1 CONN_LVDS_A1#

LVDS_A2 LVDS_A2#

0_0402_5% 0_0402_5%

2 PX@ 2 PX@

1 R425 1 R427

CONN_LVDS_A2 CONN_LVDS_A2#

LVDS_ACLK LVDS_ACLK#

0_0402_5% 0_0402_5%

2 PX@ 2 PX@

1 R428 1 R429

CONN_LVDS_ACLK CONN_LVDS_ACLK#

C

PX@ R430 2 0_0402_5%

1 1

C512 4.7U_0805_25V6-K

C517

4.7U_0603_6.3V6K

<23> VGA_LVDS_A2 <23> VGA_LVDS_A2#

3

2

2

Change footprint 20100814

Y

2

FBMA-L11-201209-221LMA30T_0805

<23> VGA_LVDS_A1 <23> VGA_LVDS_A1#

NC A

1

ACES_87142-3041-BS ME@

+LCDVDD_CONN

L29

C

<17> PCH_PWM

INVPWM DISPOFF#

2

@ +3VS

R408 @ 100K_0402_5%

1 2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

(60 MIL)

+LCDVDD_CONN

C513 4.7U_0603_6.3V6K

1 2

1

2 0_0805_5%

+3VS_CMOS

2 1

OUT IN

GND

2

1

R407 2

220K_0402_5% 2

1

3

0_0402_5% LCD_ENVDD

1 PX@

3

<23> VGA_ENVDD

R406 2

DTC124EK

1

2 1

S Change footprint 20100814

C511

W=60mils

Change footprint 20100814

R403 2 G

C508 680P_0402_50V7K @

+3VS

R401 100K_0402_5%

2

1

D 2N7002H_SOT23-3 Q79

<17> PCH_ENVDD

1

+3VS R400 150_0603_1%

1

For EMI

D

B+ 1 R398

DISPOFF#

S

D

INVPWM

2 R431 10K_0402_5% @

1

+3VS

B

B

2N7002H_SOT23-3 @ Q82

Change footprint 20100814

For GMCH DPST (20 MIL) @

+5VS +3VS

+3VS_CMOS

Q83 2

AP2301GN-HF_SOT23-3

2

CMOS@ C518 0.1U_0402_16V4Z

1 CMOS@ C519 10U_0805_10V4Z 2

CMOS@

CH751H-40PT_SOD323-2

R435 150K_0402_5% R543 0_0402_5% @

2

CMOS@ C520 0.1U_0402_16V4Z

2

<40> CMOS_OFF#

IN

R436 <24> VGA_ENBKL

DIS@ 1

3

A

GND

2

2

R716 10K_0402_5%

CMOS@

1

1

1

1

4.7V

DISPOFF#

2

+CMOS_PW

OUT

1 @

(20 MIL)

1

100K_0402_5%

1

2

BKOFF#

3

4.7K_0402_5%

D4 BKOFF#

+5VALW R434

R433 @

2

Change footprint 20100814

CMOS@

0_0402_5% 1

<40>

+3VS

1

R717

CMOS Camera Conn

R539 0_0603_5% 1 2 R596 0_0603_5% 1 2

0_0402_5% 2

ENBKL

Q84 DTC124EKAT146_SC59-3 CMOS@

A

<40>

PX@ R437 1

2

0_0402_5% 2

<17> PCH_ENBKL

2010/07/12

Issued Date

1 5

Compal Secret Data

Security Classification

R438 100K_0402_1%

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4

3

2

Title

Compal Electronics, Inc. LVDS/CAMERA

Size B Date:

Document Number

Rev 0.2

LA-6751P Friday, November 26, 2010

Sheet 1

31

of

59

A

B

C

D

+5VS

+5VS

3

3

@ D6 BAT54S-7-F_SOT23-3

JVGA_HS

2

@ D7

@ D9 BAT54S-7-F_SOT23-3

CRT Connector

+CRT_VCC

+5VS D10

2 <17> DAC_RED <17> DAC_GRN <17> DAC_BLU

DAC_RED

1 R439 PX@ 1 R440 PX@ DAC_BLU 1 R441 PX@ DAC_GRN

2 0_0402_5% 2 0_0402_5% 2 0_0402_5%

CRT_R

CRT_B

CRT_R

1

CRT_R

1

1

CRT_B

1

CRT_B

R443 150_0402_1%

R446 150_0402_1%

1 C522

C523

2

2

R445 150_0402_1%

2

CRT_G

2

<24> VGA_CRT_B

VGA_CRT_R 1 2 R442 DIS@ 0_0402_5% VGA_CRT_G 1 2 R444 DIS@ 0_0402_5% VGA_CRT_B 1 2 R447 DIS@ 0_0402_5%

2 1

1.1A_6V_SMD1812P110TF

CRT_G

<24> VGA_CRT_G

1

RB491D_SC59-3 FCM1608CF-121T03 0603 1 2 L30 FCM1608CF-121T03 0603 1 2 L31 FCM1608CF-121T03 0603 1 2 L32 1 1

2

2

C524 10P_0402_50V8J

10P_0402_50V8J 10P_0402_50V8J

CLOSE TO CONN

W=40mils

2

GREEN JCRT1 BLUE

1

T67 PAD @ RED

1 C526

2

2

C527 10P_0402_50V8J

CRT_DDC_DAT_CONN GREEN JVGA_HS BLUE

10P_0402_50V8J10P_0402_50V8J

JVGA_VS CRT_DDC_CLK_CONN 2

+CRT_VCC

R448

C528

1

100P_0402_50V8J

2

A

DIS@ R450 1

2 0_0402_5%

FCM1608CF-121T03 0603 1 2 L33

CRT_HSYNC_1

4

Y

U23 SN74AHCT1G125DCKR_SC70-5

3

<24> VGA_HSYNC

2

CONTE_80431-5K1-152 ME@

2

1

5 P HSYNC_G

OE#

2 0_0402_5%

16 17

2

G

R449 1

G G

1K_0402_5%

PX@ <17> CRT_HSYNC

1

6 11 1 7 12 2 8 13 3 9 14 4 10 15 5

2

1 C529 0.1U_0402_16V4Z

C521 0.1U_0402_16V4Z

RED

C525

2

1

F1

1

CRT_G

DIS only <24> VGA_CRT_R

JVGA_VS

1 2

@ D8 BAT54S-7-F_SOT23-3

UMA only

1

3 1

BAT54S-7-F_SOT23-3

2

@ D5 BAT54S-7-F_SOT23-3

RED

1

2

+5VS

3

GREEN

1

2

+5VS

3

BLUE

1

E

+5VS

+CRT_VCC

JVGA_HS

Check CRT footprint 7/20_OTIS 1

2

R451

1

@ C530 10P_0402_50V8J

2

1 1K_0402_5%

5

1

2

R4521

P

PX@

2

0_0402_5%

VSYNC_G

2

A G

<17> CRT_VSYNC

3

DIS@

2

0_0402_5%

FCM1608CF-121T03 0603 1 2 L34

CRT_VSYNC_1

4

Y

U24 SN74AHCT1G125DCKR_SC70-5

3

<24> VGA_VSYNC

R4531

OE#

C531 0.1U_0402_16V4Z

JVGA_VS

2

R735 0_0402_5% DIS@

<24> VGA_DDCDATA <17> CRT_DDC_CLK <24> VGA_DDCCLK

4

VGA_DDCDATA CRT_DDC_CLK VGA_DDCCLK

CRT_DDC_CLK_R 2 PX@ 1 R460 0_0402_5% 2 DIS@ 1 R461 0_0402_5%

8/14 change P/N to DMN66D0LDW-7_SOT363-6 (SB00000DH00)

1

1

R457 2.2K_0402_5%

4

2

R456 2.2K_0402_5%

5

1

+CRT_VCC

2

CRT_DDC_DATA_R 2 PX@ 1 R458 0_0402_5% 2 DIS@ 1 R459 0_0402_5%

@ R455 2.2K_0402_5%

2

CRT_DDC_DATA

1

1

R736 0_0402_5% PX@

3

CRT_DDC_DAT_CONN

2N7002DW -T/R7_SOT363-6 Q62B

2

<17> CRT_DDC_DATA

2

@ R454 2.2K_0402_5%

7/21 modify

1

+3VS

Pull high at chipset/VGA side

@ C532 10P_0402_50V8J

2

2

+3VS +3VGS

1

6 1

2N7002DW -T/R7_SOT363-6 Q62A

C533 100P_0402_50V8J

2

CRT_DDC_CLK_CONN 1 @ C534 68P_0402_50V8K 2

4

Compal Secret Data

Security Classification 2010/07/12

Issued Date

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

3

1

C

D

Title

Compal Electronics, Inc. CRT Connector

Size Document Number Custom Date:

Rev 0.2

LA-6751P

Friday, November 26, 2010

Sheet E

32

of

59

5

HDMI_CLK+_CONN HDMI_CLK-_CONN HDMI_TX0+_CONN HDMI_TX0-_CONN

4

1 2 R462 UMA_HDMI@ 1 2 R463 UMA_HDMI@ 1 2 R472 UMA_HDMI@ 1 2 R473 UMA_HDMI@

3

HDMI_TX1-_CONN

1 2 R474 UMA_HDMI@ 1 2 R475 UMA_HDMI@

@ 680_0402_1%

<17> <17> <17> <17> <17> <17> <17> <17>

680_0402_1% 680_0402_1%

1 2 UMA_HDMI@ 1 2 UMA_HDMI@

680_0402_1% 680_0402_1%

680_0402_1% 2N7002H_SOT23-3 UMA_HDMI@

D

2 G

Q95

HDMI_CLK+_CK HDMI_CLK-_CK HDMI_TX0+_CK HDMI_TX0-_CK HDMI_TX1+_CK HDMI_TX1-_CK HDMI_TX2+_CK HDMI_TX2-_CK

HDMI_CLK+_CK HDMI_CLK-_CK HDMI_TX0+_CK HDMI_TX0-_CK HDMI_TX1+_CK HDMI_TX1-_CK HDMI_TX2+_CK HDMI_TX2-_CK

<24> <24> <24> <24> <24> <24> <24> <24>

680_0402_1%

1

HDMI_TX2+_CONN R476 HDMI_TX2-_CONN R477

1

680_0402_1%

D

HDMI_TX1+_CONN

2

C535 C536 C537 C538 C539 C540 C541 C542

VGA_HDMI_CLK+ VGA_HDMI_CLKVGA_HDMI_TX0+ VGA_HDMI_TX0VGA_HDMI_TX1+ VGA_HDMI_TX1VGA_HDMI_TX2+ VGA_HDMI_TX2-

HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@

1 1 1 1 1 1 1 1

R464 R465 R466 R467 R468 R469 R470 R471

2 2 2 2 2 2 2 2

1 1 1 1 1 1 1 1

DIS_HDMI@ DIS_HDMI@ DIS_HDMI@ DIS_HDMI@ DIS_HDMI@ DIS_HDMI@ DIS_HDMI@ DIS_HDMI@

0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%

2 2 2 2 2 2 2 2

0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K

HDMI_CLK+_CONN HDMI_CLK-_CONN HDMI_TX0+_CONN HDMI_TX0-_CONN HDMI_TX1+_CONN HDMI_TX1-_CONN HDMI_TX2+_CONN HDMI_TX2-_CONN

L35

HDMI_CLK+_CK

1

1

2

2

HDMI_CLK+_CONN

HDMI_CLK-_CK

4

4

3

3

HDMI_CLK-_CONN

W CM-2012-900T_4P @

HDMI_CLK+_CK HDMI_CLK-_CK HDMI_TX0+_CK HDMI_TX0-_CK HDMI_TX1+_CK HDMI_TX1-_CK HDMI_TX2+_CK HDMI_TX2-_CK

L36

HDMI_TX0+_CK

1

HDMI_TX0-_CK

4

1 4

3

HDMI_TX0+_CONN

3

3

HDMI_TX0-_CONN

@

D

L37

HDMI_TX1+_CK

1

1

2

2

HDMI_TX1+_CONN

HDMI_TX1-_CK

4

4

3

3

HDMI_TX1-_CONN

W CM-2012-900T_4P

Change footprint 20100814

@

+3VS +3VGS

2

2

8/6 Modify

L38

HDMI_TX2+_CK

1

1

2

2

HDMI_TX2+_CONN

HDMI_TX2-_CK

4

4

3

3

HDMI_TX2-_CONN

R739 0_0402_5% DIS_HDMI@

W CM-2012-900T_4P

1

1

R738 0_0402_5% UMA_HDMI@

C

2

W CM-2012-900T_4P

+3VS

S

2

+5VS

+5VS

C

2

Pull up R for PCH OR VGA SIDE HDMI@

R478 1

0_0402_5%

R479 1

0_0402_5%

2 UMA_HDMI@ 2 DIS_HDMI@ R480 1 2 UMA_HDMI@ R481 1 2 DIS_HDMI@

<17> HDMIDAT_NB <24> VGA_HDMI_SDA

1 5

<17> HDMICLK_NB <24> VGA_HDMI_SCL

0_0402_5%

2N7002DW -T/R7_SOT363-6 Q63A

3 Q63B

3

HDMICLK_R

6

HDMI@

4

0_0402_5%

3 HDMIDAT_R

1

1

@ D11 BAT54S-7-F_SOT23-3

2 HDMIDAT_R

HDMICLK_R

@ D12 BAT54S-7-F_SOT23-3

2

2N7002DW -T/R7_SOT363-6 RB491D_SC59-3 2

+5VS

8/14 change P/N to DMN66D0LDW-7_SOT363-6 (SB00000DH00)

D13 1 +5VS_HDMI_F

F2

1

2

1.1A_6V_SMD1812P110TF HDMI@

HDMI@ R482

9/27 add F2 for safty

0_0805_5% @

+5VS_HDMI

2

+5VS

1 C543 0.1U_0402_16V4Z HDMI@ R484 2.2K_0402_5% HDMI@

B

2

R486 1 0_0402_5% 2 UMA_HDMI@ Change footprint 20100814

3

2 B

R697 DIS_HDMI@ 150K_0402_5% 1 2

E

HDMI_CLK-_CONN HDMI_CLK+_CONN HDMI_TX0-_CONN

HDMI@

HDMI_TX0-_CONN

1 R492

HDMI_TX1+_CONN

1 R493

HDMI_TX1-_CONN

1 R494

HDMI_TX2+_CONN

1 R495

HDMI_TX2-_CONN

1 R496

1 D

S

Q94 2N7002H_SOT23-3 2 DIS_HDMI@ +5VS G Change footprint 20100814 R874 100K_0402_5% DIS_HDMI@

HDMI_TX2+_CONN

20 21 22 23

A

SUYIN_100042GR019M23DZL

Compal Electronics,Ltd.

Compal Secret Data

Security Classification 2010/07/12

Issued Date

NEAR CONNECT 5

HDMI_TX1+_CONN HDMI_TX2-_CONN

2

1 R491

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKG1 CK_shield G2 CK+ G3 D0G4 D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

1

R490 HDMI_TX0+_CONN

HDMI_TX0+_CONN HDMI_TX1-_CONN R698 DIS_HDMI@ 10K_0402_5%

2

1

1

R489 HDMI_CLK-_CONN

2 DIS_HDMI@ 499_0402_1% 2 DIS_HDMI@ 499_0402_1% 2 DIS_HDMI@ 499_0402_1% 2 DIS_HDMI@ 499_0402_1% 2 DIS_HDMI@ 499_0402_1% 2 DIS_HDMI@ 499_0402_1% 2 DIS_HDMI@ 499_0402_1% 2 DIS_HDMI@ 499_0402_1%

3

1

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

HDMIDAT_R HDMICLK_R R488 100K_0402_5%

1

C Q28 DIS_HDMI@ MMBT3904_G_SOT23-3

JHDMI1

HDMI_DET

2

2N7002H_SOT23-3 Q93 UMA_HDMI@ +3VS

@ D14 BAT54S-7-F_SOT23-3

<24> HDMI_DETECT_VGA

HDMI_CLK+_CONN

A

1

1

2 1

R696 0_0402_5% @

3

D

TMDS_B_HPD#

S

<17> TMDS_B_HPD#

1

1

1

1

R483 2.2K_0402_5% HDMI@

G

2

R485 1M_0402_5% UMA_HDMI@

2

3

2

B

2

+3VS

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4

3

2

Title

HDMI CONN Size Document Number Custom

Rev 0.2

LA-6751P

Date: Friday, November 26, 2010

Sheet 1

33

of

59

A

B

C

D

E

Mini-Express Card for WLAN/WiMAX(Half)

1

1

+1.5VS +3VALW +3VS

2

<15> WLAN_CLKREQ1#

0_0402_5% 2 2 @ 0_0402_5%

WLAN_CLKREQ1#

<15> CLK_PCIE_WLAN1# <15> CLK_PCIE_WLAN1 PCI_RST#_R CLK_PCI_DB <15> PCIE_PRX_DTX_N2 <15> PCIE_PRX_DTX_P2

2

<15> PCIE_PTX_C_DRX_N2 <15> PCIE_PTX_C_DRX_P2 +3VS_WLAN

EC_TX_P80_DATA EC_RX_P80_CLK

For EC to detect debug card insert.

2

@ C545 0.1U_0402_16V4Z

1

2

C546 0.1U_0402_16V4Z

WAKE# 3.3V NC GND NC 1.5V CLKREQ# NC GND NC REFCLKNC REFCLK+ NC GND NC NC GND NC NC GND PERST# PERn0 +3.3Vaux PERp0 GND GND +1.5V GND SMB_CLK PETn0 SMB_DATA PETp0 GND GND USB_DNC USB_D+ NC GND NC LED_WWAN# NC LED_WLAN# NC LED_WPAN# NC +1.5V NC GND NC +3.3V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

53

GND

54

GND

+1.5VS_CONN LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R R498 1

2

R499 1 R500 1

2 @ 0_0402_5% 0_0402_5% 2

0_0402_5%

R501 1 R502 1

2 @ 0_0402_5% 2 @ 0_0402_5%

WL_OFF# <18> BUF_PLT_RST# <18,35,40> +3VALW +3VS

2

SMB_CLK_S3 <12,13,15> SMB_DATA_S3 <12,13,15>

USB20_N9 <18> USB20_P9 <18> 0_0402_5% 0_0402_5%

2 2

@

1 R503 1 R504

WLAN_LED#

@

WLAN_LED# <56,57>

TAITW_PFPET0-AFGLBG1ZZ4N0 ME@ R507 100K_0402_5% 3

1

3

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

2

<40,41> EC_TX_P80_DATA <40,41> EC_RX_P80_CLK

100_0402_1% R505 1 2 1 2 R506 100_0402_1%

1

2

R514 1 R497 1

2

@ C544 0.1U_0402_16V4Z

@

JWLN1 PCIE_WAKE# BT_ACTIVE

2

JUMP_43X79

1

J7 JUMP_43X79

@

2

@

1

1

1

1

J6

Mini-Express Card(WLAN/WiMAX) <16,35> PCIE_WAKE# <42> BT_ACTIVE

+1.5VS_CONN

+3VS_WLAN

Reserve for SW mini-pcie debug card. Series resistors closed to KBC side. LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R PCI_RST#_R CLK_PCI_DB

R508 R509 R510 R511 R512 R513

1 1 1 1 1 1

@ @ @ @ @ @

2 2 2 2 2 2

0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%

LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

LPC_FRAME# <14,40> LPC_AD3 <14,40> LPC_AD2 <14,40> LPC_AD1 <14,40> LPC_AD0 <14,40> BUF_PLT_RST# CLK_PCI_DB <15>

4

4

Compal Secret Data

Security Classification Issued Date

2010/07/12

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

Compal Electronics, Inc. Mini-Card/NEW Card/SIM

Size

Document Number

Rev 0.2

LA-6751P Date:

Friday, November 26, 2010

Sheet E

34

of

59

5

4

3

2

1

Power On strapping +1.7_VDDCT

+3V_LAN

+3VALW

+1.7_LX

Pin

Description

Chip Default

Close together

LED0

Layout Notice : Place as close chip as possible. 2

@

JUMP_43X79

D

Atheros request can't disable LAN power

1

2

C547 10U_0805_10V4Z

2

C548 0.1U_0402_16V4Z

1

+1.7_VDDCT @ C549 1000P_0402_50V7K

J8

1

L:Over Clock Disable

L39 1 2 +1.7_LX 4.7UH_SIA4012-4R7M_20%

LED2

1

2

H:Over Clock Enable

Note: Place Close to LAN chip L39 DCR< 0.15 ohm Rate current > 1A

H

*

H:SWR Switch mode regulator Select

*

AR8151 Pin23=LED2.

--

AR8152, Pin23 is CLKREQ D

Close to Pin40

U26

8152@

S IC AR8152-AL1E QFN 40P E-LAN CTRL

RX_N

<15> PCIE_PTX_C_DRX_P1

35

RX_P

CLK_PCIE_LAN#_C32 0_0402_5% 1 CLK_PCIE_LAN_C 33 0_0402_5% 1

2R517 2R518

<15> CLK_PCIE_LAN# <15> CLK_PCIE_LAN

<15> CLKREQ_LAN#

W AKE# SMCLK SMDATA

RBIAS

10

28 27

TEST_RST TESTMODE

VDD33

1

LAN_XTALO LAN_XTALI CLKREQ_LAN#_R

C566 0.1U_0402_16V4Z

C567 0.1U_0402_16V4Z

Near Pin34

2

1

2

C569 0.1U_0402_16V4Z

GIGA@ C565 0.1U_0402_16V4Z

Near Pin31

2

1

C568 1U_0402_6.3V4Z

GIGA@ C564 0.1U_0402_16V4Z

Near Pin19

2

7 8

PERST#

4 13 19 31 34 6

LX XTLO XTLI

41

CLKREQ# AVDDL AVDDL AVDDL AVDDL AVDDL_REG

40

+1.7_LX

5

+1.7_VDDCT

MDI2-

1 2 R522 2.37K_0402_1%

1

AVDDH AVDDH AVDDH_REG

16 22 9

+2.7_AVDDH +2.7_AVDDH +2.7_AVDDH

MDI3+ +3V_LAN

1

+1.7_VDDCT

2C561 0.1U_0402_16V4Z

2

1

2

1

2

1

2

Y4

1

2

1

2

C

1@

2 C574 1000P_0402_50V7K

1

2 C575 0.1U_0402_16V4Z

1@

2 C576 1000P_0402_50V7K

1

2 C577 0.1U_0402_16V4Z

1@ 1 1@ 1

2 C580 1000P_0402_50V7K 2 C581 0.1U_0402_16V4Z GIGA@ 2 C582 1000P_0402_50V7K 2 C583 0.1U_0402_16V4Z GIGA@

1

Note 1 : 8152 no mount MDI3+, MDI3-, MDI2-, MDI2+ resister and cap

2

Note 2 : C574, C576, C580, C582, reserved for EMI.

1

2

1

2

2

1

2

C579

1

2

27P_0402_50V8J

25MHZ_20PF_7A25000012

C578

MDI3-

C554 & C555 Close pin1 < 200mil C557 & C558 Close pin < 400mil

49.9_0402_1% 2 49.9_0402_1% R527 1 2 49.9_0402_1% R528 1 2 49.9_0402_1% R529 1 2 49.9_0402_1% R530 1 2 [email protected]_0402_1% R531 1 2 GIGA@ 49.9_0402_1% R532 1 2 GIGA@ 49.9_0402_1% R533 1 2 GIGA@ R526 1

B

LAN_XTALO

27P_0402_50V8J

MDI2+

+1.7_LX

+1.1_DVDDL +1.1_DVDDL

LAN_XTALI

2

MDI1-

1

24 37

GND

1

MDI1+

+3V_LAN

DVDDL DVDDL_REG

AR8151-AL1A_QFN40_5X5 GIGA@

1

Near Pin6

<36> <36> <36> <36> <36> <36> <36> <36>

2

1

2

MDI0MDI0+ MDI1MDI1+ MDI2MDI2+ MDI3MDI3+

Close Pin 10

VDDCT

Near Pin13

2

1

REFCLK_N REFCLK_P

25 26

+1.1_AVDDL +1.1_AVDDL +1.1_AVDDL +1.1_AVDDL +1.1_AVDDL

1

LAN_RBIAS

MDI0+ MDI0-

3

B

1

MDI0MDI0+ MDI1MDI1+ MDI2MDI2+ MDI3MDI3+

PCIE_WAKE#_R 1R519 @ 0_0402_5% 2 0_0402_5% 1R521 2

R525 GIGA@ 1 2 0_0402_5%

CLKREQ_LAN#

12 11 15 14 18 17 21 20

2

2 8152@ 0.1U_0402_16V4Z

1 C559

TRXN0 TRXP0 TRXN1 TRXP1 TRXN2 TRXP2 TRXN3 TRXP3

BUF_PLT_RST#

<18,34,40> BUF_PLT_RST# <16,34> PCIE_WAKE# <40> LAN_WAKE#

8151-AL1A

CLKREQ_LAN#

@ C558 10U_0805_10V4Z

36

Place Close to LAN chip ACTIVITY <36> LAN_LINK# <36>

1 8152@ 2 R516 0_0402_5%

C557 10U_0805_10V4Z

<15> PCIE_PTX_C_DRX_N1

Atheros

C555 1U_0402_6.3V4Z

TX_P

C554 0.1U_0402_16V4Z

20.1U_0402_16V7K PCIE_PRX_C_DTX_P130

ACTIVITY LAN_LINK#

C560 0.1U_0402_16V4Z

C5521

38 39 23

C562 1U_0402_6.3V4Z

<15> PCIE_PRX_DTX_P1

1 2 R515 5.1K_0402_5%

LED_0 LED_1 LED_2

C563 0.1U_0402_16V4Z

TX_N

GIGA@ C573 0.1U_0402_16V4Z

20.1U_0402_16V7K PCIE_PRX_C_DTX_N129

C572 0.1U_0402_16V4Z

C5531

C570 1U_0402_6.3V4Z

<15> PCIE_PRX_DTX_N1

C571 0.1U_0402_16V4Z

C

no overclocking PD 5.1K

LED0,1,2 intel Pull UP

U26

Place Close to Chip

Near Pin9

Near Near Near Pin22 Pin16 Pin37

Near Pin24

A

A

Configure Pin4

R525

C559

Configure Pin23

R516

VDDCT_REG

AR8151

CLKREQn

* * 5

CLKREQn

*

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

AR8152

2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LED[2] 4

3

2

Title

LAN-AR8151/8152 Size Document Number Custom Date:

Rev 0.1

LA-6751P

Friday, November 26, 2010

Sheet 1

35

of

59

5

4

3

2

8/23 Change

T1,T2 P/N to SP050006E00

+1.7_VDDCT

T1

D

2 R304 2

1

1 0_0603_5%

C435 GIGA@ 0.1U_0402_16V4Z

<35> <35>

MDI3+ MDI3-

<35> <35>

MDI2+ MDI2-

MDI3+ MDI3-

1

@C427 @ C427 1U_0402_6.3V4Z

1 1 2 2

C436 GIGA@ 0.1U_0402_16V4Z

MDI2+ MDI2-

1 2 3 4 5 6 7 8

D

TD+ TDCT NC NC CT RD+ RD-

TX+ TXCT NC NC CT RX+ RX-

16 15 14 13 12 11 10 9

MDO3+ MDO3MCT3 MCT2 MDO2+ MDO2-

2 R534 1 GIGA@ 75_0402_5% 2 R535 1 GIGA@ 75_0402_5%

BOTHHAND_NS0013LF GIGA@

6/23 update 1 T2 2

Place Close to T2

C438 0.1U_0402_16V4Z

<35> <35>

MDI0+ MDI0-

<35> <35>

MDI1+ MDI1-

MDI0+ MDI0-

1 MDI11

C

MDI1+ D31

2

C440 0.1U_0402_16V4Z

MDI1+ MDI1-

1 2 3 4 5 6 7 8

TCLAMP3302N.TCT_SLP2626P10-10

TD+ TDCT NC NC CT RD+ RD-

TX+ TXCT NC NC CT RX+ RX-

16 15 14 13 12 11 10 9

MDO0+ MDO0MCT0

2 R536 1 75_0402_5%

MCT1

2 R537 75_0402_5%

MDO1+ MDO1C643 22U_1206_10V7K

6 7 8 9 10

BOTHHAND_NS0013LF

1

2

2

6 7 8 9 10

@

1

C

C644 22U_1206_10V7K

@

Reserve gas tube for EMI go rural solution 20101006

5 4 3 2 1

JRJ2 <35> LAN_LINK#

LAN_LINK# @ C378 470P_0402_50V7K

MDI0MDI0+

1 +3V_LAN

220_0402_5% 2 R699

2

@ B

1

R02

GND 5 4 3 2 1

11

2

C585 1000P_1206_2KV7K

Reserve D1 for EMI go rural solution 20101006

1

12

Green LED-

11

Green LED+

MDO3-

8

PR4-

MDO3+

7

PR4+

MDO1-

6

PR2-

MDO2-

5

PR3-

MDO2+

4

PR3+

MDO1+

3

PR2+

MDO0-

2

PR1-

MDO0+

1

PR1+

10 ACTIVITY

<35> ACTIVITY

R538

@ C379 470P_0402_50V7K

2

1 220_0402_5%

9

SHLD2

16

SHLD1

15

B

SHLD2

14

SHLD1

13

Yellow LEDYellow LED+ LIYO_101007-08203-033

1

ME@ 2

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/07/12

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

LAN_Transformer Size B Date:

Document Number

Rev 0.2

LA-6751P Friday, November 26, 2010

Sheet 1

36

of

59

5

4

3

2

1

D

D

U27

2

REMOTE1-

REMOTE2+

1 C588 2200P_0402_50V7K

C590 0.1U_0402_16V4Z

@

2

2

REMOTE2-

1

1

C Q97 MMST3904-7-F_SOT323-3

2 B 2

E

3

R540 10K_0402_5% @

1

REMOTE1-

2

C587 2200P_0402_50V7K

@ C586 100P_0402_50V8J

1

VDD

SMCLK

10

EC_SMB_CK2

REMOTE1+

2

DP1

SMDATA

9

EC_SMB_DA2

REMOTE1-

3

DN1

ALERT#

8

REMOTE2+

4

DP2

THERM#

7

REMOTE2-

5

DN2

GND

6

EC_SMB_CK2 <15,24,40> EC_SMB_DA2 <15,24,40>

Under WWAN

REMOTE2+ @ C589 100P_0402_50V8J

1

1

+3VS

Close to DDR

REMOTE1+

C

2 B 2

@ Q98 MMST3904-7-F_SOT323-3

E

3

REMOTE1+

1

+3VS

1

SMSC thermal sensor placed near by VRAM

Close U20

REMOTE2-

EMC1403-2-AIZL-TR_MSOP10

REMOTE1,2+/-: Trace width/space:10/10 mil Trace length:<8"

Address 1001_101xb

C

10/5 change P/N to SA000046C00

C

B

B

FAN1 Conn +5VS JFAN1 <40> EC_TACH <40> EC_FAN_PW M

2

1

C591 10U_0805_10V4Z

1 2 3 4 5 6

1 2 3 4 G5 G6

ACES_85205-04001 ME@

A

A

Compal Electronics,Ltd.

Compal Secret Data

Security Classification 2010/07/12

Issued Date

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

EMC1403_Thermal sensor/FAN Size Document Number Custom Date: Friday, November 26, 2010

Rev 0.2

LA-6751P Sheet 1

37

of

59

A

B

C

D

E

F

G

H

Left USB Conn. +USB_VCCB

2

2

@ @

1 R660 1 R661

JUSB1

8/27 change to @

C593 470P_0402_50V7K

D16 @

WCM-2012-900T_4P USB20_N1

9/27 change C592 to 4.2H SF000002Y00

USB20_P1

4 1

4

3

1 L65

2

3 2

USB20_N1_C USB20_P1_C

VCC DD+ GND

5 6 7 8

GND1 GND2 GND3 GND4

1

SUYIN_020173GR004M58BZL ME@

1

1

1 2 3 4

USB20_N1_C USB20_P1_C

2 2 0_0402_5% 0_0402_5% 3

+

1

PJDLC05_SOT23-3

C592 220U_6.3V_M

W=80mils USB20_N1 USB20_P1

<18> USB20_N1 <18> USB20_P1

2

1

8/27 change to stuff +5VALW

+USB_VCCB

E-SATA COMBO RIGHT USB PORT

U29 1 2 3 USB_ON# 4

C594 0.1U_0402_16V4Z 2 1 <40,42,56,57> USB_ON#

GND IN IN EN

OUT OUT OUT OC#

8 7 6 5

USB_OC0#

USB_OC0# <18,56,57>

APL3510BKI_SO8

Low Active 1

C595 @ 1000P_0402_50V7K

2

SATA HDD Conn. JHDD1

2

SATA_ITX_DRX_P0 SATA_ITX_DRX_N0

<14> SATA_ITX_DRX_P0 <14> SATA_ITX_DRX_N0 <14> SATA_DTX_C_IRX_N0 <14> SATA_DTX_C_IRX_P0

SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0

C596 1 C597 1

2 0.01U_0402_16V7K 2 0.01U_0402_16V7K

SATA_DTX_IRX_N0 SATA_DTX_IRX_P0

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

+3VS

+5VS

+5VS

+3VS

1

2

1 C598 1000P_0402_50V7K

2

1 C599 0.1U_0402_16V4Z

2

1 C600 1U_0603_10V4Z

2

1 C601 10U_0805_10V4Z

2

1 C602 10U_0805_10V4Z

2

1 2 3 4 5 6 7

@ C603 0.1U_0402_16V4Z

2

GND RX+ RXGND TXTX+ GND

3.3V 3.3V 3.3V GND GND GND 5V 5V 5V GND Reserved GND 12V 12V 12V

GND GND

23 24

SUYIN_127043FB022G278ZR

3

3

@

@

ODD Power Control @ 1

J9

1

2

2

JUMP_43X79

+5VS

1

3

1

Change footprint 20100814

AP2301GN-HF_SOT23-3

2

C607

1 R675 2 100K_0402_5%

1

1

Q99 2

R552 10K_0402_5%

+5V_ODD

1

2

0.01U_0402_16V7K

2

Issued Date

2010/07/12

4

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

E

C608 10U_0805_10V4Z

Q100 DTC124EKAT146_SC59-3

Compal Electronics, Inc.

Compal Secret Data

Security Classification

1

2

OUT IN

3

2

GND

<19> ODD_EN 4

C604 0.1U_0402_16V4Z

F

Title

HDD/ODD Connector Size B

Document Number

Rev 0.2

LA-6751P Friday, November 26, 2010

Date: G

Sheet

38 H

of

59

5

4

3

CX20671 High Definition Audio Codec SoC With Integrated Class-D Stereo Amplifier. An integrated 5 V to 3.3 V Low-dropout voltage regulator (LDO). An integrated 3.3 V to 1.8V Low-dropout voltage regulator (LDO).

2

1

HDA_RST_AUDIO#

EMI

HDA_SYNC_AUDIO HDA_SDOUT_AUDIO_R 1 33_0402_5%

2 R556

HDA_BITCLK_AUDIO

@

2

@

2

@

1

2

@

1 22P_0402_50V8J C612

22P_0402_50V8J C610

22P_0402_50V8J C609

D

1 22P_0402_50V8J C611

9/27 Update U30 P/N to SA00003K410

1

2 D

@

2

2

1

C620

1

2

1

2

0.1U_0402_16V4Z

+LDO_OUT_3.3V 1

10U_0805_10V4Z C621

2

@

C618

1

0.1U_0402_16V4Z

2

2

0.1U_0402_16V4Z

1

1

1U_0603_10V4Z C619

2

0.1U_0402_16V4Z

C616

1

10U_0805_10V4Z C617

@ 2 1 0_0402_5% R558 To support Wake-on-Jack or Wake-on-Ring, the CODEC VAUX_3.3 & VDD_IO pins must be powerd by a rail that is not removed unless AC power is removed. *DSH page42 has more detail.

1

2

R557

+3VALW

6/24 change +3VS

C613

+VAUX_3.3

1

0_0402_5%

0.1U_0402_16V4Z C615

2

+3VS

10U_0805_10V4Z C614

+3VS

AVDD_3.3 pinis output of internal LDO. NOT connect to external supply.

9/28 Change to R879 for 21Z 2

5 8 2 33_0402_5% 6 4

2N7002H_SOT23-3 Q9 1R669

PC_BEEP

10

BIT_CLK SYNC SDATA_IN SDATA_OUT

1 2

2 R572 1 R573

38 37

C_BIAS PORTC_R PORTC_L

EAPD active low 0=power down ex AMP 1=power up ex AMP

SPK_L2+ SPK_L1-

11 13

SPK_R2+ SPK_R1-

16 14

NC NC NC

LEFT+ LEFTRIGHT+ RIGHT-

41

1 R351 4.7K_0402_5%

MIC_INR MIC_INL

AVEE FLY_P FLY_N

HP_OUTR_R HP_OUTL_R

C

R564

1

2 5.11K_0402_1%

R565 R567

1 1

2 10K_0402_1% 2 39.2K_0402_1%

R568 R569

+MICBIASC

23 22

Layout Note:Path from +5VS to LPW R_5.0 RPW R_5.0 must be very low resistance (<0.01 ohms)

C633 1 C634 1

R575 R574

2 2.2U_0603_6.3V4Z 2 2.2U_0603_6.3V4Z

1 1

2 2

15_0402_5% 15_0402_5%

2.2K_0402_5% 2.2K_0402_5% R570

100_0402_1%

R571

100_0402_1%

HP_OUTR <43> HP_OUTL <43>

MIC_JD <43> PLUG_IN <43>

Port C Port A

Sense resistors must be connected same power that is used for VAUX_3.3

+MICBIASC

EXT_MIC_R <43> EXT_MIC_L <43>

External MIC

Headphone

Changed from 5.1ohm to 15ohm for "zi zi"noise.

24 25 39 21 19 20

1 C638

2 1U_0603_10V4Z

1

2

CX20671-21Z_QFN40_6X6

1

2

B

+MICBIASB 1

HDA_RST_AUDIO# C584

R580 4.7K_0402_5%

1

100P_0402_50V8J

2

@

GND

+VAUX_3.3

Internal MIC

+MICBIASB

32 31 30

+5VS

Please bypass caps very close to device.

36 35 34 33

2

2 @

0.1_1206_1%

10U_0805_10V4Z

10U_0805_10V4Z C629

0.1U_0402_16V4Z C628

C626

0.1U_0402_16V4Z C627

0.1U_0402_16V4Z

2

1

2

@

12 15 17

GND

Internal SPEAKER

DMIC_CLK DMIC_1/2

+3VS

C640 @ 1 2 0.1U_0402_16V4Z R576 @ 1 2 0_0402_5% R577 @ 1 2 0_0402_5% R579 @ 1 2 0_0402_5%

B

GPIO0/EAPD# GPIO1/SPK_MUTE# PORTA_R PORTA_L

40 1

C637 @ 1 2 0.1U_0402_16V4Z

C632 PORTB_R PORTB_L B_BIAS

0_0402_5% 0_0402_5% EC_MUTE# 0_0402_5%

SENSE_A

2

2

1

PC_BEEP

@ 2

<40> EAPD <40> EC_MUTE#

LPWR_5.0 RPWR_5.0 CLASS-D_REF

1

1

10U_0805_10V4Z

1 R566

S

D

3

1

<14> HDA_SDIN0

HDA_SDOUT_AUDIO_R

2

C639

0_0402_5% 2 R578

2 G HDA_SDOUT_AUDIO 1 Change footprint 20100814

RESET#

2

1 R562

1

0.1U_0402_16V4Z C641

9 HDA_BITCLK_AUDIO_R

10U_0805_10V4Z C625

C624

8/10 update +3VS

<14> HDA_SDOUT_AUDIO

U30

29

2

2

1

0.1U_0402_16V4Z

HDA_SYNC_AUDIO

<14> HDA_SYNC_AUDIO

2

1

27 28 26

HDA_BITCLK_AUDIO

<14> HDA_BITCLK_AUDIO

1

FILT_1.65

2

HDA_RST_AUDIO#

<14> HDA_RST_AUDIO#

C

1

AVDD_3.3 AVDD_5V AVDD_HP

R563

FILT_1.8 VDD_IO VAUX_3.3 DVDD_3.3

2

1 R879 2 0_0805_5%

+5VS

10K only needed if supply to VAUX_3.3 is removed during system re-start.

3 7 2 18

2

1

0.1U_0402_16V4Z

1

10K_0402_5% C630

C622

R561

10U_0805_10V4Z C631

1

1

@

0_0402_5%

0.1U_0402_16V4Z

R560 2

+3VALW

+CLASSD_5VS

1

0_0402_5%

1U_0603_10V4Z C623

+3VS

MIC1

2

1 2

C642 1

2 2.2U_0603_6.3V4Z

MIC_INR

GNDA MIC_INL

GNDA 8/10 update

WM-64PCY_2P 45@

8/10 update for vendor suggestion

R720 0_0402_5% R598 1 @

2

FBMA-L11-160808-121LMA30T

wide 20MIL

R721

EC Beep

<40>

ICH Beep

<14>

2

BEEP#

1

D17 RB751V_SOD323 R582 1 2 33_0402_5%

1 C645

PC_BEEP 2 0.1U_0402_16V4Z

FBMA-L11-160808-121LMA30T

SPK_R1SPK_R2+ SPK_L1SPK_L2+

R720 R721 R722 R723

2 2 2 2

@ @ @ @

1 1 1 1

0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5%

SPK_R1-_CONN SPK_R2+_CONN SPK_L1-_CONN SPK_L2+_CONN

1 2 3 4

8/24 update

2

R723

10/08 update

Issued Date

2

1

2

1

2

5 6

2010/07/12

Deciphered Date

3

2

A

Title

CX20671 Codec Size C

Document Number

Rev 0.1

LA-6751P

Date: Friday, November 26, 2010 4

GND1 GND2

Compal Electronics,Ltd. 2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

1 2 3 4

ACES_88231-04001 ME@

Compal Secret Data

Security Classification

FBMA-L11-160808-121LMA30T

1

1000P_0402_50V7K

C649

2

FBMA-L11-160808-121LMA30T

1

1000P_0402_50V7K C651

R722 R585 10K_0402_5%

PC Beep

1000P_0402_50V7K C647

D30 RB751V_SOD323

A

JSPK1

1PC_BEEP1

1000P_0402_50V7K C650

2

1

HDA_SPKR

Sheet 1

39

of

59

+3VALW

KSI3 KSI4

+3VALW R595 1

2 47K_0402_5% KSO1

R597 1

2 47K_0402_5% KSO2

ENE UPDATE 08/10/21 +3VALW

+3VS

R600 R601 2.2K_0402_5%

R602 2.2K_0402_5%

R604

EC_SMB_CK1 2.2K_0402_5% EC_SMB_DA1 2.2K_0402_5% <57> <57>

EC_SMB_CK2 EC_SMB_DA2 1

2

@ C665 100P_0402_50V8J

1

2

@ C666 100P_0402_50V8J

<46> <46> <15,24,37> <15,24,37>

KSO16 KSO17

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

<16> SLP_S3# <16> SLP_S5# <19> EC_SMI#

77 78 79 80

EC_SMI#

1

+3VS

SUSWARN# INVT_PWM EC_TACH ODD_DA# EC_TX_P80_DATA EC_RX_P80_CLK

<16> SUSWARN# <31> INVT_PWM <37> EC_TACH <18,56,57> ODD_DA# <34,41> EC_TX_P80_DATA <34,41> EC_RX_P80_CLK <43> ON/OFF# <37> EC_FAN_PWM <43> NUM_LED#

EC_TACH

SUSCLK

2 0_0402_5%

EC_FAN_PWM

6 14 15 16 17 18 19 25 28 29 30 31 32 34 36

EC_RTCX1 122 SUSCLK_R 123

1 R611

SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47

1

8/23 modify

67

2 BATT_TEMP <46>

EC_FAN_PWM

CHG_ON# IREF

SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS#

119 120 126 128

CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59

73 74 89 90 91 92 93 95 121 127

EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11

100 101 102 103 104 105 106 107 108

PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7

110 112 114 115 116 117 118

V18R

124

GPIO SM Bus

GPI

KB930QF A0 LQFP 128P

R588 10K_0402_5% @

1

EC_MUTE# <39> USB_ON# <38,42,56,57>

TP_CLK TP_DATA

CMOS_OFF# <31> TP_CLK <56,57> TP_DATA <56,57>

10K_0402_5%

2

USB_ON# R594 1

H_PROCHOT#_EC 2 43_0402_1%

R665 1

CHARGE_LED0# CAPS_LED# CHARGE_LED1# SYSON ACIN

EC_LID_OUT# EC_ON PCH_POK_EC BKOFF# RF_LED#

<41> <41> <41> <41>

7/23 Modify

1 R599

FSEL#SPICS# 2 100K_0402_1%@

1 R603

H_PECI <6,19>

R591 1

2 4.7K_0402_5%

TP_DATA R592 1

2 4.7K_0402_5%

BATT_TEMP

+3VALW

2 100K_0402_1%@

ACIN

D18 1

1 R120

2 10M_0402_5%

1

@

2 R708 0_0402_5%

PCH_RTCX1_OUT <14>

SUSCLK_R

1

@

2 R709 0_0402_5%

PCH_RTCX2_OUT <14>

3

@

32.768KHZ_12.5PF_9H03200413

OSC NC

4

OSC

Y5

C347 2

S

Q37 2N7002H_SOT23-3 Change footprint 20100814

0_0402_5% R747 2 1 @ @ RB751V_SOD323 PCH_POK 2

7/28 Modify

PCH_POK <6,16>

1 2 1 2 +3VS R607 0_0402_5% R608 10K_0402_5% @

SLP_S4# <16> ENBKL <31> EAPD <39> NOVO# <43> SUSP# <10,26,44,49,51,52> PBTN_OUT# <16>

+3VALW

R606 10K_0402_5%

1

C667 4.7U_0603_6.3V6K 2 0_0402_5%

2

1

EC_PME#

LAN_WAKE# <35>

R609

2 0_0402_5%@

1 R610

1

3 @

2N7002H_SOT23-3

PCI_PME# <18>

+3VALW

6/24 Update R708,R709 must be close Y5

NC

1

2

18P_0402_50V8J @

1

@

2 100P_0402_50V8J 2 100P_0402_50V8J

H_PROCHOT# <6> D

2 G

Q102 Change footprint 20100814 EC_RTCX1

1 C663 1 C664

R737 0_0402_5% 2 1

VR_HOT#

<46,53> VR_HOT#

H_PROCHOT#_EC

7/23 Modify

BKOFF# <31> RF_LED# <56,57> PCH_APWROK <16> SA_PGOOD <50>

NOVO# SUSP# PBTN_OUT#

+5VS TP_CLK

FSTCHG <47> CHARGE_LED0# <56,57> CAPS_LED# <43> PWR_LED# <43,56,57> CHARGE_LED1# <56,57> SYSON <44,49> VR_ON <53> ACIN <16,24,47> EC_RSMRST# <16> EC_LID_OUT# <15> EC_ON <43,48> BATT_SEL_EC <47>

6/19 Add BRDID

2 10K_0402_5%

SYS_PWROK_EC <16> CE_EN_EC @ 2 1 CE_EN <31> 0_0402_5% R746 ME_FLASH <14> LID_SW# LID_SW# <56,57> FRD#SPI_SO

H_PECI_R

R695 8.2K_0402_5%

+3VALW

R593 1

USB_ON#

FRD#SPI_SO FWR#SPI_SI SPI_CLK FSEL#SPICS#

BRDID

10/6 Modify

+5VALW

CHG_ON# IREF <47> CHGVADJ <47>

FRD#SPI_SO FWR#SPI_SI SPI_CLK FSEL#SPICS#

1

BRDID

100K_0402_1% R694

@

ADP_I <46,47> IMVP_IMON <53>

2

9 22 33 96 111 125

97 98 99 109

XCLK1 XCLK0

C93 20P_0402_50V8

2

2

R740 100K_0402_5%

SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0

SPI Flash ROM

PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A

1

<16>

PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F

83 84 85 86 87 88

SPI Device Interface

GND GND GND GND GND

2

R605 10K_0402_5%

68 70 71 72

BATT_TEMP

EC_MUTE#

PS2 Interface

MP PVT DVT EVT

S

KSI[0..7] <56,57> KSI[0..7]

V V V

+3VALW

1

<56,57> <56,57>

<56,57> KSO[0..15]

KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49

max

+3VS

3

KSO[0..15]

55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82

63 64 65 66 75 76

DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F

DA Output

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

V V V

D

11/16 Modify

1

CPU1.5V_S3_GATE <10> BEEP# <39> PCH_DPWROK <16> ACOFF <45,47>

V V V

VAD_BID 0 V 0.289 0.538 0.875

2 G

C661 0.1U_0402_16V4Z

EC_SCI# BATT_LEN#

AGND

<19> <46>

2

AD

BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43

69

2 47K_0402_5%

PWM Output

PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D

CPU1.5V_S3_GATE BEEP# PCH_DPWROK ACOFF

typ

V AD_BID 0 V 0.250 0.503 0.819

2

EC_RST# EC_SCI# BATT_LEN#

12 13 37 20 38

<18> CLK_PCI_LPC <18,34,35> BUF_PLT_RST#

21 23 26 27

VAD_BID 0 V 8.2K +/- 5% 0.216 18K +/- 5% 0.436 33K +/- 5% 0.712

ECAGND

1 R590

+3VALW

10_0402_5%

INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13

11 24 35 94 113

2 1 2 1 @ C660 22P_0402_50V8J @ R589

GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC

U31

min

R695 0

1

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

1 2 3 4 5 7 8 10

0 1 2 3

1

KB_RST#

KB_RST#

2

2

GATEA20

<14> SERIRQ <14,34> LPC_FRAME# <14,34> LPC_AD3 <14,34> LPC_AD2 <14,34> LPC_AD1 <14,34> LPC_AD0

<19> <19>

100K +/- 5%

Board ID

AVCC

Change to 0 ohm P/N

2

1

VCC VCC VCC VCC VCC VCC

2

1

C658 1000P_0402_50V7K

2

1

C657 1000P_0402_50V7K

1 L45

2

1

C655 0.1U_0402_16V4Z

1 ECAGND 2 2 FBM-11-160808-601-T_0603

2

C662 0.1U_0402_16V4Z

C659 1000P_0402_50V7K

C654 0.1U_0402_16V4Z

+EC_AVCC

1

C656 0.1U_0402_16V4Z

C653 0.1U_0402_16V4Z

2

1

3.3V +/- 5%

Vcc R694

+EC_AVCC L44 1 2 +3VALW FBM-11-160808-601-T_0603

1

1

2

C367 18P_0402_50V8J @

8/23 change to reserved

Compal Secret Data

Security Classification Issued Date

2010/07/12

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc. BIOS & EC I/O Port

Size Document Number Custom Date:

Friday, November 26, 2010

Rev 0.2

LA-6751P Sheet

40

of

59

FOR EC 128KB SPI ROM (150mil PACKAGE) SA00003FL10 SA00003JD00 +3VALW R619

20mils C699 0.1U_0402_16V4Z

R617 10K_0402_5% U33

<40> FSEL#SPICS# FRD#SPI_SO

<40> FRD#SPI_SO

R618 1

FSEL#SPICS# SPI_SO 2 15_0402_5%

1 2 3 4

CS# DO WP# GND

S SUPPRE_ KC FBMA-10-100505-101T 0402

2

2

8/27 R619 change to Bead

1

1

VCC HOLD# CLK DIO

8 7 6 5

MX25L2005CMI-12G SOP

HOLD# SPI_CLK_R

R619 @ 0_0402_5% 1 2

SPI_SI_EC

1

2 15_0402_5%

SPI_CLK FWR#SPI_SI

R620

SPI_CLK <40> SPI_CLK_R

FWR#SPI_SI <40>

Colse to EC 1 @ C700 10P_0402_50V8J 2

EC DEBUG PORT

EMI

JP3 EC_TX_P80_DATA EC_RX_P80_CLK

1 2 3 4

1 2 3 4

ACES_85205-0400 ME@ FD1 1

FD2 1

FD3 1

FD4 1

H_3P8 H4 HOLEA

1

H3 HOLEA

1

H2 HOLEA

1

1

H1 HOLEA

H_3P3

H_3P0x4P5N

H6 HOLEA

H_3P0N H5 HOLEA

H_6P0 H17 HOLEA

1

H10 HOLEA

H9 HOLEA

1

1

1

H16 HOLEA

1

H15 HOLEA

H7 HOLEA

H_5P5N H14 HOLEA

1

1

H8 HOLEA

1

H13 HOLEA

1

1

H11 HOLEA

1

H12 HOLEA

1

H_2P8

1

+3VALW <34,40> EC_TX_P80_DATA <34,40> EC_RX_P80_CLK

Compal Secret Data

Security Classification Issued Date

2010/07/12

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc. LED/EC SPI ROM

Size B Date:

Document Number

Rev 0.2

LA-6751P Friday, November 26, 2010

Sheet

41

of

59

A

B

C

D

E

8/27 change to stuff 1

1

WCM-2012-900T_4P

GND IN IN EN

OUT OUT OUT OC#

2

E-SATA COMBO RIGHT USB PORT USB_OC1# <18>

2

3

4

4

3

3

USB20_N3_C

USB20_P3

1

1 L64

2

2

USB20_P3_C

+

<14> SATA_ITX_DRX_P4 <14> SATA_ITX_DRX_N4

2

C706 220U_6.3V_M

3

1 2 3 4

VCC DD+ GND

5 6 7 8

GND1 GND2 GND3 GND4 SUYIN_020173GR004M58BZL ME@

W=80mils 8/27 change to @

1

C705 470P_0402_50V7K

SATA_DTX_C_IRX_N4 0.01U_0402_16V7K 2 SATA_DTX_C_IRX_P4 2 0.01U_0402_16V7K

SATA_ITX_DRX_P4 SATA_ITX_DRX_N4 ESATA@ 1 C707 SATA_DTX_IRX_N4 1 C708 SATA_DTX_IRX_P4 ESATA@

0_0402_5% @ USB20_N3 2 R865 1USB20_N3_C USB20_P3 2 @ 1USB20_P3_C 0_0402_5% R864

<18> USB20_N3 <18> USB20_P3

2

BT MODULE CONN

1 R632 2 100K_0402_5% BT@

C709

1

0_0402_5% ESATA@

1

C735 0.1U_0402_16V4Z 2 @

@

R627 R628

1 ESATA@2 1 2 ESATA@ 1 ESATA@2 1 2 ESATA@

R629 R630

0_0402_5% SATA_ITX_DRX_P4_R 0_0402_5% SATA_ITX_DRX_N4_R ESATA_DET#_CONN 0_0402_5% SATA_DTX_IRX_N4_R 0_0402_5% SATA_DTX_IRX_P4_R

JESAT1

1 2 3 4

VBUS DD+ GND

5 6 7 8 9 10 11

GND A+ AGND BB+ GND

USB A+ = RXP A- = RXN

USB

ESATA

SHIELD SHIELD SHIELD SHIELD

12 13 14 15

2 R866

1

2 R867

1

ESATA_DET#_CONN

B- = TXN B+ = TXP

0_0402_5%

3

0.1U_0402_16V4Z

7/31 Add

2

+3VS

+3VS

BT@

USB20_P13 USB20_N13 BT_ACTIVE

USB20_P13 USB20_N13 BTON_LED BT_ACTIVE

1 2 3 4 5 6

1 2 3 4 5 G1 6 G2

EN

SATA_ITX_DRX_P4 SATA_ITX_DRX_N4

1 2

RX_0P RX_0N

VCC VCC VCC VCC

SATA_DTX_IRX_P4 SATA_DTX_IRX_N4

5 4

TX_1P TX_1N

D0 D1

3 13 17 18 19 21

ACES_87213-0600G ME@

GND GND GND GND GND PAD

2

2

1

R635 4.7K_0402_5% @

6 10 16 20 9 8

TX_0P TX_0N

15 14

SATA_ITX_DRX_P4_R SATA_ITX_DRX_N4_R

RX_1N RX_1P

12 11

SATA_DTX_IRX_N4_R SATA_DTX_IRX_P4_R

R636 0_0402_5% @

R637 0_0402_5% @

4

SN75LVCP412RTJR_QFN20_4X4 @

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2010/07/12

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

R634 4.7K_0402_5% @

1

U35

7

7 8

C711 0.01U_0402_16V7K 1 @

2

2

0.1U_0402_16V4Z C712 BT@ JBT1

3

4

Q105 DTC124EKAT146_SC59-3 @ <18> <18> IN 2 <34>

1

2

C710 0.1U_0402_16V4Z 2 @

1

GND

OUT

1

<56,57> BT_LED#

30mils

1

2

BT@ +3VS Q103 DTC124EKAT146_SC59-3 3 1 BT@ Change footprint Q104 20100814 AP2301GN-HF_SOT23-3

R633 4.7K_0402_5%

1

@

2

3

IN

2

+3VS_BT

1

2

GND

2 BT_OFF#

USB20_N2_C USB20_P2_C

FOX_3Q38111-RB1C3-7HC

OUT

0_0402_5%

<19>

JUSB2

2 R862 @1 0_0402_5% 2 R863 @1 0_0402_5%

1

R877

USB20_P2_C

D21 @

2

<19> ESATA_DET#

R631 100K_0402_5%

1 @

2

8/27 change to @

+USB_VCCC

1 BT@

C702 470P_0402_50V7K

1

<14> SATA_DTX_C_IRX_N4 <14> SATA_DTX_C_IRX_P4

1

PJDLC05_SOT23-3

USB20_N3

+5VALW

3

2

USB20_N2 USB20_P2

<18> USB20_N2 <18> USB20_P2

WCM-2012-900T_4P

D22 @

1 L63

+USB_VCCC

C704 @ 1000P_0402_50V7K

8/27 change to stuff

USB20_P3_C

1

2

1

2 USB20_N3_C

USB20_P2

ESATA and USB Conn.

APL3510BKI_SO8

Low Active

2

USB20_N2_C

1

C703 0.1U_0402_16V4Z 2 1 <38,40,56,57> USB_ON#

8 7 6 5

3

W=80mils

1

1 2 3 USB_ON# 4

3

PJDLC05_SOT23-3

+5VALW

U34

4

Left USB Conn. +USB_VCCC

+USB_VCCC

4

2

(220uF_6.3V_5.9L_ESR17m)*2=(SF000001500)

USB20_N2

B

C

D

USB ports/BT/E-SATA Size Document Number Custom Date:

Rev 0.2

LA-6751P

Friday, November 26, 2010

Sheet E

42

of

59

ON/OFF switchSW 3 Power Button

@

1

3

2

4

Power Bottom Board Conn. 8pin

6 5

SMT1-05_4P +3VALW

J11

+5VALW

2 1

2

1

D23 ON/OFFBTN#

JPW RB1

R638 100K_0402_5%

SHORT PADS

Bottom Side

3

ON/OFF#

2

51_ON#

1

ON/OFF# <40>

1 2 3 4 5 6 7 8

<40> NUM_LED# <40> CAPS_LED# <40,56,57> PW R_LED#

51_ON# <45>

NOVO_BTN# ON/OFFBTN#

DAN202UT106_SC70-3

1

9 10

EC_ON

JCR1

ACES_88058-080N

3

S

+3VS

Change footprint 20100814

R639 10K_0402_5%

1 2 3

ON/OFFBTN#

2 NOVO#

1 L67

3 2

3

USB20_N11_C

2

USB20_P11_C

ACES_88058-120N

@

2 1

51_ON#

4

1

D26

1

NOVO#

USB20_P11 1

D24 PJSOT24C 3P C/A SOT-23 @

R642 100K_0402_5%

<40>

W CM-2012-900T_4P USB20_N11 4

1 2 3 4 5 6 7 8 9 10 11 12 GND GND

2

NOVO_BTN#

EXT_MIC_L EXT_MIC_R MIC_JD 0_0402_5% USB20_P11 2 R871 1 USB20_N11 2 R870 1 0_0402_5%

<18> USB20_P11 <18> USB20_N11

ME@

+3VALW

1 2 3 4 5 6 7 8 USB20_P11_C 9 USB20_N11_C10 11 12 13 14

<39> EXT_MIC_L <39> EXT_MIC_R <39> MIC_JD

2N7002H_SOT23-3 Q106

HP_OUTL HP_OUTR PLUG_IN

<39> HP_OUTL <39> HP_OUTR <39> PLUG_IN

GND GND

D

2 G 2

EC_ON

Card Reader/Audio Jack SB CONN 8/5 modify

1

<40,48>

1 2 3 4 5 6 7 8

C635 1000P_0603_50V7K

TOP Side

NOVO_BTN#

3 DAN202UT106_SC70-3

EMI REQUEST 1ST = SCA00000E00 2ST = SCA00000R00

Issued Date

Compal Electronics,Ltd.

Compal Secret Data

Security Classification 2010/07/12

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

other IO connector Size Document Number Custom Date: Friday, November 26, 2010

Rev 0.2

LA-6751P Sheet

43

of

59

Change footprint 20100814

+5VALW TO +5VS

D

+1.5V to +1.5VS

Change footprint 20100814

+3VALW TO +3VS

E

+1.5V

1

2 R645 470_0603_5% @

C717 10U_0805_10V4Z

S

2 Q111 2N7002H_SOT23-3 @ Change footprint 20100814

1

1

2

1

2 G

SUSP

S

100K_0402_5% R648

C727 0.1U_0603_25V7K

2 R651

1

D

1.5VS_GATE 1 1

0_0402_5%

SUSP# 2 G 3

R650 0_0402_5%

S

2N7002H_SOT23-3 Q109 Change footprint @ 20100814

1

2 SUSP G Change footprint 20100814

R643 470_0603_5% @

D

+3VALW

2 D

2 G

1

D

1 SUSP

1

C718 C719 AP2301GN-HF_SOT23-3 10U_0805_10V4Z 1U_0603_10V4Z 2 2 2

C725 1U_0603_10V4Z

2N7002H_SOT23-3 Q108 @

1

C726 0.1U_0603_25V7K

1 Q8

1

2

1 2

C724 10U_0805_10V4Z

2 2

1

1

Q110 2N7002H_SOT23-3 Change footprint 20100814

S

2

1

R647 47K_0402_5%

15VS_GATE_R

10K_0402_5%

1

+VSB 2 SUSP G Change footprint 20100814

3

1

5VS_GATE2 R649 D

2 G

S

3

2N7002H_SOT23-3 Q107 @

R646 20K_0402_5%

3

4

D

+VSB

SUSP

R644 470_0603_5% @

3 1

3

1 2

4

1

+3VALW U39 +3VS DMN3030LSS-13_SOP8L-8 8 1 7 2 1 6 3 C723 5 10U_0805_10V4Z 2

1

U38 +5VALW +5VS DMN3030LSS-13_SOP8L-8 8 1 7 2 1 1 1 6 3 C720 C721 C722 5 10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z 2 2 2

Change footprint 20100814 +1.5VS

1

C

3

B

2

A

C728 C729 Q112 0.1U_0603_25V7K 2 2N7002H_SOT23-3 2 Change footprint 0.1U_0603_25V7K 20100814

S

+RTCVCC

+5VALW 1

2

1

2

S

<10,26,40,49,51,52> SUSP#

IN

SYSON

SYSON

2

2

3

IN

3

2N7002H_SOT23-3

<40,49>

1

2 1

2

2

OUT

2 SUSP G 2N7002H_SOT23-3 Change footprint 20100814

GND

Q116 @

SYSON# Q119 DTC124EKAT146_SC59-3 @

3

SUSP

@ R654 100K_0402_5%

OUT

1 2

Q117 DTC124EKAT146_SC59-3

D 2 G

S

<6,10,51> SUSP

R659 470_0603_5% @

SUSP

GND

2N7002H_SOT23-3 Q115 Change footprint 20100814

3

S

D 2 SYSON# G Change footprint 20100814

R652 100K_0402_5%

1

1 R658 22_0603_5%

D 2 SUSP Q114 G Change footprint @ 20100814 2N7002H_SOT23-3

@ R653 100K_0402_5%

+1.05VS

1 2

R656 470_0603_5% @

3

S

3

Q113 @

+0.75VS

1

D 3

1 2

R655 470_0603_5% @

3

1 2

1

+1.5V

1

+5VALW +1.8VS

For Intel S3 Power Reduction.

4

4

2010/07/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

DC Interface Size Document Number Custom Date:

Rev 0.2

LA-6751P

Friday, November 26, 2010

Sheet E

44

of

59

4

3

VIN

D

PreCHG PR102 @ 1K_1206_5% 1 2

PD102 2

1

PR104 @ 1K_1206_5% 1 2 PR107 @ 1K_1206_5% 1 2

1

1 1

PQ103 @ DDTC115EUA-7-F_SOT323-3

1

PD103 LL4148_LL34-2

PR108 @ 100K_0402_1%

2

VIN

3

@ LL4148_LL34-2

PR103 @ 1K_1206_5% 1 2

1

1

2

3

<48> +5VALWP

@ RB715F_SOT323-3

3

B+

ACIN Precharge detector Min. typ. Max. L-->H 14.991V 15.381V 15.782V H-->L 13.860V 14.247V 14.621V

A

4

3

S

2010/01/25

2010/12/31

Deciphered Date

2

1 2

PC110 @ 0.01U_0402_25V7K

1

PACIN

2

+5VALWP

BATT ONLY Precharge detector Min. typ. Max. L-->H 7.196V 7.349V 7.505V H-->L 6.138V 6.214V 6.056V

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

2 G

Compal Secret Data

Security Classification Issued Date

2 1 PR116 @ 499K_0402_1%

1 PR115 @ 205K_0402_1%

PR121 @ 66.5K_0402_1% 1 2

6251VREF

PR120 <47> @ 47K_0402_5% 2 1

D

B

3

PD106 RB751V-40_SOD323-2

PRG++ 2

PC107 2 1

@ 0.01U_0402_25V7K

8

PR114 @ 100K_0402_1% 2 1

PR119 @ 34K_0402_1% 2 1

+3VLP

PQ106 @ DTC115EUA_SC70-3

2

1

1

3

ML1220T13RE 45@

PQ105 @2N7002W-T/R7_SOT323-3

+CHGRTC

3 2

PC109 @1000P_0402_50V7K

PR118 560_0603_5% 1 2

-

1

PR117 560_0603_5% 1 2

+

O

2

+RTCBATT

1

P

+ 1

ACON

4

JRTC1 2

<47>

+RTCBATT

PU101A LM393DG_SO8

PC108 @ 0.1U_0603_25V7K 2 1

<46,48> MAINPWON

@ RB715F_SOT323-3 2 1 3

VS

2 1 PR113 @ 499K_0402_1%

PR112 @ 2.2M_0402_5% 2 1

PD105

-

C

2

1

PC106 0.1U_0603_25V7K

VL

B

2

3

VS

1

G

51_ON#

3

PR110 68_1206_5%

2

1 <43>

PR111 22K_0402_5% 1 2

2

PR101 100K_0402_5%

PC105 0.22U_0603_25V7K 2 1

N1

2

<40,47> ACOFF

2

PQ101 TP0610K-T1-E3_SOT23-3

C

2

PR109 68_1206_5%

1 2

PD104 1

PD101 LL4148_LL34-2 2 1

BATT+

PQ104 @ DDTC115EUA-7-F_SOT323-3

VIN

PQ102 @ TP0610K-T1-E3_SOT23-3

2

1 2

PC104 1000P_0402_50V7K

1 2

PC103 100P_0402_50V8J

@ 4602-Q04C-09R 4P P2.5 JDCIN1

1

1 2

1

1

2

2

D

PC102 100P_0402_50V8J

3

2

Precharge detector 15.97V/14.84V FOR ADAPTOR

PL101 SMB3025500YA_2P 1 2

PC101 1000P_0402_50V7K

4

3

PF101 7A_24VDC_429007.WRML APDIN 1 2 APDIN1

1

PR106 @ 100K_0402_1% 2 1

DC030006J00

4

2

PR105 @ 100K_0402_1% 2 1

5

Title

A

Compal Electronics, Inc. PWR DCIN / Vin Detector /Pre-charge

Size Document Number Custom

Rev 0.1

PIWG1/G2(LA-6751P/LA-6753P)

Date:

Friday, November 26, 2010

Sheet 1

45

of

54

5

4

VMB2 1 2 3 4 5 6 7 8 9

1

PH201 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 56 degree C

PL201 SMB3025500YA_2P 1 2

BATT+ D

1 2

2

PC201 1000P_0402_50V7K

PC202 0.01U_0402_25V7K

VL

ADP_I

<40,47>

A/D

2

1

PR205 @ 100K_0402_1%

2

1

2

2

8

3.48K_0402_1%

PR222 1

1 VCC TMSNS1

OT1 TMSNS2

6

4

OT2 RHYST2

PR206 9.76K_0402_1%

5

G718TM1U_SOT23-8 PR223 @ 0_0402_5%

S

1

7

3

1

GND RHYST1

2

2 G

2

1

BATT_TEMP <40>

1

PR204 21.5K_0402_1%

PH201 100K_0402_1%_TSM0B104F4251RZ 2

1 2 PR209 10K_0402_5%

PR221 100K_0402_1%

1 +3VALW

1

PQ204

1 2 PR207 6.49K_0402_1%

D

PU201

3

2N7002KW_SOT323-3

EC_SMB_DA1 <40>

2

EC_SMB_CK1 <40> <40,53> VR_HOT#

PR203 @ 10K_0402_1%

VL

1 2 PR208 43.2K_0402_1%

2

PC203 0.1U_0603_25V7K

2

VL 1

TYCO_1775789-1 @

2 1 PR202 100_0402_1%

1

EC_SMCA EC_SMDA 2 1 PR201 100_0402_1%

1 2 3 4 5 6 7 GND GND

2

VMB PF201 12A_65V_451012MRL 1 2

JBATT1 D

3

1

MAINPWON <45,48>

C

C

2

PH202 100K_0402_1%

2

2 1

<40> BATT_LEN#

D

S

2 G

VL

1

+VSBP

2

1

B

PC206 0.1U_0603_25V7K

2

1 2

PC205 0.22U_0603_25V7K

6251VREF

PR219 100K_0402_1% 1

PR217 10K_0402_1%

PR218 22K_0402_1% 1 2

2 1 PR216 100K_0402_1%

1

1

2

3

1

232K_0402_1%

3

B+

SPOK

1

PR220 1K_0402_5% 2

2

1

<48>

1

S

2 G

PQ202 TP0610K-T1-E3_SOT23-3

D PQ203 2N7002W-T/R7_SOT323-3

2 G 3

7

PU101B LM393DG_SO8

BATT_OUT <47>

2

1 O -

3

+

4

PR215

D

PC207 1U_0402_6.3V6K

PQ201 2N7002KW_SOT323-3

2

PQ205 2N7002KW_SOT323-3

1

PR211 10K_0402_1%

8 5 6

2

B

+3VS

P

PR214 10K_0402_1% 1 2

+3VALW

PR210 100K_0402_1% PR213 5.1M_0402_5% 1

G

PR212 649K_0402_1%

1

2

2

VMB2

PC204 0.01U_0402_25V7K

1

VS

PJ201 @ JUMP_43X39 1 1 2 2

+VSBP

S

+VSB

A

A

Compal Secret Data

Security Classification Issued Date

2010/01/25

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. PWR-BATTERY CONN/OTP

Size Document Number Custom

Rev 0.1

PIWG1/G2(LA-6751P/LA-6753P)

Date:

Friday, November 26, 2010

Sheet 1

46

of

54

5

4

3

P3 P2

B

CSOP

21

6251_ICOMP

5

ICOMP

CSIN

20

6251_VCOMP

6

VCOMP

CSIP

19

7

ICM

PHASE

18

2

2ACOFF-1

2 CSOP

2

CELLS

4

ACPRN

1

1 D

S

2 G

PL301 10U_LF919AS-100M-P3_4.5A_20% 2

1

2N7002W -T/R7_SOT323-3 2 PACIN G

S

C

PR324 0.02_1206_1%

CHG 1

4

2

3

BATT+

12

ACLIM

VDDP

15

VADJ

LGATE

14

GND

PGND

13

PR328 0_0603_5% BST_CHG 1

2

PC316 0.1U_0603_25V7K BST_CHGA 2 1 4 PD304 RB751V-40_SOD323-2

6251_VDDP DL_CHG

1

2

6251_VDD

PR331 4.7_0402_5% PC321 4.7U_0805_6.3V6K

ISL6251AHAZ-T_QSOP24

PC318 10U_0805_25V6K 2 1

16

PC323 10U_0805_25V6K 2 1

BOOT

PC317 10U_0805_25V6K 2 1

CHLIM

DH_CHG

PR326 4.7_1206_5%

10

6251_VADJ 11

17

PC320 680P_0603_50V7K

9

PR332 2.2K_0402_1%

UGATE

16251_SN 2

VREF

PQ313 AO4466L_SO8

8

1

5 6 7 8

1

D

3

PC310 0.1U_0603_25V7K 2 1

CSON

2

4

6251VREF

PR333 15.4K_0402_1% 1 2

B

1

<40> CHGVADJ

4

PC306 2200P_0402_50V7K

PC305 4.7U_0805_25V6-K 1 2

1DISCHG_G-1 1

6251_CSON PC311 0.047U_0402_16V7K 6251_CSOP 1 2 PR318 20_0402_5% 6251_CSIN 2 1 PC313 PR320 20_0402_5% 0.1U_0402_16V7K 6251_CSIP 1 2 PR322 2_0402_5% LX_CHG

1

22

CSON

PQ311 @2N7002W-T/R7_SOT323-3

EN

PQ309

3

3

PC322 2 1

6251_EN

<48> PR317 20_0402_5% 1 2

2200P_0402_50V7K

ACPRN

1 2 6251VREF PC315 6251_CHLIM 0.1U_0402_16V7K PR329 21K_0402_1% 1 2 6251_ACLIM

Connect to EC A/D Pin.

PD303 1SS355_SOD323-2 2

1

PR316 @ 100K_0402_5% 1 2

23

3

ACSET ACPRN

PQ310 AO4466L_SO8

2

2

1 PR330 100K_0402_1%

PR309 200K_0402_1%

2

5 6 7 8

ACSETIN

2

3

S

IREF

2

3

2 1

D

2N7002KW_SOT323-3

PQ314 2 G

<40>

PR327 154K_0402_1% 2 1

2 1 PR307 @ 191K_0402_1%

PC309 0.1U_0603_25V7K 6251_DCIN 2 1

1 26251_ICM PR323 100_0402_1%

ADP_I

1

24

2

<40,46>

PR343 0_0402_5%

<46> BATT_OUT

10K_0402_1% 2

2

DCIN

1

ACOFF

PR325 1 2ACOFF-1 2 10K_0402_5%

2

VDD

0.01U_0402_25V7K

1

<40,45>

PC314 PR321 1 26251_VCOMP-1 1

PC319 0.01U_0402_25V7K 2 1

PQ312 DTC115EUA_SC70-3

6800P_0402_25V7K 2

PQ306 DTC115EUA_SC70-3

3 2 1

ACON

PC312 1

PD302 1SS355_SOD323-2

PC307 1000P_0402_25V8J

1

4

<45>

PQ307B 2N7002KDW -2N_SOT363-6

5

PR308 10K_0402_1%

3 2 1

1 PR315 2

3

PU301

CELLS

PR319 47K_0402_1% 1 2

PACIN

PACIN

1

<45>

VIN

2

1 12

1 2 P2-2

1

3

C

BATT_OUT <46>

D

PR305 47K_0402_1% 1 2

BATT_ON

PR314 150K_0402_1%

2 G

PQ308 2N7002KW _SOT323-3

PR312 14.3K_0402_1%

2

3 1

PR313 10K_0402_1% D

S

PR311 10_1206_5%

8 7 6 5

DISCHG_G

ACSETIN

1

PR310 0_0402_5% FSTCHG 2 1

<40> FSTCHG

6 PQ307A 2N7002KDW -2N_SOT363-6

1 1

6251_VDD

DTC115EUA_SC70-3

2

PD301 RB751V-40_SOD323-2

1 2 3

2

PQ305

PQ317A @ 2N7002KDW -2N_SOT363-6

PC308 2.2U_0603_6.3V6K 1 2

P2-1

100K_0402_1%

2

4

1

2

1 BATT_ON

191K_0402_1%

BATT_OUT <46>

5

PreCHG 1

VIN

PC304 4.7U_0805_25V6-K 1 2

1

PQ317B @ 2N7002KDW -2N_SOT363-6

2

2

2 1 3

1 2 6

1

CSIN CSIP

PQ303 AO4407A_SO8

PC303 4.7U_0805_25V6-K 1 2

3

CHG_B+

2

1

2

1

1

4

PR303 @47K_0402_1%

1

2

PC301 0.1U_0603_25V7K 2 1 PR304 200K_0402_1%

2

3

DTA144EUA_SC70-3

VIN

1

5600P_0402_50V7K

2

1 PR301 47K_0402_1%

D

PC325 1 2

PL302 1.2UH_1231AS-H-1R2N=P3_2.9A_30%

1

PQ304

PR302 0.020_1206_1%

8 7 6 5

PR306

1 2 3

4

1 2 3

4

8 7 6 5

PC302 @ 0.1U_0603_25V7K

VIN

1

65W:0.020 90W:0.015

PQ302 SI4459_SO8

PC324 @ 10U_0805_25V6K 2 1

PQ301 AO4407A_SO8

2

B+

PR334 31.6K_0402_1%

<48>

VCHLIM need over 95mV

ACPRN

2

2

1 3

1 6

CELLS PACIN

PR340 0_0402_5% PR342

2

2

DTC115EUA_SC70-3

2

1 PR341 @ 0_0402_5%

<40> BATT_SEL_EC

14.3K_0402_1% PQ315A @ 2N7002KDW -2N_SOT363-6

3

PQ316

5 4

IREF=0.254V~3.048V

<16,24,40>

1

IREF=1.016*Icharge

PR335 PR336 @ 100K_0402_1%@ 100K_0402_1% ACIN

1

CC=0.25A~3A

PR338 10K_0402_1%

PR337 47K_0402_1%

CP mode for 90W adapter Vaclim=2.39*(3.9K/(3.9K+25.5K))=0.0.3544V Iinput=(1/0.015)((0.05*Vaclim)/2.39+0.05) where Vaclim=0.3544V, Iinput=3.827A

PR339 10K_0402_1% 1 2

3cell : GND 4cell : VDD

6251_VDD

2

3.2935V

1

4.35V

6251_VDD

2

1.882V

1

4.2V

6251_VDD

1

0V

4V

CP mode for 65W adapter Vaclim=2.39*(2.2K/(2.2K+21K))=0.2515V Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05) where Vaclim=0.2515V, Iinput=2.76A

2

CHGVADJ

2

Vcell

1 2

CHGVADJ=(Vcell-4)/0.10627

PQ315B @ 2N7002KDW -2N_SOT363-6

A

A

2010/01/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/01/13

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Title

CHARGER Size

Document Number

Rev 0.2

PIWG1/G2(LA-6751P/LA-6753P) Date:

Sheet

Friday, November 26, 2010 1

47

of

54

5

4

3

2

1

Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO

2VREF_8205

PJ401

2

+3VALW P

2

1

1

+3VALW

PC402 1U_0603_10V6K

@ JUMP_43X118

1

D

PJ402

2

+5VALW P

2

D

@

RT8205_B+ PJ403

PR404 20K_0402_1% 1 2

1

+5VALW

RT8205_B+

10

UGATE2

UGATE1

21

UG_5V

LX_3V

11

PHASE2

PHASE1

20

LX_5V

LG_3V

12

LGATE2

LGATE1

19

LG_5V

1 2 3 2 1

PC418 1U_0603_10V6K 2 1

2 PC420 0.1U_0603_25V7K

4

PC419 4.7U_0805_10V6K

1 2 RT8205_B+

1

3

VL

2VREF_8205

5

1

2

2

AO4712_SO8 PQ404

Typ: 175mA

+5VALWP

1 +

PC416

1

4

PR410 4.7_1206_5%

5 6 7 8

RT8205EGQW _W QFN24_4X4

PC417 680P_0603_50V7K

NC

PL402 4.7UH +-20% PCMC063T-4R7MN 5.5A 1 2

18

VIN

VREG5 17

16

GND

EN

3 2 1

UG_3V

13

5 6 7 8

PC411 0.1U_0603_25V7K 2 1

PC410 2200P_0402_50V7K 2 1

PC409 4.7U_0805_25V6-K 2 1

1

3

4

2 FB1

REF

FB2

PR408 PC413 0_0603_5% 0.1U_0603_25V7K BST_5V 1 2 1 2

PQ405B 2N7002KDW -2N_SOT363-6

PQ405A 2N7002KDW -2N_SOT363-6

PC408 4.7U_0805_25V6-K 2 1

ENTRIP1

ENTRIP2

6

5

22

SKIPSEL

8 7 6 5

ENTRIP2

6

ENTRIP1

PR414 0_0402_5% 2 1

23

BOOT1

B+

B

<45,46> MAINPWON

PGOOD

BOOT2

1

2

C

<46>

VREG3

PR412 499K_0402_1% 1 2

1 2 3

680P_0603_50V7K 2 1

PC415

150U_B2_6.3VM_R45M

SPOK

9

4

+

PC414

24

8

VFB=2.0V

PQ402 AO4466L_SO8

4 VO1

BST_3V

PR411 @ 0_0402_5% MAINPW ON 2 1

2

1

PQ403 AO4712_SO8

PR413 100K_0402_1%

PR409

+3VALWP

4.7_1206_5% 2 1

PL401 4.7UH +-20% PCMC063T-4R7MN 5.5A 1 2

VO2

15

1 2 3

PR407 2 1 2 0_0603_5% PC412 0.1U_0603_25V7K

1

7

PR406 154K_0402_1% 2

ENTRIP1

4

TONSEL

P PAD

ENTRIP2

25

1

14

AO4466L_SO8

PU401

1

PQ401

PR405 110K_0402_1% 1 2

2

PC407 4.7U_0805_10V6K

8 7 6 5

PC406 2200P_0402_50V7K 2 1

C

PR403 20K_0402_1% 1 2

+3VLP

1

1

PC405 4.7U_0805_25V6-K 2 1

2

@ JUMP_43X118

PC404 4.7U_0805_25V6-K 2 1

2

PR402 30K_0402_1% 1 2

1

Typ: 175mA PC403 0.1U_0603_25V7K 2 1

PC401 0.1U_0603_25V7K 2 1

B+

PR401 13K_0402_1% 1 2

2

JUMP_43X118

150U_B2_6.3VM_R45M 2

B

+3.3VALWP OCP(min)=5.81A +5VALWP OCP(min)=8.44A

PR415 100K_0402_1% 2 1

2

3

A

5

Compal Secret Data

Security Classification 2010/01/25

Issued Date

3

PQ408 DTC115EUA_SC70-3

PQ407 DTC115EUA_SC70-3

2

1

2

PR416 100K_0402_1%

PC421 2.2U_0603_10V7K

EC_ON

1

VS

2

S

2 1 PR417 40.2K_0402_1%

1

A

<40,43>

D

2 G

PQ406 2N7002W-T/R7_SOT323-3

PR418 200K_0402_1% 2 1

1

ACPRN

3

1

VL

Deciphered Date

2010/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4

3

2

Title

Compal Electronics, Inc. 3VALWP/5VALWP

Size Document Number Custom

Rev 0.1

PIWG1/G2(LA-6751P/LA-6753P)

Date:

Friday, November 26, 2010

Sheet 1

48

of

54

A

B

C

D

1

1

PJ505

PR501 0_0402_5% 1 2

2

1

1

B+ @ PC504 680P_0402_50V7K

2

JUMP_43X118

+

2 4

2

RT8209BGQW _W QFN14_3P5X3P5

2

PC510 4.7U_0603_6.3V6K

PC507 4.7U_0805_10V6K

2

PR509 1

PC506 220U_6.3V_M 2

DL_1.5V

1

9

1

LGATE

1

14 PGND

7

10

1

PC508 1000P_0603_50V7K

PGOOD

VDDP

+1.5VP

PR506 4.7_1206_5%

PQ502 AO4456_SO8

+5VALW

2

6

LX_1.5V

11

5 6 7 8

FB

12

CS

3 2 1

5

PHASE

VFB=0.75V

PL502 1UH_PCMC063T-1R0MN_11A_20% 1 2

1

VDD

DH_1.5V

2

4

UGATE

13

PR504 PC505 0_0603_5% 0.1U_0603_25V7K 1 2BST_1.5V-1 1 2

PR508 9.76K_0402_1%

VOUT

BST_1.5V

BOOT

TON

3

@ PC509 47P_0402_50V8J 1 2

1

NC

1

2

8

PR507 100_0603_5% 1 2

+5VALW

EN/DEM

PC501 @ .1U_0402_16V7K

2

15

PU501

GND

2

1

1

PR505 47K_0402_5%

2

3 2 1

<40,44> SYSON

4

PC503 4.7U_0805_25V6-K 2 1

PQ501 AO4406AL 1N SO8 PR503 267K_0402_1% 1 2

PC502 4.7U_0805_25V6-K 2 1

5 6 7 8

2 @

1

1.5_51117_B+

+1.5VP OCP(min)=15.6A 2

1.8VSP max current=4A 1

10K_0402_1%

2

PR510 10K_0402_1% PJ501 2

2

@

1

1

JUMP_43X118 PJ502

+1.5VP

2

2

@

+1.5V 1

1

JUMP_43X118

3

3

1 2

1

2

1

+1.8VS

1

JUMP_43X118

PC515 22U_0805_6.3VAM

2 SY8033BDBC_DFN10_3X3

2

FB=0.6Volt

PR512 30K_0402_1%

2 @

FB_1.8V

1

1

2

PR514 1M_0402_5%

6

PC514 22U_0805_6.3VAM

NC

TP

PR513 100K_0402_1%

7

11

EN_1.8V

1

2

PC516 0.1U_0402_10V7K

1

2

<10,26,40,44,51,52> SUSP#

FB

PJ504 +1.8VSP

+1.8VSP PC512 68P_0402_50V8J 2 1

EN

1

5

LX

3

LX_1.8V

2

SVIN

2

1

PVIN

8

2

PC511 22U_0805_6.3VAM

9

LX

1 2

JUMP_43X118

PVIN

PC513 PR511 680P_0603_50V7K 4.7_1206_5%

10

NC

1

1

1

1

@

2

PG

2

PL503 1UH_PCMC063T-1R0MN_11A_20% 1 2

4

PU502 PJ503

+5VALW

PR515 14.7K_0402_1%

4

2

4

Compal Secret Data

Security Classification Issued Date

2010/01/25

Deciphered Date

2010/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

Title

Compal Electronics, Inc. PWR-+1.5VP/+1.8VSP

Size Document Number Custom

Rev 0.1

PIWG1/G2(LA-6751P/LA-6753P)

Date:

Friday, November 26, 2010 D

Sheet

49

of

54

5

4

3

2

1

D

D

B+ @ PJ601

1 2

2

2

1

1

JUMP_43X118

PC603 4.7U_0805_25V6-K

1 2

5 6 7 8 PR602 280K_0402_1% 1 2

C

PQ601 AO4466L_SO8

PC602 4.7U_0805_25V6-K

51117_VCCSAP_B+

4

C

BST_VCCSAP

1

0_0402_5% PR611 2 1

9

<40>

2

PJ602 PR607 0_0402_5%

4

RT8209BGQW_WQFN14_3P5X3P5

SA_PGOOD

2 1

LG_VCCSAP

PC605 220U_6.3V_M

2

PC606 470P_0603_50V8J

+VCCSAP PR608 1 0_0402_5%

1

LGATE

1

VDDP

PGOOD

PR610 13K_0402_1%

FB

7

6

PQ602 AO4712_SO8

10

+

PR605 4.7_1206_5%

+5VALW

11

2

PC608 4.7U_0603_6.3V6K

2

1

1 2 PR609 10K_0402_5%

+3VS

CS

PGND

PR606 100_0603_1% 1 2

+5VALW

VDD

8

5

GND

4

+VCCSAP

1

LX_VCCSAP

2

PHASE

12

PC607 4.7U_0805_10V6K

2

VSSSA_SENSE

2 @

<10>

2

1

+VCCSA

1

JUMP_43X118

3 2 1

VOUT

13

1

BOOT

UGATE

PL601 2.2UH_PCMC063T-2R2MN_8A_20% 1 2

5 6 7 8

14

1

TON

PC604 0.1U_0603_25V7K BST_VCCSAP-1 1 2

2

3

PR603 0_0603_5% 1 2 UG_VCCSAP

2

2

2 PC601 @ 0.1U_0402_16V7K

NC

1

1

EN/DEM

PU601

@ PR604 47K_0402_5%

15

EN_VCCSAP PR601 0_0402_5% 1 2

<51> VCCPPWRGOOD

3 2 1

+VCCSAP OCP(min)=6.28A

PR612 2K_0402_1% 1 2

PR613 1

2

VFB=0.75V

VCCSA_SENSE

<10>

10_0402_5%

B

B

1

PR616 10K_0402_5%

2 3

S

PMBT2222A_SOT23-3 1

PR617 10K_0402_5% 2 1

1

D

PQ603 2N7002W-T/R7_SOT323-3 2 G

PQ604

1

1

2

1

PR615 15K_0402_1%

PR614 30K_0402_1%

2

1

+3VS

1

PR619 0_0402_5% 2 1

3

PR618 @ 100K_0402_5%

VCCSA_SEL

<10>

PR620 @ 10K_0402_5% 2

2

2

2 PC609 @ 4700P_0402_25V7K

VID[0] 0 0 1 1

VID[1] 0 1 1 1

VCCSA Vout 0.9 V 0.8 V 0.725V 0.675V

Require on 2011/ 2012 Required Yes/Yes Yes/Yes No/Yes No/Yes

A

A

Note:Use VCCSA_SEL to switch High & Low Level for VID[1] (ie. VCCSA_SEL) due to the VID[0] is don't care for this setting.

Compal Secret Data

Security Classification

Issued Date

2010/01/25

Deciphered Date

2010/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title Size C Date:

5

4

3

2

Compal Electronics, Inc. PWR +VCCSAP Document Number

Rev 0.1

PIWG1/G2(LA-6751P/LA-6753P) Friday, November 26, 2010

Sheet 1

50

of

54

5

4

3

2

1

PJ701 JUMP_43X118 @

D

2

2

D

PU701

6

NC

5

+3VALW

VREF

NC

7

4

VOUT

NC

8

TP

9

PJ702

2

+0.75VSP

@

1

1

+0.75VS

1U_0603_10V6K PJ703

2

2

1

1

@

+0.75VSP

JUMP_43X118 PJ704 2 2 1 1

+1.05VS_VCCPP

PC716 10U_0603_6.3V6M

1

2

JUMP_43X118

PC702

2

3

2

2

PR703

PC705 10U_0603_6.3V6M 2 1

PC703 0.1U_0402_16V7K 2 1

1

2 G

1K_0402_1%

1

S

VCNTL

G2992F1U_SO8

2

PC704 0.1U_0402_16V7K

3

1

<6,10,44> SUSP

D

GND

2

1

PR701 1K_0402_1%

PQ701 2N7002W -T/R7_SOT323-3 PR702 20K_0402_1% 1 2

VIN

2 1

2

PC701 4.7U_0805_6.3V6K

1

1

1

1

+1.5V

@

+1.05VS

JUMP_43X118

C

C

+1.05VS_VCCPP OCP(min)=20.75A

PJ705

PR705 120K_0402_1% 1 2

1

B+

1

B+ @ PC708 680P_0402_50V7K

1 +

2

3 2 1

RT8209BGQW _W QFN14_3P5X3P5

PC714 4.7U_0805_10V6K

2

1 2 4 2

PGND

DL_1.05VS_VCCP

PR708 0_0603_5%

PC711 330U_X_2VM_R6M

9

1

LGATE

B

1

10

PC712 1000P_0603_50V7K

NC

BOOT

VDDP

+1.05VS_VCCPP

1

PR707 4.7_1206_5%

PQ703 AO4456_SO8

+5VALW

2

2

11

8

@ PC715 47P_0402_50V8J 1 2

PC713 4.7U_0603_6.3V6K

CS

VFB=0.75V

PL702 1.0UH +-20% PCMC104T-1R0MN 20A

5 6 7 8

PGOOD

LX_1.05VS_VCCP

3 2 1

6

PHASE

12

1

FB

DH_1.05VS_VCCP

2

5

13

1

VDD

PC710 0.1U_0603_25V7K 1 2

2

UGATE

PR710 13.7K_0402_1%

VOUT

4

PR706 0_0603_5% BST_1.05VS_VCCP 1 2

14

1

3

7

PR709 100_0603_5% 1 2

TON

EN/DEM

2

GND

PU702

15

1 PC709 .1U_0402_16V7K

1

+5VALW

2

2 PR716

1

B

1

4 @ 10K_0402_1%

6,40,44,49,52> SUSP#

2

JUMP_43X118

PC717 100U_25V_M

PQ702 AO4406AL 1N SO8

@

2

PR704 267K_0402_1% 1 2

2

PC706 4.7U_0805_25V6-K 2 1 PC707 4.7U_0805_25V6-K 2 1

5 6 7 8

1.05VS_B+

1 +

2

PR711 4.02K_0402_1% 1 2 PR714 10_0402_5% 2 1

1 <50> PR712 10K_0402_1%

PR713

1

2

VCCIO_SENSE

<9>

+3VS A

10K_0402_1%

2

2

A

VCCPPW RGOOD

1

PR715 @ 10K_0402_1%

Compal Secret Data

Security Classification 2010/01/25

Issued Date

Deciphered Date

2010/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. PWR +1.05VS_VCCPP/+0.75VSP

Size Document Number Custom

Rev 0.1

PIWG1/G2(LA-6751P/LA-6753P)

Date:

Friday, November 26, 2010

Sheet 1

51

of

54

5

4

PD804 RB751V-40_SOD323-2 1 2

PC803 4.7U_0805_25V6-K 2 1

PL801 0.88UH +-20% PCMC104T-R88MN 20A 1 2

RT8209BGQW _W QFN14_3P5X3P5

PR830 @ 10K_0402_1%

PC810 4.7U_0805_6.3V6K

1

PC809 10U_0805_6.3V6M

2

1

PC808 10U_0805_6.3V6M

2

+ 2

1

1

PC807 10U_0805_6.3V6M

1VGA_SNB 2 2

4

+VGA_CORE

2

5

LG_VGA

9

LGATE

B+

PC806 330U_D2_2.5VY_R15M

10

+5VALW

1

@ JUMP_43X118

1

VDDP

VGA_TRIP 1 2 PR808 9.1K_0402_1%

PQ801 TPCA8065-H 1N PPAK56

3 2 1

14 BOOT

NC

1

PGOOD

SW _VGA

11

1

6

12

CS

1

PC811 PR806 680P_0603_50V7K @ 4.7_1206_5%

PC812 @ 47P_0402_50V8J 1 2

FB

PHASE

3 2 1

<25> VGA_CORE_PG C

5

UG_VGA

2

2 PR829 1 0_0402_5%

VDD

7

+3VS

PC805 4.7U_0603_6.3V6K

VOUT

4

2

2

3

13

UGATE

PGND

VGA_FB PR834 2 1 10K_0402_1%

TON

2

C

@ 1

1

VGA_V5FILT

2

8

PR807 100_0603_1% 1 2

+5VALW

4

0.1U_0603_25V7K PU801

15

PX4.0 PR801 120K PR804 @

PR805 PC804 0_0603_5% BST_VGA 1 2BST_VGA-1 1 2

EN/DEM

2

PR831 @ 120K_0402_1%

GND

PR832

PC801 0.1U_0402_16V7K

@ 10K_0402_1%

1

1

1

2

2

SUSP#

PD801 1SS355_SOD323-2 2 +5VALW

1

2

PQ802 TPCA8059-H 1N PPAK56-8

VGA_EN

2

120K_0402_1% <10,26,40,44,49,51>

PJ801 VGA_IN 5

PR804 1

1

D

PR803 205K_0402_1% 1 2

VGA_TON

PC802 4.7U_0805_25V6-K 2 1

2 PR802 @ 10K_0402_5% 1

PD805 RB751V-40_SOD323-2 1 2

<15,18,25,26> PE_GPIO1

2

+3VS

PR801 @ 0_0402_5% 2 1

<25,26> PX_MODE

D

3

1

2 PR809 2K_0402_1% 1 2 PR810 10K_0402_1%

1GVID1-1 2

GVID1-2

PQ803A 2N7002KDW -2N_SOT363-6

PR815 8.66K_0402_1%

1

1

VGA_PWRSEL1

GPU_VID1

2

1

0.9V

1

0

0.95V

PJ804 2

1.12 V

PQ804A 2 2N7002KDW -2N_SOT363-6 PC814 0.022U_0402_16V7K

+5VALW

1

PD802

2

A

2

6

1 3

FB

2

VIN

9

+VGA_PCIEP

PR826 1.15K_0402_1%

1

VOUT

1

5 4 PC818 2 1

EN

VIN VOUT

APL5912-KAC-TRL_SO8

PC817 0.01U_0402_25V7K

22U_0805_6.3V6M

1

@ RB751V-40_SOD323-2

8

PR827 @ 47K_0402_5%

PC816 4.7U_0805_6.3V6K

1

PD803

POK

VCNTL

2

PR825 @ 0_0402_5% 1 2

1

SUSP#

B

PJ805 JUMP_43X79 @

2

SUSP#

7

PC819 0.1U_0603_25V7K 2 1

<10,26,40,44,49,51>

PU802

GND

2

PR823 @ 0_0402_5% PR824 47K_0402_5% 1 2

PE_GPIO1

+VGA_PCIE

1

RB751V-40_SOD323-2 1 2

<15,18,25,26> PE_GPIO1

2

PC815 1U_0402_6.3V6K

1

2

1

+5VALW

5

1

1

2

2

1

PR820 @ 10K_0402_5%

2

@ JUMP_43X118

+1.5V

2

2 PR819 10K_0402_1%

0

1

1GVID0-1

0

2

6

+VGA_PCIEP

1

10K_0402_1%

PR818 1

2 PR822 3K_0402_5%

1

4

2 1 PR821 10K_0402_1%

1

<24> GPU_VID0

3

PQ804B 2N7002KDW -2N_SOT363-6

Robson XT Core Voltage Level

GVID0-2

2

B

+3VALW 1

PR817 3K_0402_5%

2

2 1 5 PR816 10K_0402_1%

4

<24> GPU_VID1

1

2

PC813 0.022U_0402_16V7K

VGA_PWRSEL0

GPU_VID0

2

3

PR814 @ 10K_0402_5%

PR811 30K_0402_1% 2

1

PR813 10K_0402_1% 2

PQ803B 2N7002KDW -2N_SOT363-6

6

1

1

1 PR812 2

10K_0402_1%

+3VALW

VGA_PCIE

1.0V

1.1 V

PR828

4.53K

3K

A

2

PR828 4.53K_0402_1%

2009/01/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/01/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title Size

PWR +VGA_CORE/PCIE Document Number

Rev 0.1

PIWG1/G2(LA-6751P/LA-6753P) Date:

Friday, November 26, 2010

Sheet 1

52

of

54

2 PR904 27.4K_0402_1%

PHASE2

PR928

1

2

+5VS

33 0_0402_5% LGATE2

32

C

PR931

31

1

2 0_0402_5%

PWM3

30

LGATE1

29 28 27

PHASE1

26

UGATE1

25

BOOT1

PC931 4.7U_0805_25V6-K 2 1

PC930 4.7U_0805_25V6-K 2 1 680P_0603_50V7K

PR946

PC939 2 1 2

TPCA8059-H 1N PPAK56-8

5

1 4.7_1206_5%

3 2 1

10K_0402_1% PR947 1

2

10K_0402_1% PR948 1ISEN1

3.65K_0402_1% PR951 1

2

ISEN2 2

VSUM+ 2

B

1_0402_5% PR952 1 VSUM-

PC949 4.7U_0805_25V6-K 2 1

PL905 .36UH 20% PCMC104T-R36MN1R105 30A 4 1 +CPU_CORE

1 2 1 PR962 PC954 4.7_1206_5% 680P_0603_50V7K

4

@

ISEN1

10K_0402_1% PR963 2 1

3

2

10K_0402_1% PR964 1 ISEN2

2

1_0402_5% PR966 1

2

3.65K_0402_1% PR965 1

VSUM+ 2

VSUM-

A

2

0.22U_0603_10V7K 4

PQ912

@ TPCA8059-H 1N PPAK56-8

5

PQ911

3 2 1

PR961 2.2_0603_5% PC953 2 1 2 1

3 2 1

Ipeak=26A , Imax=18.2A , 1.2Ipeak=31.2A Rdson=3.6~4.5m ohm DCR=1.1m ohm HW output cap: (1)22U_0805_6.3V *12 (2)470U_D2_2V *2(ESR=4.5m ohm)

@

Compal Secret Data

Security Classification Issued Date

4

5

PHASE1

LGATE1

5

PQ910

4

+VGFX_COREP

*OCP setting value=37A

2

@

PC948 4.7U_0805_25V6-K 2 1

UGATE1

A

*OCP setting value=71.5A

3 2 1

5

3 2 1 VSUM-

*Iccmax in Turbo Mode for SV (35W) is 53A

Icc-max=53A Rdson=3.6~4.5m ohm DCR=1.1m ohm HW output cap: (1)10U_0805_4V *10 (2)22U_0805_6.3V *15 (3)470U_D2_2V *4(ESR=4.5m ohm)

@

3

CPU_B+ PH904 10K_0402_5% ERTJ0ER103J

BOOT1

+CPU_CORE

4

TPCA8065-H 1N PPAK56

PR958 2 1 1.47K_0402_1% PC951 PR959 2 1 2 1 @ 100_0402_1% @ 330P_0402_50V7K

PQ909

@ TPCA8059-H 1N PPAK56-8

PC936

0.22U_0603_25V7K 2 1

VSUM+

PL904 .36UH 20% PCMC104T-R36MN1R105 30A 4 1 +CPU_CORE

3 2 1

2 1 @ 10_0402_1%

4

TPCA8059-H 1N PPAK56-8

PC950 1000P_0402_50V7K

PC934 0.22U_0603_10V7K

5

PR960

1

1

LGATE2

.1U_0402_16V7K

2

5

TPCA8065-H 1N PPAK56

1 PC947 2 1 330P_0402_50V7K

<9> VCCSENSE <9> VSSSENSE

PC935 1

2

ISEN1

PR956 2 1 @ 10_0402_1%

PQ908

1 2

PR953 2.61K_0402_1% 1 2 1

PR955 1 3.32K_0402_1%

1 0.22U_0402_6.3V6K PC942 2 1 0.22U_0402_6.3V6K

BOOT2 2

2

2

PHASE2 2.2_0603_5% PR944

+5VS

PC952 2 1

1

PC941 2

1

PR957 2 1 11K_0402_1%

PR954

(Ipeak=54A)

1_0603_5%

PC955 @ 0.068U_0402_16V7K 2 1

1

PC943 1 2

150P_0402_50V8J 316K_0402_1% 2 1 +CPU_CORE PR916 @ 2K_0402_1%

VSUM-

2

PC945 0.068U_0402_16V7K 2 1

2

PC923 @ 680P_0402_50V7K

PC940 1

470P_0402_50V7K

@ 499K_0402_1%

2

2

1U_0603_10V6K

PR949 2 1 499_0402_1%

1

PC944 0.22U 10V K X7R 0603 2 1

2

330P_0402_50V7K

2

PC946 2 1

PR950

PC937 @ 2 1

CPU_B+

PR945

1 ISEN2

0.22U_0402_6.3V6K PC938 10P_0402_50V8J

2 0_0603_5%

PQ907

4

PR942 1.69K_0402_1%

2

1 PC933 22P_0402_50V8J

ISEN3

PC932 2 1

1000P_0402_50V7K

8.06K_0402_1%

1 2

PR943

PR941

2

100_0402_1% @ PR922 2

CPU_B+

1 27.4K_0402_1%

B

1

@ 0.01U_0402_16V7K

ISPG UGATE2

UGATE2

change from 43P to 47P for shortage problem 2010-03-15

5

37 LGG

35 34

2

2 PR940

1

PC927 2.2U_0603_10V6K 2 1

39

38

UGG

PHG PROG1

VIN

BOOT2

PU901

24

23

36

3.83K_0402_1% 470KB_0402_5%_ERTJ0EV474J PC928 47P_0402_50V8J

3 2 1

5

3 2 1

LGATEG

PHASEG

UGATEG

1

BOOTG

40

41 PROG2

BOOTG VDD

BOOT1

22

ISUMP

UG1

21

VW

.1U_0402_16V7K PC919 1 2

2 PR924 1 590_0402_1%

2

ISNG

42

43 ISNG

NTCG

45

44 ISPG

46

47 FBG

RTNG

GND

VSENG

PH1

NTC

13

1 2

VSSP1

VR_HOT#

PH903

1

COMPG

IMON

PC929 @ 470P_0402_50V7K 2 1

2

LG1

ISL95831CRZ-T_TQFN48_6X6

ISUMN

12

PWM3

PGOOD

RTN

11

VR_ON

20

9

VDDP

19

8

10

1

TPCA8057-H 1N PPAK56-8

PC908 2 1 ISPG

7

SCLK

VSEN

2

1 PR917 2 11K_0402_1% 1 2 PC918 .1U_0402_16V7K

D

+

2

2 PR925 1ISNG @ 0_0402_5%

LG2

18

6

ALERT#

ISEN1

SVID_SCLK

0_0402_5%

PR939

PH902 10K_0402_5% ERTJ0ER103J 1 PR914 21 2 7.5K_0402_1%

+5VS

VSSP2

17

5

PR908 1_0402_5%

PC921 1 2

BOOT2

SDA

ISEN2

SVID_ALERT#

48

49 4

2

@

4

+VGFX_CORE

1 3

@

PH2

ISEN3/ FB2

2

1

PC926 0.047U_0603_16V7K

SVID_SDA

For shortage changed

PR938 1 2 499_0402_1% +1.05VS_VCCPP @

4

PQ903

PR919 @ 16.5K_0402_1%

UG2

16

1 PR933

VR_ON

LGATEG

PR913

PGOODG

15

<16>

<40,46> VR_HOT#

VSS_AXG_SENSE <10>

1000P_0402_50V7K

PQ902

0.22U_0603_10V7K

VCC_AXG_SENSE <10>

IMONG

FB

VGATE

2 1 PR936 29.4K_0402_1%

3

VWG

COMP

GFX_CORE_PWRGD

<40> IMVP_IMON

2

2

C

VSSSENSE

1

14

PR927

<9>

2 PR906 2.2_0603_5%

2

330P_0402_50V7K PC909 2 1

NTCG

2 1 PR967 @ 43_0402_1%

2 PR920 1 130_0402_1%

<9> VR_SVID_CLK

1.91K_0402_1%

BOOTG

PC907 1 2 1

B+

PL901 HCB4532KF-800T90_1812

PL902 .36UH 20% PCMC104T-R36MN1R105 30A 4 1

PHASEG

+3VS

<9> VR_SVID_ALRT#

1

4

2 1 10_0402_1%

+1.05VS_VCCPP

For shortage changed

UGATEG

2 1 10_0402_1%

PC906 1

2 1 PR912 2.55K_0402_1%

<9> VR_SVID_DAT

+3VS

PC912 680P_0402_50V7K 2 1

2 1 422_0402_1%

PC920 @.1U_0402_16V7K 1 2

PC916 2 1

PR918 18.2K_0402_1% 2 1

0.047U_0603_16V7K

2 <10> VSS_AXG_SENSE

+

2

+VGFX_CORE

PR909

PC913 150P_0402_50V8J 2 1 2 1 PR911 475K_0402_1%

2

1

PR905

2 1 PR921 54.9_0402_1% PR926 2 1 1.91K_0402_1%

PR901 @ 499K_0402_1%

+

1

330P_0402_50V7K

2

1

PC901 1000P_0402_50V7K

PR903 8.06K_0402_1% 1

2 1

PC911 39P_0402_50V7K 2 1

Parallel and tune length

1

2

PC910 470U_X_2VM_R4.5M

1

470KB_0402_5%_ERTJ0EV474J

PC904 4.7U_0805_25V6-K 2 1

PH901

2

@ 470P_0402_50V7K @ 4.99K_0402_1%

TPCA8065-H 1N PPAK56 PC903 4.7U_0805_25V6-K 2 1

PQ901

D

GFXVR_IMON

B+

1

@ TPCA8057-H 1N PPAK56-8 PC915 2 1 2PR907 1 4.7_1206_5% 680P_0603_50V7K 2 1 PR910 10K_0402_1%

1

NTCG

3 2 1

2

PR902 3.83K_0402_1% 2 1

PC905 100U_25V_M

PR915

1

CPU_B+

5

2 PC917 2 1

2

2 1 @ PC922 470P_0402_50V7K

@ 470P_0402_50V7K 1

1

3

PC902

2

4

PC914 100U_25V_M

5

Alert# PU resister need close CPU, so the PU resister in HW schematic. but DAT and CLK need close PWM-IC, so the PU resister in POWER schematic.

2010/01/25

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3

2

Title

Compal Electronics, Inc. PWR +CPU_CORE/+VGFX_CORE

Size Document Number Custom

Rev 0.1

PIWG1/G2(LA-6751P/LA-6753P)

Date:

Friday, November 26, 2010

Sheet 1

53

of

54

5

4

3

2

9HUVLRQFKDQJHOLVW3,5/LVW ,WHP

5HDVRQIRUFKDQJH

3*

To reduce charger ripple

HW request for power sequence

3DJHRI IRU3:5

0RGLI\/LVW

'DWH

3KDVH

47

Add PC323

51

Change +VGA_PCIE enable signal from PX_MODE to PE_GPIO1 PR804:120K PR831,PR801,PR825 UN-POP PR824:47K PC819:0.2uF

2010.08.15

D

1

2010.08.15

DVT D

DVT

Change Vboot setting

52

Change PR942 as 4.32K

2010.08.15

DVT

Change OCP setting

52

Change PR958 as 1.47K

2010.08.15

DVT

Add PC955 for loadline adjust

52

Add PC955

2010.08.15

DVT

Reserve pull low resistor

51

Add

2010.09.29

PVT

Remove jump

51

Remove PJ802,PJ803

2010.09.29

PVT

46

Pop PR222,PR208,PH202,PR221,PQ204 Un-Pop PR223,PR203

2010.09.29

PVT

47

Remove PJ301 Add PL302 and reserve PC324

2010.09.29

PVT

PR718,PR832

C

C

Adapter protect circuit

EMI Request

B

B

A

A

2009/01/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2009/01/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

PIR (PWR) Size Document Number Custom Date:

Rev 0.1

PIWG1/G2 Sheet

Friday, November 26, 2010 1

54

of

54

5

4

3

2

1

D

D

2

A3

PU3

B5

+3VALW

A5 B7

V

B4

V

4

EC

SYSON#

V V V

+1.5V PU5

8a (DIS) VGA_ON 8

V

V

SUSP#,SUSP

V

V

B

U49 +5VS

+1.5VSDGPU U40

U20 +3VS

+1.8VSDGPU U37

U13 +1.5VS PU8 +0.75V

V

V

VCCPPWRGOOD

+3VSDGPU Q6

PU9 +1.05VS_VCCP

PU7 +VCCSA

11 VGATE

V

DGPU_PWR_EN

7

C

6

V

SYSON

CPU

V

V

V

ON/OFF

15

VGA B

+1.0VSDGPU PU28

V

B6

V

A4

PLT_RST#

14

V

C

PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# PM_SLP_A# PM_SLP_SUS#

H_CPUPWRGD

+VGA_CORE PU998

V

PBTN_OUT#

EC_ON

PCH

5

V

B7

PM_DRAM_PWRGD

V

A5

V

51ON#

PCH_RSMRST#

V V

B3

SYS_PWROK 13

PQ2

V

B+

V

B2

+3VALW_PCH +5VALW_PCH

3

2

V

B1

2

V

BATT

U14,+3VALW_PCH QH4,+5VALW_PCH

V

B+

V

V

A2

PU2

VV

VIN

V V

BATT MODE

A1

V

AC MODE

V

PCH_PWR_EN#

VGA_PWROK

8b (DIS)

U47 CK505

V

9

V

VR_ON

PU1000 +CPU_CORE

10

A

A

Compal Secret Data

Security Classification Issued Date

2010/07/12

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. Power sequence

Size Document Number Custom

Rev 0.2

LA-6751P

Date:

Friday, November 26, 2010

Sheet 1

55

of

59

5

4

3

INT_KBD Conn.

+VCC_LID

2 0_0402_5%

1

R615 1

Kill

2 100K_0402_5%

STATUS 1,2(LOW) 2,3(HI)

KSO2

C668 1

2 @ 100P_0402_50V8J

KSO1

C669 1

2 @ 100P_0402_50V8J

KSO15

C670 1

2 @ 100P_0402_50V8J

KSO7

C671 1

2 @ 100P_0402_50V8J

KSO6

C672 1

2 @ 100P_0402_50V8J

KSI2

C673 1

2 @ 100P_0402_50V8J

KSO8

C674 1

2 @ 100P_0402_50V8J

KSO5

C675 1

2 @ 100P_0402_50V8J

KSO13

C676 1

2 @ 100P_0402_50V8J

KSI3

C677 1

2 @ 100P_0402_50V8J

KSO12

C678 1

2 @ 100P_0402_50V8J

KSO14

C679 1

2 @ 100P_0402_50V8J

KSO11

C680 1

2 @ 100P_0402_50V8J

KSI7

C681 1

2 @ 100P_0402_50V8J

KSO10

C682 1

2 @ 100P_0402_50V8J

KSI6

C683 1

2 @ 100P_0402_50V8J

KSO3

C684 1

2 @ 100P_0402_50V8J

KSI5

C685 1

2 @ 100P_0402_50V8J

KSO4

C686 1

2 @ 100P_0402_50V8J

KSI4

C687 1

2 @ 100P_0402_50V8J

KSI0

C688 1

2 @ 100P_0402_50V8J

KSO9

C689 1

2 @ 100P_0402_50V8J

KSO0

C690 1

2 @ 100P_0402_50V8J

KSI1

C691 1

2 @ 100P_0402_50V8J

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15

D

26 25

GND2 GND1

24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Reserve for ESD.

1 C694 0.1U_0402_16V4Z

S-5711ACDL-M3T1S_SOT23-3

VDD

KSO[0..15] <40,57>

2

ACES_88514-2401

3

OUTPUT

2

Lid Switch

Kill Switch

2 U32

1

D

+3VALW C695 10P_0402_50V8J

100K_0402_5%

2 R616

LSSM12-P-V-T-R_3P

1

<14,57> KILL_SW #

3

3

2

2

1

1

KILL_SW#

8/23 Change LED1/LED3/LED4 P/N to SC50000A300 SW 2

LED

LED1

White

1

<40,43,57> PW R_LED#

2

2 300_0402_5%

1 R622

+5VALW

19-213A-T1D-CP2Q2HY-3T_W HITE

Orange

JKB1

LED2

BATT_LOW_LED#

1

<40,57> CHARGE_LED1#

CONN PIN define need double check

OFF ON

LID_SW # <40,57>

GND

KSO[0..15]

<40,57>

1 R614

+3VALW

ME@

KSI[0..7]

1

KSI[0..7]

2

2

2 470_0402_5%

1 R764

+3VALW

ZZZ

Left --> White Right --> Orange

+5VS

HT-191UD5_AMBER

Change design to two LED 20101005

LED5 C

C

To TP/B Conn.

0.1U_0402_16V4Z

<40,57> TP_CLK <40,57> TP_DATA

1

2

@ C697 100P_0402_50V8J

1

2

TP_CLK TP_DATA SW /L SW /R

@ C698 100P_0402_50V8J

8 7

GND GND

6 5 4 3 2 1

6 5 4 3 2 1

<40,57> CHARGE_LED0#

DAZ0GL00100

ACES_88058-060N

C696

1

BATT_CHG_LED#

White ZZZ1

ZZZ2

2 300_0402_5%

1 R765

+5VALW

19-213A-T1D-CP2Q2HY-3T_W HITE

ZZZ3

1

<34,57> W LAN_LED#

PCB

PCB

PCB

DA80000KF10

DA40000VV10

DA40000VS10

DA8@

DA4@

DA4@

LED3

D19

@

2

White

1

2

2 300_0402_5%

1 R625

+5VS

1 R626

+5VS

RB751V_SOD323

1

<42,57> BT_LED#

19-213A-T1D-CP2Q2HY-3T_W HITE

D20

@

JTP1

2

2

RB751V_SOD323

3

LED4

White

2

4

1

3

C713 0.1U_0402_16V4Z 2 1 <38,40,42,57> USB_ON#

1 2 3 USB_ON# 4

1

6 5

SMT1-05_4P

GND IN IN EN

B

USB_OC0# <18,38,57>

Right USB Conn.

APL3510BKI_SO8

1

C716 @ 1000P_0402_50V7K

+USB_VCCA

1 C714 150U_B2_6.3VM_R35M

2 0.01U_0402_16V7K 2 0.01U_0402_16V7K

ODD_DETECT#

SATA_DTX_IRX_N2 SATA_DTX_IRX_P2

R710 1

2 0_0402_5%

+5V_ODD ODD_DA#

<18,40,57> ODD_DA#

+3VS

A

1 R554 R555 1

2 0_0402_5%

2 10K_0402_5%

8/13 update JODD1 symbol

GND A+ AGND BB+ GND

2

8 9 10 11 12 13

DP +5V +5V MD GND GND

1 2 3 4 G5 G6

ACES_85205-04001 ME@

8/27 change to stuff USB20_N0_C

W CM-2012-900T_4P USB20_N0

4

4

3

3

USB20_N0_C

USB20_P0

1

1 L66

2

2

USB20_P0_C

USB20_P0_C

GND GND

15 14

ALLTO_C18518-11305-L ME@

Compal Secret Data 2010/07/12

Issued Date

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4

JUSB3

1 2 3 4 5 6

USB20_N0_C USB20_P0_C

C715 470P_0402_50V7K

8/23 change C714 P/N to SGA00002N80

Security Classification

5

2 R868 @1 0_0402_5% 2 R869 @1 0_0402_5%

3

C605 1 C606 1

1 2 3 4 5 6 7

2

<18,57> USB20_N0 <18,57> USB20_P0

USB20_N0 USB20_P0

D25 @

A

1

SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2

<14,57> SATA_DTX_C_IRX_N2 <14,57> SATA_DTX_C_IRX_P2

SATA_ITX_DRX_P2_CONN SATA_ITX_DRX_N2_CONN

1

+

JODD1

<14,57> SATA_ITX_DRX_P2_CONN <14,57> SATA_ITX_DRX_N2_CONN

8/27 change to @

W=80mils

+USB_VCCA

2

CONN PIN define need double check

SATA ODD Conn.

2 300_0402_5%

19-213A-T1D-CP2Q2HY-3T_W HITE

RIGHT USB PORT X1

8 7 6 5

OUT OUT OUT OC#

SW /R

SW 5

2

U36 D15 PSOT24C_SOT23-3 @

SW 4 B

1

<14,57> HDD_LED#

+USB_VCCA

2

3

SW /L

2

4

1

TP_CLK TP_DATA

PJDLC05_SOT23-3

6 5 2

1 2 R679 0_0402_5%

<40,57> RF_LED#

+5VALW SMT1-05_4P

3

2

Title

Compal Electronics, Inc. KB /SW /LPC Debug Conn.

Size B Date:

Document Number

Rev 0.2

LA-6751P Friday, November 26, 2010

Sheet 1

56

of

59

5

4

3

2

JKB1 <40,56> INT_KBD Conn.

KSI[0..7]

KSI[0..7]

KSO[0..17]

KSO2

KSO[0..17] <40,56>

C668 1

2 @ 100P_0402_50V8J

KSO16

C693 1

2 @ 100P_0402_50V8J

KSO17

C692 1

2 @ 100P_0402_50V8J

KSO1

C669 1

2 @ 100P_0402_50V8J

KSO15

C670 1

2 @ 100P_0402_50V8J

KSO7

C671 1

2 @ 100P_0402_50V8J

KSO6

C672 1

2 @ 100P_0402_50V8J

KSI2

C673 1

2 @ 100P_0402_50V8J

KSO8

C674 1

2 @ 100P_0402_50V8J

KSO5

C675 1

2 @ 100P_0402_50V8J

KSO13

C676 1

2 @ 100P_0402_50V8J

KSI3

C677 1

2 @ 100P_0402_50V8J

KSO12

C678 1

2 @ 100P_0402_50V8J

KSO14

C679 1

2 @ 100P_0402_50V8J

KSO11

C680 1

2 @ 100P_0402_50V8J

KSI7

C681 1

2 @ 100P_0402_50V8J

KSO10

C682 1

2 @ 100P_0402_50V8J

KSI6

C683 1

2 @ 100P_0402_50V8J

KSO3

C684 1

2 @ 100P_0402_50V8J

KSI5

C685 1

2 @ 100P_0402_50V8J

KSO4

C686 1

2 @ 100P_0402_50V8J

KSI4

C687 1

2 @ 100P_0402_50V8J

KSI0

C688 1

2 @ 100P_0402_50V8J

KSO9

C689 1

2 @ 100P_0402_50V8J

KSO0

C690 1

2 @ 100P_0402_50V8J

KSI1

C691 1

2 @ 100P_0402_50V8J

D

<40> <40>

KSO16 KSO17

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15 KSO16 KSO17

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

ZZZ

DAZ0GM00100

1

ZZZ1

ZZZ2

ZZZ3

ZZZ4

ZZZ5

PCB

PCB

PCB

PCB

PCB

DA80000KG10

DA40000VV10

DA40000VS10

DA40000VT10

DA40000VU10

DA8@

DA4@

DA4@

DA4@

DA4@ D

+5VALW

+USB_VCCA U36 C713 0.1U_0402_16V4Z 2 1 <38,40,42,56> USB_ON#

31 32

GND GND

1 2 3 USB_ON# 4

GND IN IN EN

OUT OUT OUT OC#

RIGHT USB PORT X1

8 7 6 5

USB_OC0# <18,38,56>

APL3510BKI_SO8

1

ACES_88514-3001

Reserve for ESD.

CONN PIN define need double check

ME@

C716 @ 1000P_0402_50V7K

2

+5VS

Right USB Conn.

C

+USB_VCCA

C696

<40,56> TP_CLK <40,56> TP_DATA

1

2

@ C697 100P_0402_50V8J

1

2

@ C698 100P_0402_50V8J

TP_CLK TP_DATA SW /L SW /R

1 2 3 4 5 6

1 2 3 4 5 6

7 8

GND GND

1

1

+

C714 220U_6.3V_M

2

USB20_N0 USB20_P0

<18,56> USB20_N0 <18,56> USB20_P0

8/27 change to stuff

8/14 change to OSCAN 220U

3

TP_CLK TP_DATA

4

USB20_P0

1

2

SW /L

3

USB20_N0_C

W CM-2012-900T_4P USB20_N0

4

3

3

USB20_N0_C

2

USB20_P0_C

1 L66

2

D15 PSOT24C_SOT23-3 @

D25 @

1

SW 4

USB20_P0_C

3

6 5

4

1 2 3 4 G5 G6

ACES_85205-04001 ME@

ME@

1

1 2 3 4 5 6

USB20_N0_C USB20_P0_C

C715 470P_0402_50V7K

(220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00) 2

2 R868 @1 0_0402_5% 2 R869 @1 0_0402_5%

2

ACES_88058-060N

SMT1-05_4P

JUSB3

+USB_VCCA

JTP1

2

0.1U_0402_16V4Z

C

8/27 change to @

W=80mils

PJDLC05_SOT23-3

To TP/B Conn.

2

B

1

6 5

B

SMT1-05_4P

4

SW /R

1

3 JP13

CONN PIN define need double check

SW 5

D19

@

1

<34,56> W LAN_LED#

White

2

+5VALW +3VALW +5VS <40,56> LID_SW #

RF_LED#_R

RB751V_SOD323

SATA ODD FFC Conn. <14,56> SATA_ITX_DRX_P2_CONN <14,56> SATA_ITX_DRX_N2_CONN <14,56> SATA_DTX_C_IRX_N2 <14,56> SATA_DTX_C_IRX_P2

SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 ODD_DETECT#

C605 1 C606 1

2 0.01U_0402_16V7K SATA_DTX_IRX_N2 2 0.01U_0402_16V7K SATA_DTX_IRX_P2 R710 1 2 0_0402_5% +5V_ODD

ODD_DA#

<18,40,56> ODD_DA#

+3VS

1 R554 R555 1

2 0_0402_5%

2 10K_0402_5%

A

1 2 3 4 5 6 7 8 9 10

1 2 3 4 5 6 7 8 9 10

11 12

GND GND

D20

@

JP2 SATA_ITX_DRX_P2_CONN SATA_ITX_DRX_N2_CONN

1

<42,56> BT_LED#

<40,43,56> PW R_LED# <40,56> CHARGE_LED1# <40,56> CHARGE_LED0#

2

RB751V_SOD323

RF_LED#_R

<14,56> HDD_LED#

1 2 R679 0_0402_5%

<40,56> RF_LED#

<14,56> KILL_SW #

For 15" M/B to LED/B KILL_SW #

R884 1

@

2 100K_0402_5%

+3VALW

1 2 3 4 5 6 7 8 9 10 11 12

13 14

GND1 GND2

2 100K_0402_5% ACES_88514-01201-071

LID_SW #

11/16modify

ACES_87056-01001-001

R615 1

1 2 3 4 5 6 7 8 9 10 11 12

7/22 modify

A

ME@

ME@

Compal Secret Data

Security Classification 2010/07/12

Issued Date

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. KB /SW /LPC Debug Conn.

Size B Date:

Document Number

Rev 0.2

LA-6751P Friday, November 26, 2010

Sheet 1

57

of

59

5

4

3

2

1

PHASE

PAGE

Modification list

PURPOSE

0.2

P31

Change CRT Symbol

For CRT footprint issue

0.2

P31

Del C510

For Non-used part

0.2

P39

change C610 pin 1 net name

change C610 pin 1 net name to correct

0.2

P35

U25 change to U26

For co-lay 10/100 and GIGA

0.2

P32

Add R735,R736

For DIS only SMBus pull high

0.2

P33

Add R738,R739

For DIS only SMBus pull high

0.2

P33

Change Q63 BOM structure to HDMI@

For DIS HDMI function

0.2

P40

Add R740, C93

For EC request

0.2

P18

Change R215 pin1 net name

Change R215 pin1 net name to correct

0.2

P18

Add R741

Add R741 for Reserved PE_GPIO0

0.2

P16

Add R742, R743

For PCH power sequence

0.2

P38

Del U28, R542~R551 , J12

Del USB charger circuit

0.2

P40

Add EC pin 97,98,103

Add EC pin 97 for SYS_PWROK_EC , pin 98 for CE_EN , pin 103 for BATT_SEL_EC

0.2

P24

Change R662 pin 2 net name

0.2

P28

Del C421,C422,C431,C432,C433, L27,

0.2

P26

Add R744

Add R744 for control PE_GPIO1 from SUSP#

0.2

P39

Change J10 footprint and Add J13

Change J10 footprint by DFx request and Add J13 by vendor suggestion

0.2

P39

Change PC_Beep circuit

Change PC_Beep circuit

0.2

P6

Add R161, R182,

Follow ORB circuit

D

C

B

D

0.2

P58/59

0.2

P31

For power trace net

P56/57/58 Change JP4 to JTP1

to JKB1

C

Change connector to standard name Change connector to standard name

Change JP6 to JPWRB1

Change connector to standard name

P34

Change JP1 to JWLN1

Change connector to standard name

0.2

P42

Change JP5 to JBT1

Change connector to standard name

0.2

P43/60

Change JP7 to JCR1

Change connector to standard name

0.2

P19

Add

For ESATA detect function

0.2

P42

Add R886, R887 , C735

For ESATA detect function

0.2

P31

Add R543

For reserve EC control directly

0.2

P39

Change J10 footprint,

0.2

P42

Add R877

For reserve EC control directly

0.2

P42

SW3 BOM structure change to @

For ME ASSY concern

R542

Del C635, C636

Change J10 for DFx and Del component for layout

0.2

P24

R324 BOM structure change, del @

0.2

P25

Change Q69,Q70,Q71,Q72 to BSS138,

0.2

P42

Change ESATA from port 5 to port 4

For intel risk

0.2

P15

Add R544,R545

For Pull high SMBus

0.2

P12/13

0.2

P16

Add R182,R546

Add 186 for reserve sequence,

0.2

P20

Del Add J12, R257 change to @

For voltage drop

Del R74~R80,R82

For AMD update change Q66,Q67 pin 1 net name,

D28 change to @

For Change BACO part follow AMD reference DATA ,D28 change to @ for leakage

R88~R94,R96

Add R546 for follow CRB & ORB

0.2

P26

R161 Change Q6 to U14

Change SI2301 to SI4800 for loading current

P6

R161 change to 100K

Follow CRB

0.2

P19

Add R547 , R250 change to @

Follow Module and CRB

0.2

P18

WLAN USB port for port8 to port9

For debug port

0.2

P25

AND Gate power change to +3VGS

For VGA circuit

0.2

P24

Add R548, R549

For DIS HDMI audio strap

0.2

P39

Del J13

For layout space

P20,39,42 Add C395 , R581 , R583 , R584 , R586 , R587

For customer request reserved

0.2

P20

Add C129, C396 , Del R264

For reserved

0.2

P40

Add PIN 66 , R740,C93 change to @

Add IMVP_IMON

0.2

P9

Add R74

For VCCIO_SENSE / VSSIO_SENSE differential routing

A

Compal Secret Data

Security Classification 2010/07/12

Issued Date

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

B

For DDR3 DM Bus to GND

0.2

0.2 A

Pull high LID_SW# at M/B side

Add Q83 pin 1 power net name +CMOS_PW

0.2 0.2

For AMD new document suggestion

Add R615 in 15" and 17" page

P56/57/58 Change JP21 P43/60

U8 pin N11,N12 change to NC

R192 BOM structure hange to @

0.2 0.2

Change R662 pin 2 net name to correct Add R745,

4

3

2

Title

Compal Electronics, Inc. KB /SW /LPC Debug Conn.

Size B Date:

Document Number

Rev 0.2

LA-6751P Friday, November 26, 2010

Sheet 1

58

of

59

5

4

3

2

PHASE

PAGE

Modification list

PURPOSE

0.2

P33

Del RQ51 ~ Q54

For DIS HDMI

0.2

P39

Del J10, C637,C640,R576,R577,R579 change to @ , L40~L43 change to R720~R723

Add Q95

1

For Vendor suggestion and EMI

Del C643, R578 , MIC_INR connect MIC_INL , Add R578

Del C653, R578 connect MIC_INR/L for vendor suggestion , Add R578 for EMI

Add L75 , R264 , C917,

For intel PDDG update

0.2

P20

R259

C226 change to @

0.2

P20

Change JCR1 pin define , MIC change with HP

0.2

P9

Add C394, C397 ,C400

0.2

P26

Add R688 change to 20k, R345 change to 200k , R350 change to 330k , Q65 stuff

For VGA power sequence

0.2

P42

Change C706 P/N to SF000001500

Change to H=6 OSCAN

0.2

P10

Change C128 to @

For Reserved

0.2

P26

Change D3 change to @

For VGA leakage

0.2

P25

Change BIF_VDDC control pin net name

For correct behavior

0.2

P56

Update JODD1 symbol

For ME update drawing

0.2

P16

D29 change to @

For AC detect issue

0.2

P24

R548,R549 change to DIS@

For AC detect issue

0.2

P10

C128 change to stuff

For test on DVT

0.2

P44

Del Q118, R657

For not need

0.2

P57

Change 15" C714 to OSCAN

For ME Space ok

0.2

Change R513, R516 ,R667 P/N and from 0805 to 0603

For common part

0.2

Change C633, C634 , C642

For common part

0.2

Change D3, D29 P/N and symbol

For common part

0.2

Change U3,U11,U13,U14,U38,U39 P/N and symbol

For common part

0.2

Change U3,U11,U13,U14,U38,U39 P/N and symbol

For common part

0.2

Change Q8,Q65,Q80,Q83,Q99,Q104 P/N and symbol

For common part

0.2

Change Q1,Q37,Q93 P/N and symbol

For common part

0.2

Change Q94, Q95 P/N and symbol

For common part

0.2

Change Q3,Q4,Q7,Q9,Q66,Q67,Q68,Q73,Q74,Q75,Q76,Q77,Q78,

For common part

For correct ID

,Add R75

For CPU_CORE power reserved at Bottom side, Add R75 for reserved at cpu side and pwr side

D

C

D

C

Q79,Q82,Q85,Q86,Q87,Q102,Q106,Q107,Q108,Q109,Q110,Q111,Q112,Q113,Q114,Q115,Q116 P/N and symbol

B

0.2

P43

Change C635 part and change to @

For EMI

0.2

P18

Reserved R551

Reserved

0.2

P9

For CPU_CORE

0.2

P10

Change C53,C85,C86,C87 ,C394,C397,C400 to stuff and change C48,C80,C81,C82,C89,C90,C91 to @ Change C110,C111,C112,C113 to stuff

For VGFX_CORE

0.2

P56

Change LED1/LED3/LED4 P/N to SC50000A300

Change P/N

0.2

P36

Change

0.2

P40

Change R611,R740,C93 to stuff and change Y5,C347,C367 to @

For SUS_CLK

Change R695 to 18K, Q37 change to @,

R695 for Board ID, Q37, R747 for VR_HOT

0.2

P41

0.2

T1,T2 P/N to SP050003N00

For test pass part R747 change to stuff,

Change U33 P/N to SA00003FL10

B

For BIOS ROM

Change C509,C511,C635 to stuff

For EMI request For Sourcer request

0.2

P56

Change 14" C714 P/N to SGA00002N80

0.2

P39

0.2

P19

Change R720,R721,R722,R723 P/N to SM01000BZ00(Bead), Change C647,C649,C650,C651 to Stuff Change R303 to Stuff, and change R542 to @

0.2

P56

Change U32 P/N to SA000031C00

For common part

0.2

P36

Change T1,T2 P/N to SP050006E00

For correct part

0.2

P10

R688 change to stuff , R687 ,Q7 change to @

For S3 power reduction For EMI

P20

Change R660,R661,R862,R863,R864,R865,R868,R869 to @ , change L63,L64,L65,L66 to stuff , change R619 to Bead (SM01000DI00) Change L75 symbol

0.2 0.2

and

For EMI request For BIOS ESATA detect function

For common part

A

A

Compal Secret Data

Security Classification 2010/07/12

Issued Date

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. HW-PIR

Size B Date:

Document Number

Rev 0.2

LA-6751P Friday, November 26, 2010

Sheet 1

59

of

59

5

D

C

4

3

2

PHASE

PAGE

Modification list

PURPOSE

0.3

P10

Update Q5 symbol

For update symbol

0.3

P33

Add F2

For safty request

0.3

P39

Update U30 P/N to SA00003K410 and Add R879

For Audio update to 21Z

0.3

P10

Change C128 to D2 size and @

Change size for M/E issue

0.3

P14

Add reserve R878

For Intel DG 1.5

0.3

P37

C592 change P/N to SF000001500 (H=6)

For ME Z high ok

0.3

P25

Update Q69~Q72 to AO3414 ,D28 R873 change to BACO@ , U40 change to @

For PX4.0

0.3

P28

Add reserve C94

For reserve VGA_CORE

0.3

P29

R369 P/N change to SD034100A80

For GP part

0.3

P18

R553,R691,R684,R682,U12 change to PX@

For PX 4.0

0.3

P6

Reserved R880 to SYS_PWROK

Follow ORB

0.3

P10

R62,R63 change to 1K

Follow CRB

0.3

P19

R303 change to @,

For ESATA and PX4.0

Change M/B ID to PX4.0

1

D

0.3

P25

Q69~Q72 change to BACO @

For PX4.0

0.3

P26

R719 change to stuff, R744 change to @ , R677 change to BACO@

For PX4.0

0.3

P33

R483,R484 change connect to +5V_HDMI_F

For Add F2

0.3

P37

Change U27 P/N to SA000046C00

For Fintek

0.3

P40

Change R594 pull high to +5VALW

For leakage issue

0.3

P19

R881 change to Dtuff, R244 change to @

For intel MRC Rev0.9

0.3

P14

R878 change to stuff

For intel DG 1.5

0.3

P31

Del R432

For non-used part

C

0.3

P36

Reserved D31 , C643 , C644

For reserved EMI parts

0.3

P37

Del R581

For non-used part

0.3

P38

Del R550

For non-used part

0.3

P38

Change C592 P/N to SF000002Y00

For M/E Z high limlt

0.3

P39

Del R584, R586 , R587

For non-used part

0.3

P40

Change R600, R604 to 2.2K

0.3

P42

Del R583

For non-used part

0.3

P6

Reserved R882 connect to PCH_PWROK

Reserved for intel

0.3

P56

R765 change to 300 ohm

For LED

0.3

P25

R324, R744 , R674 change DIS@

For DIS only sku

Change R600, R604 for Battery SMBus, R695 for Board ID

Change R695 to 8.2k

B

B

A

A

Compal Secret Data

Security Classification 2010/07/12

Issued Date

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. HW-PIR

Size B Date:

Document Number

Rev 0.2

LA-6751P Friday, November 26, 2010

Sheet 1

60

of

60