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Logical Effort Model Extension to Propagation Delay Representation Benoit Lasbouygues, Sylvain Engels, Robin Wilson, Member, IEEE, Philippe Maurine, Nadine Azémard, and Daniel Auvergne

Abstract—The logical effort method is widely recognized as a pedagogical way allowing designers to quickly estimate and optimize single paths by modeling equivalently propagation delay and transition time. However, this method necessitates a calibration of all the gates of the library and appears suboptimal in real combinatorial paths for satisfying tight timing constraints. This is due to the inability of the logical effort model in capturing I/O coupling and input ramp effects that distinguish the transition time from the propagation delay. Using an analytical modeling of the supply current that flows in simple gates during their switching process, this paper introduces an extension of the logical effort model that considers the I/O coupling capacitance and the input ramp effect. Validation of this model is performed on 130-nm STMicroelectronics technology. A compact representation of CMOS library timing performance is given as a possible application of the proposed model. The choice of sampling points to be used in look-up tables as representative steps of the design range is also discussed. Index Terms—Deep-submicron analysis.

meter,

modeling,

timing

I. I NTRODUCTION

P

ERFORMANCE modeling and characterization of integrated circuits has been and is still the subject of numerous works as a critical issue either for timing characterization [1], [2] and optimization [3] or to address the yield problem related to random process variations [4] in deep-submicron meter technologies. Timing verification and circuit validation are currently performed using static timing analysis based on look-up tables characterizing each drive of gate in a discrete range of loading and input ramp conditions for critical supply voltage and temperature values. This imposes a huge number of simulations that just allow representing the design space with few loading, controlling, and operating conditions. Intermediate conditions can then be interpolated from characteristic equations [5] such as f (τIN , CL ) = AτIN + BCL + CτIN CL + D. It is well recognized that the transition time and the propagation delay exhibit a nonlinear variation with respect to control and loading conditions. This imposes, to use during the definition of the look-up table, a variable sampling step because interpolating in this range may induce significant errors. Usually, the largest error occurs for small values of the load and large Manuscript received October 28, 2004; revised May 20, 2005. This paper was recommended by Associate Editor D. Blaauw. B. Lasbouygues, S. Engels, and R. Wilson are with STMicroelectronics, Crolles Cedex 38926, France. P. Maurine, N. Azémard, and D. Auvergne are with the Laboratory of Informatic, Robotic and Microelectronic of Montpellier, 34392 Montpellier, France (e-mail: [email protected]). Digital Object Identifier 10.1109/TCAD.2005.857400

values of the input transition time. It is clear that the relative accuracy, obtained with a tabular method, is strongly dependent on the granularity of the table that is not necessarily constant but must cover a significant part of the design range. Moreover, the use of a tabular or approximate polynomial representation, without explicit indication of the sensitivity to the design or environmental parameters, does not permit the definition of metrics or bounds allowing the implementation of deterministic optimization protocols, hence the need for a simple explicit but accurate performance representation of CMOS designs. In their seminal book [6], Sutherland et al. have introduced a simple and practical delay model. They have developed the logical effort method allowing designers to get a good insight of the optimization mechanisms using easy hand calculations. Based on a CMOS extension of Mead’s τ model [7], they do represent the CMOS cell transition time with few design parameters involving the process, the topology of the switching structure, and its load. Despite its pedagogical aspect, this model does not distinguish falling and rising edges, and completely fails in representing real cell propagation delay that involves the influence of the input controlling ramp. An empirical extension of the logical effort model has been proposed in [8] to consider the input ramp effect. However, the I/O coupling capacitance effect, first introduced by Jeppson [9], is neglected in this logical effort extension and the proposed model still remains limited to the transition time representation. Moreover, with the dramatic increase of the subthreshold current, designers may want to include in their design multiple threshold voltage CMOS (MTCMOS) or use several supply voltages. As a consequence of this global trend, it is necessary to develop timing performance models that distinguish edges and transition time from propagation delay, allowing designers to deal with multiple threshold and supply voltage values without calibration time penalties. Based on a former study of CMOS timing performance [10], [11], we introduce herein a physical extension of the logical effort to consider transition time and propagation delay (measured at 50% of the supply voltage VDD ) and distinguish between falling and rising edges. Both the I/O coupling and the input ramp effects are considered by the proposed model that also clearly exhibits timing performance sensitivities to supply and threshold voltage values. The rest of the paper is organized as follows. In Section II, starting from the alpha power law model, we first physically justify the logical effort model before extending it. Section III is then devoted to the validation of the extended model and to its application to the definition of a new timing performance

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representation. Section IV discussed briefly how to choose the sampling points to be reported in traditional look-up tables to increase the accuracy of the representation. Finally, Section V is devoted to the conclusion. II. T IMING P ERFORMANCE M ODEL In the method of logical effort [4], the delay of a gate is defined by d = τ (p + gh)

(1)

where τ is a constant that characterizes the process to be used, p is the gate parasitic delay, which mainly depends on the source/drain diffusion capacitance of the transistors, g is the logical effort of the gate, which depends on the topology of the gate, and h is the electrical effort or gain, corresponding to the ratio of the gate output loading capacitance to its input capacitance and characterizes the driving possibility of the gate. Using the inverter as a reference, these different parameters can be determined from electrical simulation of each cell. However, if this simple expression can be of great interest for optimization purpose, no consideration is given to the input slew effect on the delay and to the input-to-output coupling [9]. As a result, the different parameter values cannot be assumed constant over the design space; moreover, they are temperature and supply voltage dependent. As it can be shown from [7], (1) characterizes the gate output transition time. However, timing performance must be specified in terms of cell input (output) transition time and input-to-output propagation delay. A realistic delay model must be input slope dependent and must distinguish between falling and rising signals. In order to get a more complete expression for the gate timing performance, let us develop (1), starting from a physical analysis of the switching process of an inverter. We first consider a model for the transition time and show its equivalence with the logical effort model. Then we will extend this model to the propagation delay. A. Inverter Transition Time Modeling Following [7], the elementary switching process of a CMOS structure, and thus of an inverter, can be considered as an exchange of charge between the structure and its output loading capacitance. The output transition time (defining the input transition time of the following cell) can then be directly obtained from the modeling of the charging (discharging) current that flows during the switching process of the structure and from the amount of charge (CL_TOT × VDD ) to be exchanged with the output node as τoutHL

CL_TOT × VDD = INMax

τoutLH

CL_TOT × VDD = IPMax

The fan out load includes the parasitic interconnect component. CINT is constituted of the coupling capacitance CM between the input and output nodes [12] and of the transistor diffusion parasitic capacitance CDIFF . Note that CM can be evaluated as one half the input capacitance of the P(N) transistor for input rising (falling) edge or directly calibrated on Hspice simulation. As a result, CINT is proportional to the gate input capacitance. In (2), the output voltage variation has been supposed linear and the driving element considered as a constant current generator delivering the maximum current available in the structure. Thus, the key point here is to determine a realistic value of this maximum current. Two controlling conditions must be considered. 1) Fast Input Control Conditions: In the fast input range, the input signal reaches its maximum value before the output begins to vary; in this case, the switching current exhibits a constant and maximum value Fast = KN,P WN,P (VDD − VTN,P )αN,P IMAX

(3)

deduced from Sakurai’s representation [13], αN,P is the velocity saturation index of N and P transistors, and KN,P is an equivalent conduction coefficient to be calibrated on the process. From (2) and (3), we obtain the expression of the gate transition time for a fast input control condition as Fast = τ (1 + k) τoutHL Fast τoutLH =τ

CL_TOT ≡ τ (pHL + gHL h) CIN

(1 + k) CL_TOT R ≡ τ (pLH + gLH h) k CIN

(4)

where CIN = COX LGEO (WP + WN ), k = WP /WN , is the configuration ratio between P and N transistors. τ and R are, respectively, the delay scaling factor characterizing the process and the current dissymmetry factor between N and P transistors, i.e., τ=

COX LGEO VDD KN (VDD − VT N )αN

R=

KN (VDD − VT N )αN . KP (VDD − VT P )αP

(5)

Finally, pHL,LH and gHL,LH are the parameters characterizing the topology of the inverter under consideration. They are defined by pHL =

(1 + k)(CMHL + CDIFF ) CIN

gHL = (1 + k) (2)

where VDD is the supply voltage value and CL_TOT = CINT + CEXT is the total output load, which is the sum of two contributions, the fan out load CEXT and the internal load CINT .

pLH = R

(1 + k)(CMLH + CDIFF ) kCIN

gLH = R

(1 + k) . k

(6)

LASBOUYGUES et al.: LOGICAL EFFORT MODEL EXTENSION TO PROPAGATION DELAY REPRESENTATION

As clearly shown, the expressions (4)–(6) constitute an explicit representation of the logical effort model [4] for nonsymmetrical inverters. τ and R can easily be calibrated on the process; the other parameters are directly specified on the design. They are the parameters to be controlled for performance optimization. These equations have been shown to be very accurate [14] in representing the transition time value of CMOS gates in the fast input control range; they completely represent the variation observed on the look-up tables for small values of the transition time and important loading conditions. A more accurate definition of the fast input range will be given later. 2) Slow Input Control Conditions: In the slow input range, the transistor is still in saturation when its current reaches the maximum value but its gate source voltage is smaller. In this case, the maximum switching current exhibits a smaller value. From the alpha power law model, we can write
IN (t) = KN WN

VDD t − VT N τIN

αN (7)

that leads to dI αN KN WN VDD = dt τIN




VDD t − VT N τIN

αN −1 .

(8)

Considering that the switching current is equal to zero at tVTN = VT N τIN /VDD and defining TMAX to be the time at which the switching current reaches its maximum, it comes ∆I αN KN WN VDD = ∆t τIN =

αN KN WN VDD τIN





VDD TMAX − VT N τIN

αN −1

VDD TMAX VDD TVTN − τIN τIN

αN −1 . (8a)

Defining ∆t = TMAX − TVTN , i.e., as the time spent by the transistor to deliver its maximum current, (8a) becomes αN KN WN VDD ∆I = ∆t τIN




VDD ∆t τIN

αN −1

IMAX . ≡ ∆t

(9)

(10)

Combining (9) and (10), we obtain the maximum current value for a slow input ramp applied as

Slow IN -MAX =

 1 1  α α1N K αN W αN C







N

N

τIN

2  L_TOT VDD

αN 1+αN

.

Finally, combining expressions (2) and (11) provides the transition time expression for the slow input ramp domain   1+α1 αN,P N,P    V −V   DD αN,P TN,P Slow Fast τoutHL,LH τIN . τoutHL,LH =   1    α αN,P V  DD N,P (12) Defining supply and threshold voltages dependent factor UN,P as UN,P =

VDD − VTN,P 1

.

(13)

α αN,P VDD

Equation (12), which is the extended logical effort expression of the output transition time for slow input ramp conditions, can be rewritten as  α  1 α Slow τoutHL,LH = UN N,P τINN,P τ (pHL,LH + gHL,LH h) 1+αN,P . (14) Note here that for advanced high-speed processes, in which the carrier speed saturation dominates (αN,P = 1), this expression can be simplified as  Slow τoutHL,LH = UN,P τIN τ (pHL,LH + gHL,LH h) (15) with UN,P =

VDD − VTN,P . VDD

(16)

3) Unifying Fast and Slow Domains: Considering (4) and (14), it appears that the transition time value for fast input edge Fast τout can be used as a metric for both fast and slow input ramp domains. Indeed, considering the input slope sensitivity of the different expressions results in a normalized output transition time equation of an inverter as   1 τoutHL,LH αN,P = Max (17) Fast τoutHL,LH {UN,P σHL,LH } 1+αN,P where σHL,LH is equivalent to an input slew effort

Then, under the approximation that the current variation is symmetric with respect to its maximum value, we can evaluate the total charge removed at the output node as CL_TOT VDD IMAX ∆t = . 2 2

1679

(11)

σHL,LH =

τIN . Fast τoutHL,LH

(18)

Equation (17) is of great interest. First, it gives a clear definition of the separation between fast and slow input control. Second, it supplies a new representation of performance, as shown that the output transition time of any inverter of a given library can be represented by a single expression since the right part of (17) does not depend on any design parameter. From an application point of view, using the relative axis specified by (18), an inverter family of a given library can be characterized only by a one-line look-up table. As a validation of these results, we report in Fig. 1(a) and (b) the simulated and calculated values of the normalized output transition time (with respect to σHL ) of eight inverters of a 130-nm process. In Fig. 1(a), two different methods have been applied to simulate and calculate

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TABLE I TYPICAL VALUES OF DWHL,LH (130 nm)

given library have the same internal configuration ratio (in order to balance rising and falling delays), it appears unnecessary to capture this effect to characterize a library with good accuracy. B. Extension to Gates Following [7], the extension to gates is obtained by reducing each gate to an equivalent inverter. For that we consider the worst-case situation. The current capability of the N(P) parallel array of m transistors is evaluated as the maximum current of an inverter with transistor width m times larger than that of the individual transistors constituting the array. The array of N(P) series-connected transistors is modeled as an input voltage controlled current generator with a current capability reduced by a factor DWHL,LH . This reduction factor (DW) is defined as the ratio of the current available in an inverter to that of a series-connected array of transistors of identical size, i.e., DWHL,LH =

Fig. 1. (a) Simulated (∗, ∆) and calculated (dashed, solid) values of the normalized output transition time of the eight inverters designed in 130-nm process. (b) Simulated (∗k = 1.8, ∆k = 1) and calculated (solid) values of the normalized output transition time of the 16 inverters designed in 130-nm process.

the output transition time. In case (a), the output transition time has been measured (and the model calibrated) between 40% and 60% of the signal voltage swing, while in the case (b) these values have been extrapolated (and the model calibrated) between 10% and 90%. The simulated values have been obtained for four different loading conditions (Fo = CL /CIN = 2, 5, 10, 20) and different input ramp durations (τIN = 10, 20, 30, 50, 100, 200, 400, 800, 1200, and 1600 ps). As expected, all the simulated curves pile up on the same one, which is really closed to the curves obtained by calculus. This characteristic curve represents the normalized output transition time sensitivity to the slew effort σHL . Fig. 1(b) gives the curves obtained for two different inverter families; one with an internal configuration k = WP /WN equal to 1 (∆) and another with an internal configuration ratio equal to 1.8 (∗). As expected, for fast input ramps and medium input ramps, all the simulated curves pile up on a single curve. However, for really slow input ramps, this curve splits up into two close but distinct curves. This is a direct illustration of the short circuit current that is neglected in our model. Some effort could be devoted to account of the short circuit current in this model. However, considering that all the inverters (or gates) of a

IN,P (Inv) WN,P (Inv) . IN,P (Gate) WN,P (Gate)

(19)

DW corresponds to the explicit form of the logical effort [3]. Let us evaluate the expression of DWHL,LH . In the fast input range, the maximum current that can provide an array of n serially connected transistors is defined by IR = KN,P WN,P × {VDD − VT N,P − (n − 1)RN,P IARRAY }αN,P

(20)

where WN,P is the width of the topmost transistor (the transistor having its drain connected to the output) and RN,P is the resistance of the bottom transistors. In this expression, we have considered that the top transistor (the nearest to the output) is switching, the (n − 1) bottom ones being ON and in the resistive operating mode. Using a first-order binomial decomposition of (20), we get the reduction factor for fast input controlling conditions DWHL,LH = 1 + αN,P KN,P WN,P (n − 1) × RN,P (VDD − VT N,P )αN,P −1

(21)

which is a generalization of the result introduced in [11]. We give in Table I, with respect to the number of serially connected transistors, the simulated values of DWHL,LH as well as the corresponding values of RN,P . For a DSM process (α = 1), the value of the reduction factor is DWHL,LH = 1 + KN,P WN,P (n − 1)RN,P

(22)

as proposed in [14]. Applying this reduction factor of the maximum current to the expression of the output transition

LASBOUYGUES et al.: LOGICAL EFFORT MODEL EXTENSION TO PROPAGATION DELAY REPRESENTATION

time (2) gives the normalized output transition time definition of a gate   1 τoutHL,LH αN,P = Max (23) Fast τoutHL,LH {UN,P σHL,LH } 1+αN,P where Fast τoutHL,LH = τ (pHL,LH + gHL,LH h)

(24a)

(1 + k)(CMHL + CDIFF ) CIN = DWHL (1 + k) (1 + k)(CMLH + CDIFF ) = RDWLH kCIN (1 + k) . = RDWLH k

pHL = DWHL gHL pLH gLH

(24b)

As shown, the gate transition time expression is directly derived from that of inverters, multiplying the p and g parameters by the current reduction coefficient DW. Considering (19) and (21), we have to note that, as expected, DW depends on the location on serial array of the transistor controlling the switching for an inverter DW = 1. Equations (23) and (24) clearly identifies, in the logical effort model, the contribution of the gate structure and size, the supply voltage sensitivity, the input slew dependency, and the I/O coupling that has a nonnegligible contribution for weak loading conditions. They can be use as a general representation of the transition time of a CMOS library.

transition time of the controlling and the switching gate. However, as shown in Fig. 5, the propagation delay is not linear. More precisely, the delay remains linear until the short circuit current becomes significant. The expression (25) does not take into consideration the short circuit current. However, following [10], the expression (25) can be modified in order to account for the short circuit current effect
 vT N 2CM τIN + 1 + tHL = 2 CM + CL + CDIFF
 τoutHL τIN × 1 − AHL Fast 2 τoutHL
 vT P 2CM τIN + 1 + tLH = 2 CM + CL + CDIFF
 τoutLH τIN × 1 − ALH Fast (26) 2 τoutLH where AHL and ALH are fitting parameters to be calibrated Fast , defined in fast on simulations. Using the transition time τOUT input control condition (4) as a reference, we can easily obtain a normalized expression for the gate propagation delay ΘHL,LH tHL,LH Fast τoutHL,LH vT N,P 2αHL,LH  σHL,LH +  = 2 αHL,LH + CCDIFF +h IN   τIN × 1 − AHL,LH Fast τoutHL,LH   τIN τoutHL,LH + Fast 1 − AHL,LH Fast . 2τoutHL,LH τoutHL,LH

ΘHL,LH =

C. Gate Propagation Delay Model A realistic delay model must be input slope dependent and must distinguish between falling and rising signals. As developed by Jeppson [9], considering the input-to-output coupling effect, the input slope effect can be introduced in the propagation delay tHL,LH as
 τoutHL VT N 2CM tHL = τIN + 1 + 2VDD CM + CL + CDIFF 2
 τoutHL vT N 2CM τIN + 1 + = 2 CM + CL + CDIFF 2
 τoutLH VT P 2CM tLH = τIN + 1 + 2VDD CM + CL + CDIFF 2
 τoutLH vT P 2CM τIN + 1 + . (25) = 2 CM + CL + CDIFF 2 τIN (τOUT,HL,LH ) is the transition time of the input (output) signal, generated by the controlling gate. As shown, for each edge, the delay expression is a linear combination of the output

 ΘHL,LH = 

1+vT N,P σHL,LH 2

1681

(27)

αHL,LH is the Meyer coefficient [12] for falling and rising edges. Its value is usually close from 1/2 and can be calibrated on electrical simulations. For a typical cell, the second term of (26) can be neglected for a value of the electrical effort h greater than 3 or equivalently for an important value of the input slew effort σHL,LH . For small values of h = CL /CIN (< 2), the second term of (25) and (26) dominates, and any further increase of the transistor widths is inefficient to improve the performance of the path since its speed is limited by the I/O coupling effect and the parasitic content of the gate CDIFF /CIN that has a constant value. Combining finally (23) and (27), we obtain a general expression of the normalized propagation delay of any combinational gate as that shown in (28) at the bottom of the page. As for the transition time equation (17), (23), a pin to pin propagation delay of any gate of a given library can be represented by a single expression (provided that the internal

 αN,P

vT N,P σHL,LH +{1−AHL,LH σHL,LH }{UN,P σHL,LH } 1+αN,P 2

(1 − AHL,LH σHL,LH )  + 2αHL,LH   αHL,LH + CCDIFF +h IN

(28)

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Fig. 2. Comparison between simulated and calculated values of the maximum switching current provided by an inverter (WN = 0.585, WP = 1.05, and l = 0.13 µm) for (a) different supply voltage values and (b) different loading factor values.

configuration of a gate family is kept constant) since (28) does not depend on design parameters, a part the last term that becomes quickly negligible in typical design conditions (h value ranging between 3 and 6). One of the main advantages of expressions (17), (23), and (28) is to be generic, and thus to be applicable to any CMOS gate provided to calibrate properly all the parameters. This required calibration step may have constituted a drawback; however, thanks to the compact representation of performance introduced in this paper, this step can easily and quickly be performed. III. V ALIDATION The preceding part shows that considering the I/O capacitance and the input ramp effect it is possible to extend the logical effort model to distinguish between falling and rising edges for transition time and propagation delay. This extension has been based on an accurate evaluation of the maximum charging (discharging) current that can deliver a CMOS structure with respect to the operating conditions like supply voltage, output load, and input slew. In order to validate this model, we first compare the prediction of (3), (11), and (17) with respect to Hspice simulations of an inverter designed in 130-nm technology. Different supply voltage conditions have been considered. The values of the saturation index have been obtained by fitting Sakurai’s current law on Hspice simulations using a least square approach. As an illustration of these validations, Figs. 2 and 3 give the calculated and simulated evolutions of both the maximum

Fig. 3. Comparison between simulated and calculated values of the output transition time of an inverter (WN = 0.585, WP = 1.05, and l = 0.13 µm) for different supply voltage and loading factor values.

switching current and the output transition time with respect to σHL for different supply voltage values (more detailed examples of validation of this model are available in [14]). As shown, the accuracy of the model for inverter is satisfactory. Note that the underestimation of the switching current for high supply voltage is mainly due to the short circuit current. However, this underestimation does not have a significant impact on the evaluation of the output transition time since it is measured around the maximum switching current. More precisely, we measured its value between 40% and 60% of the signal voltage swing. The model been validated for inverters, we studied its accuracy while applied to various and more complex cells. The results are reported in Fig. 4. This figure represents the dispersion of the relative errors for different gates successively loaded by 4, 24, 64, 144, 296, and 640 fF, and controlled by ramps of different durations (7, 127, 327, 667, and 1337 ps) applied on different input pins of the considered gates. As shown, the obtained errors are quite small, therefore validating the proposed extension of the logical effort. Fast as a metric of timing As previously mentioned, using τOUT performance (23), (27), the transition time and the propagation delay variations of the different drive possibilities of an inverter can be represented by a set of four laws, one by edge of each performance parameter. In order to validate this representation and thus the model, we give on Figs. 5 and 6 the simulated and calculated input transition time sensitivities of the output transition time and delay values of different

LASBOUYGUES et al.: LOGICAL EFFORT MODEL EXTENSION TO PROPAGATION DELAY REPRESENTATION

Fig. 4. Dispersion of the relative error between simulation and the proposed model.

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Fig. 6. Simulated and calculated (only for inverters for clarity) values of the normalized propagation delay of the eight different inverters (k = 1.8), five different NAND2 (k = 1.2), and five different NOR2 (k = 3.08) designed in 130-nm process.

design range. For that, indications for defining the granularity and the coverage of the design space must be available. As illustrated in Figs. 5 and 6, the nonlinearity corresponds to the fast/slow input ramp domain boundary. Thus, the evaluation of this boundary is of great interest to determine the data points to be sampled and reported in the look-up tables. The proposed model offers an easy way to determine this boundary. Indeed, we just have to find the controlling and loading conditions at which the two terms of (17) are equal. This gives Fast τoutHL,LH UN,P   CL τ = pHL,LH + gHL,LH . UN,P CIN

lim = τINLH,HL

Fig. 5. Simulated and calculated values of the normalized output transition time of eight different inverters, five different NAND2, and five different NOR2 designed in 130-µm process.

130-nm gates (at least five drive each). The simulations have been performed for a large range of loading (Fo = CL /CIN = 2, 3, 4, 5, 6, 10, 20) and controlling conditions (τIN = 10, 20, 30, 50, 100, 200, 400, 800, 1200, and 1600 ps). All the propagation delay and transition time values are normalized Fast . As shown, all the simulated sampling with respect to τOUT points (70 at least), corresponding to a particular gate, pile Fast up on one curve. This clearly demonstrates that using τOUT as a metric of performance, it is possible not only to simplify the library timing performance representation [1], [5] but also to minimize the number of data to be simulated for complete library characterization. IV. D ISCUSSION In submicron process, the transition time and the propagation delay exhibit a nonlinear variation with respect to the controlling and loading conditions. This nonlinear range must clearly be determined with closest simulation steps because interpolating in this range may induce significant errors. It is obvious that the relative accuracy, obtained with a tabular method, is strongly dependent on the granularity of the table that is not necessarily constant but must cover a significant part of the

(29)

This equation clearly defines the boundary between fast and slow input control. For a τIN value greater than this limit, the output transition time is input slew dependent, for lower values it is input slope independent. In this case, (1) of the logical effort model can be used with a good accuracy. This boundary also defines the first data point to be reported in the look-up table to accurately characterize the input slew sensitivity of the transition time. V. C ONCLUSION An accurate modeling of CMOS gate performance implies the full consideration of the gate structure, the I/O coupling, and the input ramp effects. To consider these realistic conditions, we have introduced an extension of the logical effort model. From the initial consideration of the switching condition of CMOS structures, we have defined an explicit logical effort expression for falling and rising edges of nonsymmetric gate. We have developed a realistic model of the gate performance by introducing a supply voltage and slew effort that can be calculated or evaluated on the process from the control conditions of the switching structure.

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 9, SEPTEMBER 2006

Validation of the model has been done on a 130-nm process by comparing calculated and simulated values (HSPICE) of the transition time and propagation delay of inverter, two input NAND and NOR, for different drive values for various loading and control conditions. The agreement obtained has given clear evidence of the accuracy of this simple representation of the timing performance of CMOS structures. Application has been given to the definition of a compact representation of CMOS library timing performance and to the choice of sampling points to be reported in traditional lookup tables.

R EFERENCES [1] F. Wang and S.-S. Chang, “Scalable delay model for logic and physical synthesis,” presented at the 16th IFIP World Computer Congr., Beijing, China, Aug. 21–24, 2000. [2] W.-T. Shiue and W. Wanalertlak, “Advanced cell modeling techniques based on polynomial expressions,” in Proc. 13th Int. Workshop Power and Timing Modeling Optimization and Simulation (PATMOS), pp. 550–558. [3] D. Markovic, V. Stojanovic, B. Nikolic, M. A. Horowitz, and R. Brodersen, “Methods for true energy-performance optimization,” IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1282–1292, Aug. 2004. [4] M. Orshansky and K. Keutzer, “A general probabilistic framework for worst case timing analysis,” in Proc. Design Automation Conf. (DAC), New Orleans, LA, Jun. 10–14, 2002, pp. 556–561. [5] Cadence openbook, Timing Library Format Reference, (2000, Oct.). 1. Product Version 4.3. [Online]. Available: http://www.cadence.com/ [6] I. Sutherland, B. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits. San Mateo, CA: Morgan Kaufmann, 1999. [7] C. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980. [8] X. Yu, V. G. Oklobdzija, and W. W. Walker, “Application of the logical effort on design arithmetic blocks,” in Proc. 35th Asilomar Conf. Signals, Systems and Computers, Pacific Grove, CA, Nov. 2001, pp. 872–874. [9] K. O. Jeppson, “Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay,” IEEE J. Solid-State Circuits, vol. 29, no. 6, pp. 646–654, Jun. 1994. [10] J. M. Daga and D. Auvergne, “A comprehensive delay macromodeling for submicron CMOS logics,” IEEE J. Solid-State Circuits, vol. 34, no. 1, pp. 42–55, Jan. 1999. [11] D. Auvergne, J. M. Daga, and M. Rezzoug, “Signal transition time effect on CMOS delay evaluation,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 47, no. 9, pp. 1362–1369, Sep. 2000. [12] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed. London, U.K.: Oxford Univ. Press, Jun. 2003. [13] T. Sakurai and A. R. Newton, “Alpha-power model, and its application to CMOS inverter delay and other formulas,” IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584–594, Apr. 1990. [14] P. Maurine, M. Rezzoug, N. Azémard, and D. Auvergne, “Transition time modeling in deep submicron CMOS,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 21, no. 11, pp. 1352–1363, Nov. 2002.

Benoit Lasbouygues received the M.S. degree in electrical engineering from Montpellier University, Montpellier, France, in 2003, and is currently working toward the Ph.D. degree at the Laboratory of Computer Sciences, Robotics and Microelectronics, University of Montpellier, in association with STMicroelectronics, Crolles, France. His research projects deal with high performance and low power design optimization. His interests include the modeling and analysis of environmental factors on design as voltage and temperature.

Sylvain Engels received the M.S. degree in electrical engineering from the National Polytechnic Institute of Grenoble, Grenoble, France, in 1999. In 2000, he joined the Central Research and Development Department of STMicroelectronics, Crolles, France, working on the qualification of design platforms. He is currently a Senior Engineer in the design of validation vehicles for advanced CMOS technologies. His research interests include low power design solutions, advanced design methodologies, and on-chip characterization.

Robin Wilson (M’91) received the B.Eng. degree in electrical engineering from the University College Cork, Cork, Ireland, in 1987. From 1987 to 1990, he worked within the semicustom development department of Plessey Semiconductors, Roborough, U.K. In 1990, he joined STMicroelectronics Central Research and Development Department, Crolles, France, where he is currently managing the qualification design department of the Central CAD and Design Solutions Group. His research interests include design qualification of advanced CMOS processes, statistical-based design, and logic diagnostics.

Philippe Maurine received the M.S. and Ph.D. degrees in electronics from the University of Science, Montpellier, France, in 1998 and 2001, respectively. Since 2003, he has been an Assistant Professor at the Laboratory of Computer Sciences, Robotics and Microelectronics, Montpellier, developing microelectronics in the engineering program of the university. His current field of research includes timing modeling, statistical timing analysis, and performance optimization of synchronous and asynchronous circuits.

Nadine Azémard received the M.S. and Ph.D. degrees in electronics from the University of Science of Montpellier, France, in 1987 and 1990, respectively. In 1991, she joined the CNRS and the Laboratory of Computer Sciences, Robotics and Microelectronics, Montpellier as a Searcher. She is also in charge of the development of timing analysis and optimization engine. Her current field of research includes timing analysis, timing optimization, and low power design.

Daniel Auvergne received the M.S. degree in electronics and the Ph.D. degree in solid-state physics from the University of Science, Montpellier, France, in 1966 and 1974, respectively. Since 1981, he has been a Professor at the Laboratory of Computer Sciences, Robotics and Microelectronics, Montpellier, developing microelectronics in the engineering program of the university. His current field of research includes the various aspects of very large-scale integration (VLSI) design at the physical level, such as timing and power modeling, automatic layout synthesis, performance optimization, and design for low power. He is the author or coauthor of more than 150 papers on solid state physics, integrated circuits, and design automation. He has been a reviewer for several journals. Dr. Auvergne has served on several technical program committees.