Logical Effort: Designing for Speed on the Back of an Envelope David Harris [email protected] Harvey Mudd College Claremont, CA

Outline o o o o o o o o

Introduction Delay in a Logic Gate Multi-stage Logic Networks Choosing the Best Number of Stages Example Asymmetric & Skewed Logic Gates Circuit Families Summary

Logical Effort

David Harris

Page 2 of 56

Introduction ? ? ?

Chip designers face a bewildering array of choices.

o o o

What is the best circuit topology for a function? How large should the transistors be? How many stages of logic give least delay?

Logical Effort is a method of answering these questions:

o o o

Uses a very simple model of delay Back of the envelope calculations and tractable optimization Gives new names to old ideas to emphasize remarkable symmetries

Who cares about logical effort?

o o o

Circuit designers waste too much time simulating and tweaking circuits High speed logic designers need to know where time is going in their logic CAD engineers need to understand circuits to build better tools

Logical Effort

David Harris

Page 3 of 56

Example

Decoder specification:

o o o o o

16 word register file Each word is 32 bits wide

16

Register File

Each bit presents a load of 3 unit-sized transistors True and complementary inputs of address bits a<3:0> are available Each input may drive 10 unit-sized transistors

Ben needs to decide:

o o o

How many stages to use? How large should each gate be? How fast can the decoder operate?

Logical Effort

David Harris

Page 4 of 56

16 words

4:16 Decoder

Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded processor for automotive applications. Help Ben design the decoder for a register file: 32 bits a<3:0> a<3:0>

Outline o o o o o o o o

Introduction Delay in a Logic Gate Multi-stage Logic Networks Choosing the Best Number of Stages Example Asymmetric & Skewed Logic Gates Circuit Families Summary

Logical Effort

David Harris

Page 5 of 56

Delay in a Logic Gate Let us express delays in a process-independent unit:

d abs d = ----------τ

τ ≈ 12 ps

in 0.18 µm technology

Delay of logic gate has two components: effort delay, a.k.a. stage effort

d = f+p

parasitic delay

Effort delay again has two components:

f = gh

o o

logical effort electrical effort = Cout/Cin

electrical effort is sometimes called “fanout”

Logical effort describes relative ability of gate topology to deliver current (defined to be 1 for an inverter) Electrical effort is the ratio of output to input capacitance

Logical Effort

David Harris

Page 6 of 56

Delay Plots

3 2

AN D

in ve rte r

4

g= p= d=

inp ut N

5

2-

Normalized delay: d

6

g= p= d=

effort delay

How about a 2-input NOR?

1 parasitic delay 1 2 3 4 5 Electrical effort: h = Cout / Cin

o d = f + p = gh + p o Delay increases with electrical effort o More complex gates have greater logical effort and parasitic delay Logical Effort

David Harris

Page 7 of 56

Computing Logical Effort DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current.

o o

Measured from delay vs. fanout plots of simulated or measured gates Or estimated, counting capacitance in units of transistor width:

a b

4

2 2

2

x

x

NOR2: Cin = 5 g = 5/3

4

x a

1

Inverter: Cin = 3 g = 1 (def)

Logical Effort

2 2

NAND2: Cin = 4 g = 4/3

David Harris

a b

1 1

Page 8 of 56

A Catalog of Gates Table 1: Logical effort of static CMOS gates Number of inputs Gate type 1 inverter

2

3

4

n

5

1

NAND

4/3

5/3

6/3

7/3

(n+2)/3

NOR

5/3

7/3

9/3

11/3

(2n+1)/3

multiplexer

2

2

2

2

2

XOR, XNOR

4

12

32

Table 2: Parasitic delay of static CMOS gates Gate type

Parasitic delay

inverter

pinv

n-input NAND

npinv

n-input NOR

npinv

n-way multiplexer

2npinv

p inv ≈ 1 parasitic delays depend on diffusion capacitance

2-input XOR, XNOR 4npinv

Logical Effort

David Harris

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Example Estimate the frequency of an N-stage ring oscillator:

Logical Effort:

g =

Electrical Effort:

h =

Parasitic Delay:

p =

Stage Delay:

d =

Oscillator Frequency: F =

Logical Effort

David Harris

Page 10 of 56

Example Estimate the delay of a fanout-of-4 (FO4) inverter:

d

Logical Effort:

g =

Electrical Effort:

h =

Parasitic Delay:

p =

Stage Delay:

d =

Logical Effort

David Harris

Page 11 of 56

Outline o o o o o o o o

Introduction Delay in a Logic Gate Multi-stage Logic Networks Choosing the Best Number of Stages Example Asymmetric & Skewed Logic Gates Circuit Families Summary

Logical Effort

David Harris

Page 12 of 56

Multi-stage Logic Networks Logical effort extends to multi-stage networks: 10

x

y z

g1 = 1 h1 = x/10

o

g2 = 5/3 h2 = y/x

g3 = 4/3 h3 = z/y

∏ gi

Path Logical Effort:

G =

o

Path Electrical Effort:

C out (path) H = ---------------------C in (path)

o

Path Effort:

F =

∏ fi = ∏ g i h i

20

g4 = 1 h4 = 20/z

Don’t define

H =

∏ hi

because we don’t know hi until the design is done

Can we write F = GH ? Logical Effort

David Harris

Page 13 of 56

Branching Effort No! Consider circuits that branch:

15 90

5 15

Logical Effort

90

G = H = GH = h1 = h2 = F =

David Harris

= GH?

Page 14 of 56

Delay in Multi-stage Networks We can now compute the delay of a multi-stage network:

o

Path Effort Delay:

o

Path Parasitic Delay:

o

Path Delay:

∑ fi PF = ∑ pi DF = ∑ di = D F + P DF =

We can prove that delay is minimized when each stage bears the same effort:

ˆf = g h = F 1 ⁄ N i i Therefore, the minimum delay of an N-stage path is:

NF

o

1⁄N

+P

This is a key result of logical effort. Lowest possible path delay can be found without even calculating the sizes of each gate in the path.

Logical Effort

David Harris

Page 15 of 56

Determining Gate Sizes Gate sizes can be found by starting at the end of the path and working backward.

o

At each gate, apply the capacitance transformation:

C in

o

i

C out • g i i = ---------------------ˆf

Check your work by verifying that the input capacitance specification is satisfied at the beginning of the path.

Logical Effort

David Harris

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Example z

Select gate sizes y and z to minimize delay

9C

from A to B

y A

Logical Effort:

C

G =

Electrical Effort:

H =

Branching Effort:

B =

Path Effort:

F =

Best Stage Effort:

ˆf =

Delay:

D =

z 9C

y

z

Work backward for sizes: z = y =

Logical Effort

David Harris

Page 17 of 56

B

9C

Outline o o o o o o o o

Introduction Delay in a Logic Gate Multi-stage Logic Networks Choosing the Best Number of Stages Example Asymmetric & Skewed Logic Gates Circuit Families Summary

Logical Effort

David Harris

Page 18 of 56

Choosing the Best Number of Stages How many stages should a path use?

o o

Delay is not always minimized by using as few stages as possible Example: How to drive 64 bit datapath with unit-sized inverter 1 1 1 1 Initial driver 4 2.8 8 16

8 22.6

Datapath load

N: f: D:

D = NF Logical Effort

64

64 1 64 65

1⁄N

+ P = N ( 64 )

64 2 8 18

1⁄N

64 Fastest 3 4 15

4 2.8 15.3

+ N assuming polarity doesn’t matter

David Harris

Page 19 of 56

Derivation of the Best Number of Stages Suppose we can add inverters to the end of a path without changing its function.

o

ˆ

How many stages should we use? Let N be the value of N for least delay.

N-n1 extra inverters

Logic Block: n1 stages Path effort F n1

D = NF

1⁄N

+

∑ pi + ( N – n1 )pinv 1

1⁄N 1⁄N 1⁄N ∂D ------- = – F ln ( F )+F + p inv = 0 ∂N

o

Define ρ ≡ F

ˆ 1⁄N

to be the best stage effort. Substitute and simplify:

p inv + ρ ( 1 – ln ρ ) = 0 Logical Effort

David Harris

Page 20 of 56

Best Number of Stages (continued) p inv + ρ ( 1 – ln ρ ) = 0 has no closed form solution.

o o

Neglecting parasitics (i.e. pinv = 0), we get the familiar result that ρ = 2.718 (e)

D(N) / D(N)

For pinv = 1, we can solve numerically to obtain ρ = 3.59 How sensitive is the delay to using exactly the best number of stages? 1 .6 1 .4 1 .2 1 .0

1 .5 1 1 .2 6 1 .1 5

I like to use ρ=4 (ρ = 2 .4 )

0 .0

0 .5

0 .7

1 .0

(ρ = 6 )

1 .4

2 .0

N /N

o

2.4 < ρ < 6 gives delays within 15% of optimal -> we can be sloppy

Logical Effort

David Harris

Page 21 of 56

Outline o o o o o o o o

Introduction Delay in a Logic Gate Multi-stage Logic Networks Choosing the Best Number of Stages Example Asymmetric & Skewed Logic Gates Circuit Families Summary

Logical Effort

David Harris

Page 22 of 56

Example

Decoder specification:

o o o o o

16 word register file Each word is 32 bits wide

16

Register File

Each bit presents a load of 3 unit-sized transistors True and complementary inputs of address bits a<3:0> are available Each input may drive 10 unit-sized transistors

Ben needs to decide:

o o o

How many stages to use? How large should each gate be? How fast can the decoder operate?

Logical Effort

David Harris

Page 23 of 56

16 words

4:16 Decoder

Let’s revisit Ben Bitdiddle’s decoder problem using logical effort: 32 bits a<3:0> a<3:0>

Example: Number of Stages How many stages should Ben use?

o o o

Effort of decoders is dominated by electrical and branching portions Electrical Effort: Branching Effort:

H = B =

If we neglect logical effort (assume G = 1),

o

Path Effort:

F =

Remember that the best stage effort is about ρ = 4

o

Hence, the best number of stages is: N =

Logical Effort

David Harris

Page 24 of 56

Example: Gate Sizes & Delay Lets try a 3-stage design using 16 4-input NAND gates with G = a0a0 a1a1 a2a2 a3a3 10 unit input capacitance

y

z

y z

o o o o

Actual path effort is: Therefore, stage effort should be: Gate sizes: Path delay:

Logical Effort

F = f = z = D =

David Harris

out0 96 unit wordline capacitance

out15

y =

Page 25 of 56

Example: Alternative Decoders Table 3: Comparison of Decoder Designs Design

Stages

G

P

D

NAND4; INV

2

2

5

29.8

INV; NAND4; INV

3

2

6

22.1

INV; NAND4; INV; INV

4

2

7

21.1

NAND2; INV; NAND2; INV

4

16/9

6

19.7

INV; NAND2; INV; NAND2; INV

5

16/9

7

20.4

NAND2; INV; NAND2; INV; INV; INV

6

16/9

8

21.6

INV; NAND2; INV; NAND2; INV; INV; INV

7

16/9

9

23.1

NAND2; INV; NAND2; INV; INV; INV; INV; INV 8

16/9

10

24.8

We underestimated the best number of stages by neglecting the logical effort.

o o o

Logical effort facilitates comparing different designs before selecting sizes Using more stages also reduces G and P by using multiple 2-input gates Our design was about 10% slower than the best

Logical Effort

David Harris

Page 26 of 56

Outline o o o o o o o o

Introduction Delay in a Logic Gate Multi-stage Logic Networks Choosing the Best Number of Stages Example Asymmetric & Skewed Logic Gates Circuit Families Summary

Logical Effort

David Harris

Page 27 of 56

Asymmetric Gates Asymmetric logic gates favor one input over another. Example: suppose input A of a NAND gate is most critical.

o o

Select sizes so pullup and pulldown still match unit inverter Place critical input closest to output 2

2

x a

4/3 4

o o o

Logical Effort on input A:

gA =

Logical Effort on input B:

gB =

Total Logical Effort:

g tot = g A + g B

Logical Effort

David Harris

b

Page 28 of 56

Symmetry Factor In general, consider gates with arbitrary symmetry factor s:

o o

s = 1/2 in symmetric gate with equal sizes

2

s = 1/4 in previous example

2

x a

1/(1-s) 1/s

Logical effort of inputs:

1 ------------ + 2 1–s g A = --------------------3

o o

gB

1 --- + 2 s = ------------3

1 -------------------- + 4 s(1 – s) g tot = ----------------------------3

Critical input approaches logical effort of inverter = 1 for small s But total logical effort is higher for asymmetric gates

Logical Effort

David Harris

Page 29 of 56

b

Skewed Gates Skewed gates favor one edge over the other. Example: suppose rising output of inverter is most critical.

o

Downsize noncritical NMOS transistor to reduce total input capacitance 2

2

x a

1/2

1

x a

x a

1

1/2

HI-Skewed inverter

Unskewed w/ Unskewed w/ equal rise equal fall Compare with unskewed inverter of the same rise/fall time to compute effort.

o o o

Logical Effort for rising (up) output:

gu =

Logical Effort for falling (down) output:

gd =

Average Logical Effort:

g avg = ( g u + g d ) ⁄ 2

Logical Effort

David Harris

Page 30 of 56

HI- and LO-Skewed Gates DEF: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. Skew gates by reducing size of noncritical transistors.

o o o o

HI-Skewed gates favor rising outputs by downsizing NMOS transistors LO-Skewed gates favor falling outputs by downsizing PMOS transistors Logical effort is smaller for the favored input due to lower input capacitance Logical effort is larger for the other input

Logical Effort

David Harris

Page 31 of 56

Catalog of Skewed Gates Inverter

NAND2

NOR2

4

2 2

2

4

HI-Skew ½

gu = 5/6 gd = 5/3 gavg = 5/4

1 1

gu = 1 gd = 2 gavg = 3/2

½ ½

2

1 1

1

gu = 3/2 gd = 3 gavg = 9/4

2

gu = 2 gd = 1 gavg = 3/2

LO-Skew 1

Logical Effort

gu = 4/3 gd = 2/3 gavg = 1

2 2

gu = 2 gd = 1 gavg = 3/2

David Harris

1 1

Page 32 of 56

Outline o o o o o o o o

Introduction Delay in a Logic Gate Multi-stage Logic Networks Choosing the Best Number of Stages Example Asymmetric & Skewed Logic Gates Circuit Families Summary

Logical Effort

David Harris

Page 33 of 56

Pseudo-NMOS Pseudo-NMOS gates replace fat PMOS pullups on inputs with a resistive pullup.

o o o o o

Resistive pullup must be much weaker than pulldown stack (e.g. 4x) Reduces logical effort because inputs must only drive the NMOS transistors However, NMOS current reduced by contention with pullup Unequal rising and falling efforts Quiescent power dissipation when output is low

2/3

Example: Pseudo-NMOS inverter

o o o

x

Logical Effort for falling (down) output:

gd =

Logical Effort for rising (up) output:

gu =

Average Logical Effort:

g avg = ( g u + g d ) ⁄ 2

Logical Effort

David Harris

a

Page 34 of 56

4/3

Pseudo-NMOS Gates

Inverter

NAND2

NOR2

2/3

2/3

2/3

x a

4/3

gd = 4/9 gu = 4/3 gavg = 8/9

x a

8/3

b

8/3 gd = 8/9 gu = 8/3 gavg = 16/9

x a

4/3 4/3

b

gd = 4/9 gu = 4/3 gavg = 8/9

Tradeoffs exist between power and effort by varying P/N ratio.

Logical Effort

David Harris

Page 35 of 56

Dynamic Logic Dynamic logic replace fat PMOS pullups on inputs with a clocked precharge.

o o o o

Reduces logical effort because inputs must only drive the NMOS transistors Eliminates pseudo-NMOS contention current and power dissipation Only the falling (“evaluation”) delay is critical Downsize noncritical precharge transistors to reduce clock load and power

φ

Example: Footless dynamic inverter

o

Logical Effort for falling (down) output:

gd =

1

x a

1

Robust gates may require keepers and clocked pulldown transistors (“feet”).

o o

Feet prevent contention during precharge but increase logical effort Weak keepers prevent floating output at cost of slight contention during eval

Logical Effort

David Harris

Page 36 of 56

Dynamic Gates Inverter φ Footless

φ

1

a

1

φ

1

φ

2 2

gd = 2/3

a

2

b

2

φ

1

x a

1

1

b gd = 1/3

gd = 2/3

φ

1

x a

3

b

3

φ

Logical Effort

1

x

x a

NOR2 φ

1

x gd = 1/3

Footed

NAND2

x a

gd = 1

φ

2

2

b gd = 2/3

2

3

David Harris

Page 37 of 56

Domino Gates Dynamic gates require monotonically rising inputs.

o o o

However, they generate monotonically falling outputs Alternate dynamic gates with HI-skew inverting static gates Dynamic / static pair is called a domino gate

Example: Domino Buffer

o o o o o o o o

Constraints: maximum input capacitance = 3, load = 54 Logical Effort:

G=

Branching Effort: B = Electrical Effort:

H=

Path Effort:

F=

Stage Effort:

f=

φ

p HI-Skew 54

a

HI-Skew Inverter: size = Transistor Sizes: n = p =

Logical Effort

3

David Harris

3

n

g1

g2

Page 38 of 56

Comparison of Circuit Families Assumptions:

o o o

PMOS transistors have half the drive of NMOS transistors Skewed gates downsize noncritical transistors by factor of two Pseudo-NMOS gates have 1/4 strength pullups Table 4: Summary of Logical Efforts Inverter g Circuit Style

gd

gu

Static CMOS

n-input NAND g gu

1

gd

n-input NOR g gu

(n+2)/3

gd (2n+1)/3

HI-Skew

5/6

5/3

(n/2+2)/3

(n+4)/3

(2n+.5)/3

(4n+1)/3

LO-Skew

4/3

2/3

2(n+1)/3

(n+1)/3

2(n+1)/3

(n+1)/3

Pseudo-NMOS

4/3

4/9

4n/3

4n/9

4/3

4/9

Footed Dynamic

2/3

(n+1)/3

2/3

Footless Dynamic

1/3

n/3

1/3

Adjust these numbers as you change your assumptions.

Logical Effort

David Harris

Page 39 of 56

Outline o o o o o o o o

Introduction Delay in a Logic Gate Multi-stage Logic Networks Choosing the Best Number of Stages Example Asymmetric & Skewed Logic Gates Circuit Families Summary

Logical Effort

David Harris

Page 40 of 56

Summary Table 5: Key Definitions of Logical Effort Term

Stage expression

Logical effort

g

Electrical effort

C out h = --------C in

Branching effort

n/a

(seeTable 1)

Path expression

C out (path) H = ---------------------C in (path)

B = Effort

∏ bi

f = gh f

F = GBH

Number of stages

1

N

Parasitic delay

p

Delay

d = f+p

Effort delay

Logical Effort

∏ gi

G =

(seeTable 2)

David Harris

DF =

P =

∑ fi

∑ pi

D = DF + P Page 41 of 56

Method of Logical Effort Logical effort helps you find the best number of stages, the best size of each gate, and the minimum delay of a circuit with the following procedure:

o

Compute the path effort:

o

Estimate the best number of stages:

F = GBH ˆ ≈ log F N

o

Estimate the minimum delay:

ˆ 1⁄N ˆ D = NF +P

o

Sketch your path using the number of stages computed above

o o

4

ˆf = F 1 ⁄ N

Compute the stage effort:

Starting at the end, work backward to find transistor sizes:

C in

Logical Effort

David Harris

i

C out • g i i = ---------------------ˆf

Page 42 of 56

Limitations of Logical Effort Logical effort is not a panacea. Some limitations include:

o o o

Chicken & egg problem how to estimate G and best number of stages before the path is designed Simplistic delay model neglects effects of input slopes Interconnect iteration required in designs with branching and non-negligible wire C or RC same convergence difficulties as in synthesis / placement problem

o

Maximum speed only optimizes circuits for speed, not area or power under a fixed speed constraint

Logical Effort

David Harris

Page 43 of 56

Conclusion Logical effort is a useful concept for thinking about delay in circuits:

o o o o o o

Facilitates comparison of different circuit topologies Easily select gate sizes for minimum delay Circuits are fastest when effort delays of each stage are equal and about 4 Path delay is insensitive to modest deviations from optimal sizes Logic gates can be skewed to favor one input or edge at the cost of another Logical effort can be applied to domino, pseudo-NMOS, and other logic families

Logical effort provides a language for engineers to discuss why circuits are fast.

o

Like any language, requires practice to master

A book on Logical Effort is available from Morgan Kaufmann Publishers

o http://www.mkp.com/Logical_Effort o Discusses P/N ratios, gate characterization, pass gate logic, forks, wires, etc. Logical Effort

David Harris

Page 44 of 56

Delay Plots

3 2

AN D

g=1 p=1 d=h+1

in ve rte r

4

g = 4/3 p=2 d = (4/3)h + 2

inp ut N

5

2-

Normalized delay: d

6

effort delay

1 parasitic delay 1 2 3 4 5 Electrical effort: h = Cout / Cin

o d = f + p = gh + p o Delay increases with electrical effort o More complex gates have greater logical effort and parasitic delay Logical Effort

David Harris

Page 45 of 56

Example Estimate the frequency of an N-stage ring oscillator:

Logical Effort:

g≡1

Electrical Effort:

out h = --------= 1

Parasitic Delay:

p = p inv ≈ 1

Stage Delay:

d = gh + p = 2

C C in

1 2Nd abs

1 4N τ

Oscillator Frequency: F = ------------------- = -----------

Logical Effort

David Harris

A 31 stage ring oscillator in a 0.18 µm process oscillates at about 670 MHz.

Page 46 of 56

Example Estimate the delay of a fanout-of-4 (FO4) inverter:

d

Logical Effort:

g≡1

Electrical Effort:

out h = --------= 4

Parasitic Delay:

p = p inv ≈ 1

Stage Delay:

d = gh + p = 5

C C in

The FO4 inverter delay is a useful metric to characterize process performance. 1 FO4 delay = 5τ This is about 60 ps in a 0.18 µm process.

Logical Effort

David Harris

Page 47 of 56

Branching Effort No! Consider circuits that branch:

15

G =1 H = 90 / 5 = 18 GH = 18 h1 = (15+15) / 5 = 6 h2 = 90 / 15 = 6 F = 36, not 18!

90

5 15

90

Introduce new kind of effort to account for branching within a network:

o

Branching Effort:

C on path + C off path b = ---------------------------------------------C on path

o

Path Branching Effort:

B =

∏ bi

Now we can compute the path effort:

o

Path Effort:

Logical Effort

F = GBH David Harris

Note:

∏ hi = BH ≠ H in circuits that branch

Page 48 of 56

Example z

Select gate sizes y and z to minimize delay

9C

from A to B

y

z

A C 3

Logical Effort:

G = (4 ⁄ 3)

Electrical Effort:

C out H = --------- = 9 C in

Branching Effort:

B = 2•3 = 6

Path Effort:

F = GHB = 128

Best Stage Effort:

ˆf = F 1 ⁄ 3 ≈ 5

Delay:

D = 3 • 5 + 3 • 2 = 21

9C

y

z

David Harris

9C

Work backward for sizes:

9C • (4 ⁄ 3) z = ----------------------------- = 2.4 C 5

3z • ( 4 ⁄ 3 )- = 1.92 C y = ---------------------------

5

Logical Effort

B

Page 49 of 56

Example: Number of Stages How many stages should Ben use?

o

Effort of decoders is dominated by electrical and branching portions

o

Electrical Effort:

o

Branching Effort:

•3 H = 32 --------------- = 9.6 10 B = 8 because each address input controls half the outputs

If we neglect logical effort,

o

Path Effort:

F = GBH = 8 • 9.6 = 76.8

Remember that the best stage effort is about ρ = 4

o o

Hence, the best number of stages is: N = log 476.8 = 3.1 Let’s try a 3-stage design

Logical Effort

David Harris

Page 50 of 56

Example: Gate Sizes & Delay Lets try a 3-stage design using 16 4-input NAND gates with G = 1 • 2 • 1 = 2 a0a0 a1a1 a2a2 a3a3 10 unit input capacitance

y

z

y z

o

Actual path effort is:

out0 96 unit wordline capacitance

out15

F = 2 • 8 • 9.6 = 154

o Therefore, stage effort should be: f = ( 154 )1 ⁄ 3 = 5.36 o z = 96 • 1 ⁄ 5.36 = 18 y = 18 • 2 ⁄ 5.36 = 6.7 o D = 3f + P = 3 • 5.36 + 1 + 4 + 1 = 22.1 Logical Effort

David Harris

Close to 4, so f is reasonable

Page 51 of 56

Asymmetric Gates Asymmetric logic gates favor one input over another. Example: Suppose input A of a NAND gate is most critical:

o o

Select sizes so pullup and pulldown still match unit inverter Place critical input closest to output 2

2

x a

4/3 4

o o o

b

Logical Effort on input A:

g A = 10 ⁄ 9

Logical Effort on input B:

gB = 2

Total Logical Effort:

g tot = g A + g B = 28 ⁄ 9

Logical Effort

David Harris

Effort on A goes down at expense of effort on B and total gate effort

Page 52 of 56

Skewed Gates Skewed gates favor one edge over the other. Example: suppose rising output of inverter is most important.

o

Downsize noncritical NMOS transistor to reduce total input capacitance 2

2

x a

1/2

1

x a

1

x a

1/2

Skewed inverter

Unskewed w/ Unskewed w/ equal rise equal fall Critical rising Compare with unskewed inverter of the same rise/fall time effort goes down o Logical Effort for rising (up) output: gu = 5 ⁄ 6 at expense of noncritical and o Logical Effort for falling (down) output: g d = 5 ⁄ 3 average effort

o

g avg = ( g u + g d ) ⁄ 2 = 5 ⁄ 4

Average Logical Effort:

Logical Effort

David Harris

Page 53 of 56

Pseudo-NMOS Pseudo-NMOS gates replace fat PMOS pullups on inputs with a resistive pullup.

o o o o o

Resistive pullup must be much weaker than pulldown stack (e.g. 4x) Reduces logical effort because inputs must only drive the NMOS transistors However, NMOS current reduced by contention with pullup Unequal rising and falling efforts Logical effort can be applied to domino, pseudo-NMOS, and other logic families

2/3 Example: Pseudo-NMOS inverter

o o o

x

Logical Effort for falling (down) output:

gd = 4 ⁄ 9

Logical Effort for rising (up) output:

gu = 4 ⁄ 3

Average Logical Effort:

g avg = ( g u + g d ) ⁄ 2 = 8 ⁄ 9

Logical Effort

David Harris

a

Page 54 of 56

4/3

Dynamic Logic Dynamic logic replace fat PMOS pullups on inputs with a clocked precharge.

o o o

Reduces logical effort because inputs must only drive the NMOS transistors Eliminates pseudo-NMOS contention current and power dissipation Critical pulldown (“evaluation”) delay independent of precharge size

φ

Example: Footless dynamic inverter

o

Logical Effort for falling (down) output:

gd = 1 ⁄ 3

1

x a

1

Robust gates may require keepers and clocked pulldown transistors (“feet”).

o o

Feet prevent contention during precharge but increase logical effort Weak keepers prevent floating output at cost of slight contention during eval

Logical Effort

David Harris

Page 55 of 56

Domino Gates Dynamic gates require monotonically rising inputs.

o o o

However, they generate monotonically falling outputs Alternate dynamic gates with HI-skew inverting static gates Dynamic / static pair is called a domino gate

Example: Domino Buffer

o o o o o o o o

Constraints: maximum input capacitance = 3, load = 54 Logical Effort:

G = (1/3) * (5/6) = 5/18

Branching Effort: B = 1 Electrical Effort:

H = 54/3 = 18

Path Effort:

F = (5/18) * 1 * 18 = 5

Stage Effort:

f=

5 = 2.2

HI-Skew Inverter: size =54 * (5/6) / 2.2 = 20

φ

3

p HI-Skew 54

a

3 g1 = 1/3

n g2 = 5/6

Transistor Sizes: n = 4 p = 16

Logical Effort

David Harris

Page 56 of 56

Logical Effort - Semantic Scholar

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