IJRIT International Journal of Research in Information Technology, Volume 1, Issue 11, November, 2013, Pg. 406-418

International Journal of Research in Information Technology (IJRIT)

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ISSN 2001-5569

LUT Based Computing for Memory Size Reduction T.Thangam1, K.Gowri2 1

Associate Professor, Department of ECE ,

PSNA College of Engineering and technology, Dindigul, Tamilnadu, India [email protected] 2

Associate Professor,

Department of ECE ,PSNA College of Engineering and technology, Dindigul, Tamilnadu, India [email protected]

Abstract In this paper we propose a memory based multiplier that uses LUT design for reduced memory size by a factor of two. The advantages of antisymmetric product coding (APC) and odd-multiple-storage (OMS) techniques were combined together to design an efficient memory-based multiplier to provide a reduction in LUT size to one fourth of the conventional LUT. The proposed LUT based multiplier involves 12-bit word size. This LUT design can be used for efficient implementation of high precision multiplication through input operand decomposition. The area and delay were also shown to be improved with existing results.

Keywords: Digital Signal Processing (DSP), Look-Up- Table (LUT), Antisymmetric Product Coding (APC), Odd- Multiple-Storage (OMS).

1. Introduction A memory unit has several specific applications, which include mobile devices, consumer products, automotive, biomedical instruments and space applications. The upcoming memories are expected to provide faster access and to consume less power. Embedded memories will have dominating presence in the system on- chips (SoCs), which may exceed 90%, of the total SoC content. [1].When the computational functions are performed by look-up tables (LUTs), instead of actual calculation, it closely resembles to human-like computing and the memory based computations are simple to design and offer advantages like greater potential for high-throughput, low-latency T.Thangam,

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implementation and less dynamic power. Lookup tables are tables that store numeric data in a multidimensional array consumption format. The savings in terms of processing time can be significant since retrieving a value from memory is often faster than undergoing an 'expensive' computation or input/output operation. The tables may be precalculated and stored in static program storage or calculated as part of a program initialization phase (memorization). A conventional lookup-table (LUT)-based multiplier is shown in Fig.1 [1], i n w h i c h t h e fixed coefficient A will be multiplied with input word A.

Fig.1. Conventional LUT-based multiplier

The positive binary input X with word length L generate 2L possible values of X . T h e n u m b e r o f p r o d u c t t e r m i s C = A.X for 2L possible values of 2L. Therefore, for memory-based multiplication, LUT of 2L words, consisting of precomputed product values corresponding to all possible values of X, is conventionally used. The product word (A.Xi) is stored at the location Xi for 0 ≤ Xi ≤ 2L − 1, such that if an L-bit binary value of Xi is used as the address for the LUT, then the corresponding product value ( A. Xi) is available as its output. In odd-multiple-storage (OMS) scheme to design a LUT, only the odd multiples of the fixed coefficient are required to be stored whereas the antisymmetric product coding (APC) approach reduces the LUT size to half as the product words are recoded as anti-symmetric pairs[2,3]. The APC techniques reduce the LUT table size by a factor of two. However, the OMS technique cannot be combined with the APC scheme, since the APC words generated according to odd numbers [4]. T h e r e f o r e , APC approach and modified OMS T echniq ue is combined to simplify the two’s complement operations since the input address and LUT output could always be transformed into odd integers for efficient memory based multiplication[5]. In this paper, we discuss the design of 12 bits word size LUT multiplier which is based on the work done in ref [1].

2. PROPOSED LUT DESIGN BASED ON APC AND MODIFIED OMS TECHNIQUE This section discusses about the proposed APC technique and its further optimization by combining it with a modified form of OMS. 2.1 APC technique for LUT X and A in Fig.1 are assumed be positive integers [6,7]. The table 1 shows the product words for a word X with length L = 7. It is observed that the input word X on the first column of each row is the two’s complement of that on the third column of the same row [1]. In addition, the sum of product values corresponding to these two input values on the same row is 128A. Let the product values on the second and fourth columns of a row be u and v respectively. Since u = [(u + v)/2 − (v − u)/2] and v = [(u + v)/2 + (v − u)/2], for (u + v) = 128A, we get

v − u  u = 64 A −   2 

v − u  v = 64 A +   2 

(1)

As the product values on the second and fourth columns of table 1 have a negative mirror symmetry, product words can be used to reduce the LUT size and instead of storing u and v, only [(v − u)/2] is stored for a pair of input on a given row. The 6-bit LUT addresses and corresponding coded words are listed on the fifth and sixth columns of the table1, respectively. The 6-bit address X = ( x 5 x 4 x 3 x 2 x 1 x 0 ) of the antisymmetric product code (APC) word is given by '

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'

'

'

'

'

'

407

 X L' X' = '  X L' where

if x6 = 1   if x6 = 0

(2)

X L = (x5 x4 x3x2 x1x0 ) is the six less significant bits of

X, and X’L is the two’s complement of X L. By

adding or subtracting the stored value (v − u) to or from the fixed value 64A when x6 is 1 or 0, the desired product can be obtained using the formula, Product word = 64A + (sign value) × (APC word) (3) sign value = 1 for x6 = 1 and sign value = −1 for x6 = 0. The product value for X = (1000000) corresponds to APC value “zero,” which could be derived by resetting the LUT output, instead of storing that in the LUT.

Table.1 APC words for different input values for L=7 Input ,X 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 T.Thangam,

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Product Values A 2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A 13A 14A 15A 16A 17A 18A 19A 20A 21A 22A 23A 24A 25A 26A 27A 28A 29A 30A 31A 32A

Input ,X 1111111 1111110 1111101 1111100 1111011 1111010 1111001 1111000 1110111 1110110 1110101 1110100 1110011 1110010 1110001 1110000 1101111 1101110 1101101 1101100 1101011 1101010 1101001 1101000 1100111 1100110 1100101 1100100 1100011 1100010 1100001 1100000

Product Values 127A 126A 125A 124A 123A 121A 121A 120A 119A 118A 117A 116A 115A 114A 113A 112A 111A 110A 109A 108A 107A 106A 105A 104A 103A 102A 101A 100A 99A 98A 97A 96A

Address x’5x’4x’3x’2x’1x’0 111111 111110 111101 111100 111011 111010 111001 111000 110111 110110 110101 110100 110011 110010 110001 110000 101111 101110 101101 101100 101011 101010 101001 101000 100111 100110 100101 100100 100011 100010 100001 100000

APC words 63A 62A 61A 60A 59A 58A 57A 56A 55A 54A 53A 52A 51A 50A 49A 48A 47A 46A 45A 44A 43A 42A 41A 40A 39A 38A 37A 36A 35A 34A 33A 32A

408

Input ,X 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000

Product Values 33A 34A 35A 36A 37A 38A 39A 40A 41A 42A 43A 44A 45A 46A 47A 48A 49A 50A 51A 52A 53A 54A 55A 56A 57A 58A 59A 60A 61A 62A 63A 64A

Input ,X 1011111 1011110 1011101 1011100 1011011 1011010 1011001 1011000 1010111 1010110 1010101 1010100 1010011 1010010 1010001 1010000 1001111 1001110 1001101 1001100 1001011 1001010 1001001 1001000 1000111 1000110 1000101 1000100 1000011 1000010 1000001 1000000

Product Values 95A 94A 93A 92A 91A 90A 89A 88A 87A 86A 85A 84A 83A 82A 81A 80A 79A 78A 77A 76A 75A 74A 73A 72A 71A 70A 69A 68A 67A 66A 65A 64A

Address x’5x’4x’3x’2x’1x’0 011111 011110 011101 011100 011011 011010 011001 011000 010111 010110 010101 010100 010011 010010 010001 010000 001111 001110 001101 001100 001011 001010 001001 001000 000111 000110 000101 000100 000011 000010 000001 000000

APC words 31A 30A 29A 28A 27A 26A 25A 24A 23A 22A 21A 20A 19A 18A 17A 16A 15A 14A 13A 12A 11A 10A 9A 8A 7A 6A 5A 4A 3A 2A A 0

2.2 Modified OMS for LUT design It is shown in [2] that, for the multiplication of any binary word X of size L, with a fixed coefficient A, instead of storing all the 2L possible values of C = A . X, only (2L/2) words corresponding to the odd multiples of A may be stored in the LUT, while all the even multiples of A could be derived by left-shift operations of one of those odd multiples. The LUT for the multiplication of an L-bit input with a W-bit coefficient may be designed by the algorithm used in ref [1]. In Table 2, a s shown that, at t h i r t y t w o memory locations, the eight odd multiples, A × (2i + 1) are stored as Pi, for i = 0, 1, 2. . . 31.A barrel shifter for producing a maximum of five left shifts could be used to derive all the even multiples of A. As required by (3), the word to be stored for X = (0000000) is 64A, which is obtained from A by six left shifts using a barrel shifter. I f 64A is not derived from A, only a maximum of five left shifts is required to obtain all other even multiples of A. A maximum of five bit shifts can be implemented by a two-stage logarithmic barrel shifter, but the implementation of six shifts requires a five- stage barrel shifter. Therefore, T.Thangam,

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to store 2A for input X = (0000000), the product 64A can be derived by five arithmetic left shifts. The product values and encoded words for input words X = (0000000) and (1000000) are separately shown in Table 3. For X = (0000000), the desired encoded word 64A is derived by 5-bit left shifts of 2A [stored at address (100000)]. For X = (1000000), the APC word “0” is derived by resetting the LUT output, by an active-high RESET signal given by RESET = ( x 0 + x 1 + x 2 + x 3 + x 4 + x 5 ) x 6 (4)

It may be seen from Tables 2 and 3 that the 7-bit input word X can be mapped into a 6-bit LUT address (d5d4d3d2d1d0), by a simple set of mapping relations

d i = x '' i + 1 d5 = x

''

for i = 0,1, 2,3, 4

(5)

0

where X”= (x”5x”4x”3x”2x”1x”0) is generated by shifting-out all the leading zeros of X’ by an arithmetic right shift followed by address mapping, i.e.,

YL' X '' =  ' Y L'

if x6 = 1   if x6 = 0

(6)

Table.2 OMS based design of LUT of APC words for L=7 Input ,X’ x’5x’4x’3x’2x’1x’0

Product Values

# of shifts

000001 000010 000100 001000 010000 100000 000011 000110 001100 011000 110000 000101 001010 010100 101000 000111 001110 011100 111000 001001 010010 100100

A 2×A 4×A 8×A 16×A 32×A 3A 2×3A 4×3A 8×3A 16×3A 5A 2×5A 4×5A 8×5A 7A 2×7A 4×7A 8×7A 9A 2×9A 4×9A

0 1 2 3 4 5 0 1 2 3 4 0 1 2 3 0 1 2 3 0 1 2

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Shifted Input ,X”

Stored APC words

Address d5d4d3d2d1d0

000001

P0=A

000000

000011

P1=3A

000001

000101

P2=5A

000010

000111

P3=7A

000011

001001

P4=9A

000100

410

001011 010110 101100 001101 011010 110100 001111 011110 111100 010001 100010 010011 100110 010101 101010 010111 101110 011001 110010 011011 110110 011101 111010 011111 111110 100001 100011 100101 100111 110111 111001 111011 111101 111111

11A 2×11A 4×11A 13A 2×13A 4×13A 15A 2×15A 4×15A 17A 2×17A 19A 2×19A 21A 2×21A 23A 2×23A 25A 2×25A 27A 2×27A 29A 2×29A 31A 2×31A 33A 35A 37A 39A 55A 57A 59A 61A 63A Input ,X x6x5x4x3x2x1x0 1000000 0000000

0 1 2 0 1 2 0 1 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0

001011

P5=11A

000101

001101

P6=13A

000110

001111

P7=15A

000111

010001

P8=17A

001000

010011

P9=19A

001001

010101

P10=21A

001010

010111

P11=23A

001011

011001

P12=25A

001100

011011

P13=27A

001101

011101

P14=29A

001110

011111

P15=31A

001111

100001 100011 100101 100111 110111 111001 111011 111101 111111

P16=33A P17=35A P18=37A P19=39A P27=55A P28=57A P29=59A P30=61A P31=63A

010000 010001 010010 010011 011011 011100 011101 011110 011111

Product Values 64A 0

Encoded Word 0 64A

Stored Values --2A

# of shifts -5

Address d5d4d3d2d1d0 -----100000

Table.3 Products and encoded words for X=(0000000) AND (1000000)

3. MULTIPLIER DESIGN USING MODIFIED LUT TABLE 3.1. Design of Multiplier using APC for L =7 The fig.2 shows the structure of LUT-based multiplier for a word length of L = 7. The APC technique is used which consist of a six-input LUT of 64 words to store the APC values of product words as given in the sixth column of T.Thangam,

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Table 1, except on the last row, where 2A is stored for input X = (0000000) instead of storing a “0” for input X = (1000000). An Multiplexer circuit is used for generating 7-bit addresses (x’5x’4x’3x’2x’1x’0) according to (2), where x6 is the control bit and (x5x4x3x2x1x0) are inputs. The equation (4) is used for generating RESET control signal. The output of the LUT is added with or subtracted from 64A, for x6 = 1or 0, respectively, according to (3) by the add/subtract cell. Hence, x6 is used as the control for the add/subtract cell.

3.2. Implementation of the Designed LUT Using Modified OMS The proposed APC–OMS combined design of the LUT for L = 7 and for any coefficient width W is shown in Fig. 3. It consists of an LUT of nine words of (W + 4)-bit width, a six-to-thirty three-line address decoder, a barrel shifter, an address generation circuit, and a control circuit for generating the RESET signal and control word (s1s0) for the barrel shifter. The precomputed values of A × (2i + 1) are stored as Pi, for i = 0, 1, 2, . . . , 31, at the thirty two consecutive locations of the memory array, as specified in Table 2, while 2A is stored for input X = (0000000) at LUT address “100000,” as specified in Table 3. The decoder takes the 6-bit address from the address generator and generates thirty three word-select signals, i.e., {wi, for 0 ≤ i ≤ 32}, to select the referenced word from the LUT. The 6-to-33line decoder is a simple modification of 5-to-32-line decoder, as shown in Fig. 4a. The control bits s0 and s1 to be used by the barrel shifter to produce the desired number of shifts of the LUT output are generated by the control circuit. Note that (s1s0) is a 2-bit binary equivalent of the required number of shifts specified in Tables 2 and 3. The RESET signal given by (4) can alternatively be generated as (d5 AND x6). The control circuit to generate the control word and RESET is shown in Fig. 4b. The address-generator circuit receives the 7-bit input operand X and maps that onto the 6-bit address word (d5d4d3d2d1d0), according to (5) and (6). A simplified address generator is presented later in this section.

Fig. 2. LUT-based multiplier for L = 7 using the APC technique

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Fig. 3. Proposed APC–OMS combined LUT design for the multiplication of W-bit fixed coefficient A with 7-bit input X

Fig. 4a Five -to-thirty two line address-decoder

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Fig. 4b Control circuit for generation of s0, s1, and RESET.

3.3 LUT Design for Signed and Unsigned Operands The APC–OMS combined optimization of the LUT can also be performed for signed values of A and X. When both operands are in sign-magnitude form, the multiples of magnitude of the fixed coefficient are to be stored in the LUT, and the sign of the product could be obtained by the XOR operation of sign bits of both multiplicands. When both operands are in two’s complement forms, a two’s complement operation of the output of the LUT is required to be performed for x6 = 1. There is no need to add the fixed value 64A in this case, because the product values are naturally in anti-symmetric form. The add/subtract circuit is not required in Fig. 2, instead of that a circuit is required to perform the two’s complement operation of the LUT output. For the multiplication of unsigned input X with signed, as well as unsigned, coefficient A, the products could be stored in two’s complement representation, and the add/subtract circuit in Fig. 2 could be modified as shown in Fig. 5. A straightforward implementation of sign-modification circuit involves multiplexing of the LUT output and its two’s complement. To reduce the area–time complexity over such straightforward implementation, we discuss here a simple design for sign modification of the LUT output.Note that, except the last word, all other words in the LUT are odd multiples of A. The fixed coefficient could be even or odd, but if we assume A to be an odd number, then the all the stored product words (except the last one) would be odd. If the stored value P is an odd number, it can be expressed as P = PD−1 PD −2 ........Pi ` (7) and its two’s complement is given by

P ' = P ' D −1 P ' D − 2 ........P ' i

` (8) Where P’i is the one’s complement of Pi for 1 ≤ i ≤ D − 1, and D = W + L − 1 is the width of the stored words. If we store the two’s complement of all the product values and change the sign of the LUT output for x6 = 1, then the sign of the last LUT word need not be changed. Based on (7,8), we can therefore have a simple sign-modification circuit [shown in Fig. 6(a)] when A is an odd integer. However, the fixed coefficient A could be even as well. When A is a integer. Instead of storing multiples of A, we nonzero even integer, we can express it as A’ × 2l, and A’ is an odd can store multiples of A’ in the LUT, and the LUT output can be left shifted by l bits by a hardwired shifter. Similarly, using (5) and (6), we can have an address-generation circuit as shown in Fig. 6(b), since all the shiftedaddress YL (except the last one) is an odd integer.

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Fig. 5. Modification of the add/subtract cell in Fig. 2 for the two’s complement representation of product words.

Fig. 6a Optimized implementation of the sign modification of the odd LUT output.

Fig. 6. (b) Address-generation circuit.

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4. RESULTS

Fig.7 LUT APC–OMS Optimization Top Module Symbol

Fig. 8. RTL schematic of Top Module

Fig.9. Simulation Result Table 4 Performance analysis of LUT based multiplier for different word length. Wor d size

8 bit

16 bit

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Addition scheme (Area)

CSD based multiplier (Time Delay)

Proposed LUT Based Used Un Used

Total Slack detectio n

CSD based multiplier (Time Delay)

Carry Selective Difference

12.365ns

4

9315

9319

0.087ns

Wallace Tree

12.452ns

8

9311

9319

--------

Carry Selective Difference

12.965ns

8

9311

9319

0.314ns

Wallace Tree

13.279ns

16

9303

9319

0.326ns

416

32 bit

Carry Selective Difference Wallace Tree

16.524ns

16

9303

9319

2.270ns

14.254ns

32

9287

9319

0.544ns

SYNTHESIS REPORT Source Parameters Input File Name Input Format Ignore Synthesis Constraint File

: "APC_OMS.prj" : mixed : NO

Target Parameters Output File Name Output Format Target Device

: "APC_OMS" : NGC : xc3s500e-4-fg320

Device utilization summary Selected Device Number of Slices Number of 4 input LUTs Number of IOs Number of bonded IOBs

: 3s500efg320-4 : 13 out of 4656 0% : 25 out of 9312 0% : 27 : 27 out of 232 11%

Timing Detail All values displayed in nanoseconds (ns) Timing constraint: Default path analysis Total number of paths / destination ports : 291 / 19 Delay : 9.761ns Source : X<4> (PAD) Destination : APC_PROD<10> (PAD) Data Path : X<4> to APC_PROD<10> Total : 9.761ns (7.520ns logic, 2.241ns route) (77.0% logic, 23.0% route) CPU : 0.42 / 6.28 s [ Elapsed: 0.00 / 6.00 s] Total memory usage : 159444 kilobytes Number of errors : 0 (0 filtered) Number of warnings : 26 (0 filtered) Number of infos : 2 (0 filtered)

4. Conclusion The proposed LUT multipliers for W x L = 12x7 is coded in VHDL and synthesized in XilinxISE 10.1i. Modelsim 6.3c is used for simulation, where the LUTs are implemented as arrays of constants, and additions are implemented by the Carry selective difference and Wallace tree. we have shown the possibility of using LUT based multipliers for reduced memory size.

5. REFERENCES [1] P. K . Meher, “LUT optimization for memory-based computation,” Trans. Circuits Syst.II, vol. 57, no. 4, April 2010, pp.285-289. [2] P. K. Meher, “New approach to LUT implementation and accumulation for memory-based multiplication,” in Proc. IEEE ISCAS, May 2009, pp. 453–456. T.Thangam,

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[3] P. K. Meher, “New look-up-table optimizations for memory-based multiplication,” in Proc. ISIC, Dec. 2009, pp. 663–666. [4] R.Ramya and S.Sudha, “LUT Optimization Using Combined APC-OMS Technique For Memory-Based Computation”, IJCAES., Vol.3, AUG 2013. [5] A.Srinivasalu and G.Ramanjaneya Reddy,”Optimization of memory based LUT Multiplier,”IJECIERD,vol.3,oct 2013,pp.125-132. [5] J.-I. Guo, C.-M. Liu, and C.-W. Jen, “The efficient memory-based VLSI array design for DFT and DCT,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 39, no. 10, Oct. 1992, pp. 723–733. [6] H.-R. Lee, C.-W. Jen and C.-M. Liu, “On the design automation of the memory-based VLSI architectures for FIR filters,” IEEE Trans. Consum Electron., vol. 39, no. 3, Aug. 1993 ,pp. 619–629.

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