Methodology for Characterization of NOR-NOR Programmable Logic Array VENKATA RAJESH MEKALA

Department of Electrical and Computer Engineering Texas A&M University, College Station [email protected] Abstract:

plane evaluates a product term and each column of the OR plane evaluates a PLA output.

Programmable Logic Arrays are popular implementations for “multi-input” 2-level “multioutput” functions. PLAs are advantageous for designers especially in GHz technology with deep sub-micron sizing. The regular structures of PLAs are attractive to VLSI designers because they require a small number of separate cell designs. PLAs allow “ease of testing”. The biggest advantage is that the entire design flow in the PLA generation can be automated. The main focus of the paper is to establish a quick design verification methodology for PLAs.

NOR NOR PLA The cubes are generated using NOR operation on sub-set of PLA inputs and their complements. The PLA outputs are generated by performing a NOR operation on the subset of the cubes already generated. II STRUCTURE AND OPERATION The pre-charged NOR-NOR PLA is used as a basis for characterization [1]. The schematic is as shown.

We choose dynamic PLAs which have an advantage of higher frequency of operation, lesser power consumption and easier predictability of area. The methodology involves generation of spice decks dynamically using Perl code and simulating the PLA’s pre-layout net-list in H-Spice. In the post-layout stage layouts are dynamically generated using SKILL programming in Virtuoso and simulating post-layout net-list in H-Spice. Various characterization experiments are done on PLAs using these methodologies. I INTRODUCTION Programmable Logic Array is a ‘two-level’ implementation of sum of products for ‘multi-output’ functions. The structure of a PLA is ‘regular’ and generated using automation. This helps the designer to reduce the time-to-market and quick predictability of various parameters of a sub-circuit. The “product terms” known as word-lines in the PLA are generated from PLA inputs (also called “bitlines”). The OR plane takes in the product terms and generates the PLA outputs. Each row of the AND

Figure: 1 - Structure of dynamic NOR-NOR PLA. Operation [1] When CLK is ‘low’, PLA enters “pre-charge” phase and when the CLK is ‘high’, PLA enters “evaluation” phase. In the pre-charge phase the horizontal word lines get pre-charged. The maximally loaded word line (called “dummy word-line”) is also pre-charged. This forces D_CLK to go ‘low’, cutting off the OR plane from GND, thus causing the output lines to get pre-charged. The dummy word-line is designed to be the last word-line to switch (by making it maximally loaded among all word-lines). Similarly, the completion line is also the last output line to switch,

since it is maximally loaded as well, in comparison to other outputs. The completion line switching high signals the completion of the pre-charge operation of the PLA. The word-lines of the PLA represent the cubes of the function to be implemented, run horizontally through the AND and OR plane of the PLA. The bit lines carry the inputs and their complements which run vertically through the AND plane while the output lines run vertically through the OR plane. When the clock is low, the PLA enters the pre-charge phase and the horizontal word-lines get pre-charged. A special line called the dummy line is introduced which is maximally loaded among all the word-lines to generate the delay clock for the OR plane. The dummy-line is designed to be the last word-line to get switched. Similarly the completion line is the last output line to get switched since it is maximally loaded, in comparison to the other outputs. The completion line switching high signals the “completion” of the pre-charge operation of the PLA. In the pre-charged state, all the word-lines and the output lines of the PLA are pre-charged. Now, when CLK switches high, the PLA enters the evaluation phase. In evaluation, if any of the vertical bit-lines are high, the word-line that it is connected to gets pulled low. One of the inputs and its complement is connected to the dummy word-line, so that the dummy word-lines switch low during every evaluate phase. By design the dummy word-line is the last word-line to switch low. This makes the signal D_CLK signal go high, as a result of which the GND gating transistor in the OR plane now, turns on. The output lines to which, word-lines that have switched low are connected will switch low. The completion line, which is connected to the complement of the dummy word-line, is the last line to switch low. This signals the completion of the evaluation operation.

Figure: 2 - Pre-layout methodology. In this procedure, a Perl code for generating the spice-deck for various parameters like CLK period, widths and lengths of the transistors, number of word-lines, and number of bit-lines was written and tested for correctness. The post-layout methodology is as shown in Figure: 3, which generates the layout dynamically. The intermetal capacitances and resistances are extracted using SPACE3D and Perl script respectively. The complete post-layout net-list is then simulated for results (accurate compared to pre-layout). This is an extremely useful technique which avoids hand-drawn layouts for verifying larger functions.

Figure: 3 - Post-layout simulation methodology. A sample waveform simulated for 3-inputs, 5-cubes and 3-functions is as shown in Figure: 4.

III VERIFICATION METHODOLOGY The Pre-layout automation process is as shown in Figure:

Figure: 4 Sample Output Waveforms.

Experiments 1. Simulating for different number of inputs, outputs and cubes using the pre-layout methodology. 2. Comparing bulk process PLA with SOI process PLA using pre-layout methodology. 3. Post-layout simulation using custom layout drawn. 4. Dynamically generate AND plane layout and OR plane layout using SKILL. The delay is defined as the time difference between the occurrences of CLK falling edge at VDD/2, to completion rising edge at VDD/2. The power is measured using commands in H-spice for one period of CLK. Notice that the delay is independent of function being implemented because of the insertion of the ‘dummy line’ and ‘completion line’.

Notice that the sizing of the transistors plays an important role in checking for the functionality. Many number of trials for the sizes of n-MOSs and pMOSs must be done to get the accurate functionality. An observation is that as the number of inputs or cubes or functions increase the footer n-MOS transistor whose gate is connected to ground is of larger size. It acts like a strong switch connecting the whole PLA circuit to ground in the evaluate phase. The following simulation is an extremely important simulation done to compare the performance (delay and power) of PLAs in BULK (180nm) process and SOI (100nm) process. It gives rough estimates of which process is the best. The results for various temperatures and other parameters are as shown in Tables 1, 2. The results are as follows:

Table: 1

T = 25

3-inputs 5-cubes 3-outputs

4-inputs 6-cubes 3-outputs

5-inputs 9-cubes 4-outputs

T = 100

T = -25

DELAY (ns)

POWER (µw)

DELAY (ns)

POWER (µw)

DELAY (ns)

POWER (µw)

0.6754

66.93

0.8379

70.48

0.6377

63.77

0.4275

58.77

0.5028

0.7993

141.3

0.7945

56.12

116.5

0.4030

62.33

0.3561

80.07

1. We observed sharp transitions because of lower capacitances in ‘SOI’ process compared to ‘bulk’. 2. The delays are tremendously lower compared to bulk process. Due to lower capacitance values, thus greater fan-out could be supported in SOI process. 3. The area is quite lower than bulk process. 4. The Power consumed is very low. The layout for the circuit shown in figure: 1 is custom drawn (figure: 5), the layout is optimized for area. From this layout the inter-metal capacitances are calculated using space3d (using a skeleton structure in which only the metal layers exist). The resistance values are taken from the cadence library files. The complete spice deck is created using these values has been simulated.

Table: 2 T = 25 DELAY (ns)

2-inputs 3-cubes 1-outputs

3-inputs 9-cubes 2-outputs

5-inputs 9-cubes 4-outputs

T = 100

T = -25

POWER (µw)

DELAY (ns)

POWER (µw)

DELAY (ns)

POWER (µw)

0.197

3.57

0.243

3.71

0.174

3.21

0.341

8.36

0.433

0.303

7.97

0.516

16.6

0.643

0.434

13.4

8.8

36

Figure: 5

The post-layout results vary slightly with the prelayout results, where the delay and power slightly increase. As a part of the post-layout methodology, the layout for AND plane is dynamically generated using SKILL programming. An example of generation of AND plane is as shown in Figure: 6.

CONCLUSION

Figure: 6 This can be extended to the OR plane and using a Perl wrapper, we can actually generate the complete layout of the PLA dynamically using this technique. From this instantiation the final layout could be achieved by flattening the net-list and extracting the inter-metal capacitances and resistances using space3d. The final net-list could be simulated. Thus, obtaining the simulation results in post-layout stage. IV SCOPE OF FUTURE WORK The automation could be extended to the functional optimization in SIS, and writing a Perl wrapper around various steps already automated.

The present methodology for characterizing PLAs could be used to generate Delay-tables, Power-tables and Cap-tables similar to standard cell methodology for characterizing cells and other applications. This is a quick method as every stage is automated.

REFERENCES [1] Nikhil Jayakumar, Sunil P. Khatri, “Minimum Energy Near-threshold Network of PLA based Design”. [2] J. Rabaey, Digital Integrated Circuits - a design perspective. [3] S. Bobba, I.N. Hajj, “Maximum current Estimation in Programmable Logic Arrays”.