Modeling Yield, Cost, and Quality of a Spare-enhanced Multi-core Chip Saeed Shamshiri and Kwang-Ting (Tim) Cheng

Analysis and Modeling Flow

1

1. Providing a yield and cost model for a multi-core chip in the presence of spare cores and wires, and demonstrating the improvements of the overall yield and costs. 2. Proposing a quality metric for an NoC and exploring the tradeoff between the yield and cost of a chip versus quality. 3. Illustrating that the burn-in process can be eliminated, and the manufacturing test constraints can be loosened for a spare-enhanced multi-core chip with an in-field reconfiguration mechanism. 4. Demonstrating that the contribution of each link of a mesh to the overall network reliability varies with respect to the location of the link. We propose a nonuniform distribution of spare wires, which maximizes the overall reliability of the chip.

0

2 3 No. of Spare Wires

4

Minimum Total Cost

5

Failure Rate

0.8

4

0

b) A non-complete mesh Min Distance = 5

Min Distance = 3

0

AMD(12)=2.33

Normalized AMD =

Total cost w / burn-in

Burn-in increases the cost

3 2

0.7 0.6

Burn-in reduces the cost

1 9 out of 9

9 out of 12

9 out of 16

AMD(16)=2.65

0.5

0.3

0.15

0.05

10

6

3

1

Yield

q=0 q=0.5

0.2

0.3

0.15

0.05

0.5

0.3

0.2

1

0.3

4

6

6

4

q=0.7 q=0.8

0.08

0.12 0.12

0.104

0.12 0.163

0.163

0.012 0.08

0.163

0.163 0.12

0.08

0.08

2

0.12

2 2

2 2

0.08 0.08

2 2

0.104

0.12 0.104

1

0.12

1

2 2

2 1

2 2

2 P-1-2

3 3

3 2

2 1

3 3

3 3

2

2 3

3 3

3 2

2

3 P-2-3

3 3

3

0.1

P-1

P-1-2

P-2

P-2-3

P-3

P-3-4

20 18

P-4

16 14

10

0.06

8

0.02 0

mesh 1 2 3 4

5 6

7

min cost =15.98

9 out of 16 q=0.5 q=0.6 q=0.7

12

0.08

0.04

2 2

0.12

P-0-1

Total Cost

3

6

10

Usage Probability

P-0

Four spare w ires Quality Constraint

¾In many cases, the total cost is minimal for a nonuniform pattern.

q=0.8 q=0.9

min cost =4.78

min cost =2.67

2

min cost =2.66

0 P-1

P-1-2

P-2

P-2-3

P-3

ware Soft o Dem

Overall cost and yield improves significantly. Burn-in can be eliminated. Manufacturing testing requirements can be loosened. We proposed a metric for the communication quality of an NoC; quality analysis reveals new information about the system which is hidden in the connectivity analysis. ™ Information about the communication quality help to price the chip in the market. One can optimize the overall yield as well as cost of the chip using a quality constraint. ™ We proposed to distribute the spare wires based on the contribution of each link to the overall network quality; this leads to a non-uniform distribution of spare wires.

Future work:

min cost =2.99

6 4

• Total cost increases exponentially by increasing the quality constraint. • For tighter quality constraint, more spare wires are required to maintain a high yield.

Conclusion & Future Work ™ ™ ™ ™

q=0.95

0.1-0.12 0.08-0.1 0.06-0.08 0.04-0.06 0.02-0.04 0-0.02

Three spare w ires

0.2

Conclusion:

q=0.9 Spare Wires Pattern

0

Tw o spare w ires

0.3

8

¾In many cases, changing from a uniform pattern to the next non-uniform pattern improves the yield significantly.

q=0.6

0.2

One spare w ire

0.4

0

Non-Uniform Spare Distribution

7

0.6

3

4

4

Zero spare w ire

0.1

9 out of 20

0.4

2

3

9-out-of-12 system

0.5

For an m-out-of-n chip, the quality is zero if the number of connected, fault-free cores is less than m (i.e., cnt
9 out of 16

1

Quality Constraint

No. of Spare Wires per Link 2

0.8

0 < Normalized AMD ≤ 1

4

0.8

2

1

1

Ideal AMD (m) Measured AMD (m)

1

1

A

Four spare w ires

6

0.9

With one spare wire per link

Tw o spare w ires Three spare w ires

A

0.1

a

a) A complete mesh

5

One spare w ire

8

0. 95

2 3 No. of Spare Wires

9 out of 12

10

0.8 5 0.9

a 1

Wire Usage Probability

0.08

9 out of 20

0.2

Min-Route

0.104

12

9 out of 16

0.5

Total cost w /o burn-in

9 out of 20

9 out of 12

B

0.6

0.3

5

Manufacturing Cost

14

9 out of 9

0.7

9 out of 16

0.4

6

Service Cost

0.08

0.9

b

16

0.7 5 0.8

Average Minimum Distance (AMD) / Ideal AMD

b

7

2

9 out of 16

1

9 out of 20

0

3

9 out of 12

Minimum Distance 9 out of 12

1

4

0 9 out of 9

Quality = Normalized Average Minimum Distance (AMD)

1.5

Minimum Service Cost

1

Quality of the Network

2

Total Cost

5 Cost

1

C Ser = (1 − R F ).C F

3

9 out of 20

Minimum Man Cost

6

n.(CK + Ctest ) + w.Clink + CL 2 y ′soc

2.5

9 out of 16

6

⎛ nw ⎞ nw − i i ⎟⎟(1 − y′w ) ( y′w ) i = mw ⎝ ⎠ nw

∑ ⎜⎜ i

9 out of 9

3.5

0

7

k parity

0 0. 05 0. 1 0. 15 0. 2 0. 25 0. 3 0. 35 0. 4 0. 45 0. 5 0. 55 0. 6 0. 65 0. 7 0. 75 0. 8 0. 85 0. 9 0. 95

0.2

C Man =

′ = ( y ′w _ ctrl ) kctrl ( y ′w _ parity ) ybus

0.6 5 0.7

9 out of 12

Quality, Yield, and Cost

′ f conn

0.5 5 0.6

9 out of 9

0.4

5

β −1

0.4 5 0.5

0.6

β ⎛ t ⎞ ×⎜ ⎟ µ ⎜⎝ µ ⎠⎟

Total Cost

Manufacturing Cost

Observed System Yield

0.8

4

f =

y′link

4 The lowest cost: • 3 spare blocks • 1 spare wire

4.5

1

1 − y′sw−ctrl ′ 1 − yblock

β >1

β =1

β <1

0 0.0 5 0. 1 0.1 5 0. 2 0.2 5 0. 3 0.3 5 0.4

5

3

λc × Ac × Ω c −α ) α

y′block

′ = f conn

Spare-Enhanced SoC

Yield

99% yield: • 3 spare blocks • 1 spare wire

yc′ = (1 +

2

Quality

Yield, Cost, and Burn-in 95% yield: • 11 spare blocks • No spare wire

Sep 3-4, 2009

Resilient System Design, Task 1.2.3.4.

University of California, Santa Barbara

Contributions

GSRC Annual Symposium

Spare Wires Pattern P-3-4

P-4

™ Integrate spare wires in a real multi-core chip design and measure the power and area overhead. ™ Apply a Plackett & Burman design to rank each of the system’s input parameters based on their effect on the overall yield and cost of the system.

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