MR. IMAGER - A Low-Cost Scalable Multi-channel MRI Front-End Ishaan Dalal Ashwin Kirpalani Fahd Malik

The Cooper Union for the Advancement of Science and Art New York, NY.

Branch Counselor: Dr. Fred L. Fontaine

Ishaan Dalal: IEEE Member # 41472525 35-41 Crescent St. Apt 1F Astoria, NY 11106.

MR. IMAGER - A Low-Cost Scalable Multi-channel MRI Front-End

Contents

1 Introduction

1

2 An Overview of MR. IMAGER

2

3 Design and Implementation

4

3.1

A Brief History of the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4

3.2

Input Protection and Preamplification . . . . . . . . . . . . . . . . . . . . . . . . . .

6

3.3

RF Demodulation: Direct Undersampling . . . . . . . . . . . . . . . . . . . . . . . .

7

3.4

IF Demodulation: Digital Downconversion . . . . . . . . . . . . . . . . . . . . . . . .

9

3.5

Data Transfer for Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.6

Real-Time Image Reconstruction and Display . . . . . . . . . . . . . . . . . . . . . . 10

4 Test Results and System Analysis

11

5 Conclusion

14

A Undersampling: Theory and Application

15

B Component List and Budget Estimate

17

Abstract

MR. IMAGER is a novel multi-channel Magnetic Resonance Imaging (MRI) front-end. It connects to an MRI scanner and digitally processes raw magnetic field measurements into images of the body. Innovative data acquisition techniques are used, with all digital functions integrated onto a single Field-Programmable Gate Array (FPGA). The result is a device that is an order-ofmagnitude cheaper and much more scalable than existing solutions, making it ideal for academic MRI research. A four-channel prototype has been designed, implemented and tested successfully.

1

Introduction

Figure 1: A Conventional MRI System Today, Magnetic Resonance Imaging (MRI) is a very common and effective technique for noninvasive medical diagnosis. Using strong magnetic fields, MRI induces hydrogen atoms in the body to resonate about a common radio frequency (RF). This resonance is picked up by one or more tuned coils, and their outputs are digitally sampled and processed by a data acquisition system. Specialized software running on an array of computers reconstructs the processed data into images of the body. Figure 1 shows a conventional system, consisting of the scanner (magnetic-field generators and pickup coils) and the front-end (data acquisition and image reconstruction). Conventional MRI cannot clearly image moving objects such as the heart or blood flow because of its long scan times. This problem can be solved by using parallel imaging, where multiple pickup coils compensate for image artifacts caused by a shorter scan time. Parallel imaging research requires a scalable front end that can accommodate changing numbers of pickup coils without expensive and cumbersome hardware changes; also, researchers often need access to intermediate data instead of just a final image. Available front-ends are expensive, proprietary and non-scalable black boxes, making them impractical for academic research environments. Thus, the objectives of the MR. IMAGER front-end include low cost, high scalability and complete accessibility for research purposes. We have implemented a design that achieves these

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goals through innovative data acquisition techniques and integrated all-digital hardware. Signals from up to 16 pickup coils are sampled directly at RF, with all subsequent processing performed in parallel on a single-chip Field Programmable Gate Array. MR. IMAGER is at least 25 times cheaper than available commercial front-ends1 , has a well-documented architecture and allows the download of intermediate data from any point in the processing chain for analysis. A four-channel prototype of MR. IMAGER has been realized and tested with an MRI scanner from General Electric (GE); image quality was comparable to GE’s front-end. The prototype consists of multiple self-fabricated printed circuit boards (PCB) as well as a few manufacturerprovided evaluation boards.

2

An Overview of MR. IMAGER

Figure 2: The MR. IMAGER-based MRI System The MRI pickup coils emit quadrature amplitude-modulated radio signals at 64 MHz2 . These complex RF signals are demodulated to give the original image information, which has a bandwidth of 250 KHz. This information is digitized and converted to an image with the Fourier transform. As shown in Figure 1, a conventional MRI front-end demodulates the signals with multiple analog stages, digitizes the baseband data and uses a dedicated array of high-powered computers for image reconstruction. On the other hand, MR. IMAGER (Figure 2) directly digitizes up to 16 1 2

Section 4 and Appendix B explain how this figure was arrived at. This carrier frequency is typical of 1.5 Tesla MRI scanners.

2

RF signals and performs all demodulation and image reconstruction on a single chip. Eliminating most of the analog circuitry as well as the dedicated computers makes MR. IMAGER much cheaper, smaller and faster than a conventional front-end. Multiple MR. IMAGERs allow parallel imaging research to easily scale beyond 16 coils. The MRI signals from the coils are at a very low amplitude (-30 dBm or 7 mV) and must be amplified to exploit the full resolution of the analog-to-digital converters (ADC). The amplified signals are filtered before being digitized by a 12-bit ADC and fed to MR. IMAGER’s core: a Field Programmable Gate Array (FPGA). FPGAs are large collections of basic units called ‘logic cells’. These cells can be interconnected to construct virtually any digital function; one compact chip thus replaces several discrete components such as flip-flops, counters and multiplexers. ‘Field-Programmable’ refers to the interconnects, which can be reprogrammed as many times as necessary. This streamlines development and greatly simplifies debugging as compared to making multiple revisions of custom-fabricated ICs. Hardware parallelization also lets algorithms run much faster on FPGAs than on sequential devices such as microprocessors or DSPs. MR. IMAGER uses the Virtex-II Pro FPGA from Xilinx, Inc. The FPGA is integrated on a board that contains I/O interfaces (Ethernet, USB and Serial), memory (RAM and CompactFlash) and a VGA video output. Apart from logic cells, this FPGA also contains dedicated multipliers that facilitate the implementation of signal processing structures such as filters and transforms. Two PowerPC microprocessors embedded inside the FPGA provide I/O control. The FPGA demodulates the 16 digitized channels and transforms the data into images. For clinical use, no computers are needed; the images can be displayed in real-time on any attached monitor. MR. IMAGER is a networked device that allows researchers complete access to the images as well as intermediate data.

3

3

Design and Implementation

Figure 3: The FPGA and its Evaluation Board

3.1

A Brief History of the Project

The design for MR. IMAGER presented here is very different from our original design, which was mostly analog. Since the primary concerns were cost and scalability, we attempted to mimic the data acquisition system of conventional MRI with off-the-shelf components. The design consisted of analog components such as amplifiers, RF/IF mixers and phase-locked-loops that demodulated the RF MRI signals to baseband data. It did not do digitization or image reconstruction, and scaling to multiple channels involved replicating a common set of circuitry for each channel. The analog outputs from this design were multiplexed and fed to a proprietary PC-based converter for digitizing. These were then to be split back into separate channels on a computer and finally reconstructed into an image. This analog design was built and successfully met its design specifications. However, a problem arose when the multiplexed analog outputs were sampled by the PC-based converter; the effective

4

sampling rate was much lower than what it should have been. As a result, data from all the channels was smeared together and could not be de-multiplexed for further processing. After extensive investigation, it was concluded that the ‘sigma-delta’ ADC inside the proprietary converter was not designed for sampling multiplexed signals; the manufacturer confirmed[1] this conclusion.. Purchasing a suitable ADC system would cost thousands of dollars and was not a viable option. The alternative chosen was to adapt the design by sampling on-board instead of with an external converter. Sampling directly at RF would also reduce complexity by eliminating the analog RF/IF stages. Previous experimental systems employing undersampling [2][3] used custom hardware and were single-channel devices. We wanted to use only off-the-shelf components to make a multichannel system. Thus, the key requirement was a solution that would interface to at least 16 channels, digitally demodulate (or downconvert) them and transfer the resulting data to a computer. FPGAs were ideal for the job because of their customizability and parallel processing capabilities. The number of discrete components such as counters and multiplexers would also be reduced by moving them onto the FPGA. The last stumbling block was physical implementation, since none of the components for the new design were available in the leaded packages (DIP) that were previously being used. Printed circuit boards (PCBs) were fabricated and surface-mount components soldered onto them without special equipment (we used a toaster oven). Breadboards could not be used for prototyping any more, so the design was simulated extensively to ensure that soldered PCBs worked out-of-the-box. After implementing the digital downconverters on the FPGA, the remaining logic cells were used to make MR. IMAGER a complete front-end. A 2-D Inverse Fast Fourier Transform (IFFT) and a video (VGA) controller were implemented, allowing MR. IMAGER to perform image reconstruction and directly display the final images on an attached monitor.

5

(a) Time-Domain Waveform

(b) Frequency Spectrum

Figure 4: MRI Signal and Associated Spectrum

3.2

Input Protection and Preamplification

At the start of every scan, the coils pick up high-powered RF spikes from the magnetic-field generators. These spikes can saturate the amplifiers and must be blocked. The scanner provides a control signal that is monitored by a level-sensitive comparator; within nanoseconds of detecting a spike, the comparator opens an active RF switch and blocks the spike. As soon as the spike dies down, the switch is closed and normal signal flow resumes. A typical amplitude-modulated MRI waveform (Figure 4a) is at around −30 dBm (or 7 mV), with the spectrum shown in Figure 4b. This signal is amplified by around 50 dB (to 2 V) to utilize the full dynamic range of the ADC. The gain on each channel is also adjustable to equalize the signals for parallel imaging. Since noise is of paramount importance at such large gains, a combination of fixed (40 dB) and variable-gain (0 − 20 dB) low-noise amplifiers (LNA) is used. In general, analog signals are single-ended, or referenced to ground. High-frequency analog circuitry uses differential I/O, where the signal and an inverted copy are transmitted side-by-side, referenced to each other. Any noise or stray coupling affects both signals equally and can easily be eliminated. MR. IMAGER’s analog chain is fully differential; the first LNA converts the singleended MRI signal to a differential signal. 6

Figure 5: Undersampling an MRI Signal

3.3

RF Demodulation: Direct Undersampling

In general, an analog signal must be sampled at a rate fs greater than twice its maximum frequency fH to eliminate distortion in the resultant data. For the 64 MHz MRI signal, fs > 128M Hz. Available off-the-shelf ADCs that can sample at such high rates do not have the 12-bit resolution that is required to maintain image quality. Transferring and processing multiple channels at such high data rates is also difficult without custom hardware. The fs > 2fH rate specified above is based on Shannon’s Sampling Theorem [4], and assumes that the signal to be sampled has frequency components from DC all the way to fH . For a nonbaseband signal whose spectrum does not extend down to DC, the sampling rate is determined by the bandwidth of the signal. For MRI, the information is contained in a narrow 250 KHz band around 64 MHz; therefore, in principle, a sampling rate of 500 KHz would be adequate3 . As Figure 5 illustrates, the aliasing caused by undersampling results in a frequency shift such that the desired information folds back into baseband. Appendix A presents the mathematical reasoning behind the validity of undersampling. 3 The sampling rate used is 20 MHz. While this rate is much less than 2fH ' 128M Hz, it is still higher than the absolute minimum of 500 KHz. This is common practice in real-world designs to relax the requirements of the BPF and post-processing algorithms.

7

Thus, if undersampling is employed, an RF mixer is no longer needed. Two constraints must be met for undersampling to succeed. First, the input signal must be bandpass filtered to remove any noise and spurious content outside the information bandwidth (63.875 − 64.125 MHz); otherwise, these would also fold back into baseband and corrupt the information. Second, the analog input bandwidth of the ADC used must be higher than the actual frequency (64 MHz) of the signal4 . Since an existing bandpass filter that met the specifications could not be found, one was designed using high-bandwidth op-amps. Common filter topologies such as Sallen-Key do not work well at high frequencies [5] because they place impractical requirements upon component values and tolerances. The Akerberg-Mossberg [6] topology used does not have these problems. The resulting filter response is an 8th-order Butterworth with a passband of 63.5 − 64.5 MHz and a stopband beyond 62 − 66 MHz with ≥ 40 dB attenuation. The ADCs used are two 8-channel Texas Instruments ADS5272s that have the necessary 12-bit resolution and analog input bandwidth (300 MHz). Sampled data are output serially to save on I/O pins; they are converted to parallel data for input to the next stage by a high-speed de-serializer inside the FPGA. The ADC’s sampling clock must also be phase-locked to a reference provided by the MRI scanner to ensure accurate demodulation. A digital delay-locked-loop on the FPGA generates the 20 MHz clock from the 10 MHz reference. 4 This is because the sample-and-hold circuit of the ADC must still perform at 64 MHz, even though the actual sampling is at a much lower rate.

8

3.4

IF Demodulation: Digital Downconversion

Figure 6: MR. IMAGER’s FPGA Signal Processing and Data Transfer Chain Figure 6 shows the processing path for sampled data through the FPGA. Digital downconverters (DDC) are digital versions of the classical superheterodyne radio receiver; they multiply incoming signals with a ‘local oscillator’ frequency and filter the output to recover the original information. A direct digital synthesizer5 generates 4 MHz quadrature (sine and cosine) local oscillators from a high-precision phase lookup table. The oscillators are multiplied with the MRI data from the ADC, and the resulting complex (inphase/quadrature − I/Q) data are downsampled and filtered before being transformed into an image. Regular downsampling (i.e., decimation) by ratio R works by keeping only 1/Rth of the original samples and then filtering them to prevent aliasing at the output. Typically, the filter used is a high-order FIR lowpass that needs a large number of multipliers. To conserve the limited number of FPGA multipliers, we decimate with a multiple-stage Cascaded Integrator Comb (CIC) [7] filter that uses only adders. A 4-stage CIC decimates one complete I/Q channel by 16. At this point, one final decimation/filtering step is still needed before the baseband information is ready to be reconstructed into an image. This final filter is a 16-tap poly-phase FIR that decimates by 2. Since each channel shares the same filter coefficients, resource usage has been minimized by 5

Or DDS; sometimes referred to in the literature as a ‘numerically controlled oscillator’ (NCO).

9

implementing the FIR as a single time-multiplexed multi-channel block that processes all 32 I & Q input streams.

3.5

Data Transfer for Analysis

A large amount of buffer memory is needed for temporary storage of the demodulated data. Inexpensive PC RAM is used as a buffer by implementing a memory controller on the FPGA. One of the two PowerPC microprocessors on the FPGA transfers the demodulated data to RAM. A Fast Ethernet network controller constructed from logic cells couples with a lightweight TCP/IP stack[8] running in software to make MR. IMAGER a fully-networked device. Researchers can download data or images via the File Transfer Protocol (FTP) to host applications, e.g. MATLAB T M . For scenarios where a network is not available, data can be saved to a non-volatile CompactFlash card for future use.

3.6

Real-Time Image Reconstruction and Display

In clinical use, for example, there may be a need to immediately view high-quality final images without having to use a dedicated array of computers for reconstruction. On-board reconstruction and display capabilities have been built into MR. IMAGER for use as a complete front-end. The final spatial image is derived from the frequency-domain baseband outputs of the DDCs. A 2-dimensional Inverse Fast Fourier Transform (IFFT)6 is applied to the baseband information, and p computing the magnitude ( I 2 + Q2 ) of the (I, Q) output points from the IFFT directly produces the pixels of the final image. Rather than using resource-hungry multiplies and square-roots, the magnitude is calculated with the required precision by the highly-efficient CORDIC (Coordinate Rotational Digital Computer) [10] iterative algorithm. The second PowerPC microprocessor feeds 6

Implemented on the FPGA as two 1-D FFTs and a fast matrix transpose; FFTs based on a reference design[9].

10

Figure 7: Analog Chain Circuit: BPF [left], Protection/Amplification [center], ADC [right] data in chunks of 256 (I, Q) complex points to the IFFT/CORDIC and stores the result back in RAM. Image reconstruction thus happens in real-time as information comes in from the scanner and is demodulated. The final images can be displayed on any computer monitor connected directly to the FPGA. This capability is provided by a VGA video controller custom coded in VHDL7 [11] and an external video DAC chip. MR. IMAGER’s maximum display rate of 17 frames/second8 makes it a viable candidate for emerging real-time video MRI applications[12].

4

Test Results and System Analysis

A four-channel version of MR. IMAGER has been designed and built, with testing divided into two stages: the analog chain (input protection, amplification, BPF and ADC) and the digital processing (FPGA). The analog chain, shown in Figure 7, was successfully interfaced to a 1.5T GE Signa MRI 7 8

VHSIC Hardware Description Language - a high level language for creating FPGA-based logic structures. 16 channels with 256 × 256-pixel images and sum-of-squares interpolation.

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(a) Downconverted Spectrum

(b) Final Image (Fat-and-Water Phantom)

Figure 8: Downconverted MRI Spectrum and Final Image scanner and data from four coils downloaded to an external high-speed capture board. The chain met or exceeded design specifications such as channel-to-channel isolation and signal-to-noise ratios. The digital (FPGA) portion was tested in the lab to allow instant debugging of the VHDL logic and C codes running on it. Real-world information from the GE MRI scanner (downloaded with the analog chain as mentioned above) was used as a signal source for testing the downconversion and image reconstruction processes. Figure 8a shows a post-DDC baseband spectrum. Figure 8b shows a final reconstructed image. This image is a ‘fat-and-water’ phantom9 that is a sum-of-squares interpolation of individual images from each of the four coils. The quality10 is comparable to that obtained from GE’s proprietary front end. A 16-channel MR. IMAGER with real-time video display utilizes 92.4% of available FPGA resources, as shown in Table 1. 9

A ‘phantom’ refers to artifical objects used to test MRI scanners. Clinical images were not used because of privacy (HIPAA) restrictions. 10 PSNR, to be precise. 11 This includes 3% for the DDC and the multichannel FIR that is common to all channels.

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Table 1: Resource Utilization of FPGA Blocks Component One-Channel DDC RAM, Ethernet and Video FFT CORDIC Total

Resources Used 3.5% 27.3% 4.1% 2.2%

Number Required 16 1 1 1

Total Utilization 58.8% 11 27.3% 4.1% 2.2% 92.4%

The prototype has a cost-per-channel of '$125 (Appendix B presents a detailed parts list and cost estimate). Commercial front-ends are usually sold as part of a package that includes the actual scanner. With a typical four-channel scanner estimated at $1 million[13], it is safe to assume that the front-end component is at least 10%, or $25,000-per-channel. It is only fair to note that the cost estimate for MR. IMAGER does not include labor, exterior design and most importantly, electrical and medical certifications. With all of these included, we estimate the upper limit for a mass-produced MR. IMAGER to be $1000-per-channel.

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5

Conclusion

As MRI scanning techniques continue to increase in speed and complexity, academic researchers require low-cost scalable multi-channel front-ends. The front-end must not sacrifice image quality to achieve these objectives and should allow access to intermediate data for further analysis. We have developed a 16-channel MRI front-end (‘MR. IMAGER’) that meets these goals and is less than 1/25th the cost of available front-ends. Parallel imaging with more than 16 coils can scale by using multiple MR. IMAGERs in tandem, while on-board memory and a network interface allow quick downloads of intermediate data. With the addition of any computer monitor, MR. IMAGER can reconstruct and display MRI images as the scan is being performed. Since the sampling process is entirely software-controlled, MR. IMAGER can easily be adapted for use with MRI scanners operating at frequencies other than 64 MHz, with the only hardware change being the pre-ADC bandpass filters. For emerging MRI applications (e.g., MR Angiography) that use more complicated imaging techniques, the real-time performance of MR. IMAGER can be traded for on-board image processing that is still faster than a dedicated computer array. With some additional work, MR. IMAGER’s network interface opens up the possibility of adding a ‘remote diagnosis’ feature, by relaying live video to a radiologist who may be thousands of miles away. Future work includes testing the complete system with a clinical MRI scanner as well as expanding the four-channel prototype to a full 16-channel version. An integrated PCB for the entire design will be fabricated and external enclosures looked at as MR. IMAGER approaches its final form. By greatly lowering the financial and technical barriers for academic MRI research, we sincerely hope that MR. IMAGER will speed up breakthroughs in medical diagnosis.

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A

Undersampling: Theory and Application

If an analog signal x(t) with spectrum X(f ), i.e.

Z

∞

X(f )ej2πf t df

x(t) =

(1)

−∞

is sampled to give x(n) (= x[nT ]) with digital spectrum X(ω), i.e.

x(n) =

∞ X

X(ω)ejωn

(2)

n=−∞

it follows from basic sampling theory that X(ω) and X(f ) are relates as follows. Let

X ∗ (f ) =

∞ 1 X 1 X(f − nfs ) , where fs = T n=−∞ T

(3)

Then,

X(ω) = X ∗ (f )

ω=2π ff

(4)

s

From (3), the aliasing terms are all n 6= 0. Thus, frequencies that are ±fs apart will alias into the baseband frequency f . For sampling a non-baseband signal, the theorem can be restated. Let 0 < fL < fH be the lowest and highest frequency components in the signal, with bandwidth B = fH − fL . Then, there is an integer N > 0 such that

15

N≤

fL fH
(5)

Additionally, we define r = fL − N B ∈ [0, fL ]. Then, any real-valued signal x(t) with analog spectrum X(f ), f ∈ [fL , fH ) is uniquely determined by its samples obtained at fs if



nB + r 2 B+ N −n+1





nB + r ≤ fs ≤ 2 B + N −n

 [undersampling]

(6)

or 2fH ≤ fs [regular sampling]. We now calculate the valid fs for MR. IMAGER (20 MHz). The bandwidth B = 1 MHz (63.564.5 MHz, including guard bands), N = 63 MHz and r = 0.5 MHz. Substituting these into (6) gives a number of feasible n values. For n = 57, (6) gives

18.43 MHz ≤ fs = 20 MHz < 21.17 MHz

16

(7)

B

Component List and Budget Estimate

The major components that make up MR. IMAGER are listed here along with their cost to give an estimate of our budget. Whenever possible, the prices are based on quotes provided directly by the manufacturers. Some items have been grouped together into classes, such as connectors and passive components.

Table 2: Parts List and Cost Estimate Description 12-Bit, 8-Channel 65 MSPS Analog-to-Digital Converter Differential Amplifier Video Buffer Amplifier High-Speed Comparator Fast Ethernet Transceiver RS-232 Transceiver CompactFlash Controller USB Controller 1 GB RAM Module FPGA SVGA Video DAC 100 MHz Crystal Oscillator Linear Voltage Regulator Switching Voltage Regulator SMA connectors MRI connectors Passive Components 9” × 9” 6-layer PCB Total cost for 16-Channel MR. IMAGER

Part Number

Manufacturer

$/ Unit

#

Total Price

ADS5272 THS4511 OPA693 TLV3501 LXT972ALC MAX3388E XCCACE CY7C68013 Generic PC2700 DDR XC2VP30 FMS3818 FCO-736B LT1963 TPSS461 N/A FMX006S N/A N/A

Tex. Inst. Tex. Inst. Tex. Inst. Tex. Inst. Intel Maxim Xilinx Cypress Semi Generic

65.00 3.45 1.30 1.50 6.25 2.79 65.00 8.95 67.99

2 80 16 16 1 1 1 1 1

130.00 276.00 20.80 24.00 6.25 2.79 65.00 8.95 67.99

Xilinx Fairchild Semi FoxConn Linear Tech. Tex. Inst. Molex FCT Elect. N/A Adv. Circ.

730.00 8.00 20.00 3.60 3.35 3.38 3.84 N/A 120.54

1 1 2 2 3 24 24 '300 1

730.00 8.00 40.00 7.20 10.05 81.12 92.16 100.00 120.54 1875.71

For a 16-channel MR. IMAGER, the cost-per-channel is $117. Again, it must be emphasized that this does not include costs such as labor, exterior design and electrical/medical certifications.

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References [1] B.

Black,

tem Design,

Analog-to-Digital Converter Architectures and Choices for SysAnalog

Devices

Inc.,

1988.

[Online].

Available:

http://www.analog.com/library/analogDialogue/archives/33-08/adc/final-adc.pdf [2] P. N. Morgan, R. J. Iannuzzeli, F. H. Epstein, and R. S. Balaban, “Real-Time Cardiac MRI Using DSPs,” IEEE Trans. Med. Imaging, vol. 18, no. 7, pp. 649–653, 1999. [3] H. D. Morris, et al., “A Wide-Bandwidth Multi-channel Digital Receiver and Real-Time Reconstruction Engine for use with a Clinical MR Scanner,” Proc. Intl. Soc. Mag. Reson. Med., vol. 10, no. 7, p. 61, 2002. [4] C. E. Shannon, “Communication in the Presence of Noise,” Proc. of the IRE, vol. 37, p. 1021, 1949. [5] Minimizing Component-Variation Sensitivity in Single Op Amp Filters, Maxim Integrated Products, 2001. [Online]. Available:

http://www.maxim-ic.com/appnotes.cfm/appnote

number/738 [6] D. Akerberg and K. Mossberg, “A Versatile Active RC Building Block with Inherent Compensation for the Finite Bandwidth of the Amplifier,” IEEE. Trans. Circuits and Systems, vol. CAS-21, no. 1, pp. 75–78, 1974. [7] E. B. Hogenauer, “An Economical Class of Digital Filters for Decimation and Interpolation,” IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-29, no. 2, pp. 155–162, 1981. [8] A. Dunkels, “Full TCP/IP For 8-bit Architectures,” Proc. First ACM/Usenix International Conference on Mobile Systems, Applications and Services, 2003. [9] Fast Fourier Transform v3.1, Xilinx Inc., 2004. [10] J. E. Volder, “The CORDIC Trigonometric Computing Technique,” IRE Trans. Electronic Computers, vol. EC-8, no. 3, pp. 330–334, 1959. 18

[11] C. Roth, Digital Systems Design Using VHDL, 1st ed.

PWS Pub, 1998.

[12] K. Nehrke, et al., “Free-breathing whole-heart coronary MR angiography on a clinical scanner in four minutes,” J. Mag. Res. Imag., vol. in print, 2006. [13] H. Muir, “Hope For Portable MRI Scanners,” The New Scientist, vol. 2494, 2005.

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