Multi-Chip Reticle Approach for OPC Model Verification Kunal N. Taravade∗ a, Nadya Belova a, Andrew M. Jost b and Neal P. Callan a a LSI Logic, Inc. ; bUniversity of Oregon ABSTRACT The complexity of current semiconductor technology due to shrinking feature sizes requires increased engineering efforts and expenses to deliver the final product to customers. One of the largest expense in the entire budget is reticle manufacturing. With the need to perform mask correction in order to account for optical proximity effects on the wafer level, reticle expenses have skyrocketed. For 0.13um technology one can not avoid optical proximity correction (OPC) procedure for modifying original designs to comply with design rules as required by Front End (FE) and Back End (BE) processes. Once an OPC model is generated one needs to confirm and verify the said model with additional test reticles for every critical layer of the technology. Such a verification procedure would include the most critical layers (two FE layers and four BE layers for the 130 nm technology node). This allows us to evaluate model performance under real production conditions encountered on customer designs. At LSI we have developed and verified a multi-chip reticle approach for verification of different OPC models. The proposed approach allows performing die-to-die reticle defect inspection in addition to checking the printed image on the wafer. It helps finalizing lithographic and etch process parameters. Processing wafers with overlaying masks for two consecutive BE layer (via and metal2 masks) allowed us to evaluate the robustness of OPC models for a wafer stack against both reticle and wafer induced misalignments. INTRODUCTION The design of the via reticle commenced with identifying critical circuits and modules which would appear most frequently on the 130 nm node designs and incorporating these into a multi-chip reticle format. These included a high density SRAM, as well as a critical random logic module. Two identical instances of the SRAM were included in order to facilitate die to die inspection on the reticle inspection tool. Further, in order to facilitate comparison between multiple OPC schemes (differentiated by the aggressiveness of corrections employed in each), different OPC models were applied to the logic and RAM modules. These cells were then arranged in a rectangular fashion to allow for a standard production scribe to be wrapped around each cell. In addition to the RAM and logic modules, a fourth cell, consisting of structures laid out for the purposes of lithographic testing and SEM cross-sections, was also included in the layout. The metal reticle was laid out with same configuration as the via reticle. The final layout for the two reticles is shown in Fig. 1. As indicated in the figure, each chip shown in the layout has its own scribeline wrapped around it. This scribe includes alignment marks and metrology structures to measure CDs and registration. A variety of OPC solutions, including rule and model based approaches, were included on the metal reticle. The rule based solution focused on through pitch 1-D correction, whereas the model based solutions were more rigorous, and included variations based on the aggressiveness of the corrections applied. On the via reticle, two model based solutions were applied for different DI targets, one at 190 nm and another at 220 nm. In addition to these, a number of solutions with a simple global bias were also present on the via reticle. ∗

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Proceedings of SPIE Vol. 5256 23rd Annual BACUS Symposium on Photomask Technology, edited by Kurt R. Kimmel, Wolfgang Staud (SPIE, Bellingham, WA, 2003) · 0277-786X/03/$15.00

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Figure 1: Layout of the Multichip vehicle for both Metal and Via levels.

As shown in the layout in Fig. 1, four instances each of the SRAM and logic designs were used for this vehicle. In one of the four instances, no OPC was applied, while different OPC models were applied to the remaining three designs. The top left die of the SRAM and Logic designs was blocked from OPC application. This would be the reference die for purposes of checking OPC models. Two identical copies of the SRAM designs were placed in the layout for performing die to die inspection on the reticles. Thus, the reticle allowed us to evaluate this important manufacturing procedure from the point of view of inspectability of the OPC solution we applied.

2.0 VIA RETICLE DESIGN AND CHARACTERIZATION The via reticle was designed to compare multiple approaches to resolution enhancements and process improvements that would meet all manufacturing restraints. The 4-chip layout for both the SRAM and Logic designs included two different OPC models, and a no-OPC reference cell as described earlier. Once the reticle was manufactured, a die to die inspection was performed on a Lasertec MD-2000 tool to compare the identical SRAM designs indicated in Fig.1. The intention of this comparison was to identify areas of patterning defects on the reticle caused by any aggressive OPC related features resulting in poor image fidelity.

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Two important metrics were used in the evaluation of the quality of OPC models for the via layer. One was through pitch performance for different OPC models, and the other was common process window for a +/10% CD change. The via reticle was manufactured on an Alta 3500 I-line Laser system. It is a 6% attPSM reticle and has a number of CD test cells with different biases applied to them. Those biases which cause sidelobes were eliminated from consideration. Simulations were performed to determine the optimum illumination settings using the internal Illumination Optimization (ILO) software. These results are shown in Fig. 2.

Figure 2: An example of an Illumination Optimization (ILO) run showing the optimum NA (X-axis) and outer Sigma (Y-axis) settings for maximum Depth of Focus (DOF).

Sidelobes were seen on some bias settings. In general, as the reticle bias (defined as the difference between the drawn or intended via dimension and the actual dimension on the reticle) decreases, the size of the via hole on the reticle decreases, requiring a larger exposure to hit the target. This situation causes sidelobes on the wafer, which, as shown in Fig. 3 were predicted by simulations and confirmed on the wafer.

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(b)

(c)

Figure 3: Sidelobes predicted on some bias settings. The image (a) shows predicted sidelobes in an aerial image simulation while (b) shows intensity profile along a cross-sectional line (shown on the picture on the left) indicating sidelobes. The wafer image is on the right.

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The simulations were then used to determine the bias which would not cause sidelobes on the wafer, while at the same time allow sufficient manufacturing window to resolve the space between adjacent holes. These results are shown in Fig. 4.

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Figure 4: Results of simulations showing a bias setting which eliminates sidelobes. Aerial image simulation shown in (a). Intensity profile in (b) shows no sidelobes are above the printing threshold. Wafer results are shown in (c).

Once the correct bias was chosen, cells corresponding to that bias with different OPC models were evaluated. One of the most important measures of an OPC model’s quality is how well it corrects for CD changes that occur as a result of optical effects at different pitches. This “Through-Pitch” CD metric is used to compare different OPC models, as shown in Fig. 5.

Figure 5: Comparison of Through Pitch performance for different OPC models. Model 1 was selected for production release. The CD target, and upper and lower spec limits are shown by dotted lines.

After the best OPC model was selected for further analysis, an exhaustive study of Bossung plots was conducted at various pitch values, to determine the overall common Depth of Focus. This is shown in Fig. 6 below. As seen in this, the OPC Model 1 gives a common DOF of about half a micron at 10% Exposure Latitude, which is acceptable for manufacturing.

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Figure 6: Overlapping Process Windows for various pitches shows a common DOF of 0.5 microns for OPC Model 1.

In addition to looking at wafer results, we also looked at die to die inspection using the top two identical die shown in the layout in Fig. 1.

Figure 7: Results of die to die inspection on the via reticle shows the ability of the tool to pick up patterning differences between two identical die on an attPSM substrate.

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3.0 METAL RETICLE DESIGN AND CHARACTERIZATION 3.1 Layout: As described in the introduction, the layout of the reticle for the metal layer was done in a multi-chip format with two fields consisting of critical high density RAM design, one random logic (Logic for short) chip and one test chip with process control patterns and test patterns for OPC model generation/verification (see Fig.1). Two SRAM die were laid out exactly the same for performing die-to-die reticle inspection. The random logic chip and the test die were intended for doing die-to-database reticle inspection. In turn each of three functional chips (SRAM and Logic), which were taken from a production CMOS flow, has four sub fields which include three different OPC schemes as well as a control No OPC (target) design. This scheme is identical to the one employed for the via reticle.

3.2 OPC model deployment and application: OPC VTRE model was generated using Mentor Graphics Calibre software [1]. Empirical data was collected on the targeted Mentor Graphics extended test pattern. The annular illumination source with 248nm wave length was used for wafer exposure. The 0.13um technology node metal stack was used for wafer preparation. The lithography conditions have been optimized to achieve minimum swing of the proximity curve (see fig.8) along with obtaining the wafer printed CD (DICD for short) equal to reticle CD in the target pitch. For lithography condition optimization in-house OPC package [2] was used. Iso-dense linearity shows approximately the same MEEF (fig.9) under optimal litho conditions (Litho_1). The target pitch has a common (5%EL/0.5um DOF) window with iso line. As uniformity (proximity) data under Litho_1 in fig.8 is within an acceptable (+/-10%) range of the DICD tolerance, the OPC procedure might need to be applied only for correcting 2D patterns. Therefore three schemes of the same OPC model have been adopted on the metal layer reticle to verify an additional factor called OPC aggressiveness.

Figure 8: Proximity curves under two different lithography conditions.

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Figure 9: Linearity for iso and dense (1:1) patterns under optimum Litho_1 condition. MEEF=1.15.

Three OPC models were applied on the metal reticle: 2D-only (OPC_1), Full OPC (OPC_2 same level of OPC aggressiveness as OPC_1), 2D-only with lower OPC aggressiveness level (OPC_3). In 2D-only scheme all 2D-features were tagged and passed into OPC-engine. The OPC model aggressiveness was defined by the minimum allowed distance between two trenches (external distance), which must comply with a mask shop specification for the particular writing tool. From these definitions it is clear that OPC_2 model has the highest fragmentation level as well. Overall, OPC_2 model is the easiest one for writing an OPC deck and the most complicated one for manufacturing.

3.3 Reticle performance: Reticle for metal layer OPC model verification is a regular binary one was manufactured Dupont Photomasks. Die-to-die analysis for RAM chips (which is high density design) was performed on a Lasertec MD2000 inspection tool.

3.3.1 1D-perfomance: In Fig.10 the behavior of DI CDs vs. space is shown. As one can see, there is a very little difference between uncorrected and OPC'ed lines (No OPC as well as OPC’ed CDs are within 5% range). It means the optimization of lithography conditions was done properly and mostly 2D features should be corrected. Although one should admit the Full OPC scheme (OPC_2) would not hurt if applied. An additional bias to iso features improves the EL/DOF process window (see Fig.11).

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Figure.10: Proximity curves before OPC applied and post OPC.

Figure11: Improved DOF Process window with additional bias applied to iso features.

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3.3.3 2D-performance: In Figures 12 and 13 the gap between iso/dense line ends is shown as a function of focus at a target dose which was chosen to meet the target dense pitch requirements: reticle CD = wafer CD marked in Figs. 8, and 10. As one can see, wafer gaps between line ends have been significantly improved by applying OPC_1/OPC_2 models which in essence, for line end correction, are the same. OPC_3 model is off by more than 10% from the line end target and should be dismissed if one uses only standard test cells for the OPC model justification. In Fig.14 five SEM images of RAM design are shown compare to No OPC SEM image (top) through the focus and dose variations. At the target dose/focus the critical gaps on design corrected by means of OPC_3 model matches the drawn gap better then the most aggressive OPC models. It means the more aggressive OPC_1/OPC_2 models overcorrect 2D dense design. Eventually, under certain dose/focus combination 2D line ends might bridge. The variation of dose/focus values within required range gives the robust 2D RAM performance with the least aggressive OPC_3 model with the greater external distance.

Figure12: Comparison of different post OPC iso line ends to No OPC one.

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Figure.13: Comparison of different post OPC dense line ends to No OPC ones.

Figure14: Performance of the OPC_3 model for realistic RAM design.

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CONCLUSIONS Optimum OPC models were generated and applied to via and metal layers of the critical 0.13um RAM and Logic designs in multichip fashion. For the via level, simulations were used to predict the best illumination conditions as well as the reticle bias which prevents sidelobes. These were subsequently verified on wafers. Different models were compared using through-pitch CD control, and the chosen model was shown to give an acceptable common process window for various via pitches spanning the design rules. For the metal level, the three applied OPC schemes differed by different external distance as well as by fragmentation level. For this particular work it was shown that both 2D-only and Full OPC schemes give 1D DI CDs within required range of tolerance. Even though the corrected gaps measured on the test pattern match the drawn gaps better with the higher level of OPC aggressiveness the measurements of 2D patterns from realistic designs could help in reasonable choice of OPC model restrictions.

ACKNOWLEDGEMENTS We thank John Jensen, Aftab Ahmed and the Reticle Engineering Group for their help in layout, design and data preparation.

REFERENCES [1]. Calibre User’s Manual, ver.2002.08, Mentor Graphics Corp. 2002.

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Multi-Chip Reticle Approach for OPC Model Verification

vehicle. In one of the four instances, no OPC was applied, while different OPC .... OPC VTRE model was generated using Mentor Graphics Calibre software [1].

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