International Conference on Computational Intelligence and Multimedia Applications 2007

Neural Network Based Macromodels for High Level Power Estimation Kuntal Roy Department of Electronics and Tele-Communication Engineering Jadavpur University, Kolkata - 700 032, India Email: kuntal [email protected] Abstract In this article, a neural network based macromodeling technique is proposed for high level power estimation of logic circuits. With the advent of high-density microelectronic devices, power dissipation of VLSI circuits has become a critical concern. Consequently power estimation accuracy at higher levels is an important issue to avoid costly redesign steps. Artificial Neural Network (ANN) with its capability to derive some meaning from complicated or imprecise data has been exploited for this purpose. A simple Back Propagation (BP) algorithm is employed to train a feed-forward neural network with the available data set to find out the weights and biases of the interconnecting layers, and subsequently the neural network is used as a model to determine the power dissipation for test inputs. The experimental results have been compared with that of the previous approaches and accordingly it establishes the effectiveness of the proposed approach for high level power estimation.

1. Introduction Complexity of VLSI and ULSI designs have increased rapidly due to a fast growth of semiconductor manufacturing techniques making power consumption a major design concern. Due to a limited battery life, possible cooling cost and corresponding reliability issue, power consumption can become a more critical design choice than area or speed of operation. Power consumption of modern microprocessors can exceed even 50 watts. So, power estimation techniques for designs have gained a lot of attention in research areas. A number of methodologies are proposed for gate-level power estimation [1]. But, gate-level power estimation techniques might not be useful in the sense that it can be too late to find out some problem. Accordingly, higher level power estimation is necessary and essential to avoid the costly re-design steps. Also, as millions of gates exist on a single chip, it has become practically quite impossible to do a power-aware design of each and every functional component at a low level of abstraction. So, it seems that high level power estimation [2, 3] is the only way to manage the complexity of a design. Several techniques are proposed for high-level power estimation in literature. In [4], the approach presented captures the dependence of power dissipation from its input/output switching activity. Then the resulting macromodel is used to estimate power consumption from any given input/output signal streams. The three dimensional Look Up Table (LUT) consists of average input signal probability, average input transition density and average output zero-delay transition density. It does not require any specialized analytical equations for power estimation. In [5], a modeling approach is proposed that consists of a quadratic or cubic equation containing four variables. In [6, 7], power macromodel has been proposed for behavioral library components. It is emphasized that high level synthesis is gaining

0-7695-3050-8/07 $25.00 © 2007 IEEE DOI 10.1109/ICCIMA.2007.117


acceptance in the design community. This technique is based on lookup table with three dimensions (average input probability, average input transition probability, and average output transition probability). In [8], a least mean squares (LMS) algorithm is proposed over least square fitting technique to relax computational requirements. In [9], regressionbased power modeling has been proposed at register transfer level (RTL) addressing both hard and soft macros. The model proposed in [10] is suitable for reconfigurable, synthesizable, soft macros because it is parameterized with respect to the input data size and can also be scaled with respect to different technology libraries and synthesis options. A neural network based modeling approach is proposed over the previous approaches to efficiently model the high level power consumption. The capability of neural networks is exploited as an algorithm of smart approximation. Historically, artificial neural networks (ANN) have been used in universal approximation (i.e., mapping inputs and outputs) tools capable of learning from their environment, tools for finding non-evident dependencies between data, and so on [11, 12]. Neural networks are modeled after the brain and how it processes the information. Hence, neural networks are very powerful tools. As a first step, we need to teach or train a neural network to make it familiar with the environment. A simple back-propagation (BP) feedforward network is used for experiment in this paper. Standard back-propagation is a gradient descent algorithm in which the network weights are moved along the negative of the gradient of the performance function. The term backpropagation refers to the manner in which the gradient is computed for nonlinear multilayer networks. A simple feedforward network is shown in Figure 1. It receives inputs that can be a pattern of some kind. After the neurons in the first layer receives input, it produces an output after some computation and subsequently this output becomes an input to the next layer. So, the layers feedforward the data to the next layer until the last layer is reached. In a nutshell, we need to only store the weights and biases of the connecting layers as a macromodel. We do not need to store all the experimental values as is required for lookup table based macromodel. Also, the proposed neural network model provides an output by multiplication and addition instead of searching through a lookup table. The rest of the paper is organized as follows. Section 2 describes the construction and characterization of power macromodels. The proposed neural network model is described in Section 3. The performance measures considered to assess the accuracy and effectiveness of macromodels are described in Section 4. In Section 5, experimental results along with the comparison with previous approaches is presented. Finally, Section 6 concludes the paper.

2. Power Macromodeling and Characterization A power macromodel should have the property of being simple so that we can get the estimates in a reasonable time. The big question is about what parameters are to be chosen for macromodel. It is quite reasonable that the (dynamic) power consumption depends on the circuit input switching activity. But, it can be seen from the Table 1 that the power consumption varies with respect to the number of 1s at the inputs of a Wallace tree multiplier. The variation is as high as 50 times. However, this can vary for different circuits depending on the internal structure of a circuit and it is highly pattern dependent.

3. Neural Network Model We have used back-propagation neural network model to construct the macromodel. A simple feedforward network containing three layers (input and output layer with one


Table 1. Variation of power with input-output transitions and 1s (4-bit Wallace tree multiplier). (In, Out) Transitions (16, 0) (16, 0) (16, 0) (16, 0)

(In, Out) 1s (8, 0) (8, 0) (8, 0) (8, 0)

Power 0.0025567 0.0022846 0.0027173 0.0040880

(In, Out) Transitions (16, 18) (16, 22) (16, 26) (16, 24)

(In, Out) 1s (792, 401) (792, 400) (792, 400) (792, 400)

Power 0.1291218 0.1484946 0.1118343 0.1498180

Figure 1. A generic neuron. hidden layer) is used. The number of neurons at the input and hidden layers are chosen as 8. Obviously, the output layer contains only one neuron since we have only one output that is power. A generic neuron structure is shown in Figure 3. The transfer function of the neurons at the input and hidden layers is assumed as log-sigmoid whereas a pure linear transfer function is chosen for the output neuron.

4. Performance Measures In this article, two performance measures are considered as in [6] to determine the accuracy and novelty of the proposed technique over the previous techniques. √ • RMSE, Relative Root Mean Square Error = M SE/AV G, where AV G is the average power on the test sample. • AVGE, Relative error on average = |AV Gmodel − AV G|/AV G, where AV Gmodel is the average power on the test sample employing a model. While RMSE provides information on how well the pattern dependence of power dissipation is modeled, AVGE is a measure of the accuracy in estimation of average power.

5. Experimental Results In this section we present our simulation results. Synopsys Design and Power Compiler along with Modelsim (by Mentor Graphics Corp.) are used to determine the power consumption of a circuit. We have considered a small as well as a high number of logic 1s at the input patterns to reflect the wide variation of power consumptions for a same number of input transitions. We have chosen four 4-bit multipliers (serial, booth, Wallace and parallel SA [13]) for experimental purpose. We have considered 100 consecutive input vectors applied at the two inputs of the multipliers and hence, the maximum number of logic 1s at the two inputs of a multiplier


Figure 3. Lookup table model for Par-

Figure 2. Linear equation model for Parallel SA multiplier.

allel SA multiplier.

= 2*4*100 = 800 and the maximum number of input transitions = 2*4*(100-1) = 792. Different numbers of input transitions at an interval of 8 are generated. Also, 8 sets of different inputs are considered for one specific number of input transitions. In this way, 792 (792*8/8) simulations are performed. Then the simulation results are used for characterization of linear equation, lookup table, and the proposed neural network model. Number of test input patterns is considered as 200 separately to verify the accuracy and robustness of the models. For each multiplier, the same procedure is performed. The Figures 2, 3, and 4 show the corresponding results applying different models for a parallel SA multiplier. It can be verified from the figures that the proposed neural network model is performing much better than the other two approaches. From Table 2, it can be verified that the the neural network model is performing 7 and 5 times better than the lookup table technique in calculation of RMSE and AVGE, respectively. One important point to observe is that the linear equation model really cannot be used as an efficient macromodel. However, it is noticed that the linear equation model is performing better than the lookup table model for Booth multiplier. The reason behind is that the power consumption variation for Booth multiplier is quite linear with respect to its input transitions. But still the proposed neural network model performs better than the linear equation model for Booth multiplier more than twice. So, it signifies that the proposed neural network model has been able to find out some meaning for the input patterns.

Table 2. Comparison of different models. Multiplier Serial Booth Wallace Parallel SA

Linear Equation RMSE AVGE 0.2443 0.1866 0.0512 0.0401 0.3269 0.2639 0.3269 0.2170

Lookup RMSE 0.1582 0.1683 0.1658 0.1658

Table AVGE 0.0889 0.1028 0.1036 0.0979

Neural Network RMSE AVGE 0.0228 0.0168 0.0224 0.0168 0.0283 0.0195 0.0312 0.0225

6. Conclusions A neural network model is proposed to efficiently characterize a macromodel for high level power estimation. The corresponding results are presented comparing with the previous


Figure 5. Performance vs. epochs for a sample run (4-bit Wallace tree multiplier).

Figure 4. Neural network model for Parallel SA multiplier.

approaches. It is justified from the results that the proposed neural network model performs quite generally independent of the variation of the power consumptions for different input patterns. The proposed model can be extended very easily if it needs to take care of some more parameters during macromodeling.

References [1] F. N. Najm, “A Survey of Power Estimation Techniques in VLSI Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, pp. 446–455, Dec. 1994. [2] P. Landman, “High-Level Power Estimation,” in ISLPED’96: ACM/IEEE Int. Symp. Low-Power Electronics and Design, Monterey, CA, Aug. 1996, pp. 29–35. [3] M. Nemani and F. N. Najm, “Towards a High-Level Power Estimation Capability,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 6, pp. 588–598, June 1996. [4] S. Gupta and F. N. Najm, “Power Macromodeling for High Level Power Estimation,” in Design Automation Conference, 1997, pp. 365–370. [5] ——, “Analytical Model for High Level Power Modeling of Combinational and Sequential Circuits,” in IEEE Alessandro Volta Memorial Workshop on Low-Power Design, 1999, pp. 164–172. [6] L. Benini, A. Bogliolo, M. Favalli, and G. D. Micheli, “Regression Models for Behavioral Power Estimation,” Integrated Computer-Aided Engineering, vol. 5, no. 2, pp. 95–106, 1998. [7] M. Barocci, L. Benini, A. Bogliolo, B. Ricco, and G. D. Micheli, “Lookup Table Power Macro-Models for Behavioral Library Components,” in IEEE Alessandro Volta Memorial Workshop on Low-Power Design, 1999, pp. 173–181. [8] A. Bogliolo, L. Benini, and G. D. Micheli, “Adaptive Least Mean Square Behavioral Power Modeling,” in EDTC’97: IEEE European Design and Test Conf., Paris, France, Mar. 1997, pp. 404–410. [9] ——, “Regression-Based RTL Power Modeling,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 5, no. 6, pp. 337–372, July 2000. [10] A. Bogliolo, R. Corgnati, E. Macii, and M. Poncino, “Parameterized RTL Power Models for Soft Macros,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 6, pp. 880– 887, Dec. 2001. [11] S. Haykin, Neural Networks: A Comprehensive Foundation (2nd Edition). [12] C. Bishop, Neural Networks for Pattern Recognition.

Prentice Hall, 1999.

Oxford University Press, 1995.

[13] A. Vachoux, “VHDL modeling, simulation and synthesis of a generic N-bit multiplier,” digital systems modeling lab, EPFL/STI-IMM-LSM.


Neural Network Based Macromodels for High Level ... - IEEE Xplore

A simple Back Propagation (BP) algorithm is employed to train a feed-forward neural network with the available data set to find out the weights and biases of the interconnecting layers, and subsequently the neural network is used as a model to determine the power dissipation for test inputs. The exper- imental results have ...

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