On the Design of a Multi-Mode Receive Digital-Front-End for Cellular Terminal RFICs Gernot Hueber∗ , Linus Maurer† Georg Strasser‡ , Rainer Stuhlberger¶ , Karim Chabrak§, and Richard Hagelauer∗ ∗ Research

Institute for Integrated Circuits (RIIC), Johannes Kepler University, Altenbergerstrasse 69, A-4040 Linz, Austria, +43 732 2468 7120, Email: [email protected] † Danube Integrated Circuits Engineering (DICE), Linz, Austria ‡ Linz Center of Competence in Mechatronics (LCM), Linz, Austria § Institute for Technical Electronics, University of Erlangen, Germany ¶ Institute for Communications and Information Engineering (ICIE), Linz, Austria

Abstract— Developments aimed at the software-defined-radio (SDR) concept for cellular applications received increasing attention due to necessity of multi-mode/multi-system capable terminals for next generation cellular communication systems. This paper describes a highly reconfigurable digital-front-end (DFE) enabling multi-mode capable RF receivers for cellular applications. Its main functionality includes sample-rate-conversion, channel filtering, dynamic range control, and signal conditioning for transmission via a digital interface from RFIC to baseband IC. The described partitioning shifts some of the functionality, traditionally located in the analog-front-end (channel filtering, gain control) to the digital-front-end. The technology shift towards RF-CMOS further favors this strongly digital receiver architecture.

I. I NTRODUCTION Due to the diversity in mobile communications standards, the concept of software-defined-radio (SDR) has grown major importance. Key advantages of SDR include shorter terminal development cycles and greater debugging capabilities. The ability to adopt new standard features by updating the RFIC controller firmware is a crucial advantage. Reusing configurable blocks like an, e.g. fully programmable FIR filter, for different standards reduces the needed silicon area and thus costs. Another major issue are strong market demands for 2G/3G capable RFICs at costs comparable to current 2G solutions. This paper discusses trade-offs and design considerations for a fully configurable receive DFE aimed at GSM-EDGE, IS-95, and the UMTS frequency division duplex mode (FDD) communication system. A

LNA

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Ideal software-define-radio receiver.

The architecture of the ideal software-defined-radio ([1], [2], [3], [4]) receiver with a minimum of analog components is shown in Fig. 1. Due to the excessive requirements on the ADC specification in terms of sampling rate and dynamic range requirements, the direct RF sampling architecture depicted in Fig. 1 does not seem to be a technical feasible solution. Even if the ADC sampling rate is chosen commensurate for a subsampling architecture ([5]) the resulting ADC clock jitter performance is extremely difficult to achieve.

Recently published state-of-the-art single-mode receivers include a receiver in 75-GHz, 0.35 µm SiGe BiCMOS [6], and a receiver in 0.13 µm CMOS [7], respectively, as well as a receiver capable of CDMA/WCDMA and AMPS reception in SiGe BiCMOS [8]. To the authors knowledge, the presented receiver is the only single-chip multi-mode transceiver designed for GSM-EDGE/IS-95/UMTS application in RF CMOS with a digital baseband interface, whereas the transmitter part of the presented testchip is discussed in [9]. First of all Sect. II copes with the partitioning of a multimode capable receiver architecture. The design of the digitalfront-end is presented in Sect. III, where implemented filter stages are described in detail and further enhancements are discussed. Finally the micrograph of the receiver RFIC and simulation results for the multi-mode DFE are presented in Sect. III-D and Sect. IV, respectively. II. R ECEIVER A RCHITECTURE Fig. 2 depicts the chosen receiver architecture. The analogfront-end is a zero-IF (ZIF) receiver, which is currently the dominant architecture in the cellular market ([10]). Due to ZIF architecture no images will occur, therefore, no additional filters are required. Main advantages of ZIF architecture is there are no images of the RF-signal relaxing requirements on LNA which needs no additional filtering. Furthermore baseband processing can make use of main stream technology such as CMOS. On the other hand the local oscillator (LO) has limited isolation to the RF path. The leakage of the LO signal into the RF path causes an unwanted DC-offset after down conversion. Moreover large amplitude modulated signals that are converted to the base band section via second order distortion of the IQ-mixers lead to time varying DC-offsets demanding a large second order intercept point (IP2) of the IQ-mixer. In addition the baseband signal processing is subject to considerable flicker noise in CMOS implementations due to the low signal levels at the baseband input mainly. A. RF Front-End The fractional-N type-I phase-locked loop (PLL) is fully integrated on chip. Digital tuning is employed for the loop filter, the voltage controlled oscillator (VCO) and the charge pump. A VCO with a tuning range of 1500 MHz can serve all worldwide available GSM, CDMA2000 and UMTS frequency bands.

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RF−IC A

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Fig. 2. Block diagram of the receiver, based on zero-IF topology, with the digital serial baseband interface.

with bitwidth N, loopfilter order L and over-sample-rate OSR. Tab. II-B summarizes the specification of the multi-mode ADC for this receiver, where sample rate has been chosen to 104 MHz for all modes. C. Digital-Front-End

By shifting channelization and decimation to the DFE the anti-aliasing lowpass filter specification can be kept low. A 3rd order butterworth filter with a constant cut-off frequency at 3.3 MHz for wideband standards and 1.12 MHz for narrowband standards is employed. Additionally gain control is moved partially from a analog baseband gain stage to digital domain which requires an increased dynamic range of the ADC. This requirement benefits overall analog IC area and power consumption.

D. Digital Interface

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The output signal is transferred to the baseband IC via a digital serial interface. Datarate has to be low to minimize power consumption and noise injection into the AFE. Therefore, samplerate is decimated in the filter stages by integer factors to approximately 2 times or 4 times chip/symbolrate with bitwidths up to 16 bit. By using a digital interface, all analog or mixed-mode blocks are shifted to the RFIC and the baseband IC is left purely digital.

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The DFE architecture considered is built as shown in Fig. 4. The architecture is capable of standard compliant reception of the standards depicted in tab. II-B. Adapting the DFE to the different requirements can be done by configuring the filter blocks in the DFE. Furthermore the sequencing of the DFE blocks can be changed. The DFE is built of a highly configurable cascade of filter and signal processing blocks for decimation and channel filtering (CIC, WDF, FIR, Allpass, Notch, FSRC, and CORDIC), which will be discussed thoroughly in sect. III.

Dynamic Range of adjacent Interferers SNR ADC Noise Distance 10−20 dB

III. DFE F ILTER I MPLEMENTATION Fig. 3. Dynamic range estimation at the input of the ADC for the UMTS ACS testcase.

Fig. 3 shows an exemplary estimation of the required dynamic range for the ADC. The required signal-to-noise (SNR) ratio can be calculated from the spreading gain, the coding gain, and the receiver noise-figure (NF), and the bit energy to interference ratio ([11]). B. Analog-To-Digital Converter Mode GSM IS-95 UMTS

No. of eff. bits 14 14 11.5

Dynamic range >86 dB >86 dB 71 dB

Bandwidth 240 kHz 650 kHz 1920 kHz

TABLE I S PECIFICATION OF THE MULTI - MODE ADC.

The ADC has become a key component of mobile communications systems. This stems mainly from the fact that reconfiguration of analog blocks is in many cases extremely difficult if not impossible. Shifting the reconfiguration capabilities to the digital domain alleviates the specification for most of the pure analog blocks. However, the ADC has to handle signals with much larger dynamic range and bandwidth due to the fact that worst case adjacent channel interferers have to be converted, too, without deteriorating the wanted signal band.

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With channel filtering and decimation the crucial functionality of the receiver described in sect. II-C has been implemented on silicon. With this functionality datarate can be sufficiently reduced to be transferable to the baseband IC on the digital interface. For high reconfigurability the decimation partitioning, the filter coefficients, and the sequencing of filter modules can be adapted. The filter modules yet implemented and further enhancing modules are discussed thoroughly in the following. A. Cascaded-Integrator-Comb Filter In a cascaded-integrator-comb filter (CIC) the signal is decimated by an integer factor very efficiently.The 5th order CIC filter is built of 5 cascaded integrators clocked at the input sample frequency (ADC output), followed by a configurable rate change reduction R and 5 cascaded comb stages running at the reduced output sample rate. The transfer function of a N-th order CIC is described by N  1 − z −RM (2) HCIC = 1 − z −1 The CIC filter is reconfigurable by adjusting the decimation factor R and the number of delays M in the comb stage. Due to the simplicity of the filter, integrators and combs are implemented using one adder each, SRC can be performed at minimum cost in IC area and power consumption. Nevertheless due to minimum hardware cost the major drawback in

8th European Conference on Wireless Technology 2008, Paris

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using CIC filters is the passband droop and loss in anti-aliasing attenuation if the signal is decimated to 2 times or 4 times chip or symbol rate. For this reason additional decimation stages have to be used. B. Wave-Digital-Filters The channel filtering and final integer decimation is performed in wave-digital filters (WDF) ([12], [13]) at reasonable cost in area and power due to the reduction in data rate. A N-th order lattice lowpass WDF is built of N adaptors (allpass sections) distributed over two branches. The transfer function of a first order lattice adaptors is defined by HA1 (z)=

1 − γ1 z z − γ1

a constant rate for all modes. Thus conversion to the exact chip/symbol-rate is performed in a fractional sample-rateconverter (FSRC) after channelization filtering. Therefore, the demand on the FSRC internal image reject anti-aliasing filter is reduced because no adjacent channel power folds into wanted signal band. The required fractional SRC factor is limited the range of 1 to approximately 1.3 due to the fact that integer decimation reminder can be minimized if OSR at the DFE’s input is high which is offered inherently by using ∆Σ ADCs. D. IC Implementation

(3)

and for a second order lattice adaptors by HA2 (z)=

1 + (γ2 − 1)γ1 z − γ2 z 2 −γ2 + (γ2 − 1)γ1 z + z 2

(4)

The transfer function of the overall 7-th order WDF is given by the summation of the two branches built of one first order and a second order lattice blocks for H0 and two second order adaptors for H1 H0 (z)=HA1 (z, γ0 )HA2 (z, γ3 , γ4 )

(5)

H1 (z)=HA2 (z, γ1 , γ2 )HA2 (z, γ5 , γ6 ) (6) 1 H(z) = (H0 (z) + H1 (0)) (7) 2 Although the WDF can be used perfectly for last stage decimation using halfband configuration and factor 2 decimation (performed by a 5th order WDF) and high attenuating channel filters (7th order WDF), linear phase can not be obtained. C. Further enhancements to the DFE to support a symbolrate/chiprate digital interface The function of the finite-impulse-response filter (FIR) in the multimode receiver is twofold. First task is the reduction of passband ripple induced by the CIC’s droop or WDF in the passband. Secondly the FIR performs the pulse filtering according to each communication standards specification (eg. root-raised cosine for UMTS). The reconfiguration for all standards requires full configurability of the taps. A coordinate-rotation-digital-computer (CORDIC) is used to adjust frequency offsets. A second order IIR filter is used to implement the allpass function used for phase linearization required due to group delay ripple introduced by the IIR type WDF filter stage. The notch filter is used to eliminate the DC offset induced by the ADC and the analog-front-end (AFE). Since decimation in the CIC and WDF stages is integer only, the target sample rate of exact 2 times or 4 times chip or symbolrate cannot be obtained if the ADC is clocked at

Fig. 5. Micrograph of the multi-mode transceiver testchip which has been fabricated in 0.12 µm RF-CMOS.

The micrograph of the transceiver IC shown in Fig. 5 is implemented in a 0.12 µm RFCMOS process. IV. S YSTEM S IMULATION The DFE implementation provided in this paper together with a ∆Σ ADC model has been measured and evaluated for the main cellular communication standards listed in Tab. IIB. The implementation of the DFE has been verified using error-vector-magnitude (EVM) simulations for both, with and without adjacent channel interferer. Fig. IV shows the input signal of the ADC for the UMTS adjacent channel selectivity (ACS) testcase. The power level of the desired channel is 40 dB lower than the power of the adjacent channel. Fig. IV demonstrates that the adjacent channel has been entirely extinguished at the DFE output, whereas the signal has been decimated to four times the UMTS chip-rate of 15.36 Mcps simultaneously. The resulting EVM at the DFE output is 1.8% without adjacent channel and 4 % in the ACS testcase, respectively. The IS-95 single tone desensitization testcase is shown in Fig. 8, where the interfering signal has a frequency modulation with a bandwidth of 30 kHz placed at a frequency offset of only 900 kHz from the center frequency of the wanted signal is shown in Fig. 8 The power of the interfering signal is 71 dB above the desired signal level. By reconfiguration of the decimation sequence and channel filter coefficients the

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Fig. 9. Output spectrum of DFE with an adjacent channel in the IS-95 testcase with an AMPS interferer 71 dB above wanted channel.

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end to the digital domain. This transfer relaxes requirements on the analog filters which can be downsized significantly. Additionally this concept benefits flexibility and is perfectly suitable for multi-mode communication systems.

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ACKNOWLEDGMENT

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The authors would like to thank Zdravko Boos of Infineon Technologies for his support and fruitful discussions. This work was supported by the Linz Center of Competence in Mechatronics (LCM) within the framework of the Kplus program of the Austrian government.

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Fig. 7. Output signal of DFE with an adjacent channel in the UMTS ACS testcase

receive DFE is capable of reception of IS-95 mode signals. The resulting signal at the DFE output is demonstrated in Fig. 9. The EVM simulations yields 10.8%. without interferer.Again, the DFE output rate is decimated to four times IS-95 chip-rate of 4.9152 Mcps.

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Fig. 8. Input spectrum of DFE with an adjacent channel in the IS-95 testcase with an AMPS interferer 71 dB above wanted channel.

V. C ONCLUSION This paper presents a DFE specifically designed for multimode terminal RFICs. which reflects todays technologies limits especially limits of sample rate and bandwidth for ADC, digital-front-end, power consumption and IC area. Current ADC technology provides sufficient dynamic range and bandwidth for shifting functionality from the analog-front-

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R EFERENCES [1] G. Hueber, L. Maurer, G. Strasser, K. Chabrak, R. Stuhlberger, and R. Hagelauer, “On the concept of a multi-mode agile receive digitalfront-end for cellular terminals,” in Proc. 16th IEEE International Symposium on Personal Indoor and Mobile Radio Communications, Sept. 2005. [2] G. Hueber, L. Maurer, G. Strasser, K. Chabrak, R. Stuhlberger, and R. Hagelauer, “SDR Compliant Multi-Mode Digital-Front-End Design Concepts for Cellular Terminals,” WSEAS Transactions on Electronics, vol. 2, no. 1, pp. 23–27, Jan 2005. [3] T. Hentschel, M. Henker, and G. Fettweis, “The digital front-end of software radio terminals,” IEEE Personal Commun. Mag., Aug. 1999. [4] L. Maurer, T. Burger, T. Dellsperger, R. Stuhlberger, G. Hueber, M. Schmidt, and R. Weigel, “A Digital Front-End Supported Frequency Agile Multi-Standard Wireless Receiver,” Frequenz, Journal of RFEngineering and Telecommunications, vol. 59, Jan./Feb. 2005. [5] B. Razavi, “Design considerations for direct–conversion receivers,” IEEE Trans. Circuits Syst., June 1997. [6] W. Thomann, V. Thomas, R. Hagelauer, and R. Weigel, “A Singlechip 75-GHz/0.35-µm SiGe BiCMOS W-CDMA Homodyne Transceiver for UMTS Mobiles,” in IEEE Radio Frequency Integrated Circuits Symposium, 2004. [7] J. Rogin, I. Kouchev, G. Brenna, D. Tschopp, and Q. Huang, “A 1.5-V 45-mW Direct-Conversion WCDMA Receiver IC in 0.13-µm CMOS,” IEEE J. Solid-State Circuits, vol. 38, no. 12, Dec. 2003. [8] V. Aprarin and et al., “A highly-integrated tri-band/quad-mode SiGe BiCMOS RF-to-baseband receiver for wireless CDMA/WCDMA/AMPS applications with GPS capability,” in IEEE Proc. Int. Solid-State Circuits Conf., Feb. 2002. [9] G. Strasser, G. Hueber, L. Maurer, T. Bauernfeind, S. Martin, and A. Springer, “Reconfigurable Mixed-Signal Single-Chip Transmitter for Multistandard-Terminals,” in Proc. European Microwave Week 2005 (EUMW), Oct. 2005. [10] A. Springer, L. Maurer, and R. Weigel, “RF System Concepts for Highly Integrated RFICS for W-CDMA Mobile Radio Terminals,” IEEE Trans. Microwave Theory Tech., Jan. 2002. [11] L. Maurer, C. Lanschutzer, A. Springer, and R. Weigel, “System-defined design and performance of RFICs for W-CDMA mobile radio terminals,” e&i, 2001, 118. Jg. [12] L. Gaszi, “Explicit formulas for lattice wave digital filters,” IEEE Trans. Circuits Syst., vol. CAS-32, no. 1, Jan. 1985. [13] A. Fettweis, “Wave digital filters: Theory and practice,” in Proc. IEEE, vol. 74, no. 2, Feb. 1986.

8th European Conference on Wireless Technology 2008, Paris