Computers & Industrial Engineering xxx (2011) xxx–xxx

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Overall Wafer Effectiveness (OWE): A novel industry standard for semiconductor ecosystem as a whole Chen-Fu Chien a,⇑, Chia-Yu Hsu b, Kuo-Hao Chang a a b

Department of Industrial Engineering and Engineering Management, National Tsing Hua University, Hsinchu 30013, Taiwan Department of Information Management, Yuan-Ze University (YZU), Chung-Li 32003, Taiwan

a r t i c l e

i n f o

Article history: Available online xxxx Keywords: Overall Wafer Effectiveness (OWE) Wafer productivity Fab economics Manufacturing strategy Semiconductor ecosystem Industry standard

a b s t r a c t As semiconductor industry reached nanotechnology generation and consumer electronics era, the competition is no longer among individual semiconductor companies. Indeed, the collaborations among horizontally specialized value providers are critical for the success of the companies as well as the whole ecosystem. This paper aims to propose a novel index, i.e., Overall Wafer Effectiveness (OWE), to measure wafer productivity and drive various improvement directions for semiconductor ecosystem as a whole. Furthermore, the proposed OWE can be easily extended to incorporate additional attributes such as mask-field-utilization, throughput, and yield for effective management. We conducted a number of case studies in real settings. The results have shown that OWE can be employed as a semiconductor industry standard to drive collaborative efforts among IC designers, equipment vendors, and manufacturers in the ecosystem to enhance total wafer effectiveness. This paper concludes with discussions on value propositions of proposed OWE indices and future research directions. Ó 2011 Elsevier Ltd. All rights reserved.

1. Introduction The research and application of industrial engineering are facing challenges in light of the changes of industry structures in many countries as well as the evolutionary ecosystems of various businesses. There should be a systematic methodology of ‘‘industrial engineering’’ that focuses on ‘‘the industry and ecosystem as a whole’’ as the subject of study to differentiate industrial engineering from other disciplines. Focusing on semiconductor ecosystem, this paper is part of continuous research efforts to construct a systematic methodology of industrial engineering to investigate the industry as a whole. In particular, semiconductor industry is one of the most complicated industries in which productivity enhancement, yield enhancement, continual cost reduction, fast ramp-up, on-time delivery, and cycle time reduction are the important ways for operational excellence to maintain competitive advantages (Chien & Wu, 2003). Driven by Moore’s Law (1965) that the number of transistors fabricated in the same size area will be doubled every 12–24 months to provide more capability at equal or less cost, the semiconductor industry has strived for continuous technology migration and cost reduction. Semiconductor compa-

⇑ Corresponding author. Address: Department of Industrial Engineering and Engineering Management, National Tsing Hua University, 101, Section 2, Kuang Fu Road, Hsinchu 30013, Taiwan. Tel.: +886 3 5742648; fax: +886 3 5722685. E-mail address: [email protected] (C.-F. Chien).

nies have coevolved in the ecosystem (Moore, 1993), in which the companies involved in various layers of semiconductor value chain work cooperatively and competitively to develop new technology, satisfy customer needs, and eventually incorporate the next round of innovations. Therefore, semiconductor industry has a clockspeed (Fine, 2000) faster than other industries for technology migration and thus can provide an important benchmark for other industries. Semiconductor industry is very capital-intensive, in which the co-evolution of the semiconductor industry has been driven by technical advance and economical interest to maintain the growth and profitability via modularity and virtual integration (Chien and Kuo, 2011). Indeed, corporate manufacturing strategic decisions involve the interrelated elements of the PDCCCR framework (Chien, Chen, & Peng, 2010) including pricing strategies (P), demand forecast and demand fulfillment planning (D), capacity planning and capacity portfolio (C), capital expenditure (C), and cost structure (C), that will affect the overall return (R) of a company, as illustrated in Fig. 1. In particular, productivity enhancement is critical to improve cost structure for profitability, while conventional approaches focused on miniaturization through technology advances, wafer size enlargement for scale economy, fast yield learning, tool productivity, and supply chain management. To capture the overall equipment performance for identifying and analyzing hidden performance losses, Overall Equipment Effectiveness (OEE) considering equipment availability, utilization, and output quality was developed as

0360-8352/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.cie.2011.11.024

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Price Elasticity Pricing Strategy

Demand Planning Product Mix

Margin

Structure Profitability

Return

Demand Fulfillment

Utilization

Cost Parity Cost Structure

Capacity Portfolio Capital Expenditure

Fig. 1. The PDCCCR framework of manufacturing strategy (Chien et al., 2010).

an industry standard (Nakajima, 1988; SEMI E79-0200, 2000). In particular, SEMI E10-0701 (2000) is the guideline that specifies the definition and measurement of equipment reliability, availability, and maintainability (RAM) for equipment performance based on different equipment statuses for measuring equipment RAM performance, in which equipment time can be decomposed into key blocks associated with the basic statuses and sub-statuses. Furthermore, SEMI E79-0200 (2000) defines OEE as the fraction of total time that equipment is producing effective units at theoretically efficient rates. In particular, effective units denote the number of units processed by the equipment during production time that were of acceptable quality, i.e., actual unit output minus equipment assignable rework and scrap. Nevertheless, conflicts and uncertainties often exist among these performance indices such as cycle time, throughput, WIP (work in process), utilization, and operational efficiency. OEE indices and SEMI E10 have been widely accepted as a set of industry-wide standards for measurement of equipment productivity among equipment buyers, suppliers, and manufacturers in semiconductor manufacturing. However, there is limitation for evaluating only OEE of a single machine in semiconductor manufacturing. de Ron and Rooda (2005) proposed a new metric to compare and to improve tool productivity by excluding environment factors such as operator, recipe, facilities, material availability, scheduling requirements and used only effective time as the time base. Moreover, Chien, Chen, Wu, and Hu (2007) proposed an Overall tool Group Efficiency (OGE) indices to observe the equipment performance at tool group level and applied statistical efficiency control charts to continuously monitor OEE over time. The equipment performance can be monitored from critical tool groups to single machines via longitudinal analysis and then root-cause analysis of machine statuses can be employed to identify possible performance detractors. In addition, the metrics for OEE is not sufficient to evaluate and track the performance of whole factory. SEMI E124-1107 (2007) defined a set of metrics for overall factory efficiency (OFE) that is the volume efficiency multiplied by the yield efficiency and can be decomposed into the subordinate metrics including the basic metrics as shown in Fig. 2. In particular, the production metrics are used to represent the volume efficiency that considers the performance of throughput rate, cycle time efficiency, and WIP efficiency with respect to the process efficiency. The quality metrics are used to represent yield efficiency that considers the performance of line yield and test yield with respect to the overall material efficiency. The cycle time efficiency and throughput rate efficiency, such as best-case throughput rate and actual throughput rate, can be measured by similar metrics. Thus, the OFE can be employed to evaluate how well a factory is operating compared to how well it could be with the given conditions such as product mix. The metrics of OFE are intended for evaluating the overall efficiency of factory operation, not for diagnosing

problems in the factory, though it can be used to indicate whether the factory has poor performance in specific indices such as throughput, utilization, defect density, daily starts and output (SEMI E124-1107, 2007). Alternatively, to diagnose problem and identify bottleneck for improvement in the factory, Muthiah and Huang (2006) proposed the effectiveness metrics of overall equipment effectiveness and Overall Throughput Effectiveness (OTE) for calculating equipment and system productivity for complex-connected manufacturing systems including series, parallel, assembly and expansion subsystems. Furthermore, Kuo, Chien, and Chen (2011) structured the influence relationships of the factors and developed manufacturing intelligence approach to analyze the massive production data and tool data to derive effective rules for cycle time reduction and throughput effectiveness. However, little research has been done to address productivity from the perspective of wafer exposure performance. To develop a generic methodology to address the wafer productivity for the semiconductor ecosystem as a whole, this paper aims to propose a novel standard, namely Overall Wafer Effectiveness (OWE), for measuring overall wafer exposure effectiveness. OWE can identify different types of wafer area losses owing to equipment, lithography technology, exposure pattern, and production variation. We conducted different case studies to examine the values of proposed OWE. The results showed that the proposed OWE can be used as a semiconductor industry standard and indices to drive collaborative efforts among IC designers, equipment vendors, and manufacturers for enhancing productivity and total wafer effectiveness. 2. Wafer productivity Most of the existing studies focused on improving operational efficiency such as OEE, cycle time, WIP, and throughput. In particular, since photolithography is generally the bottleneck for wafer fabrication, a number of approaches on scheduling and dispatching (Dabbas & Fowler, 2003; Chien & Chen, 2007), yield enhancement (Allan, Walton, & Holwill, 1992; Cunningham, Spanos, & Voros, 1995; Chien & Hsu, 2006), and tool productivity (Chien, Chen, et al., 2007; Leachman, 1997) in photo area are developed to improve operational efficiency. This paper proposed a novel approach for wafer productivity enhancement and cost reduction with a set of metrics. The capital investment and operating costs of wafer fabrication are rising significantly because of the increasing complexity of the manufacturing process and the costly fabrication equipment. In order to enhance the competitive advantages for wafer fabrication, it is important to reduce die costs by improving wafer productivity as the technology is keeping migration. The wafer productivity can be defined as the fraction of the effective useful wafer area to the total wafer area.

wafer productivity ¼

output effective useful wafer area ¼ input total wafer area

ð1Þ

The useful wafer area, the product of number of good die and die size, is determined by yield rate and gross die number. In particular, the problem for determining wafer exposure pattern can be structured as cutting and packing problems or knapsack problems (Chien, Hsu, & Chen, 1999, 2002; Chien, Hsu, & Deng, 2001). Most of the cutting and packing problems are known to be NP-complete. However, this problem can be done within reasonable time limit because of the specific characteristics listed as follows. Firstly, all the cut rectangular pieces of dies and fields from the circular wafer are the same sized. Secondly, the numbers of the dies and fields patterned on a wafer are unconstrained. Thirdly, the dies patterned on a wafer have with equal profit.

Please cite this article in press as: Chien, C.-F., et al. Overall Wafer Effectiveness (OWE): A novel industry standard for semiconductor ecosystem as a whole. Computers & Industrial Engineering (2011), doi:10.1016/j.cie.2011.11.024

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Fig. 2. Breakdown of OFE (SEMI E124-1107, 2007).

Furthermore, considering the semiconductor fabrication process and exposure equipment system characteristics, there are several specific constraints differentiating this problem from the twodimensional guillotine cutting problem (Beasley, 1985; Hifi, 1997). First, the wafer shape is approximate circular. Second, each horizontal and vertical sawing along the scribe line cannot cut into any die. Third, the borders of the wafer cannot be used to produce gross dies. Nevertheless, a complete field that consists of multiple dies may still pattern dies inside the effective radius when lying partly in the borders. And these kind of complete fields need to be exposed on wafer. Fourth, the primary alignment marks on wafer are used for alignment by specific exposure tool (e.g., stepper or scanner), and no pattern can be exposed above the marks. Meanwhile, there will be no pattern area between primary alignment marks and surrounding complete fields. Thus, incomplete field maybe exposed here with tolerable distance to primary alignment marks, to gain as many gross dies as possible and enhance the yield of gross dies in surrounding complete fields. Fifth, complete field or incomplete field without any gross die may be exposed in the borders to enhance yield of dies in inner side complete fields. Sixth, exposure throughput is influenced by die size and field placement layout. The count of gross die significantly influences the wafer productivity and is important in wafer fabrication. In particular, Ferris-Prabhu (1989) presented an algebraic expression that characterized relation between the die number to the wafer diameter and to the geometric parameters of the die. The algebraic expression of gross die which considered the potential

chip loss of wafer edge provides an approximate count of die firstly. Moreover, de Vries (2005) provided different forms of gross die per wafer formulas in which the exact counts of gross die per wafer were expressed as a function of die area and die aspect ratio. However, the exposure layout on a wafer in the wafer fabrication facility (fab) must optimize the gross die number by considering the equipment requirements and process limitations, e.g. the alignment mark is need for calibration and cannot be patterned. Therefore, rather than constructing a mathematical model to count the gross die per wafer exactly, Chien et al. (1999, 2002) developed an iterative cutting procedure for determining the optimal exposure pattern for 6-in. wafers which also can be applied into larger wafer with flat bottom. Chien et al. (2001) developed a two-dimensional cutting algorithm to maximize the gross die yields of the 8-in. wafers and larger circular wafers. The iterative cutting algorithm further provides a practical layout pattern for wafer fab. The wafer exposure layout not only reduces the operating cost by minimizing the number of exposures per wafer, but also increases the yield by maximizing the distance from good dies to the wafer edge (Chien et al., 1999, 2001, 2002). But, only gross die number is not sufficient and complete to represent the wafer productivity, yet use of the useful wafer area. In addition, the optimization of wafer layout pattern is local to the wafer exposure effectiveness. However, little research has been done to investigate the overall wafer exposure effectiveness. Therefore, this paper proposes a metric that considers the information of wafer area loss and useful wafer area to measure the overall wafer productivity.

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3. Overall Wafer Effectiveness

T

The terminologies and notations used are as follows: OWE (Overall Wafer Effectiveness): a metric of overall wafer exposure performance, expressing the useful wafer area for the good die divided by the total wafer area. MFU (mask-field-utilization): the utilization of mask field that would be exposed each shot, expressing the exposure field area divided by the maximum mask field area. MOWE (mask-field-utilization weighted OWE): the OWE multiplied by the MFU. Ngross: gross die number per wafer. Ngood: good die number per wafer. p: number of dies exposed within a field in the x direction. q: number of dies exposed within a field in the y direction. sx: scribe line space in the x direction. sy: scribe line space in the y direction. lmask: length of a mask. wmask: width of a mask. ldie: length of a die. wdie: width of a die. lef: length of an exposure field. Note that lef will be consisted of ldie and sx. Let lef = p  (ldie + sx) + sx. wef: width of an exposure field. Note that wef will be consisted of wdie and sy. Let wef = q  (wdie + sy). Lequipment: loss of wafer area by equipment limitation. Llitho: loss of wafer area by litho requirement limitation. Lincomplete: loss of wafer area by incomplete exposure die. Lfailure: loss of wafer area by failure die. Atotal: total wafer area, Atotal = pr2 square millimeter (mm2). r is effective radius of the wafer, i.e., radius minus the border width. Aavailable: available area on wafer, Aavailable = Atotal  Lequipment square millimeter (mm2). Aexposable: exposable area on wafer, Aequipment = Aavailable  Llitho square millimeter (mm2). Agross: gross die area on wafer, Agross = Aexposable  Lincomplete = Ngross  (ldie  wdie) square millimeter (mm2). Agood: good die area on wafer, Agood = Agross  Lfailure = Ngood  (ldie  wdie) square millimeter (mm2). AE: availability efficiency, the fraction of the available area to wafer exposure area. EE: exposure efficiency, the fraction of completed exposed die area to total wafer area. LE: litho efficiency, the fraction of the exposable area to available area. RE: rate efficiency, the fraction of area that the exposure die are complete to exposable area. YE: yield efficiency, the fraction of dice area on per exposure wafer that are accepted for assemble and package process. 3.1. OWE definition and indices To capture the overall wafer exposure performance for identifying and analyzing hidden performance loss, the total wafer area can be divided into four basic wafer area statuses, including total wafer area (Atotal), available area (Aavailable), exposable area (Aexposable), gross die area (Agross), and good die area (Agood). As shown in Fig. 3, key blocks of wafer area can be particularly associated with the basic statuses and sub-statuses to achieve the wafer area tracking resolution for improving wafer exposure effectiveness. Thus, OWE indices can be defined with wafer area statuses and related factors. In particular, the OWE is referred the fraction of good die area to total wafer area and is expressed as follows:

Fig. 3. Conceptual framework of OWE.

OWE ¼

good die areaðAgood Þ  100% total wafer areaðAtotal Þ

ð2Þ

where total wafer area means that whole area of raw wafer which is determined by used wafer size, e.g. 300 mm, 450 mm. Good die area is the area of produced dice that are passed wafer probe test. In particular, the OWE can be further decomposed into exposure efficiency and yield efficiency.

OWE ¼ ðexposure efficiencyÞ  ðyield efficiencyÞ

ð3Þ

where

good die areaðAgood Þ  100% gross die areaðAgross Þ gross die areaðAgross Þ  100% exposure efficiency ðEEÞ ¼ total wafer areaðAtotal Þ

yield efficiency ðYEÞ ¼

ð4Þ ð5Þ

Yield efficiency is the fraction of dice area on per exposure wafer that are accepted for assemble and package process. Although yield can be further decomposed into line yield, die yield and final test yield (Cunningham et al., 1995), this paper mainly considers die yield for expressing the fraction of good die area per wafer. In particular, the loss of yield efficiency is due to the defective dice area that is caused by abnormal events during wafer fabrication processes including scrap, mis-operation, equipment failure, and contamination. Exposure efficiency is the fraction of maximum complete dice area on a wafer. It represents the theoretical utility of wafer area without considering the variation during manufacturing processes. Moreover, the exposure efficiency can be further decomposed by availability efficiency, litho efficiency, and rare efficiency as follows:

exposure efficiency ¼ ðavailability efficiencyÞ  ðlitho efficiencyÞ  ðrate efficiencyÞ availability efficiency ðAEÞ ¼

ð6Þ

available areaðAavailable Þ total wafer areaðAtotal Þ  100%

ð7Þ

Availability efficiency is the fraction of area that the wafer is able use in lithography. The loss of availability efficiency is due to the area of equipment limitations, in which the wafer is not available to expose due to the other manufacturing equipment related effects including wafer edge and scribe line. The wafer edge can not be effectively utilized and produced good dies because photo resist cannot be coated in uniform thickness on the wafer border. It typically discards the width of wafer border in the range of 3 to 5 mm. The strips between dies that are designed with registration marks for metrology inspection of CD (critical dimension) and wafer backend tests including defect test, design rule test, and reliability test, and overlays registration for compensating overlay

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the ownership of the corresponding wafer area loss. Indeed, by considering different wafer area loss, OWE can also be expressed by availability efficiency (AE), litho efficiency (LE), rate efficiency (RE), and yield efficiency (YE) as follows:

errors are wafer area loss. Then, the fabricated wafer will be sawed into dies, in which different sawing equipment will cut different scribe line area.

litho efficiencyðLEÞ ¼

exposable areaðAexposable Þ  100% available areaðAavailable Þ

OWE ¼ AE  LE  RE  YE

ð8Þ

Litho efficiency is the fraction of area that the wafer can be exposed. The loss of litho efficiency is due to the area of litho requirements, in which the wafer is not available to expose since the lithography process requirement including flat bottom line, and alignment mark. The area below the flat bottom line that is used for marking wafer identification and start of wafer exposure can not be exposed. The alignment marks designed in the steppers or scanners are used for alignment in lithography process. In particular, The region of mark shielding is to avoid the damage of alignment mark and the area around alignment mark is also limited to be exposed because of the yield concern. In fact, the litho requirement could be various with different exposure technology or equipment.

rate efficiencyðREÞ ¼

gross die areaðAgross Þ  100% exposable areaðAexposable Þ

ð10Þ

3.2. Directions for OWE enhancement Considering wafer exposure operation in practice, the total wafer area can be breakdown as illustrated in Fig. 4. Different factors will cause useless wafer area and thus affect the corresponding availability efficiency, litho efficiency, rate efficiency, yield efficiency, and the derived OWE. The useless wafer area can be classified into equipment limitation loss, litho requirement loss, incomplete exposure die loss, and defective die loss with different area statuses. As shown in Fig. 4, various directions can be employed to reduce the corresponding wafer area loss to enhance the effectiveness of OWE indices, respectively. The following addresses several directions for improving OWE, rather than attempt to list all improvement methods with each specific problems.

ð9Þ (1) Availability efficiency: Availability efficiency can be enhanced by reducing non-exposable area loss including area of wafer edge and width of scribe line (Han, Derksen, & Chu, 2004). In particular, the stability and uniformity of photo resist coating around the wafer border should be enhanced, for example, Han et al. (2004) developed an extrusion spin coating method to reduce photoresist waste and to improve coating uniformity in microlithography. So that the exclusion of wafer edge can be minimized as possible. Furthermore, the reduction of scribe line width will result in a larger percentage availability of wafer area for increase of integrated circuits.

Rate efficiency is the fraction of area that the maximum gross dice possibly produced from a wafer. The loss of rate efficiency is due to the area of incomplete exposed dice which are influenced by die size and wafer layout pattern on the wafer. Since the wafer is similar circular, incomplete die area will be more while the die area is large or the shape of die is long and result in low rate efficiency. In particular, the total number of gross dies can be maximized by optimizing wafer exposure pattern to reduce exposure pattern loss (Chien et al., 1999, 2001, 2002). Thus, the wafer area status can be associated with each effectiveness components of the proposed OWE indices, which indicates

• Wafer size

5

Total wafer area

Equipment limitation area

Available area

• Scribe line • Wafer edge Litho requirement area

Exposable area

• Flat bottom line • Mark shielding effect • Area around alignment marks Incomplete exposure die area

Gross die area

• Wafer exposure pattern algorithm • Die size • Die shape Failure die area

• • • •

Good die area

Scrap Mis-operation Equipment failure Contamination

Fig. 4. Breakdown of total wafer area.

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(2) Litho efficiency: Litho efficiency can be enhanced by reducing the non-exposable area owing to the requirements of lithography technology including the flat bottom, and alignment mark. In particular, the reduction of area loss needs with innovation for lithography equipment or process. For example, the alignment mark can be designed on wafer edge or scribe line without extra area loss (Tanaka, 2006). Therefore, the loss about alignment mark including area around alignment marks and the mark shielding effect could be enhanced. (3) Rate efficiency: Rate efficiency can be enhanced by maximizing the usage of exposure wafer area which is determined by IC die size and the exposure pattern algorithm. Firstly, the gross die number per wafer has significant relationships with the feature design of IC devices (i.e., the die length and the die width). Even the die area is the same, different designs of die length and width will result in different gross die counts and different rate effectiveness. Secondly, the problem of wafer exposure pattern is to maximum the number of gross die possibly under certain constraints of equipment limitation area and litho requirement area. In addition, because wafer throughput depends on the number of exposures, each exposure field is determined whether should be exposed with a cost-effective ratio. For example, the authors (Chien et al., 1999, 2001) developed computational algorithms to optimize wafer exposure layout pattern to maximize the number of gross dies exposed on a wafer. The empirical studies showed that the algorithms can generate additional 5% gross dies in average than the existing method. (4) Yield efficiency: Yield efficiency can be enhanced by reducing die yield loss. Die yield loss are caused primarily from random variation and processing variation (Cunningham et al., 1995). Those variations can be improved during IC design, wafer manufacturing process, and wafer probe test. In IC design phase, design rules are determined the minimum feature size and spacing of all layers of the circuit geometry to attempt maximizing the yield, performance and reliability (Allan et al., 1992). Moreover, the integrated circuits will be designed for yield with consideration of the latent variation in manufacturing process (Chiang & Kawa, 2007). For example, optical proximity correction (OPC) modifies the IC layout pattern to compensate the distortion of the lithography process and make the wafer exposure pattern as close to the original intended layout pattern as possible. Moreover, during wafer manufacturing process, yield also can be improved by process and machine control in which the product recipe with respect to a particular process is modified, so as to minimize process drift, shift and variability (Moyne, del Castillo, & Hurwitz, 2001). For example, to enhance the resolution and alignment accuracy in lithography process, overlay errors should be measured accurately and controlled within a tolerance (Bode, Ko, & Edgar, 2004; Chien, Chang, & Chen, 2003; Chien, Chang, Chen, & Lin, 2005; Chien & Hsu, 2006; Lin, Chien, Hsu, & Wu, 2009). Furthermore, the rate of yield improvement also tends to be influenced by detecting process or equipment fault early, diagnosing and removing the defect effectively and classifying the failure patterns to track assignable causes quickly (Hsu & Chien, 2007). Although the present problem for maximizing Overall Wafer Effectiveness has important industrial and commercial applications, little research has been done to investigate various improvement directions systematically through the proposed OWE indices. The percentage of improvement could be approximately expected by the saving area loss to total wafer area. However, the saving loss

could not be counted as OWE improvement directly due to the geometric limitation. For a given wafer diameter, die size, equipment limitation and litho requirement limitation, the exact OWE improvement is measured as the number of good dies that is determined by wafer exposure algorithm and die yield. 3.3. Extension of OWE The proposed OWE can be easily extended for incorporating other attributes for multiple-objective decisions. For example, OWE can be integrated along the time attribute and thus link wafer exposure effectiveness with exposure cycle time or throughput. In lithography process, the exposure cycle time is significant influenced by the utilization of mask field which implies the efficiency of each shot. That is, under the same exposable wafer area, feature size design with higher utilization of mask field will just need fewer shot number and thus results in higher throughput, i.e. wafer per hour, WPH. In particular, mask-field-utilization weighted OWE (MOWE) is defined as follows:

MOWE ¼ OWE  MFU

ð11Þ

where the MFU is the utilization of mask field (Fig. 5) that is defined as follows:

MFU ¼

lef  wef  100% lmask  wmask

ð12Þ

that is generally 5 reduction of the maximum mask by using lens. In particular, exposure field size along horizontal and vertical direction can not be larger than mask field size along horizontal and vertical direction, respectively. The exposure field is determined by the die size and width of scribe line. For example, a mask field layout with 2 dice along the horizontal and vertical direction on the mask is shown in Fig. 5. The gross die number and MFU are mainly influenced by die size including die length, die width, and die area because of the geometric characteristics and the layout pattern algorithm. To consider the respect of IC designer, it is crucial to design a die feature to get more amount of gross die without increasing wafer cost. To consider the respect of wafer fabrication, it is crucial to find a die feature with few shot number per wafer without reduction of gross die simultaneously. Thus, based on the level of MOWE scores, performance of designed dice could be classified into four types as illustrated in Fig. 6. Type I Group: high OWE and high MFU. Type I Group is the best condition for a given die size with high OWE and MFU resulting in

wmask wef ldie

lmask

wdie

lef sx

sy Fig. 5. Illustration of mask field layout and mask-field-utilization.

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Low OWE High MFU

High OWE High MFU

Type II

Type I

Therefore, the availability efficiency, litho efficiency, rate efficiency, yield efficiency, and the OWE of this device can be derived as follows: Available area (Aavailable) = 66,770.88 mm2.

AE ¼

Type III

Type IV

Low OWE Low MFU

High OWE Low MFU

Aavailable 66; 770:88  100% ¼ 94:46%  100% ¼ 70; 685:83 Atotal

Exposable area (Aexposable): 66,500.48 mm2.

LE ¼

Aexposable 66; 500:48  100% ¼ 99:60%  100% ¼ 66; 770:88 Aavailable

Gross die area (Agross): 731  84 = 61,404 mm2. Fig. 6. MOWE quadrants.

RE ¼ more throughput of gross die and WPH. Therefore, all design integrated circuits should be maintained in Type I Group that has to adjust die size and shape during design to maximize wafer productivity during wafer fabrication. Type II Group: low OWE and high MFU. The design integrated circuits in Type II Group perform poorly usage of wafer area that may be derived from the unusual IC design, or non-optimal exposure layout algorithm under the effect of availability efficiency and yield efficiency are small. In particular, we have to identify the specific cause of area loss and apply further improvement. For example, owing the geometry limitation of circular wafer, the shape of larger aspect ratio will cause the lower OWE than smaller difference of aspect ratio. Thus, to enhance OWE, the die size should be driven avoid such kind of design as possible. Type III Group: low OWE and low MFU. The design integrated circuits in Type III Group will capture lots of waste and low WPH. In particular, Type III Group has integrated with Types II and IV approach. Type IV Group: high OWE and low MFU. Although OWE is high for Type IV Group, yet it requires more shot number. However, the MFU may be enhanced by adjusting slightly the size or shape for integrated circuits during design. Moreover, If the exposure steppers or scanners are the bottleneck process and the objective is to minimize the exposure cycle time per wafer, the die size may be adjusted even if the OWE is decreased slightly.

Agross 61; 404  100% ¼  100% ¼ 92:34% 66500:48 Aexposable

Good die area (Agood): (731  40)  84 = 58,044 mm2.

YE ¼

Agood 58; 044  100% ¼ 94:53%  100% ¼ 61; 404 Agross

OWE ¼ AE  LE  RE  YE ¼ 82:12%: As shown in Fig. 7, because the alignment mark is designed on scribe line, the litho efficiency is improved to generate more gross dies. The proposed OWE indices can be derived to identify specific improvement directions for enhancing overall wafer exposure effectiveness of a generic product. Furthermore, the integration with the MFU is calculated as follows:

MFU ¼

lef  wef 21:32  24:16  100% ¼ 60:03%  100% ¼ 26  33 lmask  wmask

Thus, the MOWE is calculated as follows:

MOWE ¼ OWE  MFU ¼ 82:12%  60:03% ¼ 49:30% 4. Value proposition of OWE Indeed, the proposed OWE can be applied as performance indices to measure wafer effectiveness from customer perspective to drive effective improvements from various directions for IC design, equipment, exposure technology, exposure layout pattern, and

3.4. Illustration sample of OWE and MOWE

mm2 To illustrate the proposed OWE, MFU and MOWE, a generic product CMB057 in a wafer fab that consists of exposing a device on 300-mm wafer. Because the alignment mark is designed in scribe line, therefore, the area of alignment mark and mark shielding effect are eliminated. The gross die number was determined by optimizing the wafer exposure patterns (Chien et al., 1999, 2001). The sample data are listed as follows: Total wafer area: 1502p = 70,685.83 mm2. Die size: 7 (mm)  12 (mm) = 84 mm2. Exposure die number: 3  2. Scribe line width in the x direction: 0.08 mm. Scribe line width in the y direction: 0.08 mm. Gross die number: 731. Defective die number: 40. Area of scribe line: (7.08  12.08  7  12)  731 = 1115.80 mm2. Equipment limitation area (Lequipment): 3914.96 mm2. Litho requirement area (Llitho): 270.29 mm2. mask field size: 26  33 mm2. exposure field size: 21.32  24.16 mm2.

Lequipment Llitho

Lincomplete Lfailure

Atotal

70685.83 Aavailable

66700.88 Aexposable

66500.48 Agross

61404

Agood

58044 AE

94.46%

LE

RE

YE

OWE

99.60 92.34% 94.53% 82.12%

Fig. 7. Illustration of OWE calculation.

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C.-F. Chien et al. / Computers & Industrial Engineering xxx (2011) xxx–xxx

yield enhancement among the stakeholders including IC designer, vendors, process developer, and manufacturer. Furthermore, the proposed OWE can be integrated with other attributes such as mask field utilization as a weighted OWE for driving IC design change to enhance throughput without affecting yield. In particular, four cases are used to illustrate the value of proposed OWE. 4.1. OWE for driving exposure pattern optimization To enhance OWE and especially rate efficiency, the authors (Chien et al., 1999, 2001) have developed algorithms to maximize the usage of exposure wafer area to maximize gross dies exposed on a wafer and minimize the number of exposure shots, subject to the considerations including throughput, profit, and yield such as the flat bottom line, dummy pattern (i.e., incomplete exposure shut square), the sharing rules of the dummy pattern, the width of the scribe line, the position of the alignment mark and the mask size. In practice, it relies on the experienced engineer spending a long time to try and adjust the exposure patterns because of the involved combinatorial complexity. In particular, an empirical study has been done in Taiwan (Chien et al., 1999, 2001; Lin et al., 2008). The diameter of the wafer is 200 mm, the wafer edge is 2.5 mm wide, and the size of the alignment mark is 0.8  0.8 mm2. In addition, the die yield is assumed as 99%. The detailed size data is listed in Table 1. For example, the field size of product A is 14.94  23.28 mm2, and the die size is 4.98  11.64 mm2 and each exposure shot contains six dies (i.e., 3  2). By applying the developed algorithm, the optimal solution is to produce 462 dies per wafer and OWE is 84.4%. Alternatively, the existing pattern developed by an experienced engineer who used the software provided by the stepper vendor and then adjusted the exposure pattern manually is to produce only 432 dies per wafer and the OWE is 78.92%. That is, using the developed algorithm generates 30 dies and 5.48% extra OWE from each wafer. In other words, using the developed algorithm could generate 5.48% extra area profit for this product. In particular, the developed algorithm can easily be applied and generate extra gross dies for other products as summarized in Table 1. Indeed, given the exposure constraints and geometrical characteristics, the exposable area utilization ratios of the exposure patterns generated from the proposed algorithms are fairly high for various products. 4.2. OWE for evaluating 450 mm wafer size Semiconductor industry has been one of the most complicated industries that is driven by Moore’s Law for continuous cost reduction and technology advance (Leachman, Ding, & Chien, 2007; Moore, 1965). In particular, technology advances and wafer size increase have been employed for driving cost reduction in the past decades. However, the speed of cost reduction is slowing down because the technology advances are facing R&D challenges from the physical limitation in the nano-scale technology. Thus, wafer size increase becomes more critical for continuous cost reduction. The industry should start investigating the decisions to move to the

next wafer size, 450 mm, in a manner that manages risks and meets the economics and operational needs in the future (Pettinato & Pillai, 2005). Larger wafer will improve the wafer area usage, as die size increasing especially. To evaluate the economic analysis of 450mm wafer migration (Chien, Wang, Chang, & Wu, 2007), OWE can be employed to compare the overall effectiveness between exposing the device on 300 and 450 mm wafers. The experiments were designed to collect an empirical data from a 300 mm wafer fab and used the width of scribe line is 0.08 mm in the x- and y-direction, respectively. In particular, considering the same lithography requirements for wafer exposure in real setting, different sizes of dies are exposed on 300 mm and 450 mm wafers using the proposed optimization algorithm to generate the maximum numbers of gross dies and thus derive the corresponding OWE as shown in Table 2. Comparing the OWE from exposing on 300 mm and 450 mm wafers, not only the number of gross die on 450 mm is larger than on 300 mm, but the OWE of exposing a die on 450 mm wafer is better than that of exposing the same die on 300 mm wafer. As shown in Fig. 8, the OWE gap between exposing on 300 mm and 450 mm wafers will be increased as the die size is increasingly larger when the device is getting complicated. Thus, rather than using the wafer area increase of 2.25 times, OWE can better access the benefit of wafer size increase in light of varied die sizes of increasingly complicated devices. Furthermore, wafer productivity gained by technology shrink will be declined since some pattern width cannot be shrunk effectively as technology advanced, such as I/O and analog portions of SoC (system-on-a-chip).

4.3. OWE for equipment purchase Conventionally, OEE and COO (cost of ownership) are used as the criteria to evaluate tool productivity for new equipment procurement. SEMI E35-0229 (2000) defined COO as the full cost of embedding, operating and decommissioning in a factory environment a system needed to accommodate a required volume of product material. The basic of COO is a metric for expressing the total cost divided by the total number of good wafers in a period. However, COO primarily uses WPH as throughput unit without considering the overall wafer exposure effectiveness per wafer. In particular, the WPH and overall wafer exposure effectiveness are both important considered to evaluate the equipment productivity in lithography equipments. Therefore, OWE indices can be used for evaluation and selection of new lithography equipment. In particular, the demand of electronic product in small size such as RFID (Radio Frequency Identification) devices is increasing recently. Thus, the width of scribe line has larger impact as the die size is small. However, the advanced scribe technology for dice cutting or sawing need newer and more expensive equipment. To evaluate the benefit of shrinking scribe line and drive the vendor of dicing saw equipment, equipments with four types of scribe line widths for exposing several RFID on 300 mm wafer were compared as follows. In particular, assuming yield efficiency is 95%. As shown

Table 1 OWE comparison for different exposure pattern layout algorithm. Specification of device

Existing solution of domain experts

Proposed solution

OWE improvement (%)

le  we

kh  kv

Ngross

ER (%)

OWE (%)

Ngross

ER (%)

OWE (%)

14.94  23.28 18.26  20.44 18.26  17.28 13.58  15.22 11.28  12.50

32 22 23 22 11

432 269 512 520 182

85.91 86.11 92.37 92.14 88.03

78.92 79.10 84.85 84.64 80.87

462 282 517 524 182

91.87 90.27 93.27 92.85 88.03

84.40 82.92 85.68 85.29 80.87

5.48 3.82 0.83 0.65 0.00

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C.-F. Chien et al. / Computers & Industrial Engineering xxx (2011) xxx–xxx Table 2 OWE comparison between 300 mm and 450 mm wafers. No.

ld

wd

ld  wd

CTN025 CTN036 CTN049 CTN064 CTN081 CTN100 CTN121 CTN225 CTN400 CTN625 CTN800

5 6 7 8 9 10 11 15 20 25 25

5 6 7 8 9 10 11 15 20 25 32

25 36 49 64 81 100 121 225 400 625 800

300 mm

450 mm

OWE difference (%)

Ngross

OWE (%)

Ngross

OWE (%)

2276 1744 1278 972 761 615 503 264 144 89 62

84.67 84.50 84.25 83.89 83.31 82.54 82.05 79.89 77.54 74.74 70.74

6006 4153 3034 2309 1816 1462 1201 630 345 215 166

89.69 89.30 88.80 88.27 87.86 87.33 86.80 84.67 82.43 80.27 79.32

5.01 4.81 4.55 4.38 4.55 4.79 4.76 4.78 4.89 5.53 8.59

Fig. 8. OWE comparison between 300 mm and 450 mm wafer size.

Fig. 9. OWE comparison under different width of scribe line.

in Table 3, the exposure efficiency is mainly dominated by availability efficiency as die size is shrinking due to the scribe line width. Fig. 9 shows that OWE is negatively correlated with the scribe line width, which will become increasingly significant as the device gets smaller. Therefore, using the dicing saw equipment with smaller scribe line can improve the wafer productivity for the product with small size such as RFID and sensors. Indeed, OWE can effectively support new equipment purchase decisions with the information.

large enough to accommodate the microcircuitry of integrated circuits to ensure desired functionality. IC designer would make orders and provide the pattern layout information including die size and shape for wafer foundry. In particular, the die size and shape are fixed in mask fabrication. Then, photolithography engineer in fabrication will set optimal die placement positions with maximum gross die number and minimum shot number to decide the wafer exposure patterns. In particular, the gross die number and exposure shot number per wafer have significant relationships with the die size and shape (i.e., the combination of die length and the die width). As recognized in Section 3, the higher MFU will require few shots for a wafer and result in better efficiency for wafer exposure. However, even the die sizes are with the same area, different die shape will result in different gross die counts and different exposure times. In order to produce most gross dies on a wafer and minimize exposure shots as possible while the die size and shape are fixed,

4.4. OWE to drive design for manufacturing As global competition continues to strengthen in semiconductor industry, wafer fabrication has to maintain competitive advantages by cost reduction including more gross die and higher WPH. In the design phase, the designer will typically choose the die size

Table 3 Available efficiency and OWE for various rectangular die designs and scribe line width. sh  sv

0.07  0.07

ld  wd

EA (%)

OWE (%)

EA (%)

OWE (%)

EA (%)

OWE (%)

EA (%)

OWE (%)

2.52 3.62 6.91 7.42 7.48 9.86

87.84 88.97 90.68 90.98 91.04 91.61

82.37 84.28 84.55 84.65 83.21 84.97

86.80 88.07 90.01 90.34 90.41 91.06

81.39 83.65 83.98 84.00 82.35 84.35

85.78 87.19 89.33 89.71 89.78 90.51

80.41 83.07 83.33 83.38 81.52 83.82

84.78 86.32 88.68 89.09 89.16 89.97

79.46 82.34 82.71 82.85 80.69 83.30

(CMS018) (CMS063) (CMS124) (CMS202) (CMS210) (CMS256)

0.08  0.08

0.09  0.09

0.10  0.10

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the wafer exposure pattern should be optimized (Chien et al., 1999, 2001). However, in order to optimize wafer exposure patterns in light of existing device features, given a wafer size, non-exposable area and the constraints of device design, MOWE can drive design adjustment of alternative die size during design phase to increase gross dies and enhance MFU simultaneously during fabrication. To illustrate the die size suggestion for MOWE improvement, Table 4 provides an existing product CMB057_00 with the die size (7  12) mm2 which has shown in Section 3. The initial MOWE is 49.30% due to the lower MFU (60.03%). The OWE difference among different designs with the same die area is changed gradually as shown in Fig. 10, yet the MOWE is varied among different designs as shown in Fig. 11. First, considering the die area is constant and die shape is adjustable, the MFU can be substantially enhanced at least 80% from one die size of CMB057 with No. 04, 05, 09, 10, 11, 14, and 15, which result in higher MOWE as shown in Fig. 10. Moreover, the initial OWE (82.12%) also can be enhanced by comparing the exposure performance from those patterns, for example, the design of 7.80  10.78 (82.78%), 8.43  9.97 (82.68%), and 11.93  7.04 (82.24%). Furthermore, if the wafer exposure machines (i.e., steppers or scanners) are not bottleneck, it can find an appropriate die size for improving OWE per wafer, e.g. CMB057_12 (83.12%). However, it may not always be desirable to maximize the number of gross die and minimize the equipment shot numbers. If the overall equipment efficiency is low because of the exposure machines, it is important to minimize the shot number per wafer by using the design with higher MFU. The improvement of exposure cycle time is beneficial even if the OWE is slightly reduced, e.g. the CMB057_04. Thus, use of OWE and extended MOWE indices can make a trade-off between the throughput enhancement and cycle time reduction. In particular, the six alternative designs with higher OWE and MOWE are suggested, based on patent pending algorithms, to obtain more gross dies with less shot number than the original design for win–win collaboration between IC designer and foundry. In sum, the proposed OWE creates the following values. Firstly, it provides a comprehensive framework to effectively monitor wafer exposure effectiveness and enhance productivity by identifying different improvement directions of exposure technology, optimization of exposure pattern, equipment improvement and wafer size evaluation and thus being able to drive them effectively. Secondly, OWE can be used as a criterion for new photo equipment purchase by comparing equipment wafer productivity. Thirdly, OWE can be weighted with mask utilization to consider both throughput and output to enhance exposure efficiency and

Fig. 10. OWE for various rectangular die designs with 84 mm2 area.

Fig. 11. MOWE for various rectangular die designs with 84 mm2 area. Table 4 Exposure performance for various rectangular die designs with 84 mm2 area. CMB057 die size design

Exposure performance (%)

No.

ld

wd

OWE

MFU

MOWE

00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16

7.00 4.27 4.84 5.07 5.86 6.35 6.63 6.64 7.021 7.795 7.813 8.425 8.897 9.075 11.931 12.186 14.840

12.00 19.69 17.36 16.58 14.34 13.23 12.68 12.65 11.963 10.775 10.752 9.970 9.441 9.257 7.041 6.894 5.660

82.12 80.32 81.33 81.78 81.90 82.35 82.56 82.35 82.22 82.78 82.57 82.68 83.12 82.46 82.24 82.58 82.22

60.03 60.27 50.15 50.12 80.11 80.04 60.06 60.06 60.03 89.97 89.99 89.94 60.03 60.04 80.02 80.02 60.21

49.30 48.41 40.79 40.99 65.60 65.91 49.58 49.46 49.36 74.48 74.30 74.36 49.90 49.51 65.80 66.08 49.50

effectiveness at the same time. Indeed, an algorithm based on the proposed OWE has been developed to effectively derive the optimal die designs for achieving multiple business objectives simultaneously and has been granted USA invention patent (Lin et al., 2008). 5. Conclusion From industry fundamental objective, this paper proposed the OWE indices to effectively monitor wafer exposure performance and enhance wafer productivity rather than focusing only on OEE of individual equipment. In particular, OWE indices are expressed with wafer area and thus different types of wafer area loss can be identified in a comprehensive framework to clarify ownership of wafer effectiveness loss among IC designers, fab, equipment vendors and thus drive effective improvements for wafer availability, exposable rate, and exposed rate, yield, and MFU. In addition,

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the proposed OWE can be integrated with other attributes such as throughput as weighted OWE to address multiple operation and business objectives. Furthermore, OWE can be easily extended for incorporating other attributes such as process time or throughput to thus link with cycle time. For example, a normalized index such as OWE/time can be employed to drive throughput improvement and cycle time reduction. Furthermore, it may also consider profit or average selling price (e.g. profit  OWE/time) to thus link wafer exposure operation with business strategy. The coevolution of the semiconductor ecosystem has been driven by the pressure for continuous technology advancements as well as the cost reduction. As semiconductor industry reached nanotechnology generation and consumer electronics era, the competition is no longer among individual semiconductor companies. Indeed, the collaborations among horizontally specialized value providers are critical for the success of the companies as well as the whole supply chain. The proposed OWE can be employed as an industry standard for measuring wafer productivity and identifying effective directions for improvement. Further research should be done to apply OWE and the associated indices in various contexts. It is also insightful to derive results from more empirical studies that lead to the identification of more effective measurement of productivity of individual process step and whole production system. Acknowledgements This research is supported by National Science Council, Taiwan (NSC 99-2221-E-007 -047 -MY3; NSC 100-2218-E-155-003), Ministry of Education (100N2073E1), and Taiwan Semiconductor Manufacturing Company. References Allan, G. A., Walton, A. J., & Holwill, R. J. (1992). An yield improvement technique for IC layout using local design rules. IEEE Transactions on Semiconductor Manufacturing, 11(11), 1355–1362. Beasley, J. E. (1985). Algorithm for unconstrained two-dimensional guillotine cutting. Journal of the Operational Research Society, 36(4), 297–306. Bode, C. A., Ko, B. S., & Edgar, T. F. (2004). Run-to-run control and performance monitoring of overlay in semiconductor manufacturing. Control Engineering Practice, 12, 893–900. Chiang, C., & Kawa, J. (2007). Design for manufacturability and yield for nano-scale CMOS. Springer. Chien, C.-F., Chang, K.-H., & Chen, C. (2003). Design of sampling strategy for measuring and compensating overlay errors in semiconductor manufacturing. International Journal of Production Research, 41(11), 2547–2561. Chien, C.-F., Chang, K.-H., Chen, C., & Lin, S. (2005). Overlay error model, sampling strategy and associated equipment. USA Invention Patent US6975974B2. Chien, C.-F., & Chen, C. (2007). Using GA and CTPN for modeling the optimizationbased schedule generator of a generic production scheduling system. International Journal of Production Research, 45(8), 1763–1789. Chien, C.-F., Chen, H., Wu, J.-Z., & Hu, C. (2007). Construct the OGE for promoting tool group productivity in semiconductor manufacturing. International Journal of Production Research, 45(3), 509–524. Chien, C.-F., Chen, Y., & Peng, J. (2010). Manufacturing intelligence for semiconductor demand forecast based on technology diffusion and product Life cycle. International Journal of Production Economics, 128(2), 496–509. Chien, C.-F., Hsu, S., & Chen, C. (1999). An iterative cutting procedure for determining the optimal wafer exposure pattern. IEEE Transactions on Semiconductor Manufacturing, 12(3), 375–377. Chien, C.-F., Hsu, S., & Chen, C. (2002). Procedure of alignment for optimal wafer exposure pattern, USA Invention Patent US6368761 B1. Chien, C.-F., Hsu, S., & Deng, J. (2001). A cutting algorithm for optimizing the wafer exposure pattern. IEEE Transactions on Semiconductor Manufacturing, 14(2), 157–162.

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