Power Aware Management of Packet Switches Lykomidis Mastroleon∗ , Daniel O’Neill∗ , Benjamin Yolken† and Nicholas Bambos∗† ∗ Department

of Electrical Engineering, of Management Science and Engineering, Stanford University Stanford CA 94305 Email: {lmastro,dconeill,yolken,bambos}@stanford.edu † Department

Abstract—In this paper, we extend the idea of Dynamic Power Management (DPM) to network packet switches, devices whose increasing speeds and densities are leading to costly and physically cumbersome power dissipation problems. In particular, we take a system-level approach, examining how operations in an input-queued (IQ) switch can be scheduled to balance power consumption on the one hand with average delay on the other. To accomplish this, we formulate a quadratic cost model which accounts for the power / delay tradeoff and then pose the scheduling problem in terms of a dynamic program. Using techniques from the field of linear quadratic regulation (LQR), we then solve for the optimal control in a relaxed system model and use this to create a novel scheduling algorithm: power aware maximum weight matching (PAMWM). Initial simulation results suggest that, under low load conditions, our algorithm results in significant power savings compared to MWM, with little performance degradation.

I. I NTRODUCTION Power management is an increasingly critical issue in the operation of large data centers. With numerous racks of servers, storage, and networking equipment, these centers can consume upwards of 200W per square foot, a figure which will only increase in the future as computing architectures become more powerful and more dense [1]. Such power demands are not only expensive from a utility standpoint, but also introduce the need for complex and expensive equipment to dissipate the heat produced. Current designs can stress modern cooling systems to their limits; in the future, power demands, rather than other technological factors, may become the main constraint in the design of new architectures and devices. Such concerns, therefore, have motivated considerable study of power management in computing, at both the circuit and system level. In the case of the latter, which the focus of this paper, much research has focused on the so-called Dynamic Power Management (DPM) paradigm [2]. This involves the application of various techniques to match power consumption to the system computing load. When the latter is low, for instance, system components can be selectively slowed down or turned off, reducing power with little sacrifice in overall performance. Such techniques have been successfully applied to microprocessors and hard disk drives, among other devices [1]–[3]. Little work, however, has applied system-level DPM techniques to network packet switches, whose power consumption is rapidly increasing as network speeds and required throughputs become larger. At the same time, however, total

power consumption is limited by physical constraints within the switch as well as compliance with customer demands and industry standards (e.g. Network Equipment Building System (NEBS)) [4]. Without improved management, power consumption could become a significant impediment to advances in switch design and performance. The effect of DPM on performance depends on the particular algorithm selected and the switch design. One particularly popular design involves using an input-queued (IQ) architecture. Such switches offer the advantages of high bandwidth and scalability, but require intelligent scheduling policies to operate efficiently. These policies have been studied thoroughly in the literature from the perspectives of throughput, QoS, complexity, etc. [5]–[8]. However, as switch power consumption becomes an increasingly hard constraint, such policies will also need to address the power-performance trade off. In this paper we consider power-aware scheduling in IQ packet switches. In particular, we assume that the switch can operate in different performance modes. Such modes adjust switch power consumption by either speeding up or slowing down the switch fabric. As the throughput increases, however, the power consumption also increases. Thus, in addition to deciding which queues to service, the switch scheduler must also decide which speed to use. The optimal decision depends on the operator’s relative weights between performance and power. The concept of a power managed IQ switch, along with the associated scheduling algorithms, was first developed in [9] and then further refined in [10]. The first assumes linear power and convex delay costs, and then formulates the scheduling problem in terms of a constrained, convex program. The second paper assumes quadratic costs and then uses a dynamic programming approach to develop scheduling heuristics. In this paper, we also assume quadratic costs but instead apply techniques from the field of linear-quadratic regulation (LQR) to choose approximately optimal schedules. This approach not only provides closed-form controls but also leads to policies that are easy to implement and highly scalable with switch size. Moreover, as we discuss later, such policies perform well in simulations when compared to currently used scheduling algorithms. The remainder of this paper is organized as follows. In section II, we describe the basic switch and cost models used

for our analysis. In section III, we present a relaxed cost minimization problem, its solution, and a proposed switch scheduling algorithm. The performance of our algorithm is evaluated in Section IV. Finally, in section V, we conclude and discuss directions for future research.

6 6 s2

II. BASIC M ODEL AND P ROBLEM F ORMULATION Consider a canonical N × N , IQ packet switch composed of line card processing units (LCPs), virtual output queues (VOQs), and a crossbar switching fabric. There are N LCPs, one at each input. Each LCP contains N VOQs, one for each output. Such a design prevents the head-of-line blocking problem. The VOQs are conventionally indexed as V OQi,o where i, o ∈ N ≡ {1, . . . , N } and i refers to the input port and o to the destination output port. In what follows these queues are indexed sequentially by q ∈ Q ≡ {1, . . . , Q} where Q = N 2 . The first N queues pertain to V OQ1,o o ∈ N , the VOQs associated with the first input port, and so on. Time is slotted and indexed by t = {0, 1, 2, . . .}. Queued packets are serviced from the VOQs at the beginning of each time slot with new packets arriving at the end of each slot. The former is done subject to the “crossbar constraint”- i.e., that no output simultaneously receives packets from more than one input VOQ and that no input simultaneously transfers packets to more than one output. The set of service configurations corresponding to these constraints can be described mathematically as a set of matching vectors. Each such vector cj ∈ {0, 1}Q has exactly N non-zero entries, corresponding to a subset of VOQs that satisfies the “crossbar constraint” above. Note that there are N ! such configuration vectors (j ∈ J ≡ {1, . . . , N !}). We will denote the set of all possible matching configurations by C ≡ {cj , j ∈ J }. For example in the N = 2 case, the set of matching configuration vectors is C = {[1 0 0 1]T , [0 1 1 0]T }. Suppose that, moreover, the switch can be idle or operate in one of M active, operational modes. Assume that these modes are indexed by m ∈ M ≡ {0, . . . , M }. At each time slot, the system scheduler chooses both a matching, as discussed above, and a mode. When the switch is idle (m = 0), no packets are served. For any other mode (m 6= 0), we assume that at most m packets are serviced from each “matched” VOQ. So, at any time slot, the system may be in one service configuration s = mc. General stability results for switches of this type are discussed in [11], [12]. We will denote the set of all M N ! + 1 feasible service configurations by S ≡ {mc : m ∈ M, c ∈ C}. See Fig. 1 above for an illustration. We can now describe the system dynamics algebraically. The backlog state xt of the switch at any time t is the Qdimensional vector of packet populations in the individual queues, that is: xt = [xt1 , . . . , xtq , . . . , xtQ ]

(1)

where xtq is total workload (number of waiting packets) existing in VOQ q ∈ Q at time t.



3

6 6

A. Switch Model

  2 1

: -

 :

: -

-

-

s1

Fig. 1. Illustration of service configurations in hypothetical 2 × 1 switch with 3 performance modes. Service vectors in set 1 are the most power efficient, but also provide the least throughput. Configurations in 3 allow for maximum throughput, but use the most power. Set 2 has power and throughput characteristics in between.

The service state st of the system at time t is the service vector: st = [st1 , . . . , stq , . . . , stQ ]

(2)

chosen from S by the control that the system operates under. Given backlog xt and service vector st used in time slot t, the number of packets removed from queue q and departing is simply: dtq = min{xtq , stq }

(3)

where the min accounts for the case when there are fewer packets in the VOQ than the service configuration can remove. Thus, the departure vector at time t is: dt = [dt1 , . . . , dtq , . . . , dtQ ]

(4)

With the above notation, the packet backlog in the system at time t can then be expressed as: xt+1 = xt − dt

(5)

and so we can write: x t = x0 −

t−1 X

dτ

(6)

τ =0

where x0 represents the initial system workload. Note that if all s ∈ S and x0 are integer vectors, then {xt , t ≥ 0} evolves on the non-negative integer lattice ZQ +. B. Operational Costs and Tradeoffs Suppose that at each time slot, the switch schedular faces a cost that is a function of the system state, xt , and service configuration choice, st , in that slot. The schedular’s objective, mathematically formalized later, is to minimize the total cost experienced over a finite time horizon. In this paper, we assume that this cost is the sum of two terms: one measuring “power consumption” and a second reflecting “packet delay.” Thus, our function reflects the tradeoff between the latter two operational metrics.

Power consumption and its associated costs arise from several different sources. An idle switch consumes an approximately fixed amount of power. Much of this power is consumed at the semiconductor device level, due to leakage currents or due to older non-power aware circuit designs. This static power consumption can be significant but is best addressed by DPM at the individual device level and is neglected in what follows. At the system level, switch power consumption is related to the work done by the switch. As larger numbers of packets are received, routed, and forwarded, the power needed to operate the switch increases. In this paper, we assume that the power cost term grows quadratically in the total switch throughput, reflecting the increased activity necessary to process packets and also the increased cooling necessary to keep the system at useful operating temperatures. The throughput of a switch can be measured at its output and is determined by the sequence of service states a switch selects. Analytically, we assume that at time slot t the service state is st , then the power cost is of the form (st )T F(st ), where the outflow cost matrix F is symmetric and positive semidefinite F  0. Packet delay, on the other hand, is measured by the backlog (queue lengths) of the VOQs. We assume a quadratic cost for each queue. This metric is used to to incrementally penalize the growth of a queue and reflects the intuitive notion that a packet arriving at a longer queue will impact average queue delay more than a packet arriving at a shorter queue. Similar to power costs, we assume that if at time slot t the backlog state is xt , then the backlog cost is of the form (xt )T B(xt ), 1 where the Backlog cost matrix B is symmetric and positive semidefinite B  0. III. S YSTEM C ONTROLS AND S CHEDULING A LGORITHMS A. Optimal Control with No Arrivals Ignore arrivals for the moment and consider the objective of emptying the switching system with the minimum possible total cost. We define the minimum cost-to-go function J, at time slot t and backlog state xt , as: J(xt ) =

∞ X τ =t


(xτ )T B(xτ ) + (sτ )T F(sτ )

(7)

Note that this function does not depend on the actual time slot t but only on the backlog state xt (trivial time translation arguments can be used to prove this). To calculate J(xt ), we can write down Bellman’s equation:  t T J(xt ) = min (x ) B(xt ) + (st )T F(st ) + J(xt − dt ) t

B. Linear Quadratic Regulator Relaxation As mentioned earlier, st ∈ S and xt evolve on the nonnegative integer lattice ZQ + . We now lift any integrality conditions and assume that service vectors s˙ , the initial backlog x˙ 0 and the backlog vector {x˙ t , t ≥ 0} are in RQ . Then, the following Linear Quadratic Regulator (LQR) relaxation of (8) can be formed: n o ˙ x˙ t − s˙ t ) ˙ x˙ t ) = min (x˙ t )T B(x˙ t ) + (˙st )T F(˙st ) + J( J( s˙ t ∈RQ

(9)

where s˙ t is the “LQR service” vector, at time slot t when x˙ t ˙ t ) is the minimum cost-tothe “LQR backlog vector” and J(x go function that corresponds to the LQR relaxation. The optimal solution for the LQR problem described by (9) can be computed as follows: s˙ t = Wx˙ t

(10)

where the weight matrix W is defined as: W = (F + P)−1 P

(11)

and P  0 is the solution of the Algebraic Ricatti Recursion (ARE): P = B + P − P(F + P)−1 P B = P(F + P)−1 P

(12)

Also, under the the optimal control described by (10), the LQR minimum cost-to-go function is equal to: ˙ x˙ t ) = (x˙ t )T P(x˙ t ) J(

(13)

Note that since B is symmetric and positive definite BT = B  0, so all its eigenvalues are positive. If we denote by λq > 0 its q-th positive eigenvalue (q ∈ Q), then we can define its eigenvalue vector as λ = [λq ]. Furthermore, we know that there exists V and such that VT = V−1 and T . With this in mind, we can further define B = V diag(λ)Vp 
B1/2 = V diag λq VT and B−1/2 = (B1/2 )−1 (notice that the latter and also B−1 exist since B  0). Clearly, it is true that B = B1/2 B1/2 . So assuming that there exists P−1 , from (12), we can conclude that: B = P(F + P)−1 P B PB

−1

−1

−1

=P

−1

(F + P)P

P = (F + P) ¨ ¨ = B−1/2 FB−1/2 + P ¨ PP

⇔ ⇔ ⇔ (14)

s ∈S

(8)

The infinite horizon Dynamic Program (DP) described by (8) can be computationally intractable. For this reason, in the following subsection we use a relaxation that is computationally reasonable. 1 zT

(ZT ) denotes the transpose of vector z (of matrix Z)

¨ = B−1/2 PB−1/2 ⇔ P = B1/2 PB ¨ 1/2 Now note where P that since B−1/2 FB−1/2 is symmetric and positive semidefinite, all its eigenvalues are non-negative. If we denote by µq ≥ 0 its q-th positive eigenvalue (q ∈ Q), then we can define the eigenvalue vector as µ = [µq ]. Furthermore, we know that there exists U and such that UT = U−1 and ¨ is B−1/2 FB−1/2 = U diag(µ)UT . So if we assume that P

¨ = U diag(ν)UT , where ν = [νq ] ∈ RQ and of the form P + ¨ then (14) suggests that: νq is the q-th eigenvalue of P, νq2 = µq + νq ,

(q ∈ Q)

p νq = 0.5 + 0.5 1 + 4µq ,

(q ∈ Q)

⇒ (15)

since νq ≥ 0. So:

(16)

Notice that P as defined in (16) always satisfies the ARE (12). So we can rewrite (11) as follows: p

T 1/2  U B (17) W = B−1/2 U diag 2/ 1 + 1 + 4µq C. Additional Cost Assumptions

In this paper all queues are considered to have equal importance so we assume that B = bI where b > 0 is the backlog scale factor. Inter-queue backlog relationships are not considered here, but are an area of on going research. This implies that the total backlog cost during every time slot t is: Q X

(xtq )2

(18)

q=1

The power cost is assumed to be composed of two parts. The first part reflects the cost of transferring packets across the crossbar itself and is measured as the sum of the packets transferred squared. The second component is associated with the cost of forwarding the packets on from the switch and is calculated as the sum of the individual packets transferred squared. F = f0 11T + f1 I 2 , where f0 is a positive real constant (f0 ∈ R+ ∪{0}) and f1 is a non-negative real constant (f0 ∈ R+ ). This implies that the total power cost during every time slot t is: (st )T F(st ) = f0 (1T st )2 + f1

Q X

(21)

P = U diag ([(p1 + Qp0 ), p1 1]) UT = p0 11T + p1 I

(22)

Let us also define:   p w1 = 2/ 1 + 1 + 4b−1 f1 (23)    p (24) w0 = Q−1 w1 − 2/ 1 + 1 + 4b−1 (f1 + Qf0 )

So now (17), takes the follow form:

W = U diag ([(w1 − Qw0 ), w1 1]) UT = −w0 11T + w1 I (25) Now let f0 >> f1 . This means that the power cost is approximately equal f0 (1T st )2 and really only depends on 1T st which under optimal LQR control is equal to: 1T s˙ t = 1T (−w0 11T + w1 I)x˙ t = (w1 − Qw0 )1T x˙ t −1  p 1T x˙ t = 2 1 + 1 + 4b−1 (f1 + Qf0 ) = w1 ˜ T x˙ t

−1  p . where w ˜ = 2 1 + 1 + 4b−1 (f1 + Qf0 ) D. Switch Control Algorithm

(stq )2

(19)

q=1

With these additional assumptions B−1/2 FB−1/2 = b F = b−1 (f0 11T + f1 I). Clearly, the latter matrix has one eigenvalue equal to b−1 (f1 + Qf0 ) and (Q − 1) eigenvalues equal to b−1 f1 . So in this case: ( b−1 (f1 + Qf0 ) q = 1 µq = b−1 f1 q ∈ {2, . . . , Q} −1

Clearly, u1 = Q−0.5 1 is an eigenvector of b−1 (f0 11T + f1 I) that corresponds to µ1 . Note that uT 1 u1 = 1. Furthermore, we know that there exists a set of orthonormal eigenvectors uq (q ∈ {2, . . . , Q}) than are orthogonal to u1 . That is there 3 exists uq (q ∈ {2, . . . , Q}) such that uT q uq 0 = 1q 0 =q . Also for q ∈ {2, . . . , Q}, b−1 (f0 11T + f1 I)uq = b−1 f1 uq . So U = [u1 , . . . , uQ ]. Note that U is independent of b, f0 , and f1 . 21

(20)

So:

p 
 P = B1/2 U diag 0.5 + 0.5 1 + 4µq UT B1/2

(xt )T B(xt ) = b

Let us define:   p p1 = 0.5 1 + 1 + 4b−1 f1     p p0 = Q−1 0.5 1 + 1 + 4b−1 (f1 + Qf0 ) − p1

(0) is a vector of appropriate size with all its elements equal to one

(zero) 31 {statement} is equal to one if the statement is true and zero otherwise

The analysis in the previous section motivates the following algorithm: Algorithm 1 Power-Aware MWM (PAMWM) 1: if (xt = 0) then 2: Switch idle (m = 0) 3: else 4: Set configuration to: argmaxc {cT xt } 5: Set mode to: argminm {|mN − w1 ˜ T xt |} 6: end if At each time slot, we thus use MWM to compute the appropriate “matching” but the LQR result above to choose the operational mode. IV. S IMULATED P ERFORMANCE In this section, we evaluate the performance of the proposed scheme via simulation and contrast it to the benchmark MWM scheduler.

600 500 400 300 200 100 0 0

0.2

0.4 0.6 Constant Rate Load

0.8

400 350

250 200 150 100 50 0.2

0.4 0.6 Max Rate Load

0.8

(d) Backlog Cost under Periodic Rate Load Fig. 2.

40 20 MWM LQR PA MWM 0.2

0.4 0.6 Constant Rate Load

0.8

1

600 400 200

500

60 40 20 MWM LQR PA MWM 0.2

0.4 0.6 Max Rate Load

0.8

0.2

0.4 0.6 Constant Rate Load

0.8

1

(c) Total Cost under Constant Rate Load

80

0 0

MWM LQR PA MWM

800

0 0

1

100

MWM LQR PA MWM

300

0 0

60

(b) Power Cost under Constant Rate Load Average Power Cost per Time Slot

Average Backlog Cost per Time Slot

(a) Backlog Cost under Constant Rate Load

80

0 0

1

1000 Average Total Cost per Time Slot

100

MWM LQR PA MWM

Average Total Cost per Time Slot

700

Average Power Cost per Time Slot

Average Backlog Cost per Time Slot

800

1

(e) Power Cost under Periodic Rate Load

MWM LQR PA MWM

400 300 200 100 0 0

0.2

0.4 0.6 Max Rate Load

0.8

1

(f) Total Cost under Periodic Rate Load

Results from first set of experiments. Power, backlog, and total cost are plotted versus load for both PAMWM and MWM.

A. Experimental Setup Two sets of experiments were conducted. In the first set, the average backlog and power costs were computed for a variety of arrival rates from two different distributions. In the second set, the tradeoff between power and backlog costs was considered and compared to MWM. Both sets of experiments were run on a modeled 4×4 switch (N = 4) with 10 operation modes (M = 10). The backlog cost matrix was set to the identity matrix (B = I) and the outflow cost matrix was assumed equal to F = Q−1 11T + 10−8 I ≈ Q−1 11T . All VOQs started empty. At most 10 packets were simulated to arrive to each VOQ at each time slot according to some stochastic arrival process. In particular, we considered two different packet arrival processes that result in uniform loading (i.e. all VOQs subject to the same average load): Binomial i.i.d. Traffic: Under this model, packets arrive at VOQs independently according to a binomial distribution with parameters (M, N −1 ρ). We examined a range of traffic loads: ρ ∈ {0.01, 0.05, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.85} for the first experiment set and ρ ∈ {0.3, 0.4, 0.5, 0.6, 0.7} for the second. Note that we always have ρ < N −1 which, for a N × N switch, is necessary ensure stability. Markov Modulated Binomial (MMB) Traffic: MMB is used to simulate bursty traffic. Traffic arrives in one of two states: High and Low. Transitions between the two states occur probabilistically (here assumed to be 0.1.) While in a given state traffic arrives according to an i.i.d. binomial distribution. In the simulations, traffic drawn while in the High state has binomial

distribution (M, N −1 ρ). Likewise traffic drawn while in the Low state arrives with binomial distribution(M, 0.4N −1 ρ). We considered the same range of values of ρ as for the simple Binomial i.i.d case. Note that Binomial i.i.d traffic is a degenerate case of MMB traffic with only a single state. B. Simulation Results Figure 2 compares the performance of PAMWM and MWM in the first experiment set. While average backlog is very similar in both cases, PAMWM has considerably lower power cost, especially for a system that is moderately to lightly loaded. At high traffic loads the PAMWM average power cost rapidly increases for the binomial i.i.d. case, matching the intuition that at greater loads PAMWM converges to MWM. For the MMB case, average power costs also increase, but less rapidly, reflecting the PAMWM’s ability to reduce power when backlog is small and arrivals are in the low state. The results of the second experiment set are presented in Figure 3(a) for binomial inputs and Figure 3(b) for MMB traffic. Each curve was generated assuming a fixed average arrival rate and using the modified cost function: (xτ )T B(xτ ) + (sτ )T ξF(sτ )

(26)

for ξ ∈ {0.25, 0.5, 0.75, 1, 1.5, 2, 2.5, 3, 3.5, 4}. The curves thus depict the Pareto surface for the switch for a given average traffic rate. In all cases depicted, the average power cost used by the switch is improved over MWM, although at very high loads PAMWM closely approximates

100 MWM LQR PA MWM

90 80 70 60 50 40 30 20 10 0

2 4 6 8 Average Backlog Cost per Time Slot

10

(a) Power-Backlog Cost Trade off under Constant Rate Load of Variable Intensity Fig. 3.

Average Power Cost per Time Slot

Average Power Cost per Time Slot

100

MWM LQR PA MWM 80

60

40

20

0 1

2 3 4 5 6 Average Backlog Cost per Time Slot

7

(b) Power-Backlog Cost Trade off under Constant Rate Load of Variable Intensity

Second experiment results. Power and backlog are plotted for various loads as a function of the relative weight parameter, ξ.

MWM and the differences are reduced. The kink in each curve reflects the situation when the switch has reduced its service rates (to conserve power) to just above the average traffic arrival rates. At such service rates VOQ backlog can build quickly and average backlog grows commensurately. V. C ONCLUSION In this paper, we have thus extended prior research on system-level DPM by applying LQR techniques to the tradeoff between switch backlog and power consumption. Our resulting algorithm, PAMWM, has several desirable features: it is consistent with MWM, is computationally tractable, and can yield attractive performance tradeoffs. Pareto performance curves are consistent with intuition about power usage and average backlog. Several open questions remain regarding PAMWM and are areas of ongoing research: the stability of PAMWM, its dynamic behavior under varying loads, and the effect of B cost matrices with nonzero off diagonal elements, thereby coupling different queues. Additional areas of ongoing research include the modification of MWM using weighting matrices to reflect desired relationships between VOQs and service vectors. R EFERENCES [1] “Power and cooling in the data center,” AMD Corporation, Tech. Rep., 2005. [2] L. Benini, A. Bogliolo, and G. De Micheli, “A survey of design techniques for system-level dynamic power management,” IEEE Transactions on VLSI Systems, vol. 8, no. 3, June 2000. [3] “Addressing power and thermal challenges in the datacenter,” Intel Corporation, Tech. Rep., 2004. [4] C. Minkenberg, R. P. Luijten, F. Abel, W. Denzel, and M. Gusat, “Current issues in packet switch design,” SIGCOMM Computer Communication Review, vol. 33, no. 1, pp. 119–124, Jan. 2003. [5] N. McKeown, A. Mekkittikul, V. Anantharam, and J. Walrand, “Achieving 100% throughput in an input-queued switch,” IEEE Transactions on Communications, vol. 47, no. 8, pp. 1260–1267, Aug. 1999. [6] A. Mekkittikul and N. McKeown, “A practical scheduling algorithm to achieve 100% throughput in an input-queued switch,” in Proceedings of IEEE INFOCOM, San Francisco, CA, Mar. 1998, pp. 792 – 799.

[7] C.-S. Chang, W.-J. Chen, and H.-Y. Huang, “Birkhoff-von neumann input-buffered crossbar switches for guaranteed-rate services,” IEEE Transactions on Communications, vol. 49, no. 7, pp. 1145–1147, Jul. 2002. [8] P. Giaccone, B. Prabhakar, and D. Shah, “Randomized scheduling algorithms for high-aggregate bandwidth switches,” IEEE Journal on Selected Areas in Communications, vol. 21, no. 4, pp. 546–559, May 2003. [9] N. Bambos and D. O’Neill, “Power management of packet switch architectures with speed modes,” in Proceedings of Allerton Conference on Communication, Control and Computing, Allerton, IL, Oct. 2003. [10] A. Dua, B. Yolken, and N. Bambos, “Power managed packet switching,” in Proceedings of IEEE International Conference on Communications, Glasgow, Scotland, June 2007. [11] K. Ross and N. Bambos, “Projective cone schedules in queueing structures; geometry of packet scheduling in communication network switches,” in Proceedings of Allerton Conference on Communication, Control and Computing, Allerton, IL, USA, 2-4 October 2002, pp. 626– 635. [12] ——, “Local search scheduling algorithms for maximal throughput in packet switches,” in Proceedings of IEEE INFOCOM Conference, Hong Kong, 7-11 March 2004, pp. 1158–1169.