Power Managed Packet Switching Aditya Dua∗ , Benjamin Yolken† , and Nicholas Bambos∗† ∗ Department

of Electrical Engineering, of Management Science and Engineering, Stanford University Stanford CA 94305 Email: {dua,yolken,bambos}@stanford.edu

† Department

Abstract— High power dissipation in packet switches and routers is fast turning into a key problem, owing to increasing line speeds and decreasing chip sizes. To address this issue, we introduce and develop the notion of a Power-Managed InputQueued (PMIQ) switch in this paper. A PMIQ switch is an input-queued switch with an additional hierarchy of control to regulate the power dissipated by the switch. We formulate the joint scheduling and power management problem for a PMIQ switch as a dynamic program (DP). Leveraging intuition gained from provable structural properties of the optimal solution to the DP, we propose the Power-Aware Switch Scheduling (PASS) switch management policy. PASS dynamically selects the rate/speed at which the switch operates, in conjunction with the switch configuration, as a function of the backlogs of the input buffers. PASS can easily be tuned to tradeoff high power consumption for larger queuing delays. Experimental results show that PASS yields an attractive power-delay tradeoff relative to the benchmark maximum weight matching (MWM) scheduler. The low computational complexity of PASS makes it amenable to implementation in large, high-speed switches. Index Terms— Switching, Packet scheduling, Power management, Dynamic programming.

I. I NTRODUCTION The input-queued (IQ) packet switching architecture, owing to its scalability, has been the subject of much attention in high-speed networking. The low memory bandwidth of IQ switches, however, must be compensated for by employing intelligent scheduling algorithms. Scheduler design for IQ switches has been addressed extensively in the literature (e.g., see [1]–[4]). However, system level switch design often overlooks physical requirements like power consumption, which are typically addressed only at the circuit level. Power consumption is becoming an increasingly serious problem, especially for single chip network routers, where the switch fabric contributes significantly to the overall power consumption [5], [6]. It was noted in [6] that power consumption increases almost linearly with switch throughput. As line speeds keep increasing, the problem of high power consumption in switches will continue to gain prominence. Advances in VLSI design are being leveraged to densely pack digital electronic circuitry, resulting in unprecedented power densities (> 10W/cm2 ). Consequently, issues like packaging and thermal cooling are fast becoming critical factors in router design. The need for thermally resilient packaging and sophisticated cooling techniques add significantly to design and operational costs. In addition, excessive power dissipa-

tion may result in reduced reliability and, in extreme cases, physical damage to the system. High power density is a problem common to all system-onchip (SoC) designs. Dynamic power management techniques have been addressed at the circuit level as well as the system level in the literature. See [7], [8] and references therein for an overview. System level techniques, of primary interest to us here, curb power usage by employing dynamic power management (DPM) to adaptively vary the number of active system components at any time, or by employing dynamic voltage scaling (DVS) to adjust the processor clock frequency and supply voltage to meet instantaneous performance requirements. These techniques have been shown to provide a performance-power tradeoff for applications as diverse as IEEE 802.11 MAC design and microprocessor design. Wassal et. al. [9] studied traffic-aware system level design of low-power VLSI switching fabrics in a non-linear optimization framework. Wang et. al. [10] proposed power efficient router micro-architectures for network-on-chip (NoC) implementations and reported significant power savings over baseline architectures. Simunic et. al. [11] studied DVS and DPM for NoCs, based on renewal theory, in an optimization framework. Bambos et. al. [12] introduced the notion of a power managed packet switch (PMPS), which adjusts its operating characteristics to meet performance requirements, while seeking to minimize power consumption. Motivated by the relevance and severity of the high power consumption/density problem in packet switches, we propose the Power-Managed Input-Queued (PMIQ) switch architecture in this paper. Our work is akin to [12] in spirit. A PMIQ switch has two key components: the scheduler and the power manager. While the scheduler performs the task of selecting a switch configuration, the power manager is an added hierarchy of control which adaptively configures the speed mode of the switch based on queue backlogs. The speed mode determines the rate at which packets are transferred across the switch fabric. While the switch would typically be operated in high speed modes when heavily loaded, there is strong motivation to operate the switch in lower speed modes under light loading conditions, in order to reduce power consumption. However, reduced power consumption comes at the expense of increased packet delays. Thus, inherent in a PMIQ switch is a fundamental power-delay tradeoff, which we quantify in this paper.

The remainder of this paper is organized as follows. In Section II, we describe the PMIQ switch and formulate the joint scheduling and power management (SPM) problem within a dynamic programming (DP) framework [13]. In Section III, we reduce the SPM problem for a canonical 2 × 2 switch into an approximately equivalent problem for a parallel queue single-server model and present structural properties of the optimal control policy for the latter. We leverage these properties to propose the Power-Aware Switch Scheduling (PASS) algorithm in Section IV. We experimentally evaluate the performance of PASS in Section V and contrast it to the benchmark maximum weight matching (MWM) scheduler [1]. Finally, we conclude the paper in Section VI. II. P ROBLEM D EFINITION A. The PMIQ switch architecture Consider an N × N switch with buffering only at the input ports and virtual output queues (VOQs) to prevent head-of-line (HOL) blocking. There are N VOQs at each input port, one corresponding to each output port. Let Qij denote the VOQ which buffers packets destined from input port i to output port j. The switch operates in slotted time. In each time-slot, at most one packet can be transferred from (to) each input (output) port to (from) one of the output (input) ports. We refer to concurrent packet transfers which happen within a time-slot as a scheduling cycle. It is the task of the scheduling algorithm to select a switch configuration (i.e., a matching between input and output ports) for each scheduling cycle. With each switch configuration, we associate an N 2 -length configuration vector, comprised of 0-1 entries. For an N × N switch, there are N ! possible configuration vectors, with the 2 ith configuration vector denoted by vi ∈ {0, 1}N . If vi (n) = 1, input port dn/N e is connected to output port (n − 1) mod N +1, when the ith configuration is exercised. Each configuration vector has exactly N non-zero entries. For instance, there are two configurations for a 2 × 2 switch, corresponding to vectors v1 = (1, 0, 0, 1) and v2 = (0, 1, 1, 0). Suppose that S consecutive time-slots are grouped together to form a super-slot, where S ∈ {1, 2, . . .}. Now, consider operating the switch in the following fashion: At the beginning of each super-slot, the switch manager selects a switch configuration and a speed mode k ∈ {1, . . . , S}. Speed mode k corresponds to exercising the chosen configuration k times within the super-slot (k scheduling cycles in S time-slots). The switch is idled for the remaining S − k time-slots in the superslot. Speed mode S corresponds to “normal” switch operation, where one scheduling cycle occurs per time-slot (no idling). We call a switch operated in this fashion a Power-Managed Input-Queued (PMIQ) switch. Each scheduling cycle dissipates energy in the switch. A PMIQ switch with S speed modes dissipates the most energy per time-slot (power) when operated in speed mode S and the least energy per time-slot when operated in speed mode 1. However, there is one scheduling cycle per time-slot when speed mode S is used, in contrast to just one scheduling cycle every S time-slots when speed mode 1 is used. Clearly,

average packet latencies will be lower if higher speed modes are used more frequently. This discussion highlights the fundamental power-delay tradeoff inherent in a PMIQ switch. We will now characterize this tradeoff in a dynamic programming (DP) framework. B. DP formulation: Optimally draining the VOQs Consider a scenario where at least one VOQ is non-empty initially (at time 0, say) and no future packet arrivals occurs to any of the VOQs. The switch is set in one of N ! possible configurations (indexed by I) and one of S speed modes at the beginning of every super-slot by a scheduling and power management (SPM) algorithm. Say the SPM selects configuration vector vi , i ∈ I and speed mode k ∈ {1, . . . , S}, given the backlog vector b = (b11 , . . . , bN N ), where bij denotes the backlog of VOQ Qij . A “power cost” P (k) is incurred for choosing speed mode k. Also, a “backlog cost” B(b0 ) is incurred, where b0 = (b − kvi )+ is the new backlog vector at the end of the current super-slot. Here, (x)+ = max(x, 0), element-wise, and 0 is a vector with all zero entries. We assume that P (·) and B(·) are non-negative, strictly increasing, and convex functions. Thus, the total cost of selecting configuration vector vi and speed mode k, given the backlog vector b, is P (k) + B((b − kvi )+ ). The objective of the buffer draining problem∗ is to find a sequence of SPM decisions, such that the total cost (power plus backlog) incurred in emptying all VOQs (starting with any initial backlog vector b) is minimized. This is an instance of a shortest path problem [13], which is amenable to analysis in a DP framework. Let V (b) denote the least possible cost incurred in draining all buffers, given the initial backlog vector b. V (b) is known as the value function in DP terminology and can be computed from the following Bellman’s equations:   0 0 min {V (b ) + P (k) + B(b )} , (1) V (b) = min i∈I

k=1,...,S

where b0 = (b − kvi )+ . The number of possible actions for each backlog vector is N !S, which is extremely large even for moderate values of N (e.g. 16! ≈ 2 × 1013). Thus, solving (1) to obtain the optimal SPM decision in each backlog state is clearly impractical from an implementation perspective, and heuristic solutions with lower complexity must be sought. III. T HE S INGLE -S ERVER PARALLEL -Q UEUE H EURISTIC In this section, we develop a low complexity heuristic SPM algorithm based on reducing the switch scheduling problem to one of scheduling parallel queues on a single server. A. Problem reduction For ease of exposition and analysis, we focus initially on the canonical 2 × 2 IQ switch. The switch can be set into one of two possible configurations, namely v1 = (1, 0, 0, 1) and ∗ Although we consider a static scenario with no packet arrivals, any Markovian arrival process can be easily incorporated into the DP framework. Our motive is to develop algorithms agnostic to statistical assumptions on input traffic. As experimental results show, algorithms based on the solution to the buffer draining problem are robust under different arrival statistics.

v2 = (0, 1, 1, 0). VOQs Q11 and Q22 are scheduled by the former configuration while VOQs Q12 and Q21 are scheduled by the latter configuration. Now, consider the following construction: Given backlog vector b = (b11 , b12 , b21 , b22 ), insert an appropriate number of “dummy packets” into the VOQs such that Q11 and Q22 have the same backlog (say, b1 ), and Q12 and Q21 have the same backlog (say, b2 ). In particular, b1 = max(b11 , b22 ) and b2 = max(b12 , b21 ). Next, consider a sequence of meta-packets generated by “fusing” the packets (both real and dummy) of Q11 and Q22 , and another sequence by “fusing” the packets of Q12 and Q21 . Correspondingly, visualize two meta-queues, mQ1 and mQ2 , which buffer these two sequences of metapackets, respectively (thus, their backlogs are b1 and b2 ). Note that if the switch is set in configuration v1 and speed mode k, then k meta-packets of meta-queue mQ1 are served in a super-slot. Likewise, if the switch is set in configuration v2 and speed mode k, then k meta-packets of meta-queue Q02 are served. Thus, the above construction approximately transforms the buffer draining problem for a 2 × 2 IQ switch into a buffer draining problem for two parallel meta-queues being served by a single server. While the optimal decisions for the two problems are not identical in general (due to the introduction of dummy packets), the single-server formulation provides key insights and yields low complexity near-optimal SPM algorithms for a PMIQ switch. B. DP formulation: Optimally draining the meta-queues We now formulate the buffer draining problem for the single-server model constructed in Section III-A as a DP. The development is along the lines of Section II-B. We recycle much of the notation and explicitly distinguish between the two problems (SPM for a PMIQ switch and SPM for a singleserver model) wherever the context may seem ambiguous. The two configuration vectors in this case are v1 = (1, 0) and v2 = (0, 1), corresponding to scheduling meta-queues mQ1 and mQ2 , respectively. The server can be operated in one of S speed modes. A power cost P (k) and a backlog cost B((b−kvi )+ ) are incurred if configuration vi and speed mode k are selected when the backlog vector is b = (b1 , b2 ). The objective is find the sequence of decisions such that the total power and backlog cost incurred in draining the meta-queues is minimized. Denoting the value function by V (b1 , b2 ), we have the following Bellman’s equations ∀ b1 , b2 > 0: V (b1 , b2 ) = min{

min {V ((b1 − k)+ , b2 ) + P (k) + B((b1 − k)+ , b2 )}, | {z }

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min {V (b1 , (b2 − k)+ ) + P (k) + B(b1 , (b2 − k)+ )}, k=1,...,S | {z } Schedule mQ2 , speed mode k

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and the boundary conditions V (0, 0) = 0, V (b1 , 0) =

min {V ((b1 −k)+ , 0)+P (k)+B((b1 −k)+ , 0)},

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min {V (0, (b2 −k)+ )+P (k)+B(0, (b2 −k)+ )}.

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(4) While the above formulation is valid for arbitrary choice of non-negative, non-decreasing, and convex cost functions P (·) and B(·), for the purposes of illustration and some explicit computations, we now focus on the special class of quadratic cost functions, i.e., P (k) = λk 2 , λ > 0 and B(b1 , b2 ) = b21 + b22 . The parameter λ captures the power-delay tradeoff. Choosing a large value for λ is tantamount to reducing power dissipation in the switch at the expense of increased packet delays, and vice-versa. C. Structural properties of the optimal policy In this section, we present key structural properties of the optimal SPM policy for the single-server problem (for quadratic cost functions). Our first result addresses the optimal scheduling policy.

Theorem 1 (Optimality of LmQF): The longest meta-queue first (LmQF) policy is optimal, i.e., it is optimal to schedule mQ1 when b1 ≥ b2 , and optimal to schedule mQ2 else. Proof: The proof is by induction. We omit details due to space constraints. The idea is to establish that if it is optimal to schedule mQ1 when the backlogs are b1 , b2 , it also optimal to schedule mQ1 (respectively mQ2 ) when the backlogs are b1 + 1, b2 (respectively b1 , b2 + 1). The optimality of LmQF is intuitive by symmetry. Our next result concerns the optimal power management policy. Theorem 2 (Optimality of Threshold Type Policy): The optimal power management policy is of the threshold type, i.e., ∃ 0 = t1,0 (b2 ) ≤ t1,1 (b2 ) ≤ . . . ≤ t1,S (b2 ) and 0 = t2,0 (b1 ) ≤ t2,1 (b1 ) ≤ . . . ≤ t2,S (b1 ), such that •

•

For b1 ≥ b2 , is it optimal to select speed mode k for b1 ∈ (t1,k−1 (b2 ), t1,k (b2 )]. For b1 < b2 , it is optimal to select speed mode k for b2 ∈ (t2,k−1 (b1 ), t2,k (b1 )].

Proof: The proof is by contradiction and induction. We omit details due to space constraints. The idea is to establish that as b1 increases (with b1 > b2 ) or b2 increases (with b1 ≤ b2 ), the optimal speed mode can only increase. The thresholds {t1,k (b2 )} and {t2,k (b1 )} are backlog dependent speed mode thresholds — the optimal speed mode increases by one every time the backlog crosses one of these thresholds and otherwise remains constant. By symmetry, t1,k (b) = t2,k (b), ∀ b, k. Also, we have: Lemma 1 (Monotonicity of Thresholds): t1,k (b2 ) is non increasing in b2 and t2,k (b1 ) is non-increasing in b1 , for every k ∈ {0, . . . , S}.

Theorem 1 and 2 jointly characterize the optimal SPM decisions for the buffer draining problem for the single-server model (under quadratic costs). For illustration, the optimal decision regions for a typical choice of parameters (S = 4, λ = 103 ) are depicted in Fig. 1.

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D. Approximate computation of speed mode thresholds In this section, we approximately compute the optimal speed mode thresholds of Theorem 2 in closed form, which we will use to develop a low complexity heuristic SPM algorithm. As a first step, consider the boundary conditions for the DP, given by (3) and (4). No scheduling decisions need to made when the backlogs of one of the meta-queues is zero. A power management decision, however, still needs to be made. To do so, the thresholds t1,k (0) and t2,k (0) must be computed. We invoke a fluid caricature model to approximately compute these thresholds in closed form. Fluid caricature model: Consider the buffer draining problem for a single-queue single-server continuous-time system. The queue is non-empty at time 0 and no new work arrives to the system. At each time-instant, the server chooses a rate r > 0 to drain the queue, as a function of the remaining workload w. A backlog (workload) cost is incurred at rate W (w), and a power (rate) cost is incurred at rate R(r). To establish an equivalence with the discrete-time model, we set W (w) = w2 and R(r) = λr2 . The goal is to compute the optimal buffer draining rate r? (w) as a function of residual workload w, such that the total cost incurred in emptying the buffer is minimized. For this model, we can show Lemma 2: The optimal buffer draining rate as a function of w residual workload is given by r? (w) = √ . λ Proof: We omit the proof due to space constraints. The key idea is to consider a Taylor expansion of the value function around w and examine the limiting case δ ↓ 0.

We will use the optimal buffer draining rate for the continuous-time fluid model to approximate the speed mode thresholds t1,k (0), t2,k (0) in the discrete-time model. In particular, we set t1,k (0) = bwk c, where wk = inf{w : r? (w) > k}. In words, the thresholds are approximated by “integer crossings” of r? (w). By symmetry, t1,k (0) = t2,k (0) , tk = √ bk λc. See Fig. 2 for an illustration with S = 16 and λ = 200. The approximation becomes increasingly accurate as the number of speed modes increase, because the fluid

Fig. 2. Optimal speed mode as a function of backlog computed from the DP boundary conditions, and the fluid caricature model.

caricature model corresponds to the limiting regime S → ∞. Radial Approximation: Having approximated the speed mode thresholds t1,k (0) and t2,k (0) in closed-form, we now propose the following heuristic optimal power management policy: Choose speed mode k when the backlog vector b is contained inside a circle of radius tk and outside a circle of radius tk−1 , i.e., t2k−1 < b21 + b22 ≤ t2k . This is equivalent to the following radial approximations for the speed mode thresh q  q 2 2 tk − b2 , and t2,k (b1 ) = t2k − b21 . olds: t1,k (b2 ) =

We now have an approximate closed form description of the optimal SPM decisions (LmQF + radial approximation), which does not require explicit solution of the DP equations (2)-(4). The approximation is parameterized by the powerdelay tradeoff parameter λ and the thresholds tk . It follows from Lemma 2 that tk (for every k) increases as λ increases. Consequently, the decision regions corresponding to lower speed modes grow bigger as λ increases. This is consistent with intuition and the motivation for introducing λ. IV. P OWER AWARE S WITCH S CHEDULING (PASS) We now leverage the above solution developed for the single-server buffer draining problem to design an SPM algorithm for the PMIQ switch. In particular, we propose the following Power Aware Switch Scheduling (PASS) algorithm for a 2 × 2 PMIQ switch, which is executed the beginning of every super-slot: 1) Given the VOQ backlogs b11 , b12 , b21 , and b22 , set b1 = max(b11 , b22 ), and b2 = max(b12 , b21 ). 2) Set the switch in configuration v1 = (1, 0, 0, 1) if b1 ≥ b2 , else set the switch in configuration v2 = (0, 1, 1, 0). q 3) Set the switch in speed mode k if b21 + b22 ∈ (tk−1 , tk ], √ where tk = k λ, as computed in Section III-D.

A. PASS for bigger switches Consider a typical switch configuration vector v for an N × N switch, which by definition is of the form v = [eTπ(1) . . . eTπ(N ) ]T , where ej denotes the standard j th vector in RN , xT denotes the transpose of vector x, and π is a permutation of {1, . . . , N }. Next, define the circular

shift operation C(v) , [eTπ(N ) eTπ(1) . . . eTπ(N −1) ]T , and recursively define C i (v) = C(C i−1 (v)), i ∈ N. By convention, C 0 (v) = v. Note that C N (v) = v and C i (v) = C i mod N (v). Thus, starting with any configuration vector v, we can generate −1 a configuration subset Sv = {C i (v)}N i=0 by applying the circular shift operation N − 1 times in succession. In fact, using this construction, the set of configuration vectors of size N ! can be split into (N − 1)! disjoint subsets of size N each. Every configuration subset Sv has the special property that each VOQ is served by exactly one configuration in this subset. If we restrict the switch operation to only one configuration subset, then by virtue of the aforementioned property, the buffer draining problem for an N × N switch can be reduced to the buffer draining problem for a system with N parallel meta-queues and a single server, similar to the 2 × 2 case. It can be shown that operating the switch using a single configuration subset is optimal from a throughput perspective when the switch ports are uniformly loaded. For non-uniform loading, subset based switch operation can be combined with an appropriate subset selection policy without loss of throughput. We refer the reader to [14] for further discussion of these aspects. Since our focus is on characterizing the power-delay tradeoff for a PMIQ switch rather than its throughput properties, we only consider the uniform loading scenario here, so that it suffices to operate the switch using a single configuration subset −1 Sv = {C i−1 (v)}N i=0 . We have the following straightforward extension of PASS: 1) Compute the backlogs b1 , . . . , bN of the meta-queues corresponding to the N configurations in Sv . In particular, if C i (v) serves VOQs Q1,π(1) , . . . , QN,π(N ), then the backlog of the corresponding meta-queue is given by bi = max bj,π(j) . j=1,...,N

2) Compute i? = arg max{bj } and set the switch in ?

configuration C i

j=1,...,N −1

(v). q 3) Select speed mode k if b21 + . . . + b2N ∈ (tk−1 , tk ], √ where tk = k λ, as computed in Section III-D. B. Another heuristic: PA-MWM We propose another heuristic SPM algorithm, namely, Power-Aware Maximum Weight Matching (PA-MWM). The PA-MWM algorithm makes its power management decision based on the total backlog in the system and its scheduling decision based on the benchmark MWM scheduling policy. In particular, given the VOQ backlogs b11 , . . . , bN N and the sum N X N X bij , speed mode selection for a PMIQ backlog B = i=1 j=1

switch based on sum backlog B is equivalent to speed mode selection for a single-queue single-server system (where the queue has backlog B). Thus, PA-MWM selects speed mode k if B ∈ (tk−1 , tk ], where tk = kbλc, as computed in Section III-D. Once again, λ is interpreted as a power-delay tradeoff parameter. After selecting a speed mode, PA-MWM makes its scheduling decision based on MWM.

V. S IMULATION R ESULTS In this section, we experimentally evaluate the performance of the PASS and PA-MWM, and contrast them to the MWM scheduler. We consider a uniform loading scenario, i.e, all VOQs are subject to the same average packet arrival rate. All buffers are assumed to be empty initially. The switch can be set into four possible speed modes (S = 4). We report results for two different packet arrival processes: 1) Bernoulli i.i.d. Traffic: Under this model, in every timeslot, a packet arrives to each VOQ (independent of other VOQs, and past/future time-slots) with probability p and no packet arrives with probability 1 − p. Fig. 3 and Fig. 4 depict the power-backlog (equivalently, power-delay) tradeoff for a 2 × 2 switch and a 4 × 4 switch, respectively. For PASS, the 4 × 4 switch is operated using one configuration subset only (as discussed in Section IV-A). Each curve for PASS and PA-MWM corresponds to a different choice of tradeoff parameter λ. The arrival rate p increases from left to right along each curve. As expected, both average power consumption and average backlog increase with p. For any fixed p, MWM has the lowest average backlog and the highest power consumption. PASS and PA-MWM provide a powerdelay tradeoff, which can be tuned by varying λ. In many cases, both PASS and PA-MWM yield power savings of 30-40% with only a marginal increase in average backlog, especially under light to moderate loading conditions. 2) Markov Modulated Bernoulli (MMB) Traffic: Under this model, packets arrive to each VOQ according to independent Bernoulli processes, whose rates are modulated by independent finite-state Markov chain (FSMC). The MMB model has often been employed in the literature to simulate bursty packet arrivals. We assume that the FSMC has two states — LO and HI. Packets arrive with probability pLO and pHI in the two states, where pLO < pHI . In each time-slot, the FSMC for each VOQ transitions its state (from LO to HI or HI to LO), with probability q. For our simulations, we fix pLO = 0.1, q = 0.3, and vary pHI to vary the load on the switch. Fig. 5 and Fig. 6 depict the power-backlog tradeoff for a 2 × 2 switch and a 4 × 4 switch, respectively. The results are qualitatively similar to those in the Bernoulli i.i.d. traffic case. Our simulation results clearly demonstrate the power-delay tradeoff achieved by PASS and PA-MWM. The former has a computational complexity O(N/S) per time-slot, while the latter has a complexity O(N 3 /S) per time-slot. The tradeoff point for both policies can be tuned by varying the parameter λ. Both policies yield significant power savings relative to the benchmark MWM policy (with no power management) at the expense of a moderate increase in average packet delay. We expect our findings to extend to bigger switches, different traffic models, and non-uniform loading scenarios. Adaptively tuning the design parameters λ and S in accordance with switch loading is a subject of ongoing research. VI. C ONCLUSIONS To address the increasingly important problem of high power consumption in packet switches, this paper proposed the

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Power-Managed Input-Queued (PMIQ) switch architecture. A PMIQ switch is an IQ switch with an additional layer of decision making to regulate the power dissipated by the switch. A PMIQ switch can be dynamically configured to operate in different speed modes depending upon its loading conditions. The proposed scheduling and power management algorithm (PASS) was experimentally shown to offer an attractive powerdelay tradeoff at manageable implementation complexity. The power management ideas presented here can also be combined with other known scheduling algorithms, as demonstrated through the proposed PA-MWM algorithm. The power management problem was studied here in the context of an IQ switch. The formulation, however, is quite generally applicable to any resource allocation scenario where allocating an idle resource to a job waiting in the system incurs a cost, thereby inducing a natural “push-pull” effect between the number of active resources and average job waiting time. R EFERENCES [1] N. McKeown, A. Mekkittikul, V. Anantharam, and J. Walrand, “Achieving 100% throughput in an input-queued switch”, IEEE Trans. Communications, vol. 47, no. 8, pp. 1260-1267, Aug. 1999. [2] A. Mekkittikul and N. McKeown, “A practical scheduling algorithm to achieve 100% throughput in input-queued switches”, IEEE INFOCOM 1998, pp. 792-799, San Francisco, CA, Mar. 1998. [3] C.S. Chang, W.J. Chen, and H.Y. Huang, “Birkhoff-von Neumann input-buffered crossbar switches for guaranteed-rate services”, IEEE Transactions on Communications, vol. 49, no. 7, pp. 1145-1147, Jul. 2001.

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Average backlog

Fig. 6.

Power-Backlog tradeoff for a 4 × 4 switch under MMB traffic

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