Process Variation Tolerant Standard Cell Library Development using Reduced Dimension Statistical Modeling and Optimization Techniques Shubhankar Basu , Priyanka Thakore, Ranga Vemuri University of Cincinnati, Cincinnati, Ohio, USA basusr,thakorpn,ranga @ececs.uc.edu Abstract Parametric yield has a direct impact on the profit yield of designs. In sub-90nanometer domains, ensuring acceptable parametric yield by corner case analysis has become inaccurate. Increasing clock requirements and process variations, necessitates the use of statistical modeling and analysis techniques for performance optimization. However, the dimensionality of statistical techniques due to the randomness of process variations has continued to grow, resulting in increased design complexity and run-time, and degrading accuracy. Design of standard cell libraries that are tolerant to process variations is still inadequate. This continues to result in expensive re-spins leading to significant design time overhead and low profit yield. In this paper, we present a novel technique to build analytical equivalent models, using statistical techniques, for intra-gate variability of physical parameters. This reduces the dimension of the response surface method to model the gate delay. We use these models to optimize the gate delay in the presence of process variations. Experimental results show the effectiveness of using the variation tolerant standard cells, resulting in better performance tolerance in designs.

1 Introduction Parametric Yield [13] is defined as the fraction of manufactured samples that meet the performance constraints. Several reports [6, 5, 2] present the need for new design methodologies that account for parametric yield. Performance in sub-90nanometer technologies are extremely sensitive to variations in manufacturing, process and environmental conditions. The components of variation are classified as inter-die variations and intra-die variations. Inter-die variations refer to parameter variations that have the same value across a die. Intra-die variations refer to parameter variations that varies within a single die. Portions of the intra-die variability may be spatially correlated, while portions of them are uncorrelated and random. Some of the device parameters that are affected by such variations are oxide-thickness ( ), effective chan), threshold voltage ( ), and effective nel length ( width ( ). [14] cites typical variance of such parameters for different technologies. The different sources of parameter variation together with their complex sensitivity to performance, has made the traditional worst-case timing

analysis, a pessimistic and an inaccurate choice. This has led to the need for statistical modeling techniques that simultaneously consider the different sources of variations. Randomness of the uncorrelated components of intragate variability has led to a significant increase in the dimensionality of the modeling problem. This has resulted in the need for reduced dimension modeling techniques that are used in a response surface method to develop an accurate statistical model for performance functions (parameters) such as gate delay. In our work, we develop equivalent parameters that analytically combine the random variables (physical parameters), using statistical sampling techniques, based on the topology of the circuit, and their combined sensitivity to the performance function. The equivalent parameters significantly reduce the dimension for response surface modeling. The model also captures the statistical variations in intra-gate transistor parameters for different combination of inputs, and uses statistical ’min’ and ’max’ functions to capture the real worst case scenarios. Design optimization for a reliable design often necessitates a tradeoff decision between cost (design time overhead, area, power etc) and performance (clock frequency, etc.). Extensive research [4, 11] points towards gate sizing to optimize delay, power or area at the chip level. Several post-silicon design optimization methods exist [3, 12]. However the cost due to redesign, and/or additional silicon area still remains in the overall design cost. In a sea-of-gate design technique, pre-designed standard cells occupy almost 75% of the chip real estate. While a lot of research has taken place in post-layout Statistical Static Timing Analysis (SSTA) techniques [1, 7], optimally designed variation-tolerant standard cell libraries are still inadequate. In this work, we use the reduced dimension statistical gate-delay models to optimize the standard cells, and build a library of variation-tolerant cells. The new cells may be used for a chip-level optimization of the critical and nearcritical timing paths. Experimental results show that with no other optimization at the design level, these standard cells can reduce the overall performance variation of designs due to process variations. The rest of the paper is organized as follows. Section 2 proposes a gate delay model using reduced dimension equivalent parameters and Response Surface Method (RSM) taking into consideration the intra-gate variability. Section 3 describes the optimization procedure for de-

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The transistor characteristics are linked to its physical parameters [9]. In this work we consider the transistor oxide thickness ( ), zero-biased threshold volt), effective width ( ) and effective channel age ( length ( ) as the physical parameters. The physical parameters of each transistor can be expressed as a vector

Figure 1. a) PDF for random all parameter variation b)PDF for uniform parameter variation

p

veloping variation-tolerant standard cells. Section 4, details the experimental results obtained for several combinational gates, and using them in two circuits. Finally, Section 5 states the conclusion and future work.

2 Reduced Dimension Gate Delay Modeling Fig. 1 shows how an uniform variation for physical parameter may lead to an under estimation of worst case points as found out by random variations of all parameters for a 2-input NAND gate. In this work we use response surface methods (RSM) [10] to model gate delay as a function of the randomly varying physical parameters of devices. Under the effect of process variation, the worst case delay of a gate is no longer predictible based on the combination of the inputs. Instead a typical non-worst case input combination may lead to worser propagation delay. Therefore, in order to size the transistors to optimize the intrinsic gate delay in the presence of process variation, we need to consider all the combinations of the input. In our work to develop a single performance goal, we combine the delay for different input combinations with every set of process parameters into a metric called tdlay, which is the average of all the high-to-low and low-to-high transition delays of the gate. We express tdlay as:

(1) where ’b’ is the number of inputs to the gate and ’a’ denotes the number of combinations that causes the output of the gate to discharge (h-l). Subsequenty, the worst case gate-delay used in this paper is defined as the largest tdlay observed over different combinations of the randomly varying physical parameters during the experiments. We define nominal delay as the intrinsic delay of the standard cells with nominal values of the physical parameters. Worst case delay variation is defined as the maximum percentage deviation from the nominal delay.

where T denotes a transistor. Under the conditions of intergate and intra-gate variation, each physical parameter may be expressed as: (2) represents the mean value of the parameter, where denotes the inter-gate variation and represent the intragate variability. The intra-gate variability is a combination of correlated and uncorrelated random variables. As pointed out in [9, 13], the simplest method of expressing the intra-gate variability parameter is by representing each transistor’s physical parameters as a separate random variable. However that increases the dimensionality of the RSM significantly, often requiring large run time and introducing unwanted error. We develop a new technique to develop statistical equivalent expression which reduces the dimensionality of the RSM modeling while capturing the relation amongst the parameters and their combined sensitivity to the gate delay.

2.2 Derivation of gate delay model In [9] Okada et al has proposed a statistical gate-delay modeling technique which takes into account the intra-gate variation alongside the inter-gate variation. The authors , to represent the sensitivity of use sensitivity constant transistor variation to the gate delay. Using response surface method (RSM), the method expresses gate delay for a complex gate with several channel connected transistors, as a linear combination of the physical parameters together with transistor parameter sensitivity. In the following section we give a brief introduction to the work in [9] and discuss about the possibility of inaccuracy in the measurement of delay variation due to intra-gate variability using this method. Consider that there are m transistors in the gate and is assigned to each transistor in the gate, where is a rsm coefficient. The average value of each parameter ( ) is considered constant for all the transistors in the gate and the inter-gate parameter variation ( ) is a constant for a single chip. With the above considerations, the gate-delay obtained from the rsm modeling ( ) is

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expressed as: (3)

(4)

parameters variation without consideration of the relative variation. is formally defined as the root-mean-sqare . The of the variances of each intra-gate variation composite intra-gate delay variation is evaluated as a sum of the intra-gate delay variation of each transistor. The authors use the following set of transformation to express the delay variation of gate due to intra-gate variability in terms of the sensitivity of each transistor and the intra-gate delay variation of each transistor.

Since the physical parameters ( and ) are often correlated, they are transformed into uncorrelated parameters ( and ) using PCA [8]. PCA transforms the correlated parameters into uncorrelated parameters using the following derivation:

(15) (16) (17)

(5) where is a matrix with eigenvectors for the correlation matrix of p and is a matrix of the eigenvalues corresponding to the eigen vectors of the correlation matrix represent on the diagonal. The diagonal elements of the standard deviations of the parameters. Using the above transformation the inter-gate and intra-gate physical parameters may be expressed as: (6) (7) The gate delay in the presence of inter-gate and intra-gate variation is therefore expressed as:

(18) Therefore the gate delay with the inter-gate and intragate parameter variation is expressed as:

(19) In [9] the authors make use of individual sensitivity of the transistors to evaluate the intra-gate variation component of gate delay. There are a few important considerations that the authors use to achieve this. We highlight these as they form the basis of introducing our technique to capture the delay due to intra gate parameter variation. 1. Sensitivity is calculated as a difference between slow case and typical case.

(8) (9) where

2. The simplified model assumes the sensitivity constants of transistors on charging and discharging paths to be equal. 3.

(10) (11) (12) (13) We express the above expression for gate delay as: (14) The authors in [9] model the delay variation due to intra-gate variability ( ) using an arbitraty value ( ) and a sensitivity constant ( ) which is used as a proportionality constant for each transistor. The authors consider the number of transistors (m) in the charging and discharging paths and assigns a sensitivity ( ) to each of them. The authors introduce the term intra-gate delay variation( ), which is the delay variation due to intra-gate

is computed as the sum of the sensitivity times the arbitrary constant for all transistors in the charging or discharging path for each combination of input.

Computing the sensitivity using typical and slow case analysis necessitates a prior knowledge of the corresponding parameter values. This makes the method similar to a corner case based analysis, which may either be overestimated or underestimated due to the difficulty in finding the real worst case or best case parameter values. Besides this, there may be multiple combinations of parameter values that lead to similar slow case condition. The sensitivity of the transistors to the output corresponding to a specific input combination is not a constant and may vary depending on the relative contribution due to parameter values. Also the consideration of equal sensitivity for charging and discharging path is a rather simplistic assumption which would not be accurate in most cases. For these reasons we need to consider the relative variation of the transistor parameters based on the topology of the circuit in order to capture the real worst cases and their combined sensitivity to the output for each combination of the input. Also

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in order to generate the gate delay model the has to be found for each input combination. However for the purpose of optimization of the standard cells, this would lead to increasing number of cases to consider. We therefore use our combined metric ( ) to model and optimize the standard cells. In our work we develop statistical equivalent pa) for the physical parameters of a gate. rameters ( The equivalent parameters are analytical combinations of each type of parameter for all the transistors in the gate. The combination is based on the topology of the gate. The equivalent parameters represent the relative variation across different transistors in the gate during switching. Under the effect of intra-gate parametric variation, some of the typical input combinations may give rise to the slowest (worst case) delay of the gate. This is dependant on the set of parameter values for all the transistors in the gate. They are therefore sampled using the statistical ’min’ and ’max’ functions. Section 2.3 details the development of the statistical equivalent parameters. We express the gate delay variation due to intra-gate variability ( ) using linear RSM [10] as:

(20)

where L is the number of physical parameters considered. In this work we consider four physical parameters. Each equivalent parameter has a best case and a worst case expression. Hence L=4 and the number of equivalent pais rameters would be 2*4=8. is the rsm constant and the linear rsm coefficient associated with each equivalent parameter. The equivalent parameters of different physical parameters in a single transistor are often correlated [13]. The uncorrelated parameters are derived from the correlated variables using PCA[8] as follows:

(21) where is a matrix with eigen vectors of the as column vectors and correlation matrix of is a matrix with eigenvalues of the correlation matrix of the diagonal. The matrix of diagonal represent the standard deviations for the equivalent physical parameters. The transformation into orthogonal basis vectors using PCA reduces the number of variables for rsm into first few principal components. If p is the nos. of principal components, the delay variation due to intra-gate variability can be expressed as:

Figure 2. (a) NAND2X1 circuit topology (b) Connectivity graph of NAND2X1 (c) Possible combinations of Path PUN and Path PDN for charging and discharging the Output

2.3 Statistical Equivalent Intra-Gate Variability Model The randomness of the physical parameters for intragate variability add to the uncertainty in modeling. The statistical equivalent intra-gate variability model in our work follows the concept of transistor sizing by relating each parameter to a RC equivalent circuit and the way they are sensitive to the gate delay in the charging and discharging paths. Fig. 2a shows the topology of a 2-input NAND gate and Fig. 2b shows the connectivity graph for the NAND gate. We define the terms Path PUN and Path PDN as: Path PUN implying a path from Vdd to Output which consists of series-parallel combination of transistors Path PDN implies a path from Output to Gnd which consists of series-parallel combination of transistors. Referring to Fig. 2c, we have three different combinations of Path PUN and Path PDN. Transistor delay is not linearly proportional to the combination of all its physical parameters. From basic semiconductor physics, with every other parameter remaining constant a transistor’s delay dependence on physical parameters can be expressed as : 1. Transistor Delay

Vth

2. Transistor Delay

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3. Transistor Delay 4. Transistor Delay Let represent the parameters which are inversely represent the paproportional to transistor delay, and rameters which are directly proportional to transistor delay. Therefore series combination of and , denoted and respectively are given by: by (23)

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(24)

where m denotes the number of transistors connected in series. Similarly the parallel combination of and , and respectively are given by: denoted by

(25) (26)

where n denotes the number of transistors connected in parallel. Our algorithm iteratively traverses a topology (spice netlist) to generate an equivalent combination for the different parameters ( and ) in the circuit. Conventional transistor sizing entails a best and worst case analysis based on the input combintaions to the gate. However, these methods consider constant physical parameter values. Under the effect of process variations, the physical parameter values become random in nature. Therefore for the metric of performance measurement (tdlay), a conventional typical case, or a best case may become a worst case scenario. It is therefore important to sample such cases using a statistical ’min’ and ’max’ function during the design of experiments, for model generation. We classify the samples as best case and worst case equivalent parameters. The best case parameters lead to the best case tdlay, while the worst case implies the equivalent parameter leading to a worst case tdlay. The ’min’ and ’max’ sampling of the equivalent parameters aids in finding the real worst case values of the equivalent parameters that leads to the worst delay of the gate. The set of such samples is obtained during design of experiments, by running a limited number of monte carlo simulation using HSpice. The equivalent parameter worst and best cases can therefore be expressed as:

The goodness of fit measure for the RSM model is obtained using a residual computation and technique [10] within 99% confidence interval. Our target is to obtain the . The gate delay model for each standard value of cell, with an accurate consideration of intra-gate variability can be used for statistical static timing analysis under the effect of process variation.

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Optimizing the standard cells

The second part of this work is to optimize the transistor sizes using the reduced dimension statistical model for gate delay ( ) in order to reduce the worst case variation due to intra-gate parameter variation. The cost penalty due to area increase may be substantially improved by us) instead of considering uniform variabiling the ( ity for physical parameters. Our algorithm for deterministic gate sizing is based on the method proposed by [11]. The objective of the deterministic sizing in our work is to compute the sizes of transistors such that the standard cell meets the worst case gate-delay constraints while consuming the minimum power and having the least area penalty. The delay of a gate is dependant not only on the transistor characteristics, but is a function of the input transition and load capacitance, when placed in a circuit. In an objective to optimize the gate sizes to reduce the variation in nominal delay in the presence of process variations, it is important to characterize the gates across different input slew and load capacitance ( ) combinations. We size the transistors across different parameter values and for different combinations of slew and capacitive load, such that the worst case gate delay ( ) is less than or equal to the nominal delay for the specific slew and capac). itive load combination ( Our optimization problem can be defined as: Minimize s.t.

where w implies worst case, b implies best case,j implies index, k implies index. For the 2-input NAND gate shown in Fig. 2 the statistical equivais expressed as: lent of

where is the cost due to the width of a transistor in the gate. and are the weights assigned to gate delay and power respectively based on the tradeoff decision of the represents the gate dedesign implementation. lay for the combination of slew rate and load capacitance.

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The algorithm starts from the minimum sized transistors, and picks up the combination of candidate transistor sizes, that satisfies the cost function. Similar methods is repeated over several combinations of the transistor sizes and for different combintaions of slew and load capacitance, until it reaches the error tolerance for the cost functions. The values of physical equivalent parameters are generated as pseudo random numbers which are in the range obtained during the design of experiments for model generation. Our results show that using our algorithm the percentage penalty in area is atmost 10% more than using monte carlo simulation-in-the-loop based methods, while achieving a significant reduction in run time.

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In the experiments we use our reduced dimension RSM based models for optimizing the gate delay for four standard gates: INVX2, NAND2X1, NAND3X1, XOR2X1. The nominal gates have been taken from MOSIS scmos library scaled for use with predictive technology model cards for spice simulation. The experiments were run on Sun Blade 1000 machines with Solaris operating system. Fig. 3 shows the pre-optimized and post-optimized gate delay variation for the NAND2X1 (2-input NAND gate). Experiments show that the reduced dimension rsm model has a modeling error of 3.2%. The pre-optimization worst case gate-delay variation is 17.55% and the postoptimization worst case gate-delay variation is 3.086%. We achieve an improvement in worst case gate-delay variation by around 14%. The worst case average power consumption is increased by 10%, and the area penalty due to transistor sizing is approximately 15%. Fig. 4 shows the improvement in worst case gate-delay for the the postoptimized NAND2X1 as compared to the pre-optimized NAND2X1 across different combinations of slew rate and load capacitance. Table 1. shows the result of optimization for all the four gates INV(INVX2), NAND2(NAND2X1), NAND3(NAND3X1) and XOR2(XOR2X1) using Reduced Dimension models. We introduce the following abbreviations: G Name of Gate F Function Name ( or ) Pre Pre-optimization worst case variation(%) Post Post-optimization worst case variation(%) I Improvement(% reduction) in worst case variation Area Penalty (%) AP Monte Carlo techniques often tend to generate accurate results at the expense of huge computational cost, where the error reduces with number of samples in the form of iterations n as [13]. Table 2. shows the comparison of area penalty using reduced dimension rsm models and iterations of monte carlo simulations in the loop. Results show that our optimization technique for the standard cells incurs around 10% more area penalty than that using monte carlo based simluation in loop and optimization approach.

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Name We introduce the following abbreviations: G of Gate PMC Area penalty due to Monte Carlo optimization(%) PRD Area penalty due to model based optimization (%) We use the variation-tolerant standard cells to implement two circuits: 15 stage ring oscillator (time delay oscillator) Mod-2 counter (Frequency = 500MHz) The spice netlist extracted were used with 65nm predictive mos model cards for both the designs. We have two metrics of measurement: Operating frequency of design (measuring the path delay). Average power consumption of the design. Monte carlo simulation was performed for three different cases: a) nominal design without any variation, b) design with random parametric variation using the original (preoptimized) gates, and c) design with random parametric variation using the optimized gates. Table 3 presents the results showing the improvement obtained in worst case delay variations, together with the percentage increase in

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Table 2. Area penalty due to MC and reduced dimension model G INV NAND2 NAND3 XOR2 Figure 4. Comparison of Gate Delay for different input slew and load capacitance combinations of NAND2X1

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Pre 18.385 34.186 17.755 12.843 18.495 3.122 16.210 22.510

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I 7.627 -17.4 14.669 -10.01 18.138 -10.457 15.035 -19

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Table 3. delay and average power consumption with nominal and optimized standard cells D Ring Osc. Modulo-2 Counter

Table 1. pre-optimization and postoptimization variation of gate delay and average power consumption together with area penalty G INV

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mization of circuits. A library of characterized variationtolerant cells is being developed to be included during the logic synthesis and layout stages.

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References

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[1] A. Agarwal et al. Statistical timing analysis for intra-die process variations. In IEEE ICCAD, 2003. [2] D. Blaaw and K. Chopra. Cad tools for variation tolerance. In IEEE Design Automation Conference, 2005. [3] C. Kim et al. Self calibrating circuit design for variation tolerant vlsi systems. In IEEE International On-Line Testing Symposium(IOLTS), 2005. [4] O. Coudert. Gate sizing for constrained delay/power/area optimization. IEEE Transactions on VLSI Systems, 5(4):465–472, December 1997. [5] L. R.-C. et al. Integration of design for manufacturability (dfm) practises in design flows. In IEEE 6th Symposium of Quality Electronic Design(ISQED), 2005. [6] ITRS. Semiconductor roadmap 2005. Technical report, International Technology Roadmap for Semiconductors. [7] J.A.G. Jess et al. Statistical timing for parametric yield prediction of digital integrated circuits. In IEEE Design Automation Conference, 2003. [8] Juha Karhunen. Adaptive algorithms for estimating eigenvectors of correlation type matrices. In IEEE Intl. Conf. on Acoustics, Speech, and Signal Processing, 1984. [9] K. Okada et al. A statistical gate-delay model considering intra-gate variability. In IEEE ICCAD, 2003. [10] Khuri and Cornell. Response Surfaces, Designs and Analyses. Marcel Dekker Inc., NY, USA, 1996. [11] M.R. Guthaus et al. Gate sizing using incremental parameterized statistical timing analysis. In IEEE ICCAD, 2005. [12] Q. Chen et al. Process variation tolerant online current monitor for robust systems. In IEEE International On-Line Testing Symposium(IOLTS), 2005. [13] Srivastava, Sylvester and Blaaw. Statistical Analysis and Optimization for VLSI: Timing and Power. Springer Science + Business Media Inc., NY, USA, 2005. [14] X. Li et al. Asymptotic probability extraction for nonnormal distribution of circuit. In IEEE ICCAD, 2004.

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average power consumption of the designs. A negative percentage of worst delay variation using post optimized gates implies that the worst delay is less than than the nominal delay of the circuit. We introduce the following abreviations: D Design name WD nom Worst delay variation using nominal gates WD opt Worst delay variation using optimized gates I Improvement in worst case delay variation PP Penalty in average power consumption due to delay optimization

5 Conclusion As technology continues to scale further down and the needs for performance continue to increase, it would become increasingly challenging to make tradeoff decisions between area, reliability of performance, and cost. Design methodologies therefore face a rising demand of tight integration at all stages of the cycle together with manufacturing process. In this work, we presented an alternative methodology aiming to bind intra-gate process variation with the gate delay and average power consumption. We optimize the gate delays based on the reduced dimensional model developed and showed their effect on circuit performance. The consideration of interconnect parasitic needs to be included while doing a detailed analysis and opti-

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