Quantitative Verification of Reconfigurable Manufacturing Systems: DEVS Approach Moon-Ho Hwang Department of Electrical and Computer Engineering Wayne State University Detroit, MI 48202, USA Email: [email protected]

Abstract— This paper introduces a method of the quantitative verification of a reconfigurable manufacturing system (RMS) by using a class of DEVS, called schedule-controllable DEVS (SC-DEVS). Based on the achievability of the finite-state global behavior of SC-DEVS networks, we can create the finite behavior model of a RMS consisting of dense-timed & interacting multicomponents. Based on the states’ finiteness, this paper proposes Min and Max processing times as quantitative verification indices th,at reflect the optimistic and the pessimistic cases of processing activities, respectively. By using Min/Max Processing times, a reconfigurable cluster tool is exemplified as a study on the improved effectiveness caused by introducing the parallel process module and/or the higher-performance transport module in this paper.

I. I NTRODUCTION In order to reduce the lead time of a system’s development and to increase the system’s flexibility and adaptability, the reconfigurable concept is introduced in manufacturing systems. As the consensus of advantage of the reconfigurable manufacturing system (RMS) has prevailed; research on modeling and verification of RMS are also needed more than ever before [1]. As a modular approach, one of the popular modeling methods in RMSs is the parallel composition of automata[2], which synchronizes transitions of two automata if their associated events are identical[3]. Due to synchronization of identical events, however, the automaton should be differently modelled in the situation to avoid the unwanted synchronization, even though associated modules in the real world are exactly identical. For example, Fig. 1(a) shows a cluster tool having three identical process modules, such as PM1, PM2 and PM3. Since we don’t want that PM2 activated to work when PM1 receives a wafer from the transport module, PM1, PM2 and PM3 must be differently modelled by having different names of events in the parallel composition approach. Thus, from the viewpoint of modularity, the composition-based model construction which has made the model dependent in situations causes the weak model’s re-usability. Unlike the parallel composition of components, the discrete event system specification (DEVS) provides higher modularity by introducing a coupling scheme, called coupled DEVS or DEVS network formalism, in which an influencer generates a output event, and the output event is sent to its influencee, according to the coupling relations [4]. Due to the modular

Fig. 1.

Reconfigurations of a Cluster Tool

and hierarchical feature of the DEVS formalism, its models for identical modules are also identical; for example, PM1, PM2 and PM3 are identical, as shown in Fig. 2(d), and the selective synchronization is modelled in the coupling relations, as shown in Fig. 3. In addition to is higher modularity, the real-time execution method of the DEVS model has been developed, so the procedure from modeling and implementation can be constructed as an unified environment [5], [6]. In spite of its all advantage, the simulation has been accepted as the only one analysis method of DEVS models for decades [7]. Because a DEVS network generally has its infinite states space caused by its real-valued time base. However, since the simulation is a method to trace one possible behavior of a system, an infinite number of simulation runs can be required to verify the whole behavior of the DEVS model. Thus, the simulation-based analysis of DEVS might

Min/Max processing time analysis in Section IV. Section V presents the conclusion and further research directions. II. B RIEF R EVIEW: S CHEDULE -C ONTROLLABLE DEVS A. Atomic SC-DEVS An atomic SC-DEVS specifies the dynamic behavior. Definition 1 (Atomic SC-DEVS): An atomic model of SCDEVS is a 10-tuple,

Fig. 2.

Atomic SC-DEVS Models for a Cluster Tool

Fig. 3.

A DEVS Network Model for a Cluster Tool

M =< X, Y, S, ta, δx , ρ, δτ , λ, s0 , SF > where, • X is a finite set of input events. • Y is a finite set of output events. • S is a non-empty and finite states set. +,∞ • ta : S → Q0 is the maximum sojourning time of a state where Q+,∞ denotes a set of non-negative rational 0 numbers with infinity. • δx : S × X → S is the external transition function. • ρ : S × X → {0, 1} is the reschedule indicating function. • δτ : S → S is the internal transition function. ² ² • λ : S → Y is the internal output function where Y is Y ∪ {²} and ² is the non-event such that ² 6∈ X ∪ Y . • s0 ∈ S is the initial state. • SF ⊆ S is a set of acceptable states. ¥ Since a graphic representation, as shown in Fig. 2s gives us more insight than a formal one, we use the following graphicc notations throughout this paper. • Input port or Output port: In or Out Arrow; • State: Rounded Rectangle Node – Initial State s0 : Arced node without source – Acceptable State: Double Lined Node – Life Time of s: s, ta(s) • External Transition δx (ss , ?x) = sd ?x

•

be criticized for its incompleteness. Recently, classes of DEVS, such as schedule-preserved DEVS (SP-DEVS) [8] and schedule-controllable DEVS (SCDEVS) [9], have been introduced to overcome the problem of the infinite-state space of DEVS. A finite number of states, even with dense-time delay, leads to verify the quantitative properties, such as cycle time and utilization, as well as qualitative properties, such as safetyness and fairness [8], [10]. In particular, SC-DEVS are able to reduce the number of states by eliminating the waiting self-loop transitions of SP-DEVS [9]. This paper focuses on a SC-DEVS-based quantitative verification method of a reconfigurable manufacturing system as follows. Section II introduces the brief review of SC-DEVS in terms of atomic SC-DEVS and coupled SC-DEVS. Section III proposes the optimistic and pessimistic processing times, called Min/Max processing times, of process executions based on the SC-DEVS structure. As a reconfigurable manufacturing system, a cluster tool is exemplified in the experiment of the

– Reschedule ρ(ss , ?x) = 1: ss −→ sd ?x – Continued ρ(ss , ?x) = 0: ss 99K sd Internal Transition δτ (ss ) = sd !y

– With Output λ(ss ) =!y: ss −→ sd 1 . Example 1 (SC-DEVS Model of the Transport Module): The transport module in the cluster tool is illustrated in Fig. 2(b) by the above graphic notations. Its formal presentation with the 10-tuple is as follows: X={?IHS:(s, d), ?IW[6]} where s and d are the source and destination indices for picking and placing, and IW[6] means IW1,IW2,. . ., IW6; Y ={!OHS, !OS[6], !OW[6]}; S={Idle(I), MoveToPick(MI), StreachToPick(STI), WaitReceive(W), ShrinkAfterPick(SRI), MoveToPlace(ML), StreachToPlace(STL), ShrinkAfterPlace(SRL) }; ta(I) = ta(W) = ∞, ta(STI) = ta(SRI) = ta(STL) = ta(SRL) = 2, ta(MI) = t1 , ta(ML) = t2 where t1 and t2 are determined by the current & destination locations, and the rotation speed of TM; δx (I,?IHS:(s,d)) = MI, δx (W,?IWs) = SRI; ρ(I,?IHS:(s,d)) = 1, ρ(W,?IWs) = 1; δτ (MI)) = SRI, δτ (STI)) 1 To distinguish event types, this paper uses ‘?’ before an input event, ‘!’ for an output event

= W; δτ (SRI)) = ML, δτ (ML)) = STL; δτ (STL)) = SRL; λ(MI)) = ², λ(STI)) = !OWs; λ(SRI)) =!OHS:1, λ(ML)) = ²; λ(STL)) = !OWd; s0 =I; SF = {I}; ¤ Given M =< X, Y, S, ta, δx , ρ, δτ , λ, s0 , SF >, the total states set, denoted by Q, considers the remaining time r at s ∈ S such that Q = {(s, r)|s ∈ S, 0 ≤ r ≤ ta(s)}

(1)

Based on the total state set, the state transition function δ : Q × X ∪ Y ² → Q describes the dynamics of SC-DEVS as follows. For (s, r) ∈ Q, e ∈ X ∪ Y ² ,  (δx (s, e), r) for ρ(s, e) = 0    (δ (s, e), ta(δ (s, e)) for ρ(s, e) = 1 x x δ((s, r), e) =  (δ (s), ta(δ (s))) for e = λ(s) ∧ r = 0 τ τ    (s, r) otherwise (2) By using the state transition function defined in Equation (2), we can track the state trajectory caused by a sequence of timed events. The execution trajectory δˆ : Q × (T, X ∪ Y ∪ {²}) → Q is a partial function such that for q ∈ Q, e ∈ X ∪ Y ∪ {²} and t ∈ R+,∞ (non-negative real 0 numbers with infinity) ( for ω = (t, e) ˆ ω) := δ(q, e) δ(q, (3) ˆ ω 0 ), e) for ω = ω 0 (t, e) δ(δ(q, B. Definition of SC-DEVS network Definition 2 (Structure of SC-DEVS Network): A SC-DEVS network is a 7-tuple, N =< X, Y, C, Zxx , Zyx , Zyy , select > where • X(Y ) is the finite set of input (output) events. • C = {Mi |Mi =< Xi , Yi , Si , tai , ρi , δxi , δτ i , λi , s0i , SF i >} is the finite set of sub-component SC-DEVSs, which can be atomic SC-DEVS or coupled SC-DEVS models. It is assumed that all of the leaf nodes are atomic SC-DEVS models and hierarchical depth to all leaf notes are finite. S • Zxx ⊆ X × Xi is the external input coupling Mi ∈C •

relation. Zyx ⊆

S Mi ∈C

Yi ×

S

Xi is the internal coupling

Mi ∈C

•

relation. S Zyy = Yi → Y is the external output coupling

•

function. select : 2C − ∅ → C is a tie-breaking function

Mi ∈C

¥ The SC-DEVS network for the reconfigurable cluster tool is shown in Fig. 3. We focus our attention of SC-DEVS networks to the non-partially rescheduled SC-DEVS network whose behavior can be described with an atomic SC-DEVS model [9].

III. Q UANTITATIVE V ERIFICATION Measuring the quantitative properties of a system are possible in many ways. This paper restricts our interest in quantitative analysis to the processing time of an activity that starts and ends with specific events. A typical example of an activity in a manufacturing system is the processing activity that consists of the arrival of material and its departure as a product. 2 e¯0 e¯1 ˆ ω) = q −→ Let an execution trajectory be δ(q, q1 −→ e¯n , and ei ∈ q2 . . . qn −→ qn+1 where e¯i = (ti , ei ), ti ∈ R+,∞ 0 X ∪ Y {²} for i = 0 to n and n > 0. Given an events sequence of ω, its initial timed event and last timed event are defined as i(ω) = e¯0 and l(ω) = e¯n ; its initial event and last event are defined as ie (ω) = e0 and le (ω) = en ; its initial event time and last event time are it (ω) = t0 and lt (ω) = tn ; the ˆ ω)) is the time duration processing time from q and ω P T (δ(q, from the initial event time to and the last event time; that is, ˆ ω)) = lt (ω) − it (ω) = tn − t0 . P T (δ(q, A. Min/Max Processing Times from a State A set of events sequence staring with an event es and ending with an event ee from a state s Π(s, es , ee ) is defined ˆ as Π(s, es , ee ) = {((s, r), ω)|∃r s.t. δ((s, r), ω) ∧ ie (ω) = es ∧ le (ω) = ee }. Given Π(s, es , ee ), a sub-execution sequences to i-th event ˆ ω 0 )|ω 0 = of Π(s, es , ee ) is denoted by Π(s, es , ee , i) = {δ(q, ˆ e¯0 e¯1 · · · e¯n ) ∈ Π(s, es , ee )} where 0 ≤ i ≤ n. e¯0 e¯1 · · · e¯i ∧ δ(q, The minimum processing time of Π(s, es , ee , i), denoted ˆ ω)), can be by M inT (s, es , ee , i) = M inimum P T (δ(q, ˆ δ(q,ω)∈Π(s,e s ,ee ,i)

calculated as follows. M inT (s, es , ee , 0) = 0 and ( 0 for ei ∈ X M inT (s, es , ee , 1) = ta(s1 ) otherwise

(4)

For 1 < i ≤ n, M inT (s, es , ee , i) =  M inT (s, es , ee , i − 1)    M in (s, e , e , i − 1) T s e     M inT (s, es , ee , i − 1) + ta(si )

for ei ∈ X for ei ∈ Y ² ∧ ej ∈ X, j = 0 to i − 1 otherwise (5) Obviously, the minimum processing time of Π(s, es , ee ), the processing time of the optimistic case, is defined as M inT (s, es , ee ) := M inT (s, es , ee , n). In contrast, we can consider the pessimistic case. The maximum processing time to the i-th event of Π(s, es , ee , i) is deˆ ω)) noted by M axT (s, es , ee , i) = M aximum P T (δ(q, ˆ δ(q,ω)∈Π(s,e s ,ee ,i)

is the slowest processing time to its i-th event, as follows. M axT (s, es , ee , 0) = 0 and M axT (s, es , ee , 1) = ta(s1 )

(6)

2 Another possible index for a quantitative property might be the resource utilization.

For 1 < i ≤ n, M axT (s, es , ee , i) = ( M axT (s, es , ee , i − 1) ρ(si , ei ) = 0 M axT (s, es , ee , i − 1) + ta(si ) otherwise

(7)

Obviously, the maximum processing time of Π(s, es , ee ) is defined as M axT (s, es , ee ) := M axT (s, es , ee , n). Example 2 (Min/Max Processing Times from a state): Let’s evaluate Min/Max processing times of the TM shown in Fig. 2(c), from its state Idle(I) starting from ?IHS:(s, d) and ending with !OHS:0 that is the entire cycle of picking and placing transportation. M inT (I,?IHS:(s, d),!OHS:0)=ta(MI) + ta(STP) + ta(W) + ta(SRI) + ta(ML) + ta(STL) + ta(SRL) = t1 + 2 + 0 + 2 + t2 + 2 + 2 = 8 + t1 + t2 , while M axT (I,?IHS:(s, d),!OHS:0) = ta(MI) + ta(STP) + ta(W) + ta(SRI) + ta(ML) + ta(STL) + ta(SRL) = t1 + 2 + ∞ + 2 + t2 + 2 + 2 = ∞. ¤ B. Min/Max Processing Times from Multiple States Generally speaking, there are more than one execution sequences triggered by the starting event es and reaching to the ending event ee . Given two events es and ee , a set of execution sequences es to ee , denoted from Π(eSs , ee ) is a set of event sequences such that Π(es , ee ) = Π(s, es , ee ) Π(s,es ,ee )6=∅

The minimum processing time of es and ee , denoted by M inT (es , ee ), is defined as M  inT (es , ee ) = ∞ for Π(es , ee ) = ∅ ˆ  M inimum M inT (P T (δ(q, ω))) otherwise ˆ δ(q,ω)∈Π(e s ,ee )

(8) Theorem 1: Given an event pair es and ee of M , checking M inT (es , ee ) is decidable in polynomial time. Proof: Given a state s of M , searching for the shortest paths to the rest of the states is bound in O(|E|log|S|) when using Dijkstra’s algorithm with priorityqueue implementation[11]. Let Ss = {s|δ(q, es ) = s}. Thus, the complexity of this problem is less then the all-pair shortest path problem whose complexity is bound in O(|Ss ||E|log|S|). To calculate the pessimistic processing time, we need to consider three other cases in which the processing time might be pessimistically infinite. First, Π(es , ¬ee ) is a set of execution sequences starting from es but unable to generate ee . Sec→ª→ ˆ ω) ∈ Π(es , ee )|ω has a loop. }. ond, Π (es , ee ) = {δ(q, →ª→

Because the execution in Π (es , ee ) has a loop, the infinite cyclic execution in a loop can be possible in the pessimistic case. 6∞

The last execution sequence treated as special is Π(es , ee ) = ˆ ω) ∈ Π(es , ee )|@ω 0 : δ( ˆ δ(s, ˆ ω), ω 0 ) s.t. i(sub(ω 0 )) = {δ(q, 0 es ∧ l(sub(ω )) = ee } where sub(ω 0 ) is a substring of ω 0 . 6∞

That is, an element in Π(es , ee ) cannot repeat the execution sequence es to ee in some cases.

Fig. 4.

Categorization of Π(es , ee )

Fig. 4(a)(b) and (c) show Π(es , ¬ee ) 6= ∅, 6∞

→ª→

Π (es , ee ) 6= ∅

and Π(es , ee ) 6= ∅, respectively. Meanwhile, Fig. 4(d) illus6∞

→ª→

trates the case Π(es , ¬ee ) = Π(es , ee ) = Π (es , ee ) = ∅. Considering these cases, the pessimistic processing time of es and ee , denoted M axT (es , ee ), is defined as M axT (es , ee ) =  ∞ for Cond∞ ˆ M aximum M ax (P T ( δ(q, ω))) otherwise T 

(9)

ˆ δ(q,ω)∈Π(e s ,ee )

→ª→

where Cond∞ is the case of Π(es , ¬ee ) 6= ∅∨ Π (es , ee ) 6= 6∞

∅ ∨ Π(es , ee ) 6= ∅. Theorem 2: Given an event pair es and ee of M , checking M axT (es , ee ) is decidable in polynomial time. Proof: Let Ss = {s|δ(q, es ) = s}. Since depthfirst search requires time proportional |S|+|E| [11], findˆ ˆ ing δ((s, ta(s)), ω) ∈ Π(es , ¬ee ) and δ((s, ta(s)), ω) ∈ →ª→

Π (es , ee ) for all s ∈ Ss is also bound in O(|Ss |(|S|+|E|)). If a path ω from es and ee without cycle from s ∈ Ss is found, the path should be tested if it is connected to a state that is transited to es and it leads to another path to ee . For this test, we need the transitive closure of M whose complexity is bound in O(|S|3 ) [11]. A sub-graph not screened out by previous testes of →ª→

6∞

Π(es , ¬es ), Π (es , ee ), Π(es , ee ), is an acyclic graph whose longest path can be calculated by the topological shorting with O(|S| + |E|) [11]. Since every complexity of each step is bound in polynomial time, the whole process can be done in polynomial time. IV. I LLUSTRATIVE E XAMPLE : A C LUSTER T OOL In this section, we evaluate performances of various configurations in a reconfigurable manufacturing system by using the Min/Max processing time evaluation. As an typical example of a reconfiguration manufacturing system, a cluster tool (CT) consisting of one or two cassette modules (CM), more than three processing modules (PM), and a transport module, is used here. The CT system can be reconfigured as shown in

TABLE I I NTERFACES AND S TATE VARIABLES OF C ONTROLLER CTC TRL

Fig. 1 (a), (b), (c), and (d), and whose couplings for signal or material flows are as illustrated in Fig. 3.

port name ?ICM[ncm] ?IPM[npm] ?ITM !OCM[ncm] !OPM[npm]

A. Experimental Setup In operation of a cluster tool, there might be a variety of configurations. This paper restricts the variations into three factors: single CM (SCM) vs dual CM (DCM), serial PMs (SPM) vs parallel PMs (PPM), and low-performance TM (LTM) vs high-performance TM (HTM). As a result, there are eight different cases: with combinations of CM and PM, SCM-SPM, DCM-SPM, SCM-PPM and DCM-PPM cases are shown in Fig. 1(a), (b), (c), and (d), respectively, and each case has two branches of LTM and HTM. We assume that there is one type of a cassette which has 12 slots for accommodating a batch lot of wafers. The cassette arrives at a cassette module (CM) and stays there until all its wafers are processed. This CT performs three types of processes: cleaning, etching, and drying, whose processing times are 20, 50, and 30 seconds, respectively. In the serial processing layout, as shown in Fig. 1(a) and (b), these processes are assigned to PM1, PM2, and PM3, respectively. In the parallel processing layout as shown in Fig. 1(c) and (d), the bottleneck process, etching, can be performed either in PM2 and PM3, so PM4 performs the drying process. Therefore, wafer flows for all layouts are • SCM-SPM: CM1 → PM1 → PM2 → PM3 → CM1 • DCM-SPM: {CM1, CM2} → PM1 → PM2 → PM3 → {CM1, CM2} • SCM-PPM: CM1 → PM1 → {PM2, PM3} → PM4 → CM1 • DCM-PPM: {CM1, CM2} → PM1 → {PM2, PM3} → PM4 → {CM1, CM2} The wafer-transfer among CM and PM is performed by the transportation model (TM). We consider two different performance TMs in terms of rotation speed: LTM ’s rotation speed is 18 degrees a second; that of HTM is 36 degrees a second. Both have the same stretching & shrinking times with their arms as 2 seconds. 1) Controller: A SC-DEVS model for the cluster-tool controller, called CTCtrl, is modelled as shown in Fig. 2(a). Its interface and state variables, internal state transitions, and external state transitions are summarized in Tables I, II and III, respectively. Here, ncm, nsl, and npm stand for the number of cassette modules (=2), slots (=12), and process modules (=3), respectively. We give the higher priority to CM2 than CM1 in the selection situation of DCM cases (Fig. 1(c) and (d)). The maximum sojourning time function ta, the rescheduleindicating function ρ, and the output function λ are defined as follows. DvTime CTCtrl::ta() { if(phase == Idle){ if(TM == Idle) { for(int i=0; i
!OTM

name phase CM[ncm][nsl] PM[npm] W[ncm][nsl] TM bTM tp SPM index

Interface port value bool;/*0: Empty (E), 1: Ocuppied (O)*/ integer;/* 0:E, 1:O, 2: Finished */ bool; /*1: picked, 0: placed */ bool; /*1: send out a cassette */ float; /* tp : processing time */ struct { integer hs , vs , hd , vd ; }; output /* indexes of source & destination */ State Variables type {Wait, CmdTranfer, CmdProcess, CmdCM-Out }; {OccupiedByNew (ON), Sending (S), Empty (E), Reserved (R), OccupiedByFinished (OF) }; {ON, S, E, R, OF, Processing (P) }; integer;/* current location index of wafer[i][j]*/ struct { integer hs , vs , hd , vd ; }; bool; /* 0: TM is idle, 1: TM is working */ float; /* processing time of PM index*/ bool;/* 1: single PM, 0: parallel PM*/ integer;/* commend target index of CM or PM*/ type input input input output output

TABLE II I NTERNAL S TATE T RANSITIONS OF C ONTROLLER CTC TRL C# C1-1

C1-2

C1-3

Pre-Condition j=ncm to 0, k=nsl to 0 CM[j][k]=ON∧PM[0]=E ¬ C1-1 ∧ SPM=1 ∧∃i, j s.t. j=i+1∧PM[i]=OF∧PM[j] = E ¬ C1-1 ∧ SPM=0 ∧ PM[0]=OF∧PM[1]=E; i:=0,j:=1∨ PM[0]=OF∧PM[2]=E; i:=0,j:=2∨ PM[1]=OF∧PM[3]=E; i:=1,j:=3∨ PM[2]=OF∧PM[3]=E; i:=2,j:=3 ¬ C1-2 ∧∃j, k s.t. PM[npm-1]=OF∧ W[j][k]=npm-1

C2

¬ C1-3 ∧∃i s.t. PM[i]=ON

C3

¬ C2 ∧∃i, ∀j, s.t. CM[i][j] = OF

Post-Condition phase := CmdTranfer; CM[j][k]=S; PM[0]=R; W[j][k]=ncm; TM:=(j,k,ncm,0); phase := CmdTranfer PM[i]=S; PM[j]=R; W[l][m]:=j for W[l][m]=i TM:=(ncm+i,0,ncm+j,0);

phase := CmdTranfer PM[npm-1]=S; W[j][k]:=j TM:=(ncm+npm-1,0,j,k); phase := CmdProcess; PM[i]:=P;tp :=tp (PM[i]); index :=ncm+i; phase := CmdCM-Out; CM[i]=S; index:=i;

return 0.0; } } bool CTCtrl::rho(const DvMessage& x) { if(phase != Idle) return 0; else if(x == ?ICM1:1 || x == ?ICM2:1) { if(bTM == false) for(int i=0; i
TABLE III E XTERNAL S TATE T RANSITIONS OF C ONTROLLER CTC TRL Input Event ?ICM[i]:1

Pre-Condition CM[i]=E

?ITM:1 ?ITM:1 ?ITM:0 ?ITM:0 ?IPM[i]:1 ?IPM[i]:2 ?IPM[i]:0 ?ICM[i]:0

TM.hs
Post-Condition CM[i]:=O; W[i][k]=i for k=0 to nsl-1 CM[i][k]=OF for k=0 to nsl-1 CM[TM.hs ][TM.vs ]:=E; PM[TM.hs −ncm]:=E; CM[TM.hd ][TM.vd ]:=OF; PM[TM.hd −ncm]:=ON; PM[i]:=ON; PM[i]:=OF; PM[i]:=E; CM[i]:=E;

2) Plant Models: The models in the plant are constructed using SC-DEVS. Fig. 2(b), (c) and (d) are SP-DEVS-based models: the cassette module, the transport module and the process module, respectively. 3) Non-partially Rescheduled Network: Before addressing results of our experiments, we need to address that the SCDEVS network of this section is a non-partially rescheduled SC-DEVS network which guarantees the finiteness of its state space [9]. There are two input events: ?A1 and ?A2, and they are coupled to CM1, CM2, and CTCtrl, such that (?A1,CM1.?A), (?A1,CTCtrl.?ISCPM1), (?A2,CM2.?A), and (?A2,CTCtrl.?ISCPM2). Notice that δx (Empty,?A)=Occupied and ta(Occupied)=∞ for both CM1 and CM2 (see Fig. 2(b)), so they have no relation of partially rescheduled case. And CTCtrl controls its continued or rescheduling case as follows (see CTCtrl::rho(DvMessage& x) implementation): when the signal ?ISCPM1 or ?ISCPM2 arrives, if (1) CTCtrl is commanding, (2) TM is working (bTM != false), or (3) TM is idle (bTM == false) and there is a working PM module (PM[i]==P), CTCtrl continues its schedule. This prevents partially-rescheduled cases. B. Experimental Results The experimental test bench was built in the C++ language c with the XSY° library [12] by using the Microsoft VC++.Net [13] compiler. The hardware platform was Presario, X1000, Compaq with 1 GHz Intel centrinoTM CPU and 1 GByte RAM. Table IV summarizes the experimental results. As we can see in the first and second columns, we have carried out experiments in eight different cases: {SCM,DCM}× {SPM, PPM} × {LTM, HTM}. For achieving the Min/Max processing times for processing all wafers in a cassette, we generate the global behavior model as an atomic SC-DEVS model from the SCDEVS network of each cluster tool configuration. The number of states and the number of its transitions and the generating time in the behavioral model are summarized in Table IV in columns: |S|, |E| and Tg (sec), respectively. The columns, titled es and ee , show the starting and ending events of the events sequence concerned; for example, ?A1 (!D1) in the configuration C1 means the arrival (departure) of

a cassette to (from) CM1, while ?A2 (!D2) is that of CM2. Therefore, Table IV also illustrates the optimistic (=fastest) processing time in the M inT (es , ee ) column, as well as the pessimistic (=latest) processing time in M axT (es , ee ). Here, the first column of M inT (es , ee ) means the value of M inT (es , ee ), while the second column (numbers in parentheses) stands for the time needed to calculate M axT (es , ee ) in seconds. The same format is used in the columns for M axT (es , ee ). One of interesting things is that M inT (?A1,!D1) is equal to M axT (?A1,!D1) in each single CM case (configurations C1 to C4) because there is no interference of CM2, so once a cassette arrives at CM1, the processing sequence is performed in a straightforward manner. The performance improvement cause by the high-performance transport module (HTM) is 838796 = 42 sec. for each cassette. Meanwhile, the performance improvement cause by the parallel processing module (PPM) is 838-729 = 109 sec. for each cassette. When introducing both HTM and PPM, the improvement is 838-621.5 = 216.5 sec. When we introduce the dual cassette module (DCM), the behavior of the CT becomes complicated as |S| and |E| are increased. Even though there is newly introduced CM, CM2, all wafers in the cassette of CM1 is straightforwardly processed in the optimistic case. Therefore, M inT (?A1,!D1) values in configurations pairs of (C1,C5), (C2,C6), (C3,C7) and (C4,C8) are identical, respectively. However, the pessimistic case of processing times should be totally different because the priority of CM2 is higher than CM1, M axT (?A1,!D1) values for all C5 to C8 configurations are much slower than M inT (?A1, !D1) and M axT (?A2,!D2). In terms of the improved effectiveness caused by introducing PPM and HTM, (5,5002,819.5)/5,500*100=48.7% reduction in M axT (?A1,!D1) is the most dominant when compared to the others, such as 22.5% in M axT (?A2,!D2) , 25.8% in M inT (?A1,!D1), 25.7% in M inT (?A2,!D2). V. C ONCLUSION AND F URTHER R ESEARCH This paper introduced a method of the quantitative verification of a reconfigurable manufacturing system by using a class of DEVS, called schedule-controllable DEVS (SCDEVS). Based on the achievability of the finite-state global behavior of SC-DEVS networks, we could create the finite behavior model of a reconfigurable cluster tool. By introducing the optimistic and pessimistic process times that were based on the finite-states atomic SC-DEVS, we could verify the improved effectiveness caused by introducing the parallel process module and/or the higher-performance transport module. In our proposed approach, the verified SC-DEVS is a concrete and independent module so that it is also able to work as a component in a higher level of systems. For example, the cluster tool used in the paper can be applied to a fabrication lab level. For the application of a detailed model to a higher level, behavioral equivalency or tolerance-based model abstraction and symbolic model presentation [14] are needed to increase scalability.

TABLE IV G ENERATING G LOBAL B EHAVIOR AND M IN /M AX P ROCESSING T IMES Global Behavior |S| |E| Tg 847 847 1.0 922 922 1.0 701 701 1.0 734 734 1.0

C#

Configuration

C1 C2 C3 C4

SCM-SPM-LTM SCM-SPM-HTM SCM-PPM-LTM SCM-PPM-HTM

C5

DCM-SPM-LTM

18,202

19,502

31.0

C6

DCM-SPM-HTM

21,401

22,931

52.0

C7

DCM-PPM-LTM

20,644

21,868

46.0

C8

DCM-PPM-HTM

24,167

25,714

59.0

ACKNOWLEDGMENT This work was partially supported by the Post-doctoral Fellowship Program of Korea Science & Engineering Foundation (KOSEF). R EFERENCES [1] Y. Koren and U. Heisel and F. Jovane and T. Moriwaki and G. Pritchow and H. Van Brussel and A.G. Ulsoy, “Reconfigurable Manufacturing Systems,” CIRP Annals, vol. 48, no. 2, pp. 527–540, 1999, keynote paper. [2] E.W. Endsley and M. R. Lucas and D.M. Tilbury, “Software Tools for Verification of Modular FSM Based Logic Control for Use In Reconfigurable Machining Systems,” in Proceedings of 2000 Japan-USA Symposium on Flexible Automation, Ann Arbor, MI, 2000. [3] C.G. Cassandras and S. Lafortune, Introduction to Discrete Event Systems, 2nd ed. Kluwer Academic Publishers, 1999. [4] B.P. Zeigler, Multifacetted Modeling and Discrete Event Simulation, 1st ed. London,Orlando: Academic Presse, 1984. [5] ——, “DEVS Representation of Dynamical Systems: Event-based Intelligent Control,” Proceedings of IEEE, vol. 77, no. 1, pp. 72–80, 1989. [6] ——, “Extending the DEVS-Scheme Knowledge-Based Simulation Environment for Real-Time Event-Based Control,” IEEE Transactions on Robotics and Automation, vol. 9, no. 3, pp. 351–356, June 1993. [7] Yu-Chi Ho, “Forward to the Special Issue,” Discrete Event Dynamic Systems:Theory and Applications, p. 111, 1993. [8] M.H. Hwang and S.K. Cho, “Timed Analysis of Schedule Preserved DEVS,” in 2004 Summer Computer Simulation Conference, A. Bruzzone and E. Williams, Eds. San Jose, CA: SCS, 2004, pp. 173–178. [9] M.H. Hwang, “Generating Finite-State Behavior of Reconfigurable Automation Systems: DEVS Approach,” in Proceed. of 2005 IEEECASE. IEEE, 2005, pp. Edmonton,Canada, submitted. [10] ——, “Tutorial: Verification of Real-time Systems Based on SchedulePreserved,” in Proceedings of 2005 DEVS Integrative M & S Symposium, SCS. http://kalman.eng.wayne.edu/mhhwang, 2005, submitted. [11] R. Sedgewick, Algorithms in C++, Part 5 Graph Algorithm, 3rd ed. Boston: Addison Wesley, 2002. c : DEVS-based Modeling, Verification, and Execu[12] M.H. Hwang, XSY° tion Software, http://kalman.eng.wayne.edu/mhhwang, 2005. [13] Microsoft, Visual C++. Net, http://msdn.microsoft.com/visualc/, 2002. [14] J.R. Burch and E.M. Clarke and K.L. McMillan and D.L. Dill and L.J. Hwang, “Symboling Model Checking: 1020 States and Beyond,” Information and Computation, vol. 98, no. 2, pp. 143–170, 1992.

es

ee

?A1 ?A1 ?A1 ?A1 ?A1 ?A2 ?A1 ?A2 ?A1 ?A2 ?A1 ?A2

!D1 !D1 !D1 !D1 !D1 !D2 !D1 !D2 !D1 !D2 !D1 !D2

M inT (es , ee ) 838.0 796.0 729.0 621.5 838.0 851.0 796.0 802.5 729.0 750.0 621.5 632.5

(5.0) (5.0) (4.0) (4.0) (112.0) (112.0) (14.0) (14.0) (10.0) (9.0) (12.0) (12.0)

M axT (es , ee ) 838.0 796.0 729.0 621.5 5,500.0 941.0 5,206.0 894.0 3,318.0 868.5 2,819.5 729.0

(6.1) (6.1) (5.2) (5.2) (236.0) (27.0) (544.0) (52.0) (298.0) (28.0) (830.0) (96.0)