Microprocessors and Applications –MT6401 2 Marks 1. What is the difference between Microprocessor and Microcomputer? Microprocessor: Microprocessor is a simple central processing unit (CPU) on a single chip (remember the word ‘Single Chip’). It includes Arithmetic logic unit (ALU), control unit (CU), registers, instruction decoders, bus control circuit etc. but everything should be on a single chip.

Microcomputer: A microcomputer is the association of microprocessor and the peripheral I/O devices, support circuitry and memory (both data and program). It is not necessary to be on a single chip (remember this point, not in a single chip).

2. What is the difference between machine language and assembly language? Machine Language: The machine language is the internal language of the computer system. It is a difficult programming language to handle by any humans. It is usually made up of a binary string of 0s and 1s that is understood by the machine to follow any instructions. In fact, we can say that the machine can only recognize these 0s and 1s and nothing else. So, it is a language of the lowest degree made for machines only. A programme therefore prefers to use either a high-level programming language or an assembly language to deliver various instructions by translating it to machine understandable codes known as machine codes. Assembly Language: Assembly language is a second generation programming language used in the computer systems. In assembly language, a programmer uses symbolic instructions instead of machine language instructions and descriptive names for data items and memory location. An assembly language program is written according to strict rules and then translated by an assembler into machine code. It is machine dependant language hence it is not portable. It has very less restrictions and also features high interaction between the operating system and the hardware thus enabling to write easy hardware dependant programs. The various symbolic notations used in the assembly language are called mnemonics.

3. What is the function of ALE and READY pin in 8085? ALE(Address Latch Enable) It is an output signal used to give information of AD0AD7 contents, It is a positive going pulse generated when a new operation is started by

microprocessor, When pulse goes high it indicates that AD0-AD7 lines are address, When it is low it indicates that the contents are data.

Ready pin: This is an active high input control signal, It is used by microprocessor to detect whether a peripheral has completed (or is Ready for) the data transfer or not, the main function of this pin is to synchronize slower peripheral to faster microprocessor, If ready pin is high the microprocessor will complete the operation and proceeds for the next operation, If ready pin is low the microprocessor will wait until it goes high.

4. Why the Program is counter and the Stack pointer 16 bit registers? Even though the 8085 is an 8-bit computer, the program counter and stack pointer are 16 bits wide in order to support the address bus, which is also 16 bits wide. 5. Define instruction cycle, machine cycle and T-state. Instruction cycle is defined, as the time required completing the execution of an instruction. Machine cycle is defined as the time required completing one operation of accessing memory, I/O or acknowledging an external request. Tcycle is defined as one subdivision of the operation performed in one clock period 6. What is the function of IO/M signal in the 8085? It is a status signal. It is used to differentiate between memory locations and I/O operations. When this signal is low (IO/M = 0) it denotes the memory related operations. When this signal is high (IO/M = 1) it denotes an I/O operation. 7. What is the function of RIM and SIM instruction available in 8085? Read Interrupt Mask (RIM) RIM is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and to read serial input data bit. RIM loads 8-bit data in the accumulator with the following

interpretation: Actually RIM does the following three tasks: 1 Read the interrupt mask (bit 2, 1, 0). 2Identify pending interrupts (bit 6, 5, 4). 3 Receive serial input data bit (bit 7). SIM is a multipurpose interrupt used to implement the 8085 interrupts (RST 7.5, 6.5, 5.5) and serial data output. SIM interprets the accumulator content as follows: Actually, SIM does the following three tasks: 1 Mask the interrupts (bit 2, 1, 0). 2 Reset RST 7.5 (bit 4). This is mainly used to overwrite RST 7.5 without serving it. 3 To implement serial I/O (bit 7, 6). If bit 6 = 1 is used to enable serial I/O and bit 7 is used to transmit serial output data bit. 8. Define interrupts of 8085? Interrupts can be classified into two types: maskable interrupts and non-maskable interrupts. The maskable interrupts can be delayed or rejected but the non –maskable interrupts cannot be delayed or rejected. Interrupts can also be classified into vectored and non-vectored interrupts. In vectored interrupts, the address of the service routine is hard wired. But in nonvectored interrupts the address of the service routine needs to be supplied externally by the device. INTR is a maskable interrupt. When the interrupt occurs, the processor fetches from the bus on instruction, usually one of EI and DI instructions 9. What is the addressing capacity of 8085 microprocessor? Since the address bus width is of 16-bit, maximum you can access is 64kb i.e. 65536 bytes only. 10. What is the need of interfacing? A microprocessor can perform various functions depending on how you connect them up to other hardware. An interface device is like a two-way street. Interface devices are always connected as something that you would do (input) that triggers a result (output). For example, a computer's microprocessor can still perform without a keyboard or screen. Then what's the point? The keyboard acts as the input and the screen is the output, which a user can read. So without interface devices, microprocessors are much more useless, even though they can still run perfectly fine. 11. What is DMA? Direct Memory Access (DMA) During any given bus cycle, one of the system components connected to the system bus is given control of the bus. This component is said to be the master during that cycle and the component it is communicating with is said to be the slave. The CPU with its bus control

logic is normally the master, but other specially designed components can gain control of the bus by sending a bus request to the CPU. After the current bus cycle is completed the CPU will return a bus grant signal and the component sending the request will become the master. Taking control of the bus for a bus cycle is called cycle stealing. Just like the bus control logic, a master must be capable of placing addresses on the address bus and directing the bus activity during a bus cycle. The components capable of becoming masters are processors (and their bus control logic) and DMA controllers. Sometimes a DMA controller is associated with a single interface, but they are often designed to accommodate more than one interface. 12. What is cycle stealing related to DMA? Cycle stealing is used to describe the "stealing" of a single CPU cycle to allow a DMA engine to perform a DMA operation. This is opposed to block operation where a DMA engine would request a bus, hold it for a complete transaction (typically 16-32 bytes but could last much longer) before releasing to a CPU. Cycle stealing generally occurs when the entire DMA transfer of data is finished; the DMA controller interrupts the CPU. 13. Define burst mode? Burst mode is a temporary high-speed data transmission mode used to facilitate sequential data transfer at maximum throughput. Burst mode data transfer rate (DTR) speeds can be approximately two to five times faster than normal transmission protocols. Different types of devices employ a burst mode, including random access memory (RAM), hard drive interfaces and accelerated graphics ports. Burst mode functionality is devicedependent, and does not require input from other devices. 14. What is a closed loop process control and an open loop process control? What are the advantages of closed loop control systems? In a typical process control application , the microprocessor continuously monitors one or more process variables and generates outputs to the electro mechanical elements which in turn controls the process variables. This kind of control is known as closed loop control. If the microprocessor outputs the control variables to human operators through displays or monitors who in turn apply the necessary control inputs then the control strategy is known as open loop control. Advantages: It is fully automatic and it reduces the error since the error is given as a feedback.

15. What is a data converter?

A data converter is one which converts an Analog to digital signal or a Digital signal to an analog signal. They are used in most of the applications such as temperature monitoring system. 16. What are the steps involved to interface an A/D converter to a microprocessor? The microprocessor should: 1. Send a pulse to the start pin 2. Wait until the end of the conversion 3. Read the digital signal at the input port 17. Write the steps necessary to initialize a counter in write operations? ♦ Write a control word into the control register ♦ Load the low-order address byte ♦ Load the high order byte 18. What is the purpose for scan section in Keyboard interface? The scan section has a scan counter and four scan lines. These scan lines can be decoded using a 4-to-16 decoder to generate 16 lines for scanning. 19. List the operating modes of 8255A PPI? ♦ Two 8-bit ports (A and B) ♦ Two 4-bit ports (CU and CL) ♦ Data bus buffer ♦ Control logic 19. What are the angular steps in which a stepper motor can be rotated? The number of steps required to complete one full rotation depends on the step angle of the stepper motor. The step angle can vary from 0.72 degrees to 15 degrees per step. Depending on that 500 to 24 steps may be required to complete one rotation. In position control applications the selection on motor should be based on the minimum degree of rotation that is required per step. 20. What are the sensors used normally for temperature measurement? Thermostat, Thermocouple, RTD (Resistive temperature detector) and Thermistors are some of the temperature sensors. 21. Write a simple delay subroutine involving a register pair of 8085?

22. How will you interface a transducer with a microprocessor? The transducer converts temperature or any other parameter to an analog voltage. This voltage signal is read by the A/D converter which is in turn interfaced with Microprocessor.

23. What are the advantages of using Microprocessors or microcontrollers in automobile?

24. What are the parameters that control the air – fuel ratio in a fuel igniter of an automobile?

The width and timing of the pulses which are determined by the engine speed, engine temperature and air flow are the main parameters which control the air fuel ratio of the engine in an automobile.

PART - B

16 Marks 1) With a neat diagram explain the architecture of 8085 microprocessor?

It consists of five essential blocks. (1) ARITHMEDIC LOGIC SECTION (2) REGISTER SECTION (3) THE INTERRUPT CONTROL SECTION

(4) SERIAL I/O SECTION (5) THE TIMING AND CONTROL UNIT

The description of each unit follows. There is an internal bi directional bus of 8 bits. All the internal registers which transfer data to the internal bus are tri state registers.

(1) ARITHMETIC LOGIC SECTION: This section consists of (a) Accumulation(A)

(b) Temporarily Register (TR) (c) A flag register (FR) (d) An arithmetic logic unit (ALU)

(1) ACCUMULATION (A): It is an 8 bit tri state register accessible to the user. Its tri state output is connected to the internal bus in addition; it has a two state 8 bit output. The content of the accumulator is always available at this two state output as the accumulator can be manipulated through instruction. Its content can be incremented its content can be decremented. Its content can be transferred to memory location. The content of a memory location can be transfers to the accumulator. All these can be done through instructions. The result of an arithmetic operation carried out by ALU shall also be stored back in the accumulator the result of the operation, hence the name accumulator. (2) TEMPORARILY REGISTER (TR): This is an 8 bit register not accessible to the user. It is used by the μp for internal operations. The second operand as and when necessary shall be loaded into this register by the μp before the desired operation takes place in the ALU. The register has 8 bits two state output. This shall be the second operand to the ALU. (3) ARITHMETIC LOGIC UNIT (ALU): ALU is a combination logic block which performs the desired operation on the two operands. One from the A and the other from the TR as the dictate of the control signals. Generated by the timing & control unit. In 8085 μp binary addition operation, binary subtraction operations are the only arithmetic section possible. The result of only arithmetic section possible. The results of the operation shall the stored back in a accumulator when the instruction to be executed is subtraction operation, then the content of the TR shall subtracted from the content of the accumulator and result shall be stored back in the accumulator. (4) FLAG REGISTER: Flag register is a bit register accessible to the user through instruction each bit in the flag register has a specific functions only of the bit are used

The three crossed bits are redundant bits and not used. They can be either ‘0’or ‘1’. It is immaterial but normally forced to be zero. These five bits are affected as a result of execution of an instruction. All instruction execution do not affected the flags e.g. data transferring operation do not affect these flags the arithmetic operation effect all these flags the meaning & the effect of the flags are as follow; CY CARRY FLAG BIT: this particular bit is SET if there is a carry from the MSB position during an addition operation or if there is a borrow during the Subtraction operation, otherwise this flag is RESET. P-PARITY FLAG BIT: The E flag is SET if the result of an operation contains even no’s of 1’s otherwise it is RESET.

AC- AOXILIARY CARRY FLAG BIT: This bit is SET if there is a carry from A 3 bit to A4 bit of the accumulator during the process of executing operation connected with an accumulator otherwise it is RESET. The AE flag is useful for arithmetic & is used in a particular instruction known as DAA (Decimal adjust accumulates). Z-ZERO FLAG: Zero flag bit is SET if the result of an operation is zero, otherwise it is RESET. S-SIGN FLAG: This flag is SET if the MSB of the result is a ‘1’ otherwise it is RESET. As an example, let us consider the execution of the instruction ADDB. ADD is the mnemonic for addition B is the second operand. The first operand is known to exist as the content of the accumulator. The meaning of the instruction is add the content of the B register to the content of A register and store the result back in the accumulator, symbolically, we write the macro RTL complemented.

(A) (A) + (B). Let us suppose the contents of the A& B register are, (A) = 9BH & (B) = A5H.before the execution of the instruction. It means content of (A) & (B) are,

As a result of addition there is a carry from A3 will be A4 position in the example and therefore, AC will be SET. Also there is a carry from the MSB cut & therefore CY flag will also be SET soon after the execution of ADD B instruction the accumulator certain (A) = (0100 0000)2 40 H and is not zero. Therefore the Z flag is RESET to zero. Also the result certain only one ‘1’ an add number. Therefore the parity pit will also be RESET to ‘0’, therefore, the sign flag shall be RESET to ‘0’. Thus the flag register contains soon after the execution instruction are 0001 0001 B = 11H. As a second example, consider another instruction DCR C. DCR is the mnemonic for decrement. C is the operand. This information means decrement the content of the C register by ‘1’ and store it back in the C register, the MACRO RTL implemented is

Let us suppose C contains (C) =D2H before the execution of the instruction after the instruction, C shall contains D1H and therefore in not zero. Therefore the flag register will be affected as follows.

On the other hand, if a contains 01H just before the execution if the instruction, C shall contain 00H. Since the result of the operation is ‘0’ the zero flag shall now be SET to ‘1’. Other flag will be affected in the normal way. These flag bits are utilized in many instructions for branding operations during the execution of a programme normally one of these bits are tested for TRUE or FALSE condition depending upon the condition the programme branches. This is shown in fig

REGISTER SECTION: There are 6-8 bit register designed B, C, D, E, H, & L. all are accessible to the user. In an instruction these six 8bit register along with the accumulator A shall be identified by a 8 bit code designated either SSS or DDD. Whenever SSS is used, it corresponds to service register. Whenever, DDD is used, it corresponds to destination register. The code used as follows,

Note in the above code 110 is not used. Whenever 110 is used for SSS or DDD, it means a specific register pair (H,L), together to from 16 bit register known as memory address register (MAR) or M- pointer. As an example considers the instruction MOV V1, V2 This is an ALP statement, MOV is the mnemonic for move, and V1, v2 are the operand register, in the statement, V2 is the source register and V1 is the destination register. The meaning of the instruction is MOVE the contents of v2 register into V1 register5. Symbolically this basic operation can be described by a basic RTL statement (V1) ---- (V2). This is a single byte instruction. The single byte being the operation code. The arrangement of the op code single byte is shown in fig 19.

The opcode is read is together 0111 1100 B = 7CH. when the instruction7CH is executed content of ‘H’ register shall be transferred to ‘A’ register. Note that content of H register is not destroyed. However, the original content of ‘A’ register is lost. Let us take another example for the use of code 110. Consider the instruction MOV D, M This is an ALP statement, M is the source of the operand and D is the destination register. MOV is the mnemonic for move. The meaning of the instruction is move the content of this memory location whose address is available in (H, L) pair into the D register. This is a single byte instruction.

The operation code is 01010110 B = 56 B

Whenever the instruction 56H is executed content of the memory location whose address is available in (H,L) pair shall be loaded into the D register. The content of the memory location is not destroyed. However, the content of the memory location Y1 Y0 H whose address is X3 X2 X1 X0 H available in (H,L) pair goes into the D register. The original content of D is lost. This is illustrated in fig 20. The six general purpose register B, C, E, H, L can also be combined together as register pairs are possible. (B,C) pair with lower order 8 bits & B higher order 8 bits; (P,E) pair , E lower order 8 bits, D higher order 8 bits, (H,L) pair with Llower order 8 bits & H – higher order 8 bits. There is another register name stock pointer, (S,F) which is 16 bits register itself. Whenever an instruction refers to the register pair (B,C), (D,E), (H,L), or (S,P) a 2 bit code RP is used to identify the register pairs (R stands for the register pairs. (R stands for one bit & P stands for other bit)

2) Briefly explain addressing modes of 8085 with example and instruction size. The various ways of specifying data (or operands) for instructions are called as addressing modes. The 8085 addressing modes are classified into following types: 1. 2. 3. 4. 5.

Immediate addressing mode Direct addressing mode Register addressing mode Register indirect addressing mode Implicit addressing mode

Immediate Addressing mode In this mode operand is a part of the instruction itself is known as Immediate Addressing mode. If the immediate data is 8-bit, the instruction will be of two bytes. If the immediate data is 16 bit, the instruction is of 3 bytes. Ex: (1). ADI DATA ; Add immediate the data to the contents of the accumulator. (2).LXIH 8500H : Load immediate the H-L pair with the operand 8500H (3). MVI 08H ; Move the data 08 H immediately to the accumulator (4). SUI 05H ; Subtract immediately the data 05H from the accumulator (ii) Direct Addressing mode: The mode of addressing in which the 16-bit address of the operand is directly available in the instruction itself is called Direct Addressing mode. i.e., the address of the operand is available in the instruction itself. This is a 3-byte instruction. Ex: (1). LDA 9525H; Load the contents of memory location into Accumulator. (2). STA 8000H; Store the contents of the Accumulator in the location 8000H (3). IN 01H; Read the data from port whose address is 01H. (iii). Register addressing modes: In this mode the operands are microprocessor registers only. i.e. the operation is performed within various registers of the microprocessor. Ex: (1). MOV A, B;

Move the contents of B register to A register.

(2). SUB D;

Subtract the contents of D register from Accumulator.

(3). ADD B, C;

Add the contents of C register to the contents of B register.

(iv). Register indirect addressing modes: The 16-bit address location of the operand stored in a register pair (H-L) is given in the instruction. The address of the operand is given in an indirect way with the help of a register pair. So it is called Register indirect addressing mode. Ex: (1). LXIH 9570H : Load immediate the H-L pair with the address of the location 9570H

MOV A, M accumulator

: Move the contents of the memory location pointed by the H-L pair to

(v). Implicit Addressing mode: The mode of instruction which do not specify the operand in the instruction but it is implicated, is known as implicit addressing mode. i.e., the operand is supposed to be present generally in accumulator. Ex: (1).CMA; complement the contents of Accumulator (2).CMC; Complement carry (3). RLC; Rotate Accumulator left by one bit (4). RRC; Rotate Accumulator right by one bit (5). STC; Set carry. Instruction and data formats: The format of a typical instruction is composed of two parts: an operation code or op-code and an operand. Every instruction needs an opcode to specify the operation of the instruction is and then an operand that gives the appropriate data needed for that particular operation code. Depending upon the size of machine codes, the 8085 instructions are classified into three types. (a) One byte (single) instructions. (b)Two byte instructions. (c) Three byte instructions. One-byte instructions: A 1 byte instruction include the opcode and the operand in the 8 bits only which is one byte. Ex: 1. MOV C, A

Hex code = 4FH (one byte)

2. ADD B Hex code = 80H (one byte) 3. CMA Hex code = 2FH (one byte)

Two-byte instructions: The two byte instruction is one which contains an 8-bit op-code and 8-bit operand (Data). Ex: 1. MVI A, 09

Hex code = 3E, 09 (two bytes)

2. ADD B, 07 Hex code = 80, 07 (two bytes) 3. SUB A, 05 Hex code = 97, 05 (two bytes)

Three-byte instructions: In a three byte instruction the first byte is opcode and second and third bytes are operands i.e. 16-bit data or 16-bit address. 1. LDA 8509 Hex code = 3A, 09, 85 (Three bytes) 2. LXI 2500 Hex code = 21, 00, 25 (Three bytes) 3. STA 2600 Hex code = 32, 00, 26 (Three bytes)

DATA FORMATS: The 8085 is an 8-bit microprocessor which process only on binary numbers. Since t is very difficult to understand these numbers by a common user, So we are using different data formats to code these binary numbers. ASCII, BCD, signed integers and unsigned integers are some of the data formats. The ASCII code is a 7-bit alpha-numeric code that represents decimal numbers, English alphabets and certain special characters. The ASCII stands for “American Standard code for Information Interchange”. The term BCD stands for binary coded decimal, used for the decimal numbers from 0-9. An 8-bit register can store two BCD numbers. A signed integer can be both either negative or positive number. In 8085 microprocessor the most significant bit is used for the sign. Here 0 denotes positive sign and 1 denotes the negative sign. An integer without a sign is represented by all the 8-bits in a microprocessor register. So, the largest number that can be processed at one time is FFH. The numbers larger than 8-bits like 16, 24, 32 bits can be processed by dividing them in groups of 8-bits. 3) Draw and explain the timing diagram for the 8085? Timing Diagram is a graphical representation. It represents the execution time taken by each instruction in a graphical format. The execution time is represented in T-states.

Instruction Cycle The time required to execute an instruction is called instruction cycle.

Machine Cycle The time required to access the memory or input/output devices is called machine cycle.

T-State The machine cycle and instruction cycle takes multiple clock periods.   A portion of an operation carried out in one system clock period is called as T-state.  Machine cycles of 8085 The 8085 microprocessor has 5 (seven) basic machine cycles. They are

1. Opcode fetch cycle (4T) 2. Memory read cycle (3 T) 3. Memory write cycle (3 T) 4. I/O read cycle (3 T) 5. I/O write cycle (3 T)

1.Opcode fetch machine cycle of 8085 : Each instruction of the processor has one byte opcode. The opcodes are stored in memory. So, the processor executes the opcode fetch machine cycle to fetch the opcode from memory. Hence, every instruction starts with opcode fetch machine cycle. The time taken by the processor to execute the opcode fetch cycle is 4T. In this time, the first, 3 T-states are used for fetching the opcode from memory and the remaining T-states are used for internal operations by the processor.

Memory Read Machine Cycle of 8085: The memory read machine cycle is executed by the processor to read a data byte from memory. The processor takes 3T states to execute this cycle. The instructions which have more than one byte word size will use the machine cycle after the opcode fetch machine cycle.

Memory Write Machine Cycle of 8085 The memory write machine cycle is executed by the processor to write a data byte in a memory location. The processor takes, 3T states to execute this machine cycle.

I/O Read Cycle of 8085 The I/O Read cycle is executed by the processor to read a data byte from I/O port or from the peripheral, which is I/O, mapped in the system. The processor takes 3T states to execute this machine cycle. The IN instruction uses this machine cycle during the execution.

Timing diagram for STA 526AH STA means Store Accumulator -The contents of the accumulator is stored in the specified address(526A). The opcode of the STA instruction is said to be 32H. It is fetched from the memory 41FFH(see fig). - OF machine cycle Then the lower order memory address is read(6A). - Memory Read Machine Cycle Read the higher order memory address (52).- Memory Read Machine Cycle The combination of both the addresses are considered and the content from accumulator is written in 526A. - Memory Write Machine Cycle Assume the memory address for the instruction and let the content of accumulator is C7H. So, C7H from accumulator is now stored in 526A.

Timing diagram for INR M Fetching the Opcode 34H from the memory 4105H. (OF cycle) Let the memory address (M) be 4250H. (MR cycle -To read Memory address and data) Let the content of that memory is 12H. Increment the memory content from 12H to 13H. (MW machine cycle)

Timing diagram for MVI B, 43H. Fetching the Opcode 06H from the memory 2000H. (OF machine cycle) Read (move) the data 43H from memory 2001H. (memory read)

4) Discuss in detail the basic concepts in memory interfacing, explain how an address is decoded and how the microprocessor reads from this memory. For interfacing memory devices to microprocessor 8085, following important points are needed. i) Microprocessor 8085 can access 64Kbyes memory since address bus is 16-bit. But it is not always necessary to use full 64Kbytes address space. The total memory size depends upon the application. ii) Generally EPROM (or EPROMs) is used as a program memory and RAM (or RAMs) as a data memory. When both, EPROM and Ram are used, the total address space 64Kbytes is shared by them. iii) the capacity of program memory and data memory depends on application. iv) It is not always necessary to select 1 EPROM and 1 RAM. We can have multiple ERPOMs and multiple RAMs as per the requirement of applications. v) we can place EPROM/RAM anywhere in full 64 Kbytes address space. But program memory (EPROM) should be located from address 000H since reset address of 8085 microprocessor is 0000H. vi) it is not always necessary to locate EPROM and RAM in consecutive memory addresses. The memory interfacing requires to : Select the chip Identify the register Enable the appropriate buffer. Microprocessor system includes memory devices and I/O devices. It is important to note that microprocessor can communicate (read/write) with only one device at a time, since the data, address and control buses are common for all the devices. In order to communicate with memory or I/O devices, it is necessary to decode the address from the microprocessor. Due to this each device (memory or I/O) can be accessed independently. The following section describes common address decoding techniques. Address Decoding Techniques: Absolute decoding/ full decoding Linear decoding/ Partial Decoding. Absolute decoding: In absolute decoding technique, all the higher address lines are decoded to select the memory chip, and the memory chip is selected only for the specified logic levels on these high-order

address lines; no other logic levels can select the chip. Fig shows the memory interface with absolute decoding. This addressing technique is normally used in large memory systems.

Linear decoding In small systems, hardware for the decoding logic can be eliminated by using individual highorder address lines to select memory chips. This is referred to as linear decoding. Fig shows the addressing of RAM with linear decoding technique. This technique is also called partial decoding. It reduces the cost of decoding circuit, but it has a drawback of multiple addresses.

The above fig shows the addressing of RAM with linear decoding technique. A15 address line, is directly connected to the chip select signal of EPROM and after inversion it is connected to the chip select signal of the RAM. Therefore, when the status of A15 line is connected to the chip select signal of the RAM. Therefore, when the status of A15 line is ‘zero’, EPROM gets selected and when the status of A15 line is ‘one’ RAM gets selected. The status of the other address lines is not considered, since those address lines are not used for generation of chips select signals

5) How will you interface multiple devices to the 8085 processor using DMA

data transfer? Explain the HOLD and HALTstate in detail.

6) Draw and explain the functional blocks of 8255 PPI. Data Bus Buffer This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status informa-tion are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups.

(CS) Chip Select. A "low" on this input pin enables the communcation between the 8255 and the CPU. (RD) Read. A "low" on this input pin enables 8255 to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to "read from" the 8255. (WR) Write. A "low" on this input pin enables the CPU to write data or control words into the 8255. (A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. They are normally connected to the least significant bits of the address bus (A0 and A1). (RESET) Reset. A "high" on this input initializes the control register to 9Bh and all ports (A, B, C) are set to the input mode.

Group A and Group B Controls The functional configuration of each port is programmed by the systems software. In essence, the CPU "outputs" a control word to the 8255. The control word contains information such as "mode", "bit set", "bit reset", etc., that initializes the functional configuration of the 8255. Each of the Control blocks (Group A and Group B) accepts "commands" from the Read/Write Control logic, receives "control words" from the internal data bus and issues the proper commands to its associated ports.

Ports A, B, and C The 8255 contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or "personality" to further enhance the power and flexibility of the 8255. Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both "pull-up" and "pull-down" bus-hold devices are present on Port A. Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer. Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B.

7) With the help of a programmable interval timer ( 8253) how will design a real time clock, detect power failure and detect the presence of objects?

Detecting power failure

8) How to interface a keyboard with 8085 using 8255? Write an 8085 program to check for a key closure debounces the key and places the reading in the accumulator.

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In most keyboards, the key switches are connected in a matrix of Rows and Columns.

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Getting meaningful data from a keyboard requires three major tasks: 1. Detect a keypress 2. Debounce the keypress. 3. Encode the keypress (produce a standard code for the pressed key). 4. A logic ‘0’ is read by the microprocessor when the key is pressed. 5. Key Debounce:  Whenever a mechanical push-bottom is pressed or released once, the mechanical components of the key do not change the position smoothly, rather it generates a transient response. These may be interpreted as the multiple pressures and responded accordingly.

• The rows of the matrix are connected to four output Port lines, & columns are connected to four input Port lines. •

When no keys are pressed, the column lines are held high by the pull-up resistors connected to +5v.

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Pressing a key connects a row & a column.

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To detect if any key is pressed is to output 0’s to all rows & then check columns to see it a pressed key has connected a low (zero) to a column.

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Once the columns are found to be all high, the program enters another loop, which waits until a low appears on one of the columns i.e indicating a key press.

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A simple 20/10 msec delay is executed to debounce task.

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After the debounce time, another check is made to see if the key is still pressed. If the columns are now all high, then no key is pressed & the initial detection was caused by a noise pulse.

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To avoid this problem, two schemes are suggested:

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Use of Bistable multivibrator at the output of the key to debounce it.

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The microprocessor has to wait for the transient period (at least for 10 ms), so that the transient response settles down and reaches a steady state.

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If any of the columns are low now, then the assumption is made that it was a valid keypress.

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The final task is to determin the row & column of the pressed key & convert this information to Hex-code for the pressed key.

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The 4-bit code from I/P port & the 4-bit code from O/P port (row & column) are converted to Hex-code.

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interface a 4x4 keyboard with 8086 using 8255 and write an ALP for detecting a key closure and return the key code in AL. The debouncing period for a key is 10ms. Use software key debouncing techniqe. DEBOUNCE is an available 10ms delay routine.

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Port-A .. Output .... for selecting a row of keys

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Port-B .. Input …. For sensing a closed key.

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Port address:

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Port-A

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Port-B 8002h

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CWR 8006h

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Construct the control word

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CWR = 1 0 0 0 0 0 1 0B = 82h

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8000h

;ALP for key board interface

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code segment

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assume cs:code

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start: mov al,82h

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mov dx,8006h

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out dx,al

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mov bl,00h

;for key code

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xor ax,ax

;clear flags

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mov dx,8000h ;port-A address

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out dx,al

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add dx,02

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wait: in al,dx

;port-b address ; read columns

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and al,0fh

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cmp al,0fh

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jz wait

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call DEBOUNCE

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;wait 10ms

mov al,7fh

• •

;mask data lines D7-D4

nextrow:

mov bh,04h

;set row counter

rol al,01

;to ground next row

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mov ch,al

;save rotated data

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sub dx,02

;port-A address

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out dx,al

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add dx,02

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in al,dx

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and al,0fh

;mask D7-D4

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mov cl,04

;set column counter

ror al,01

;move D0 in CF

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nextcol:

;port-B address to get keypress

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jnc codekey ;key closure is found if CF=0

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inc bl

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dec cl

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jnz nextcol

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mov al,ch

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dec bh

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jnz nextrow

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jmp wait

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;for get next key code

codekey: mov al,bl

;move key code to al

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mov ah,4ch

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int 21h

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DEBOUNCE PROC NEAR

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mov cl,0e2h back: nop

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dec cl

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jnz back

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ret

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;return to DOS prompt

DEBOUNCE endp

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code ends

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end start

9) With a schematic diagram and flow chat explain a typical automotive application based on 8085 microprocessor.