Redefining a New-Formed Average Model for ThreePhase Boost Rectifiers/Voltage Source Inverters Runxin Wang, Student Member, IEEE, Jinjun Liu, Member, IEEE School of Electrical Engineering, Xi'an Jiaotong University, Xi'an 710049, CHINA E-mail: [email protected] Abstract-1 Average model of three-phase PWM converters is important in both theory and practical engineering. To remedy defects possessed by the existing average models of three-phase boost rectifiers and voltage source inverters (VSI), this paper proposes and derives another new-formed models that are easyto-use and more suitable for computer simulation. During establishing switching models, the number of independent state variables as well as independent state equations are definitely determined to avoid redundant equations when dealing with circuits that contain cut set purely consisting of inductors or voltage loop purely consisting of capacitors; during deriving average models, redundant variables are properly introduced and added into models, which makes the models easy to be understood and easy to be used. Inductor currents are taken directly as state variables. No extra assumptions are made except relying only on KCL and KVL. Requirements to three-phase ac voltages are effectively removed; therefore the models are suitable for any input/output voltage waveforms, regardless whether they are sinusoidal or non-sinusoidal, balanced or unbalanced, symmetrical or asymmetrical. Simulation examples are provided to verify the models’ validity. Index Terms- ac-dc, dc-ac, power converters, power supply circuits, circuit simulation, simulation model

I.

INTRODUCTION

Average model of the three-phase boost rectifier/voltage source inverter (VSI) is important in both theory and practical engineering. In theory, it provides a measure to analyze and predict the converter’s large-signal behaviors, based on which small-signal researches in dq0 coordinate can also be carried out under sinusoidal situations. In computer simulation engineering practice, sometimes the model is directly used to replace the switching circuits in simulation environments to make the simulation run faster, which is effective especially for those with large circuit scales. The concept of the three-phase average model is not a new one and development of models can be traced back to at least more than ten years ago. As examples, two rectifier models, which can be found in literature [1, 2] and [3] respectively, are listed in Fig. 1 and Fig. 2. They are widely spread in and accepted by research and engineering areas. However, among these models, including those for inverters that are not listed, there exist exact the following or similar deficiencies:

1.

2.

3.

Each of them is valid for only the specific topology under study and not the general one that have a canonical form so to be suitable for both Y- and △-connected ac sources; The model in Fig. 2 takes the phase-currents flowing through the △ -connected ac sources rather than the inductor currents directly as the state variables. This made the results seem not intuitive; Both models adopted a balance assumption among input variables or even variables to be solved during deriving, i.e. e1 + e2 + e3 = 0 in Fig. 1 and iab + ibc + ica = 0 in

Fig. 2, which potentially limited their application ranges or even brought confusions. To remedy above defects, this paper aims to redefine another new-formed general average models for both the boost rectifier and VSI, under the following conditions or meeting the following requirements: 1. Keeping inductor branches stay in the model and taking the inductor currents as the state variables when dealing with the inductor cut set; 2. Discarding any extra assumptions among variables to be solved, only relying on KCL and KVL; 3. Removing any assumptions to ac source/load voltages, that is, requiring the models be suitable for any input/output voltage waveforms, regardless whether they are sinusoidal or non-sinusoidal, balanced or unbalanced, symmetrical or asymmetrical; 4. Clearly showing how to deal with circuits containing cut set purely consisting of inductors or voltage loop purely consisting of capacitors.

d i1 1 3 ⎛ ⎞ = − R L i1 − ⎜ d 1 − ∑ d k ⎟ v d + e1 dt 3 k =1 ⎝ ⎠ d i2 1 3 ⎛ ⎞ L = − R L i2 − ⎜ d 2 − ∑ d k ⎟ v d + e 2 3 k =1 dt ⎝ ⎠ di 1 3 ⎛ ⎞ L 3 = − R L i3 − ⎜ d 3 − ∑ d k ⎟ v d + e 3 dt 3 k =1 ⎝ ⎠ L

C

This work was supported by the National Nature Science Foundation of China (NSFC) under Grant Number 50677053.

978-1-422-2812-0/09/$25.00 ©2009 IEEE

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dvd 1 1 vd + eL = d 1 i1 + d 2 i 2 + d 3 i3 − dt Ro Ro

Figure 1 The derived model in literature [1, 2] for boost rectifiers with Y-connected ac sources[1, 2].

makes that there can only exist two independent voltages among the three line-to-line ones. Therefore, without losing generality, if regarding terminal of line C as the common point and taking vAC and vBC as the independent voltages, the ac sources can be equated by the Yconnected sources shown in Fig. 4.

iab + ibc + ica = 0

⎡ iab ⎤ ⎡ vAB ⎤ ⎡ d ab ⎤ d ⎢ ⎥ 1 ⎢ ⎥ 1 ⎢ ⎥ i = v − dbc vdc bc BC dt ⎢ ⎥ 3L ⎢ ⎥ 3L ⎢ ⎥ ⎢⎣ ica ⎥⎦ ⎢⎣ vCA ⎥⎦ ⎢⎣ d ca ⎥⎦ ⎡ iab ⎤ dvdc 1 ⎢ ⎥ 1 = [ d ab dbc d ca ] ⎢ ibc ⎥ − vdc dt C RC ⎢⎣ ica ⎥⎦

B. Switches In both rectifier and VSI, the three phase-legs in the switch network appear to the inductor cut set as △-connected timevariant controlled voltage sources, of which the line-to-line voltages are governed by

⎡ vab ⎤ ⎡ 1 −1 0 ⎤ ⎡ sa ⎤ ⎡ sab ⎤ ⎢ v ⎥ = ⎢ 0 1 −1⎥ ⎢ s ⎥ v = ⎢ s ⎥ v . ⎢ bc ⎥ ⎢ ⎥ ⎢ b ⎥ dc ⎢ bc ⎥ dc ⎢⎣ vca ⎥⎦ ⎢⎣ −1 0 1 ⎥⎦ ⎢⎣ sc ⎥⎦ ⎢⎣ sca ⎥⎦

Figure 2 The derived model in literature [3] for boost rectifiers with △-connected ac sources[3].

The rest of this paper is organized as follows. Section 2 and 3 derive the model for boost rectifiers. Section 4 and 5 derive the model for VSI. Section 6 verifies the models by simulation results. Section 7 discusses the proposed model’s compatibility with existing models. Conclusion remarks are given in section 8. II. BOOST RECTIFIER SWITCHING MODEL Fig. 3 shows boost rectifiers with Y- or △-connected ac sources. Four parts are labeled according to their functions. The following will discuss constraints introduced by each part and present the boost rectifiers’ switching model. vA

iA

vB iB

A

iA

B

iB

LA

R LA

LB

R LB

vC

iA

v AB

C

iB

vCA

In Eq. (2), vdc is the dc side load voltage for rectifier or the dc source voltage in VSI; si (i=a, b, c) is the switching function of each phase-leg; sjk= sj-sk (j, k=a, b, c) is the phase-to-phase switching function. Considering KVL relations expressed equivalently by the following two equations: sab + sbc + sca ≡ 0 (3)

vab + vbc + vca ≡ 0 ,

LC

iC

(4)

the phase-legs’ effect to the inductor cut set can be equated by only two line-to-line voltages, i.e. sacvdc and sbcvdc. These two controlled voltages constitute the Y-connected sources shown in Fig. 5. sac vdc

a

iC

(2)

v dc

b

C

a

iA

iA

Ro

sab vdc

c

R LC

a

b

vBC

iB

sbc vdc sca vdc

b iB

iC

sbc vdc

Figure 3 Three-phase three-wire PWM boost rectifier.

A. AC Sources For the external circuits outside of three-phase ac sources, there exist the following relations between any different ac source connection modes: On one hand, in accordance with substitution theorem, any source connection modes can substitute each other if they can provide exact the same line-to-line voltages. On the other hand, the KVL relation vAB + vBC + vCA ≡ 0 (1) vA

iA

A

vB iB B

vC

iC C iA

A

iB

B

iC

C

vBC

iA

iB

iC

v AB

vCA

vAC

A

B

C

c

c

iC

C. Inductor Current Equations The KCL relation among the inductor currents makes iA + iB + iC ≡ 0 .

(5)

Hence two equations with two independent variables are enough to solve out all the three currents. By applying equivalent circuits in Fig. 4 and Fig. 5 to the inductor cut set, as shown in Fig. 6, and selecting iA, iB as the independent current variables, the voltage equations along loop AacCA and BbcCB respectively can be written as ⎡ diA ⎤ LC ⎤ ⎢ dt ⎥ ⎡ LA + LC ⎢ ⎥ ⎢ L LB + LC ⎥⎦ ⎢ diB ⎥ C ⎣ . (6) ⎣⎢ dt ⎦⎥

⎡ RL + RLC = −⎢ A ⎣⎢ RLC

vBC

Figure 4 Equivalent circuit of 3-phase ac sources in boost rectifier.

978-1-422-2812-0/09/$25.00 ©2009 IEEE

iC

Figure 5 Equivalent circuit of three-phase bridge–legs in boost rectifier.

1681

⎤ ⎡iA ⎤ ⎡v AC ⎤ ⎡ sac ⎤ vdc + − ⎥ RLB + RLC ⎦⎥ ⎣⎢iB ⎦⎥ ⎣⎢ vBC ⎦⎥ ⎣⎢ sbc ⎦⎥ RLC

If three inductor branches have exactly same parameters, i.e. existing LA = LB = LC = L and RLA = RLB = RLC = RL , Eq. (6) can be simplified to

⎡ diA ⎤ ⎢ dt ⎥ 1 ⎡iA ⎤ 1 ⎡ 2 −1⎤ ⎡v AC ⎤ ⎢ ⎥ = − RL ⎢ ⎥ + L ⎣iB ⎦ 3L ⎢⎣ −1 2 ⎥⎦ ⎣⎢ vBC ⎦⎥ . ⎢ diB ⎥ ⎢⎣ dt ⎥⎦ 1 ⎡ 2 −1⎤ ⎡ sac ⎤ vdc − 3L ⎢⎣ −1 2 ⎥⎦ ⎢⎣ sbc ⎥⎦ vAC A

iA

B

iB

vBC

C

LA

R LA

LB

R LB

LC

iC

R LC

a

1 1 vZ = − v AC − vBC , 3 3 1 1 d Z = − d ac − dbc 3 3 which satisfy the following equations

vX + vY + vZ = 0 d X + dY + d Z = 0

(7)

sac vdc

sbc vdc b

dvdc 1 = [da dt C

c

sb

⎡ iA ⎤ ⎢ ⎥ 1 d c ] ⎢ iB ⎥ − vdc RC ⎢⎣ iC ⎥⎦

db

iA

(8)

N

III. BOOST RECTIFIER AVERAGE MODEL With Eq. (5) and the obvious relations among switching functions, Eq. (7) and Eq. (8) actually make up a compact but sufficient switching model for boost rectifiers. By averaging each variable in them, a three-order model can be obtained:

⎡ diA ⎤ ⎢ dt ⎥ 1 ⎡ i ⎤ 1 ⎡ 2 −1⎤ ⎡ vAC ⎤ ⎢ ⎥ = − RL ⎢ A ⎥ + ⎢ ⎥ L ⎣ iB ⎦ 3L ⎣⎢ −1 2 ⎦⎥ ⎣ vBC ⎦ ⎢ diB ⎥ ⎢⎣ dt ⎥⎦ , 1 ⎡ 2 −1⎤ ⎡ d ac ⎤ − vdc ⎢ ⎥ ⎢ ⎥ 3L ⎣ −1 2 ⎦ ⎣ dbc ⎦ dvdc 1 = [ da dt C

db

978-1-422-2812-0/09/$25.00 ©2009 IEEE

vZ

L

iB

L

RL

d Y v dc

iC

L

RL

d Z vdc

N'

Figure 7 Inductor current model for boost rectifier.

d b iB

d c iC

v dc

C

Ro

(9) Figure 8 Load voltage model for boost rectifier.

During generating Eq. (13), no assumptions are made except KCL constraint iA + iB + iC ≡ 0 . Moreover, thanks to Eq.

where di (i=a, b, c) are the duty ratios, x is the averaged variable corresponding to x. To make the model seem easy-to-use, define:

In addition, define another two redundant variables

vY

d a iA

⎡ iA ⎤ ⎢ ⎥ 1 d c ] ⎢ iB ⎥ − vdc RC ⎢⎣ iC ⎥⎦

⎡ vX ⎤ 1 ⎡ 2 −1⎤ ⎡ v AC ⎤ ⎢ v ⎥ = 3 ⎢ −1 2 ⎥ ⎢ v ⎥ ⎣ ⎦ ⎣ BC ⎦ ; ⎣ Y⎦ ⎡ d X ⎤ 1 ⎡ 2 −1⎤ ⎡ d ac ⎤ ⎢ d ⎥ = 3 ⎢ −1 2 ⎥ ⎢ d ⎥ ⎣ ⎦ ⎣ bc ⎦ ⎣ Y⎦

(12)

of which the corresponding circuit model is illustrated in Fig. 7 and Fig. 8. This circuit model remains to be a three-order system although it seems having four dynamic components. vX d X vdc R L

D. Load Voltage Equations The load voltage equation can be easily written as

⎡iA ⎤ 1 sc ] ⎢⎢iB ⎥⎥ − vdc . R ⎢⎣iC ⎥⎦

.

Substituting input/control variables in Eq. (9) by Eq. (10) and adding a new redundant equation, Eq. (9) becomes: ⎡ diA ⎤ ⎢ dt ⎥ ⎡ iA ⎤ ⎢ ⎥ ⎡v X ⎤ ⎡d X ⎤ ⎢ diB ⎥ = − 1 R ⎢ i ⎥ + 1 ⎢ v ⎥ − 1 ⎢ d ⎥ v L B Y Y dc ⎢ dt ⎥ L ⎢ ⎥ L⎢ ⎥ L⎢ ⎥ , (13) ⎢⎣ iC ⎦⎥ ⎢ ⎥ ⎢⎣ vZ ⎥⎦ ⎢⎣ d Z ⎥⎦ ⎢ diC ⎥ ⎢⎣ dt ⎥⎦

Figure 6 Circuit for solving inductor currents in boost rectifier.

dv C dc = [ sa dt

(11)

(10)

(12), the system in Fig. 7 is natively balanced, regardless whether the original input/control signals are balanced or not. Due to that the current following through the “neutral line” in Fig. 7 is always zero, this line can be safely removed. Even after having done so, there should be no voltage differences between node N and N’ at any time, i.e. vN ' N = v N ' − v N ≡ 0 . (14) IV. VSI SWITCHING MODEL Parallel with section 2, this section will present the switching model for VSI, circuit of which is shown in Fig. 9.

1682

iA

A

LA

iA

R LA

CA

iB

B

A

LB

iB

b

R LB

iC

C

LC

iC

R LC

RC CC

B iA

A

c

⎡ diA ⎤ ⎢ dt ⎥ ⎡iA ⎤ 1 ⎡ 2 −1⎤ ⎡ sac ⎤ 1 vdc ⎢ ⎥ = − RL ⎢ ⎥ + L ⎣iB ⎦ 3L ⎢⎣ −1 2 ⎥⎦ ⎢⎣ sbc ⎥⎦ . ⎢ diB ⎥ ⎢⎣ dt ⎥⎦ 1 ⎡ 2 −1⎤ ⎡ v AC ⎤ − 3L ⎢⎣ −1 2 ⎥⎦ ⎢⎣ vBC ⎥⎦

RB CB

a Vdc

If the three branches have exactly same parameters as that for deriving Eq. (7), Eq. (15) can be simplified to

RA

C AB

C

RAB C CA

iB

B

C BC

RC A

RBC

iC

C

Figure 9 Three-phase three-wire PWM voltage source inverter (VSI).

A. Switches As having shown in section 2.B, the line-to-line voltages at the switches side in VSI follow Eq. (2). By selecting sacvdc and sbcvdc as independent voltages, the Y-connected equivalent sources can be constituted as shown in Fig.10.

sac vdc

sbc vdc

sac vdc iA

sab vdc iB

scavdc

iB

c iC

b

iC

iC

c

c

Figure 10 Equivalent circuit of three-phase bridge–legs in VSI.

B. Load Network The three-phase load, including filter capacitors, is connected to the inductor cut set directly in VSI. Its effect to the inductors can be represented by the equivalent Y-connected sources as shown in Fig. 11, if still specifying vAC and vBC as the independent voltages, similar to dealing with ac sources in section 2.A.

B

RA

iA

CA

RB

iB

CB

A

C

CC

B

A

RAB

C

CCA

iB C BC

C

vAC

iB

vBC

iA C AB

B

iA

RC

iC

LB

R LB

LC

R LC

vAC A

vBC B

C

D. Load Voltage Equations Modeling load voltage just by considering that in Fig. 9 goes a little too far from practical engineering, because the load is always much more complicated than simple compositions of resistors and capacitors. However, due to the load’s influence to the inductor cut set only depends on the line-to-line voltages excited by currents injected into the load, it is meaningful to do so although the obtained model reflects only the simplest situation. Line-to-line voltages on complex load can be modeled be complex equations or obtained directly by circuit in simulation environments. 1. Y-Connected Load The effect of inductor cut set is identical to that of two independent current sources as shown in Fig. 13. The voltages on three capacitors are mutually independent and they can be represented by the following equations:

iC

RC A

CA

dvA 1 = iA − vA dt RA

CB

dvB 1 = iB − vB . dt RB

CC

dvC 1 = iC − vC dt RC

RBC

iC

Figure 11 Equivalent circuit of the three-phase load network in VSI.

C. Inductor Current Equations By applying the equivalent circuits in Fig. 10 and Fig. 11 to the inductor cut set, as shown in Fig. 12, and selecting iA, iB as two independent current variables, the voltage equations can be written as ⎡ di A ⎤ LC ⎤ ⎢ dt ⎥ ⎡ LA + LC ⎢ ⎥ ⎢ L LB + LC ⎥⎦ ⎢ diB ⎥ . (15) C ⎣ ⎣⎢ dt ⎦⎥ ⎡ RLA + RLC = −⎢ ⎢⎣ RLC

R LA

Figure 12 Circuit for solving inductor currents in VSI. sbc vdc

A

LA

a

sbc vdc b

iB

b iA

a

a iA

(16)

⎤ ⎡ i A ⎤ ⎡ sac ⎤ ⎡ v AC ⎤ ⎥ ⎢ ⎥ + ⎢ ⎥ vdc − ⎢ ⎥ RLB + RLC ⎥⎦ ⎣ iB ⎦ ⎣ sbc ⎦ ⎣ vBC ⎦ RLC

978-1-422-2812-0/09/$25.00 ©2009 IEEE

(17)

Obviously KVL relations exist between capacitor voltages and line-to-line voltage as:

v AC = v A − vC vBC = vB − vC

.

(18)

If the loads in three phases have exactly same parameters, i.e. existing C A = CB = CC = C and RA = RB = RC = R , Eq. (17) can be simplified to

1683

V. VSI AVERAGE MODEL

⎡ dv A ⎤ ⎢ dt ⎥ ⎡ vA ⎤ ⎢ ⎥ ⎡iA ⎤ dvB ⎥ ⎢ ⎥ 1 ⎢ ⎥ . ⎢ C v = i − ⎢ dt ⎥ ⎢ B ⎥ R ⎢ B ⎥ ⎢⎣ vC ⎥⎦ ⎢ ⎥ ⎢⎣iC ⎥⎦ ⎢ dvC ⎥ ⎣⎢ dt ⎦⎥ iA

The average models for VSI are composed of the commonly used inductor current model and the load voltage models respectively for Y-connected load and △-connected load.

(19)

A. Inductor current model Eq. (16) can be averaged to

⎡ diA ⎤ ⎢ dt ⎥ 1 ⎡ i ⎤ 1 ⎡ 2 −1⎤ ⎡ d ac ⎤ vdc ⎢ ⎥ = − RL ⎢ A ⎥ + L ⎣ iB ⎦ 3L ⎢⎣ −1 2 ⎥⎦ ⎢⎣ dbc ⎥⎦ ⎢ diB ⎥ . (22) ⎢⎣ dt ⎥⎦ 1 ⎡ 2 −1⎤ ⎡ v AC ⎤ − 3L ⎢⎣ −1 2 ⎥⎦ ⎢⎣ vBC ⎥⎦

+ vA − A

RA CA

iB

+ vB − B

RB

CB

+ vC C

−

RC CC

Figure 13 Y-connected load in VSI.

2. △-Connected Load The loop purely containing capacitors in △-connected load makes there only exist two independent equations in describing circuit shown in Fig. 14. By selecting vAC and vBC as independent voltages, the following equation can be obtained:

Very similar to that for boost rectifiers, by adopting definitions in Eq. (10)~ (11) as well as defining the redundant current iC, Eq. (22) can be rewritten as

⎡ diA ⎤ ⎢ dt ⎥ ⎡ iA ⎤ ⎢ ⎥ ⎡d X ⎤ ⎡vX ⎤ ⎢ diB ⎥ = − 1 R ⎢ i ⎥ + 1 ⎢ d ⎥ v − 1 ⎢ v ⎥ , L B Y dc Y ⎢ dt ⎥ L ⎢ ⎥ L⎢ ⎥ L⎢ ⎥ ⎢⎣ iC ⎥⎦ ⎢ ⎥ ⎢⎣ d Z ⎥⎦ ⎢⎣ vZ ⎥⎦ ⎢ diC ⎥ ⎢⎣ dt ⎥⎦

(23)

+ + +

_

_

_

+

_

_

+

_

+

⎡ dv AC ⎤ −C AB ⎤ ⎢ dt ⎥ ⎢ ⎥ CBC + C AB ⎥⎦ ⎢ dvBC ⎥ of which the circuit model is shown in Fig. 15. This model ⎢⎣ dt ⎥⎦ . (20) contributes two orders although seems having three dynamic 1 1 ⎡ 1 ⎤ components. It validates for any load connection modes. − ⎢R + R ⎥ ⎡ v ⎤ ⎡i ⎤ R vX CA AB AB d X vdc ⎥ AC + a RL = −⎢ L iA 1 1 1 ⎥ ⎢⎣ vBC ⎥⎦ ⎢⎣ib ⎥⎦ ⎢ + ⎢ −R RBC RAB ⎥⎦ AB ⎣ vY If the loads in three phases have exactly same parameters, i.e. d Y v dc RL L iB N N' existing C AB = CBC = CCA = C and RAB = RBC = RCA = R , Safe! Eq. (20) is simplified to vZ d Z v dc ⎡ dv AC ⎤ RL L −1 iC ⎢ dt ⎥ 1 ⎡ vAC ⎤ 1 ⎡ 2 −1⎤ ⎡ia ⎤ + ⎢ ⎥=− RC ⎣⎢ vBC ⎦⎥ C ⎢⎣ −1 2 ⎥⎦ ⎣⎢ib ⎦⎥ . ⎢ dvBC ⎥ (21) Figure 15 Inductor current model for VSI. ⎢⎣ dt ⎥⎦ B. Y-Connected Load 3 1 ⎡v AC ⎤ 1 ⎡ 2 1 ⎤ ⎡ia ⎤ Averaging Eq. (19) makes =− + R 3C ⎢⎣ vBC ⎥⎦ 3C ⎢⎣1 2 ⎥⎦ ⎢⎣ ib ⎥⎦ ⎡ dv ⎤ ⎡CCA + C AB ⎢ −C ⎣ AB

A

ia

⎢ dt ⎥ ⎡vA ⎤ ⎢ ⎥ ⎡ iA ⎤ dvB ⎥ ⎢ ⎥ 1 ⎢ ⎥ ⎢ C = i − v , ⎢ dt ⎥ ⎢ B ⎥ R ⎢ B ⎥ ⎢⎣vC ⎥⎦ ⎢ ⎥ ⎢⎣ iC ⎥⎦ dv C ⎢ ⎥ ⎢⎣ dt ⎥⎦

A

RAB

CAB

+

B +

v BC

CBC

v AC

RBC

CCA

RCA

_

ib

_

C

Figure 14 △-connected load in VSI.

978-1-422-2812-0/09/$25.00 ©2009 IEEE

(24)

of which the circuit model is shown in Fig. 16. Fig. 15 and Fig. 16 compose of the whole model for VSI with the Y-connected loads. Totally the model has five orders.

1684

A. Inductor Current Model Fig. 18 shows a circuit that emulates a three-phase boost rectifier. Randomly selected disturbance signals without any assumptions are inserted into both the ac source side and the switches network side. The waveforms of line-to-line voltages at two sides of inductor cut set and the current responses are shown in Fig. 19, one by one from the top to the bottom. Fig. 20 shows the proposed model, which takes the four independent voltages measured in Fig. 18 as input signals. The response waveforms of inductor currents shown in Fig. 21 (the lower) are absolutely same to that in Fig. 19. The voltage difference between N’ and N (the upper in Fig. 21) appears to be as low as hundreds of fV (10-15 V), which effectively proves Eq. (14).

+ vA − A

RA CA

iB

+ vB − B

RB

CB

iC

+ vC C

−

RC CC

Figure 16 Load voltage model for Y-connected load in VSI.

C. △-Connected Load Averaging Eq. (21) makes ⎡ dv AC ⎤ ⎢ dt ⎥ 3 1 ⎡v AC ⎤ 1 ⎡ 2 1 ⎤ ⎡ iA ⎤ . + ⎢ ⎥=− ⎢ ⎥ R 3C ⎣⎢ vBC ⎦⎥ 3C ⎢⎣1 2 ⎥⎦ ⎣ iB ⎦ ⎢ dvBC ⎥ ⎣⎢ dt ⎦⎥

(25)

U2 X1

Reforming Eq. (25) slightly and adding a redundant voltage vCA lead to

1m

L1

R9

I_A 1m 1 R1 V_ab

V7

10m

1m

L2

R10

V9

V4

V11

V6

V3

V8

V10

V5

E1

I_B

1m 1 R2

V_BC

(26)

1m R3 E3

V2

V_bc 10m

1m

L3

R11

1

E2

I_C

V_CA

V_ca

Figure 18 Simulation based on the boost rectifier circuit. V_CA V_ca V_bc

By defining the following current:

⎡ iAB ⎤ ⎡ 1 −1⎤ ⎢ ⎥ 1⎢ ⎥ ⎡ iA ⎤ , = i 1 2 BC ⎢ ⎥ 3⎢ ⎥ ⎢i ⎥ ⎢⎣ iCA ⎥⎦ ⎢⎣ −2 −1⎥⎦ ⎣ B ⎦

10m

V_AB

Switches_Network_Voltage / V

⎡ dv AB ⎤ ⎢ dt ⎥ ⎡ v AB ⎤ ⎡ 1 −1⎤ ⎢ ⎥ ⎢ dvBC ⎥ = − 3 1 ⎢ v ⎥ + 1 ⎢ 1 2 ⎥ ⎡ iA ⎤ . BC ⎥ ⎢i ⎥ ⎢ dt ⎥ R 3C ⎢ ⎥ 3C ⎢ ⎢⎣ vCA ⎥⎦ ⎢⎣ −2 −1⎥⎦ ⎣ B ⎦ ⎢ ⎥ ⎢ dvCA ⎥ ⎣⎢ dt ⎦⎥

V1

V_BC V_AB V_ab

I_C I_B I_A

300 200 100 0 -100 -200 -300

Ac_Source_Voltage / V

600

(27)

400 200 0 -200 -400 -600 40

the circuit model can be drawn as that in Fig. 17, in which the circulating current along ABCA can be predicted to be zero, even if linking the loads to form a closed loop as shown. Fig. 15 and Fig. 17 compose of the whole model for VSI with the △-connected loads. The model totally has four orders.

Inductor_Current / A

iA

20 0 -20 -40 10

0

20

30

40

50

time/mSecs

10mSecs/div

Figure 19 Simulation results from Fig. 18.

A

iAB

C

R

iC A

B

iBC

vBC

C

vAC

C

R

R

Figure 20 Simulation based on boost rectifier model. N' I_C I_B

C

I_A

Voltage_N'N / fV

200

Figure 17 Load voltage model for △-connected load in VSI..

100

0

-100

-200

VI. SIMULATION VERIFICATION The methodology in Fig. 7 (or Fig. 15) and Fig. 17 reflects the main ideas of this paper. Using the POP (Periodic Operating Point) analysis[4] tool in SIMPLIS environment, this section will verify these models’ validity.

978-1-422-2812-0/09/$25.00 ©2009 IEEE

1685

Inductor_Current / A

40

20

0

-20

-40

10

0

20

30

40

50

time/mSecs

Figure 21 Simulation results from Fig. 20.

10mSecs/div

10Meg R4

B. Load Voltage Model in VSI Fig. 22 shows a circuit that emulates a three-phase △ connected VSI load. Randomly selected current signals (waveform as shown in the lowest line in Fig. 22) are injected into capacitor networks respectively through the real circuit and through the model. The responding waveforms of line-toline voltages are shown in the second and the third lines in Fig. 23. They are identical to each other. The circulating current shown in the top line appears to be hundreds of nA, which indicates the prediction in section 5.C is correct hence the three phase can be treated individually. U2 X1

I3 I_A I1 V_AB I4

1m C1

10 R1

I_B

1m C3

I2 V_BC

1m C2

10 R3

⎡VX ⎤ ⎡ 2 −1⎤ ⎡V ⎤ ⎢ ⎥ ⎢ (28) 3 ⎢VY ⎥ = ⎢ −1 2 ⎥⎥ ⎢ AC ⎥ .  V ⎢VZ ⎥ ⎣⎢ −1 −1⎥⎦ ⎣ BC ⎦ ⎣ ⎦ If virtually assuming vAC, vBC come from Y-connected sinusoidal sources (vA, vB, vC), the phasor diagram drawn in Fig. 24 shows that vX, vY and vZ comprise a Y-connected threephase system with each phase has a voltage value exactly same to the virtually original one. That is to say, in sinusoidal situations, the effects of sources in XYZ are identical to that of the sources in real circuits. Further derivations indicate that in fact above conclusion applies generally and has nothing to do with the shapes of input signals waveforms. The model can be used in power analysis, and also can be transformed to the dq0 coordinate safely. 3VZ

10 R2

I_C

VCA

V_CA

F1 333.33333m

F2 -333.33333m

F6 -333.33333m

1m C4

VB

10 R4

V_CA_Model

1m C6

F3 333.33333m

3VX

VA

I_Model

V_AB_Model F5 -666.66667m

VAB

VC

VAC

2VAC

VBC

10 R6

2VAC − VBC

3VY 1G R7

V_BC_Model

F4 666.66667m

1m C5

10 R5

2VBC

2VBC − VAC

Figure 24 Phasor diagram. Figure 22 Simulation circuit of △-connected load in VSI.

Load Voltage @ Model / V

Load Voltage @ Ckt / V

Circulating Current / nA

V_CA_Model V_CA V_BC_Model

V_BC V_AB_Model V_AB

I_Model I_C I_B

VIII.

I_A

40 20 0 -20 -40 40 20 0 -20 -40 40

Line Current / A

CONCLUSION

This paper proposes and derives a new-formed average model for three-phase boost rectifiers/voltage source inverters. Being a general model that distinguishes from existing ones mainly by removing constraint requirements to three-phase input/output voltages and intuitively taking inductor currents as state variables, it is hopeful to be easily used in theoretical analysis as well as in simulation environments as that reported in [5]. The proposed model is compatible with existing ones for further researches such as those in dq0 coordinate.

200 150 100 50 0 -50 -100 -150

20 0 -20 -40 0

20

40

60

80

time/mSecs

ACKNOWLEDGMENT

100 20mSecs/div

Figure 23 Simulation results from Fig. 22.

The authors thank SIMPLIS Technologies, Inc. for software support.

VII. COMPATIBILITY WITH EXISTING MODELS Eq. (13) (or Eq. (23)) is widely suitable to be used in solving inductor currents excited by any instantaneous values of source voltages or duty ratios, no matter whether they are sinusoidal, balanced, symmetrical, or not. On the other hand, during the derivations, only the vectors of inductor currents and their derivatives to time are kept unchanged. Therefore, generally speaking, after transforming voltages into XYZ coordinate, further proofs should be provided to make sure other properties deduced from the model, such as the power transferred from the ac side to the dc side, are identical to that in the original circuit. The proofs exist. For example, in sinusoidal situations, the following phasor relations exist:

978-1-422-2812-0/09/$25.00 ©2009 IEEE

REFERENCES [1] [2] [3] [4] [5]

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Rusong Wu, S. B. Dewan and G. R. Slemon, “Analysis of an ac-to-dc voltage source converter using PWM with phase and amplitude control,” IEEE Trans. on Ind. Appl. 1991, 27(2): 355～363. Rusong Wu and G. R. Slemon, “A PWM ac to dc converter with fixed switching frequency,” IEEE Trans. on Ind. Appl. 1990, 5(26): 880～885. Dushan Boroyevich, “Modeling and control of PWM converters,” Power electronics short course presented in Xi’an Jiaotong University, China, Aug. 18-19, 2006. Also seen in teaching materials in CPES. Transim Technology Corporation, “SIMPLIS reference manual,” UK: Cantena Software Ltd, 2008. Runxin Wang and Jinjun Liu, “Modeling current-mode-controlled threephase converters for simulating multiple-module inter-connected power supply systems,” IEEE PESC 2008, Rhodes, Greece, June 15-19, 2008, pp. 1796~1800.