DESIGN OF HD6402 UART IC FOR APPLICATION IN SERIAL COMMUNICATION A DISSERTATION SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE AWARD OF THE DEGREE OF BACHELOR OF ENGINEERING IN ELECTRONICS AND COMMUNICATION TO GUJARAT UNIVERSITY GUIDED BY

PREPARED BY

Asst.Prof. PRAKASH PATEL

Mr.RAVI SHAH

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT L.D.R.P. Institute of Technology & Research, Sector-15, Gandhinagar-382015 MAY-2011

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L.D.R.P. Institute of Technology & Research, Gandhinagar

Certificate This is to certify that the work presented in the dissertation entitled DESIGN OF HD6402 UART IC FOR APPLICATION IN SERIAL COMMUNICATION Has been carried out by Mr. RAVI SHAH ID No.: _____________

Seat No.:_________

Year: MAY 2011

In a manner sufficiently satisfactory to warrant its acceptance as a partial fulfillment of the requirement for the award of the DEGREE OF BACHELOR OF ENGINEERING IN ELECTRONICS AND COMMUNICATION This is a bonafide work done by the student and has not been submitted to any other University/Institute for the award of any other Degree/Diploma

Guided By:

Asst.Prof. PRAKASH PATEL

Head of Department:

Asst.Prof. S.E.MENDHE

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DISSERTATION APPROVAL SHEET The Dissertation entitled DESIGN OF HD6402 UART IC FOR APPLICATION IN SERIAL COMMUNICATION Is submitted by Mr. RAVI SHAH of L.D.R.P. Institute of Technology & Research, Gandhinagar is Approved for the Award of the DEGREE OF BACHELOR OF ENGINEERING IN ELECTRONICS AND COMMUNICATION BY GUJARAT UNIVERSITY INTERNAL EXAMINER(S):

EXTERNAL EXAMINER(S):

Date:

Place:

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ACKNOWLEDGEMENT We forward our dedicated gratitude to The Almighty GOD, who let helped me in everything I did for project and report. This Report is the result of the dedication and encouragement of many individuals.Our sincere & heartful appreciation goes to all of them .Our sincere thanks to Assit.Prof.S.E.MENDHE and Assit.Prof.PAKASH.PATEL of L.D.R.P.--I.T.R, GANDHINAGAR for his helpful suggestions on the organization of project on “DESIGN OF HD6402 UART IC FOR APPLICATION IN SERIAL COMMUNICATION”.His valuable advice and time that they gave me could not be expressed by any means of literature. They went as far as they could to help me, only to make my efforts as successful and enjoyable it can out to be. I would also like to thank the staff of E.C. department to permit me to use lab facilities whenever I needed. We enjoyed in preparing this project and hope you enjoy reading it.  Ravi Shah

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ABSTRACT A universal asynchronous receiver/transmitter, abbreviated UART, is a type of "asynchronous receiver/transmitter", a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in conjunction with communication standards such as EIA RS 232, RS-422 or RS-485. The universal designation indicates that the data format and transmission speeds are configurable and that the actual electric signaling levels and methods(such as differential signaling , etc.) typically are handled by a special driver circuit external to the UART. UART is usually an individual (or part of an) integrated circuit used for serial communications over a computer or peripheral device serial port. UARTs are now commonly included in microcontrollers. A dual UART, or DUART, combines two UARTs into a single chip. Coding using VHDL : The key advantage of VHDL when used for systems design is that it allows the behaviour of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires). To start coding in VHDL, one needs a simulation tool. The simulation tool that we have used here is Xilinx ISI9.2i.First the required code for HD 6402 UART circuit was written in VHDL and simulated so as to obtain the required output waveforms. Burning the code on Spartan kit : After the coding was completed, VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device. The programmable logic device used here is FPGA Spartan kit. Experimental work : The above coding and burning methods were completed and the output was observed on FPGA kit. The HD 6402 UART code was implemented using VHDL while burning was done using Spartan kit.

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TABLE OF CONTENT LIST OF FIGURE CHAPTER 1 INTRODUCTION 1.1 The UART: What it is and how it works? 1.2 Serial versus parallel 1.3 Synchronous Serial Transmission 1.4 Asynchronous Serial Transmission 1.5 Bits, Baud and Symbols 1.6 Asynchronous Serial Reception 1.7 Other UART Functions CHAPTER 2 HISTORY OF UART & VHDL 2.1 History of UART 2.2 History of VHDL CHAPTER 3 THEORY 3.1 UART PROTOCOL 3.2 Basic VHDL theory CHAPTER 4 IMPLEMENTATION FLOW OF HD 6402 UART IC CHAPTER 5 XILINX ISE SIMULATOR CHAPTER 6 VHDL PROGRAM RESULTS CHAPTER 7 CONCLUSION CHAPTER 8 BIBLIOGRAPHY APPENDIX SOURCE CODE FOR UART SOURCE CODE FOR TEST BENCH OF UART

IV 01 01 02 03 03 03 04 05 06 06 06 08 08 10 14 23 40 42 43 44 56

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LIST OF FIGURE Figure 1.1 Serial data transmission 01 Figure 1.2 Asynchronous serial transmission 03 Figure 1.3 Shows this multiplexing format & Asynchronous Code Format 04 Figure 3.1 Character frame of UART 08 Figure 3.2 BLOCK DIAGRAM OF HD 6402 UART 10 Figure 3.3 Example of (a) structural description (b) behaviour description 11 Figure 3.4 Structure of count2 13 Figure 4.1 TRANSMITTER TIMING (NOT TO SCALE) 16 Figure 4.2 Pin diagram of HD 6402 UART IC 16 Figure 4.3 Functional diagram & Control definition 17 Figure 4.4 PIN Description in detail 18 Figure 4.5 RECEIVER TIMING (NOT TO SCALE) 20 Figure 4.6 SERIAL DATA FORMAT 20 Figure 4.7 Start Bit Detection 20 Figure 4.8 Signal detail used in CODE 21 Figure 4.9 TYPICAL SERIAL DATA LINK 22 Figure 4.10 Electrical specification and switching waveform of data input cycle , control register load cycle , status flag output enable timer or data output enable time. 22 Figure 5.1 ISE Help Topics 23 Figure 5.2 Project Device Properties 24 Figure 5.3 Define Module 25 Figure 5.4 New Project In Ise 26 Figure 5.5 Initialize Timing 30 Figure 5.6 Test Bench Waveform 31 Figure 5.7 Behavior Simulation Selection 31 Figure 5.8 Simulation Results 32 Figure 5.9 Prompt To Add Ucf File To Project 32 Figure 5.10 Clock Period 33 Figure 5.11 Pad To Setup 33 Figure 5.12 Clock To Pad 34 Figure 5.13 Timing Constraints 34 Figure 5.14 Post Implementation Design Summary 35 Figure 5.15 All Constraints Met Report 35 Figure 5.16 Package Pin Locations 36 Figure 5.17 Package Pin Locations Prior To Pin Location Constraints 37 Figure 5.18 Package Pin Locations After Pin Location Constraints 37 Figure 5.19 Impact Welcome Dialog Box 38 Figure 5.20 Assign New Configuration File 39

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CHAPTER 1 INTRODUCTION 1.1 The UART: What it is and how it works? A UART (Universal Asynchronous Receiver/Transmitter) is the microchip with programming that controls a computer's interface to its attached serial devices.Specifically, it provides the computer with the RS-232C Data Terminal Equipment(DTE) interface so that it can "talk" to and exchange data with modems and other serial devices. As part of this interface, the UART also: • Converts the bytes it receives from the computer along parallel circuits into a single serial bit stream for outbound transmission • On inbound transmission, converts the serial bit stream into the bytes that the computer handles • Adds a parity bit (if it's been selected) on outbound transmissions and checks the parity of incoming bytes (if selected) and discards the parity bit • Adds start and stop delineators on outbound and strips them from inbound transmissions • Handles interrupts from the keyboard and mouse (which are serial devices with special ports) • May handle other kinds of interrupt and device management that require coordinating the computer's speed of operation with device speeds . Serial transmission is commonly used with modems and for non-networked communication between computers, terminals and other devices.

Figure 1.1 serial data transmission The communications links across which computers—or parts of computers—talk to one another may be either serial or parallel. A parallel link transmits several streams of data (perhaps representing particular bits of a stream of bytes) along multiple channels (wires,printed circuit tracks, optical fibres, etc.); a serial link transmits a single stream of data. At first sight it would seem that a serial link must be inferior to a parallel one, because it can transmit less data on each clock tick. However, it is often the case that serial links can be clocked considerably faster than parallel links, and achieve a higher data rate. A number of factors allow serial to be clocked at a greater rate: • Clock skew between different channels is not an issue (for unclocked serial links) • A serial connection requires fewer interconnecting cables (e.g. wires/fibres) and hence occupies less space. The extra space allows for better isolation of the channel from its surroundings • Crosstalk is less of an issue, because there are fewer conductors in proximity. Page 8

In many cases, serial is a better option because it is cheaper to implement. Many ICs have serial interfaces, as opposed to parallel ones, so that they have fewer pins and are therefore cheaper. In telecommunications and computer science, serial communications is the process of sending data one bit at one time, sequentially, over a communications channel or computer bus. This is in contrast to parallel communications, where all the bits of each symbol are sent together. Serial communications is used for all long-haul communications and most computer networks, where the cost of cable and synchronization difficulties make parallel communications impractical. Serial computer buses are becoming more common as improved technology enables them to transfer data at higher speeds. 1.2 Serial versus parallel The Serial Port is harder to interface than the Parallel Port. In most cases, any device you connect to the serial port will need the serial transmission converted back to parallel so that it can be used. This can be done using a UART. On the software side of things, there are many more registers that you have to attend to than on a Standard Parallel Port. (SPP) So what are the advantages of using serial data transfer rather than parallel? 1. Serial Cables can be longer than Parallel cables. The serial port transmits a '1' as -3 to 25 volts and a '0' as +3 to +25 volts where as a parallel port transmits a '0' as 0v and a '1' as 5v. Therefore the serial port can have a maximum swing of 50V compared to the parallel port which has a maximum swing of 5 Volts. Therefore cable loss is not going to be as much of a problem for serial cables than they are for parallel. 2. You don't need as many wires than parallel transmission. If your device needs to be mounted a far distance away from the computer then 3 core cable (Null Modem Configuration) is going to be a lot cheaper that running 19 or 25 core cable. However you must take into account the cost of the interfacing at each end. 3. Infra Red devices have proven quite popular recently. You may of seen many electronic diaries and palmtop computers which have infra red capabilities build in.However could you imagine transmitting 8 bits of data at the one time across the room and being able to (from the devices point of view) decipher which bits are which? Therefore serial transmission is used where one bit is sent at a time. IrDA-1 (The first infra red specifications) was capable of 115.2k baud and was interfaced into a UART.The pulse length however was cut down to 3/16th of a RS232 bit length to conserve power considering these devices are mainly used on diaries, laptops and palmtops. Microcontrollers have also proven to be quite popular recently. Many of these have in built SCI (Serial Communications Interfaces) which can be used to talk to the outside world. Serial Communication reduces the pin count of these MPU's. Only two pins are commonly used, Transmit Data (TXD) and Receive Data (RXD) compared with at least 8 pins if you use a 8 bit Parallel method (You may also require a Strobe). There are two primary forms of serial transmission: Synchronous and Asynchronous.Depending on the modes that are supported by the hardware, the name of the communication sub-system will usually include a A if it supports Asynchronous communications, and a S if it supports Synchronous communications. Both forms are described below. Page 9

1.3 Synchronous Serial Transmission Synchronous serial transmission requires that the sender and receiver share a clock with one another, or that the sender provide a strobe or other timing signal so that the receiver knows when to “read” the next bit of the data. In most forms of serial Synchronous communication, if there is no data available at a given instant to transmit, a fill character must be sent instead so that data is always being transmitted. Synchronous communication is usually more efficient because only data bits are transmitted between sender and receiver, and synchronous communication can be more costly if extra wiring and circuits are required to share a clock signal between the sender and receiver.A form of Synchronous transmission is used with printers and fixed disk devices in that the data is sent on one set of wires while a clock or strobe is sent on a different wire. Printers and fixed disk devices are not normally serial devices because most fixed disk interface standards send an entire word of data for each clock or strobe signal by using a separate wire for each bit of the word. In the PC industry, these are known as Parallel devices.The standard serial communications hardware in the PC does not support Synchronous operations. This mode is described here for comparison purposes only. 1.4 Asynchronous Serial Transmission Asynchronous serial communication describes an asynchronous transmission protocol in which a start signal is sent prior to each byte, character or code word and a stop signal is sent after each code word. The start signal serves to prepare the receiving mechanism for the reception and registration of a symbol and the stop signal serves to bring the receiving mechanism to rest in preparation for the reception of the next symbol. A common kind of start-stop transmission is ASCII over RS-232, for example for use in teletypewriter operation.

Figure 1.2 Asynchronous serial transmission In the diagram, a start bit is sent, followed by eight data bits, no parity bit and one stop bit, for a 10-bit character frame. The number of data and formatting bits, and the transmission speed, must be pre-agreed by the communicating parties.After the stop bit, the line may remain idle indefinitely, or another character may immediately be started. 1.5 Bits, Baud and Symbols Baud is a measurement of transmission speed in asynchronous communication. Because of advances in modem communication technology, this term is frequently misused when describing the data rates in newer devices. Traditionally , a Baud Rate represents the number of bits that are actually being sent over the media, not the amount of data that is actually moved from one DTE device to the other. The Baud count includes the overhead bits Start, Stop and Parity that are generated by the sending UART and removed by the receiving UART. This means that seven-bit words of data actually take 10 bits to be completely transmitted. Therefore, a modem capable of moving 300 bits per second from one place to another can normally only move 30 7-bit words if Parity is used and one Start and Stop bit are present. If 8-bit data words are used and Parity bits are also used, the data rate falls to 27.27 words per second, because it now takes 11 bits to send the eight-bit words, and the modem still only sends 300 bits per second. The formula for converting bytes per second into a baud rate and vice versa was simple until error correcting modems came along. These modems receive the serial stream of bits Page 10

from the UART in the host computer (even when internal modems are used the data is still frequently serialized) and converts the bits back into bytes. These bytes are then combined into packets and sent over the phone line using a Synchronous transmission method.This means that the Stop, Start, and Parity bits added by the UART in the DTE (the computer) were removed by the modem before transmission by the sending modem.When these bytes are received by the remote modem, the remote modem adds Start, Stop and Parity bits to the words, converts them to a serial format and then sends hem to the receiving UART in the remote computer, who then strips the Start, Stop and Parity bits.The reason all these extra conversions are done is so that the two modems can perform error correction, which means that the receiving modem is able to ask the sending modem to resend a block of data that was not received with the correct checksum. This checking is handled by the modems, and the DTE devices are usually unaware that the process is occurring. By striping the Start, Stop and Parity bits, the additional bits of data that the two modems must share between themselves to perform error-correction are mostly concealed from the effective transmission rate seen by the sending and receiving DTEequipment. For example, if a modem sends ten 7-bit words to another modem without including the Start, Stop and Parity bits, the sending modem will be able to add 30 bits of its own information that the receiving modem can use to do error-correction without impacting the transmission speed of the real data. The use of the term Baud is further confused by modems that perform compression. A single 8-bit word passed over the telephone line might represent a dozen words that were transmitted to the sending modem. The receiving modem will expand the data back to its original content and pass that data to the receiving DTE. Modern modems also include buffers that allow the rate that bits move across the phone line (DCE to DCE) to be a different speed than the speed that the bits move between the DTE and DCE on both ends of the conversation. Normally the speed between the DTE and DCE is higher than the DCE to DCE speed because of the use of compression by the modems. Because the number of bits needed to describe a byte varied during the trip between the two machines plus the differing bitsper-seconds speeds that are used present on the DTE-DCE and DCE-DCE links, the usage of the term Baud to describe the overall communication speed causes problems and can misrepresent the true transmission speed. So Bits Per Second (bps) is the correct term to use to describe the transmission rate seen at the DCE to DCE interface and Baud or Bits Per Second are acceptable terms to use when a connection is made between two systems with a wired connection, or if a modem is in use that is not performing error-correction or compression. Modern high speed modems (2400, 9600, 14,400, and 19,200bps) in reality still operate at or below 2400 baud, or more accurately, 2400 Symbols per second. High speed modem are able to encode more bits of data into each Symbol using a technique called Constellation Stuffing, which is why the effective bits per second rate of the modem is higher, but the modem continues to operate within the limited audio bandwidth that the telephone system provides. Modems operating at 28,800 and higher speeds have variable Symbol rates, but the technique is the same. 1.6 Asynchronous Serial Reception A multiplexed data communication pulse can only be in one of two states but there are many names for the two states. When on, circuit closed, low voltage, current flowing, or a logical zero, the pulse is said to be in the "space" condition. When off, circuit open, high voltage, current stopped, or a logical one, the pulse is said to be in the "mark" condition. A character code begins with the data communication circuit in the space condition. If the mark condition appears, a logical one is recorded otherwise a logical zero. Figure 1.3 shows this multiplexing format & Asynchronous Code Format. start|<- five to eight data bits ->| stop bit(s) Page 11

0 ---- - - - - - - - - - - Space(logic low, high data-wire voltage) |||||||||||| |S|1|2|3|4|5|6|7|8|S|S| |||||||||||| 1 - - - - - - - - - - - -------Mark(logic high, low data-wire voltage) The least-significant bit is always transmitted first. If parity is present, the parity bit comes after the data bits but before the stop bit(s).The start bit is always a '0' (logic low), which is also called a space. Ironically, the logic low '0' corresponds to a high voltage on the data wire. The start bit signals the receiving DTE that a character code is coming. The next five to eight bits, depending on the code set employed, represent the character. In the ASCII code set the eighth data bit may be a parity bit. The next one or two bits are always in the mark (logic high, i.e., '1') condition and called the stop bit(s). They provide a "rest" interval for the receiving DTE so that it may prepare for the next character which may be after the stop bit(s). The rest interval was required by the old mechanical Teletypes which used a motor driven camshaft to decode each character. At the end of each character the motor needed time to strike the character bail (print the character) and reset the camshaft. There are six basic steps in receiving a serial character code into a parallel register. First,to keep track of time, the receiver employs a clock which "ticks." When the line is in the space condition, the receiver samples the line 16 times the data rate. In other words, a data interval is equal to 16 clock ticks. In this way the receiver can determine the beginning of the start bit and "move over" to the center of the bit time for data sampling.Second, when the line goes into the mark state, declare a "looking for start bit" condition and wait one half the bit interval or eight clock ticks. Third, sample the line again and if it has not remained in the mark condition, consider this to be a spurious voltage change and go back to step one. Fourth, if the line was still in the mark state, then consider this a valid start bit. Shift the start bit into an eight-bit shift register and wait one bit time or 16 clock ticks. Fifth, after one bit time sample the line (the data should have been there for the last eight clock ticks, and should remain for eight more clock ticks). Now shift the sample into the shift register. Sixth, continue steps four and five seven more times. After the eighth shift, the start bit will "migrate" into a flip-flop indicating character received.Go to step one.Before the transmitter and receiver UARTs will work, they must also agree on the same values of five parameters. First, both sides must agree on the number of bits per character. Second, the speed or Baud of the line must be the same on both sides. Third,both sides must agree to use or not use parity. Fourth, if parity is used, both sides must agree on using odd or even parity. Fifth, the number of stop bits must be agreed upon. Having said all this, most DTEs today employ eight data bits, no parity, and one stop bit. Thus there is a rule-of-thumb that the number of characters per second is equal to the Baud divided by 10 for a typical RS-232 or RS-423 data line. 1.7 Other UART Functions In addition to the basic job of converting data from parallel to serial for transmission and from serial to parallel on reception, a UART will usually provide additional circuits for signals that can be used to indicate the state of the transmission media, and to regulate the flow of data in the event that the remote device is not prepared to accept more data. For example, when the device connected to the UART is a modem, the modem may report the presence of a carrier on the phone line while the computer may be able to instruct the modem to reset itself or to not take calls by raising or lowering one more of these extra signals. The function of each of these additional signals is defined in the EIA RS232-C standard. Page 12

CHAPTER 2 HISTORY OF UART & VHDL 2.1 History of UART Some early telegraph schemes used variable-length pulses (as in Morse code) and rotating clockwork mechanisms to transmit alphabetic characters. The first UART-like devices (with fixedlength pulses) were rotating mechanical switches (commutators). These sent 5-bit Baudot codes for mechanical teletypewriters, and replaced morse code. Later, ASCII required a seven bit code. When IBM built computers in the early 1960s with 8-bit characters, it became customary to store the ASCII code in 8 bits. Gordon Bell designed the UART for the PDP series of computers. Western Digital made the first single-chip UART WD1402A around 1971; this was an early example of a medium scale integrated circuit. An example of an early 1980s UART was the National Semiconductor 8250. In the 1990s, newer UARTs were developed with on-chip buffers. This allowed higher transmission speed without data loss and without requiring such frequent attention from the computer. For example, the popular National Semiconductor 16550 has a 16 byte FIFO, and spawned many variants, including the 16C550, 16C650, 16C750, and 16C850. Depending on the manufacturer, different terms are used to identify devices that perform the UART functions. Intel called their 8251 device a "Programmable Communication Interface".MOS Technology 6551 was known under the name "Asynchronous Communications Interface Adapter" (ACIA). The term "Serial Communications Interface" (SCI) was first used atMotorola around 1975 to refer to their start-stop asynchronous serial interface device, which others were calling a UART.

2.2 History of VHDL VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as fieldprogrammable gate arrays and integrated circuits. VHDL was originally developed at the behest of the U.S Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment. That is to say, VHDL was developed as an alternative to huge, complex manuals which were subject to implementation-specific details.The idea of being able to simulate this documentation was so obviously attractive that logic simulators were developed that could read the VHDL files. The next step was the development of logic synthesis tool that read the VHDL, and output a definition of the physical implementation of the circuit.Due to the Department of Defense requiring as much of the syntax as possible to be based on Ada, in order to avoid re-inventing concepts that had already been thoroughly tested in the development of Ada, VHDL borrows heavily from the Ada programming language[Ada is a structured, staticallytyped, imperative, wide-spectrum,and object-oriented highlevel computer programming language, extended from Pascal and other languages. ] in both concepts and syntax. The initial version of VHDL, designed to IEEE standard 1076-1987, included a wide range of data types, including numerical (integer and real), logical (bit and boolean), character andtime, Page 13

plus arrays of bit called bit_vector and of character called string. A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered. This required IEEE standard 1164, which defined the 9-value logic types: scalar std_ulogic and its vector version std_ulogic_vector. The updated IEEE 1076, in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type to allow ISO-8859-1 printable characters, added the xnor operator, etc. Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class in C++) and removed some restrictions from port mapping rules. In addition to IEEE standard 1164, several child standards were introduced to extend functionality of the language. IEEE standard 1076.2 added better handling of real and complex data types. IEEE standard 1076.3 introduced signed and unsigned types to facilitate arithmetical operations on vectors. IEEE standard 1076.1 (known as VHDL-AMS) provided analog and mixed-signal circuit design extensions.Some other standards support wider use of VHDL, notably VITAL (VHDL Initiative Towards ASIC Libraries) and microwave circuit design extensions. In June 2006, the VHDL Technical Committee of Accellera (delegated by IEEE to work on the next update of the standard) approved so called Draft 3.0 of VHDL-2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier. Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators, more flexible syntax of case and generate statements, incorporation of VHPI (interface to C/C++ languages) and a subset of PSL (Property Specification Language). These changes should improve quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of VHDL for system-level descriptions. In February 2008, Accellera approved VHDL 4.0 also informally known as VHDL 2008, which addressed more than 90 issues discovered during the trial period for version 3.0 and includes enhanced generic types. In 2008, Accellera released VHDL 4.0 to the IEEE for balloting for inclusion in IEEE 1076-2008. The VHDL standard IEEE 1076-2008 was published in January 2009.

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CHAPTER 3 THEORY 3.1 UART PROTOCOL A universal asynchronous receiver/transmitter, abbreviated UART, is a type of "asynchronous receiver/transmitter", a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in conjunction with communication standards such as EIA RS 232, RS-422 or RS-485. The universal designation indicates that the data format and transmission speeds are configurable and that the actual electric signaling levels and methods(such as differential signaling , etc.) typically are handled by a special driver circuit external to the UART. UART is usually an individual (or part of an) integrated circuit used for serial communications over a computer or peripheral device serial port. UARTs are now commonly included in microcontrollers. A dual UART, or DUART, combines two UARTs into a single chip. Many modern ICs now come with a UART that can also communicate synchronously; these devices are called USARTs (universal synchronous/asynchronous receiver/transmitter). Transmitting and receiving serial data : The Universal Asynchronous Receiver/Transmitter (UART) takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes. Each UART contains a shift register which is the fundamental method of conversion between serial and parallel forms. Serial transmission of digital information (bits) through a single wire or other medium is much more cost effective than parallel transmission through multiple wires. The UART usually does not directly generate or receive the external signals used between different items of equipment. Separate interface devices are used to convert the logic level signals of the UART to and from the external signaling levels. Communication may be "full duplex" (both send and receive at the same time) or "half duplex" (devices take turns transmitting and receiving). Character framing : Each character is sent as a logic low start bit, a configurable number of data bits (usually 8 or 7, sometimes 6,5), an optional parity bit, and one or more logic high stop bits. The start bit signals the receiver that a new character is coming. The next five to eight bits, depending on the code set employed, represent the character. Following the data bits may be a parity bit. The next one or two bits are always in the mark (logic high, i.e., '1') condition and called the stop bit(s). They signal the receiver that the character is completed. Since the start bit is logic low (0) and the stop bit is logic high (1) then there is always a clear demarcation between the previous character and the next one.

Figure 3.1 Character frame of UART Receiver : All operations of the UART hardware are controlled by a clock signal which runs at a multiple (say, 16) of the data rate - each data bit is as long as 16 clock pulses. The receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit. If the apparent start bit lasts at least one-half of the bit time, it is valid and signals the start of a new character. If not, the spurious pulse is ignored. After waiting a further bit time, the state of the line is again sampled and the resulting level clocked into a shift register. After the required number of bit periods for the character length (5 to 8 bits, typically) have elapsed, the contents of the shift register is made Page 15

available (in parallel fashion) to the receiving system. The UART will set a flag indicating new data is available, and may also generate a processor interrupt to request that the host processor transfers the received data. In some common types of UART, a small first-in, first-out FIFO buffer memory is inserted between the receiver shift register and the host system interface. This allows the host processor more time to handle an interrupt from the UART and prevents loss of received data at high rates. Transmitter : Transmission operation is simpler since it is under the control of the transmitting system. As soon as data is deposited in the shift register after completion of the previous character, the UART hardware generates a start bit, shifts the required number of data bits out to the line,generates and appends the parity bit (if used), and appends the stop bits. Since transmission of a single character may take a long time relative to CPU speeds, the UART will maintain a flag showing busy status so that the host system does not deposit a new character for transmission until the previous one has been completed; this may also be done with an interrupt. Since full-duplex operation requires characters to be sent and received at the same time, practical UARTs use two different shift registers for transmitted characters and received characters. Transmitting and receiving UARTs must be set for the same bit speed, character length, parity, and stop bits for proper operation. The receiving UART may detect some mismatched settings and set a "framing error" flag bit for the host system; in exceptional cases the receiving UART will produce an erratic stream of mutilated characters and transfer them to the host system. Special receiver conditions Overrun error : An "overrun error" occurs when the receiver cannot process the character that just came in before the next one arrives. Various devices have different amounts of buffer space to hold received characters. The CPU must service the UART in order to remove characters from the input buffer. If the CPU does not service the UART quickly enough and the buffer becomes full, an Overrun Error will occur. Underrun error : An "underrun error" occurs when the UART transmitter has completed sending a character and the transmit buffer is empty. In asynchronous modes this is treated as an indication that no data remains to be transmitted, rather than an error, since additional stop bits can be appended. This error indication is commonly found in USARTs, since an underrun is more serious in synchronous systems. Framing error : A "framing error" occurs when the designated "start" and "stop" bits are not valid. As the "start" bit is used to identify the beginning of an incoming character, it acts as a reference for the remaining bits. If the data line is not in the expected idle state when the "stop" bit is expected, a Framing Error will occur . Parity error : A "parity error" occurs when the number of "active" bits does not agree with the specified parity configuration of the USART, producing a Parity Error. Because the "parity" bit is optional, this error will not occur if parity has been disabled. Parity error is set when the parity of an incoming data character does not match the expected value. Break condition : A "break condition" occurs when the receiver input is at the "space" level for longer than some duration of time, typically, for more than a character time. This is not necessarily an error, but appears to the receiver as a character of all zero bits with a framing error.Some equipment will deliberately transmit the "break" level for longer than a character as an out-of-band signal. When signaling rates are mismatched, no meaningful characters can be sent, but a long "break" signal can be a useful way to get the attention of a mismatched receiver to do something (such as resetting itself).

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Figure 3.2 BLOCK DIAGRAM OF HD 6402 UART :

3.2 Basic VHDL theory VHDL is a language for describing digital electronic systems. It arose out of the United States Government’s Very High Speed Integrated Circuits (VHSIC) program, initiated in 1980. In the course of this program, it became clear that there was a need for a standard language for describing the structure and function of integrated circuits (ICs). Hence the VHSIC Hardware Description Language (VHDL) was developed, and subsequently adopted as a standard by the Institute of Electrical and Electronic Engineers (IEEE) in the US.VHDL is designed to fill a number of needs in the design process. Firstly, it allows description of the structure of a design that is how it is decomposed into subdesigns, and how those sub-designs are interconnected. Secondly, it allows the specification of the function of designs using familiar programming language forms. Thirdly, as a result, it allows a design to be simulated before being manufactured, so that designers can quickly compare alternatives and test for correctness without the delay and expense of hardware prototyping. The purpose of this booklet is to give you a quick introduction to VHDL.This is done by informally describing the facilities provided by the language, and using examples to illustrate them. This booklet does not fully describe every aspect of the language. For such fine details, you should consult the IEEE Standard VHDL Language Reference Manual. However, be warned: the standard is like a legal document, and is very difficult to Page 17

read unless you are already familiar with the language. This booklet does cover enough of the language for substantial model writing. It assumes you know how to write computer programs using a conventional programming language such as Pascal, C or Ada. The remaining chapters of this booklet describe the various aspects of VHDL in a bottom-up manner.The facilities of VHDL which most resemble normal sequential programming languages. These include data types, variables, expressions, sequential statements and subprograms. Then examines the facilities for describing the structure of a module and how it it decomposed into sub-modules. Then covers aspects of VHDL that integrate the programming language features with a discrete event timing model to allow simulation of behaviour. These facilities are combined to form a complete model of a system. One should be attentive towards the following points: 1) The purpose of VHDL. 2) The overall structure of VHDL 3) The VHDL development and execution sequence 4) The VHDL simulation cycle 5) Basic VHDL object types and declarations 6) The syntax and semantics of basic VHDL sequential statements 7) The syntax and semantics of basic VHDL concurrent statements 8) VHDL modeling techniques for the simulation and evaluation of gate-level digital circuits.

Figure 3.3 Example of (a) structural description (b) behaviour description Describing Structure : A digital electronic system can be described as a module with inputs and/or outputs. The electrical values on the outputs are some function of the values on the inputs. Figure1-1(a) shows an example of this view of a digital system. The module F has two inputs, A and B, and an output Y.Using VHDL terminology, we call the module F a design entity, and the inputs and outputs are called ports. One way of describing the function of a module is to describe how it is composed of submodules. Each of the sub-modules is an instance of some entity, and the ports of the instances are connected using signals Figure1-1(b) shows how the entity F might be composed of instances of entities G, H and I. This kind of description is called a structural description. Note that each of the entities G, H and I might also have a structural description. Describing Behaviour : In many cases, it is not appropriate to describe a module structurally. One such case is a module which is at the bottom of the hierarchy of some other structural description. For example, if you are designing a system using IC packages bought from an IC shop, you do not need to describe the internal structure of an IC. In such cases, a description of the function performed by the module is required, without reference to its actual internal structure. Such a description is called a Page 18

functional or behavioral description. To illustrate this, suppose that the function of the entity F in Figure1-1(a) is the exclusive-or function. Then a behavioural description of F could be the Boolean function More complex behaviours cannot be described purely as a function of inputs. In systems with feedback, the outputs are also a function of time. VHDL solves this problem by allowing description of behaviour in the form of an executable program. Discrete Event Time Model : Once the structure and behaviour of a module have been specified, it is possible to simulate the module by executing its behavioural description. This is done by simulating the passage of time in discrete steps. At some simulation time, a module input may be stimulated by changing the value on an input port. The module reacts by running the code of its behavioural description and scheduling new values to be placed on the signals connected to its output ports at some later simulated time. This is called scheduling a transaction on that signal. If the new value is different from the previous value on the signal, an event occurs, and other modules with input ports connected to the signal may be activated. The simulation starts with an initialization phase,and then proceeds by repeating a two-stage simulation cycle. In the initialization phase, all signals are given initial values, the simulation time is set to zero, and each module’s behavior program is executed. This usually results in transactions being scheduled on output signals for some later time. In the first stage of a simulation cycle, the simulated time is advanced to the earliest time at which a transaction has been scheduled. All transactions scheduled for that time are executed, and this may cause events to occur on some signals. In the second stage, all modules which react to events occurring in the first stage have their behaviour program executed. These programs will usually schedule further transactions on their output signals.When all of the behaviour programs have finished executing, the simulation cycle repeats. If there are no more scheduled transactions, the whole simulation is completed. The purpose of the simulation is to gather information about the changes in system state over time. This can be done by running the simulation under the control of a simulation monitor. The monitor allows signals and other state information to be viewed or stored in a trace file for later analysis. It may also allow interactive stepping of the simulation process, much like an interactive program debugger. A Quick Example : In this section we will look at a small example of a VHDL description of a two-bit counter to give you a feel for the language and how it is used. We start the description of an entity by specifying its external interface, which includes a description of its ports. So the counter might be defined as: entity count2 is generic (prop_delay: Time := 10 ns); port (clock : in bit; q1, q0 : out bit); end count2; This specifies that the entity count2 has one input and two outputs, all of which are bit values,that is, they can take on the values '0' or '1'. It also defines a generic constant called prop_delay which can be used to control the operation of the entity (in this case its propagation delay). If no value is explicitly given for this value when the entity is used in a design, the default value of 10ns will be used. An implementation of the entity is described in an architecture body. There may be more than one architecture body corresponding to a single entity specification, each of which describes a different view of the entity.

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Figure 3.4 structure of count2 Behavioural description of counter could be written as: architecture behaviour of count2 is begin count_up: process (clock) variable count_value : natural := 0; begin if clock = '1' then count_value := (count_value + 1) mod 4; q0 <= bit'val(count_value mod 2) after prop_delay; q1 <= bit'val(count_value / 2) after prop_delay; end if; end process count_up; end behaviour;

Shown in Figure3.4 in different architecture : This can be written in VHDL as: architecture structure of count2 is component t_flipflop port (ck : in bit; q : out bit); end component; component inverter port (a : in bit; y : out bit); end component; signal ff0, ff1, inv_ff0 : bit; begin bit_0 : t_flipflop port map (ck => clock, q => ff0); inv : inverter port map (a => ff0, y => inv_ff0); bit_1 : t_flipflop port map (ck => inv_ff0, q => ff1); This process has a variable called count_value to q0 <= ff0; store the current state of the counter.The variable q1 <= ff1; is initialized to zero at the start of simulation, and end structure; retains its value between activations of the process. When the clock input changes from '0' to In this architecture, two component types are '1', the state variable is incremented, and declared, t_flipflop and inverter, and three transactions are scheduled on the two output ports internal signals are declared. Each of the based on the new value. The assignments use the components is then instantiated, and the ports of generic constant prop_delay to determine how the instances are mapped onto signals and ports of long after the clock change the transaction should the entity. For example, bit_0 is an instance of the be scheduled. When control reaches the end of the t_flipflop component, with its ck port connected process body, the process is suspended until to the clock port of the count2 entity, and another change occurs on clock. The two-bit its q port connected to the internal signal ff0. The counter might also be described as a circuit last two signal assignments update the entity composed of two T-flip-flops and an inverter, as ports whenever the values on the internal signals shown in Figure3.4. change.

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CHAPTER 4 IMPLEMENTATION FLOW OF HD 6402 UART IC CMOS Universal Asynchronous Receiver Transmitter (UART) Features • 8.0MHz Operating Frequency (HD-6402B) • 2.0MHz Operating Frequency (HD-6402R) • Low Power CMOS Design • Programmable Word Length, Stop Bits and Parity • Automatic Data Formatting and Status Generation • Compatible with Industry Standard UARTs • Single +5V Power Supply • CMOS/TTL Compatible Inputs Description The HD-6402 is a CMOS UART for interfacing computers or microprocessors to an asynchronous serial data channel.The receiver converts serial start, data, parity and stop bits.The transmitter converts parallel data into serial form and automatically adds start, parity and stop bits. The data word length can be 5, 6, 7 or 8 bits. Parity may be odd or even. Parity checking and generation can be inhibited. The stop bits may be one or two or one and one-half when transmitting 5-bit code. The HD-6402 can be used in a wide range of applications including modems, printers, peripherals and remote data acquisition systems. Utilizing the Intersil advanced scaled SAJI IV CMOS process permits operation clock frequencies up to 8.0MHz (500K Baud). Power requirements, by comparison, are reduced from 300mW to 10mW. Status logic increases flexibility and simplifies the user interface.

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Transmitter Operation The transmitter section accepts parallel data, formats the data and transmits the data in serial form on the Transmitter Register Output (TRO) terminal (See serial data format). Data is loaded from the inputs TBR1-TBR8 into the Transmitter Buffer Register by applying a logic low on the Transmitter Buffer Register Load (TBRL) input (A). Valid data must be present at least tset prior to and thold

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following the rising edge of TBRL. If words less than 8 bits are used, only the least significant bits are transmitted. The character is right justified, so the least significant bit corresponds to TBR1 (B). The rising edge of TBRL clears Transmitter Buffer Register Empty (TBRE). 0 to 1 Clock cycles later, data is transferred to the transmitter register, the Transmitter Register Empty (TRE) pin goes to a low state, TBRE is set high and serial data information is transmitted. The output data is clocked by Transmitter Register Clock (TRC) at a clock rate 16 times the data rate. A second low level pulse on TBRL loads data into the Transmitter Buffer Register (C). Data transfer to the transmitter register is delayed until transmission of the current data is complete (D). Data is automatically transferred to the transmitter register and transmission of that character begins one clock cycle later.

FIGURE 4.1 TRANSMITTER TIMING (NOT TO SCALE) FIGURE 4.2 Pin diagram of HD 6402 UART IC

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FIGURE 4.3

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FIGURE 4.4

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Receiver Operation Data is received in serial form at the Receiver Register Input (RRI). When no data is being received, RRI must remain high. The data is clocked through the Receiver Register Clock (RRC). The clock rate is 16 times the data rate. A low level on Data Received Reset (DRR) clears the Data Receiver (DR) line (A). During the first stop bit data is transferred from the Receiver Register to the Receiver Buffer Register (RBR) (B). If the word is less than 8 bits, the unused most significant bits will be a logic low. The output character is right justified to the least significant bit RBR1. A logic high on Overrun Error (OE) indicates overruns. An overrun occurs when DR has not been cleared before the present character was transferred to the RBR. One clock cycle later DR is reset to a logic high, and Framing Error (FE) is evaluated (C). A logic high on FE indicates an invalid stop bit was received, a framing error. A logic high on Parity Error (PE) indicates a parity error.

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FIGURE 4.5 RECEIVER TIMING (NOT TO SCALE)

FIGURE 4.6 SERIAL DATA FORMAT Start Bit Detection The receiver uses a 16X clock timing. The start bit could have occurred as much as one clock cycle before it was detected, as indicated by the shaded portion (A). The center of the start bit is defined as clock count 7 1/2. If the receiver clock is a symmetrical square wave, the center of the start bit will be located within ±1/2 clock cycle, ±1/32 bit or 3.125% giving a receiver margin of 46.875%. The receiver begins searching for the next start bit at the center of the first stop bit.

FIGURE 4.7 Start Bit Detection

FIGURE 4.8 Signal detail used in CODE Refer on page 21

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FIGURE 4.9 TYPICAL SERIAL DATA LINK

FIGURE 4.10 Electrical specification and switching waveform of data input cycle , control register load cycle , status flag output enable timer or data output enable time.

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CHAPTER 5 XILINX ISE SIMULATOR The ISE 9.1i Quick Start Tutorial provides Xilinx PLD designers with a quick overview of the basic design process using ISE 9.1i. After you have completed the tutorial, you will have an understanding of how to create, verify, and implement a design. This tutorial contains the following sections: • “Getting Started” • “Create a New Project” • “Create an HDL Source” • “Design Simulation” • “Create Timing Constraints” • “Implement Design and Verify Constraints” • “Reimplement Design and Verify Pin Locations” • “Download Design to the Spartan™-3 Demo Board” For an in-depth explanation of the ISE design tools, see the ISE In-Depth Tutorial on the Xilinx® web site at: http://www.xilinx.com/support/techsup/tutorials/

Getting Started Software Requirements To use this tutorial, you must install the following software: • ISE 9.1i For more information about installing Xilinx® software, see the ISE Release Notes and Installation Guide at: http://www.xilinx.com/support/software_manuals.htm. Hardware Requirements To use this tutorial, you must have the following hardware: • Spartan-3 Startup Kit, containing the Spartan-3 Startup Kit Demo Board Starting the ISE Software To start ISE, double-click the desktop icon, or start ISE from the Start menu by selecting: Start → All Programs → Xilinx ISE 9.1i → Project Navigator Note: Your start-up path is set during the installation process and may differ from the one above. Accessing Help At any time during the tutorial, you can access online help for additional information about the ISE software and related tools.

FIGURE 5.1: ISE Help Topics Page 30

To open Help, do either of the following: • Press F1 to view Help for the specific tool or function that you have selected or highlighted. • Launch the ISE Help Contents from the Help menu. It contains information about creating and maintaining your complete design flow in ISE.

Create a New Project Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit demo board. To create a new project: 1. Select File > New Project... The New Project Wizard appears. 2. Type tutorial in the Project Name field. 3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is created automatically. 4. Verify that HDL is selected from the Top-Level Source Type list. 5. Click Next to move to the device properties page. 6. Fill in the properties in the table as shown below: ♦ Product Category: All ♦ Family: Spartan3 ♦ Device: XC3S200 ♦ Package: FT256 ♦ Speed Grade: -4 ♦ Top-Level Source Type: HDL ♦ Synthesis Tool: XST (VHDL/Verilog) ♦ Simulator: ISE Simulator (VHDL/Verilog) ♦ Preferred Language: Verilog (or VHDL) ♦ Verify that Enable Enhanced Design Summary is selected. Leave the default values in the remaining fields.When the table is complete, your project properties will look like the following: FIGURE 5.2: Project Device Properties

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7. Click Next to proceed to the Create New Source window in the New Project Wizard. At the end of the next section, your new project will be complete.

Create an HDL Source In this section, you will create the top-level HDL file for your design. Determine the language that you wish to use for the tutorial. Then, continue either to the “Creating a VHDL Source” section below, or skip to the “Creating a Verilog Source” section. Creating a VHDL Source Create a VHDL source file for the project as follows: 1. Click the New Source button in the New Project Wizard. 2. Select VHDL Module as the source type. 3. Type in the file name counter. 4. Verify that the Add to project checkbox is selected. 5. Click Next. 6. Declare the ports for the counter design by filling in the port information as shown below:

FIGURE 5.3 : Define Module 7. Click Next, then Finish in the New Source Wizard - Summary dialog box to complete the new source file template. 8. Click Next, then Next, then Finish. The source file containing the entity/architecture pair displays in the Workspace, and the counter displays in the Source tab, as shown below:

FIGURE 5.4 : New Project in ISE On page 26 Page 32

Using Language Templates (VHDL) The next step in creating the new source is to add the behavioral description for the counter. To do this you will use a simple counter code example from the ISE Language Templates and customize it for the counter design. 1. Place the cursor just below the begin statement within the counter architecture. 2. Open the Language Templates by selecting Edit → Language Templates… Note: You can tile the Language Templates and the counter file by selecting Window → Tile Vertically to make them both visible. 3. Using the “+” symbol, browse to the following code example: VHDL → Synthesis Constructs → Coding Examples → Counters → Binary →Up/Down Counters → Simple Counter 4. With Simple Counter selected, select Edit → Use in File, or select the Use Template in File toolbar button. This step copies the template into the counter source file. 5. Close the Language Templates. Final Editing of the VHDL Source 1.Add the following signal declaration to handle the feedback of the counter output below the architecture declaration and above the first begin statement: Page 33

signal count_int : std_logic_vector(3 downto 0) := "0000"; 2. Customize the source file for the counter design by replacing the port and signal name placeholders with the actual ones as follows: ♦ replace all occurrences of with CLOCK ♦ replace all occurrences of with DIRECTION ♦ replace all occurrences of with count_int 3. Add the following line below the end process; statement: COUNT_OUT <= count_int; 4. Save the file by selecting File → Save. When you are finished, the counter source file will look like the following: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitive in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is Port ( CLOCK : in STD_LOGIC; DIRECTION : in STD_LOGIC; COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); end counter; architecture Behavioral of counter is signal count_int : std_logic_vector(3 downto 0) := "0000"; begin process (CLOCK) begin if CLOCK='1' and CLOCK'event then if DIRECTION='1' then count_int <= count_int + 1; else count_int <= count_int - 1; end if; end if; end process; COUNT_OUT <= count_int; end Behavioral; You have now created the VHDL source for the tutorial project. Skip past the Verilog sections below, and proceed to the “Checking the Syntax of the New Counter Module”section. In present project, ----------------------------------------------------------------------------- Modeling UART: HD-6402 -- Top Level Design -- by Ravi Shah 30/4/2011 ---------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; Page 34

use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.my_package.all; ---------------------------------------------------------------------------entity UART_6402 is port( TRC: in std_logic; MR: in std_logic; TBRL: in std_logic; SFD: in std_logic; CRL: in std_logic; RRC: in std_logic; RRI: in std_logic; RRD: in std_logic; DRR: in std_logic; CLS2: in std_logic; CLS1: in std_logic; PI: in std_logic; EPE: in std_logic; SBS: in std_logic; TBR: in std_logic_vector(7 downto 0); TRE: out std_logic; TBRE: out std_logic; TRO: out std_logic; OE: out std_logic; PE: out std_logic; FE: out std_logic; DR: out std_logic; RBR: out std_logic_vector(7 downto 0) ); end UART_6402; ----------------------------------------------------------------------------architecture struct of UART_6402 is component trans port( TRC: in std_logic; MR: in std_logic; TBRL: in std_logic; SFD: in std_logic; CRL: in std_logic; CTRLWORD:in std_logic_vector(4 downto 0); TBR: in std_logic_vector(7 downto 0); TRE: out std_logic; TBRE: out std_logic; TRO: out std_logic ); end component; component recei port( RRC:

in std_logic; Page 35

MR: in std_logic; RRI: in std_logic; SFD: in std_logic; RRD: in std_logic; DRR: in std_logic; CRL: in std_logic; CTRLWORD:in std_logic_vector(4 downto 0); OE: out std_logic; PE: out std_logic; FE: out std_logic; DR: out std_logic; RBR: out std_logic_vector(7 downto 0) ); end component; signal ctrl_w1, ctrl_w2: std_logic_vector(4 downto 0); begin process(CLS2,CLS1,PI,EPE,SBS) begin ctrl_w1(4) <= CLS2; ctrl_w1(3) <= CLS1; ctrl_w1(2) <= PI; ctrl_w1(1) <= EPE; ctrl_w1(0) <= SBS; ctrl_w2(4) <= CLS2; ctrl_w2(3) <= CLS1; ctrl_w2(2) <= EPE; ctrl_w2(1) <= SBS; ctrl_w2(0) <= PI; end process; U1: trans port map(TRC,MR,TBRL,SFD,CRL,ctrl_w1,TBR,TRE,TBRE,TRO); U2: recei port map(RRC,MR,RRI,SFD,RRD,DRR,CRL,ctrl_w2,OE,PE,FE,DR,RBR); end struct; Checking the Syntax of the New Counter Module When the source files are complete, check the syntax of the design to find errors and typos. 1. Verify that Synthesis/Implementation is selected from the drop-down list in the Sources window. 2. Select the counter design source in the Sources window to display the related processes in the Processes window. 3. Click the “+” next to the Synthesize-XST process to expand the process group. 4. Double-click the Check Syntax process. Note: You must correct any errors found in your source files. You can check for errors in the Console tab of the Transcript window. If you continue without valid syntax, you will not be able to simulate or synthesize your design. 5. Close the HDL file. Page 36

Design Simulation Verifying Functionality using Behavioral Simulation Create a test bench waveform containing input stimulus you can use to verify the functionality of the counter module. The test bench waveform is a graphical view of a test bench. Create the test bench waveform as follows: 1. Select the counter HDL file in the Sources window. 2. Create a new test bench source by selecting Project → New Source. 3. In the New Source Wizard, select Test Bench WaveForm as the source type, and type counter_tbw in the File Name field. 4. Click Next. 5. The Associated Source page shows that you are associating the test bench waveform with the source file counter. Click Next. 6. The Summary page shows that the source will be added to the project, and it displays the source directory, type and name. Click Finish. 7. You need to set the clock frequency, setup time and output delay times in the Initialize Timing dialog box before the test bench waveform editing window opens. The requirements for this design are the following: ♦ The counter must operate correctly with an input clock frequency = 25 MHz. ♦ The DIRECTION input will be valid 10 ns before the rising edge of CLOCK. ♦ The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK. The design requirements correspond with the values below. Fill in the fields in the Initialize Timing dialog box with the following information: ♦ Clock High Time: 20 ns. ♦ Clock Low Time: 20 ns. ♦ Input Setup Time: 10 ns. ♦ Output Valid Delay: 10 ns. ♦ Offset: 0 ns. ♦ Global Signals: GSR (FPGA) Note: When GSR(FPGA) is enabled, 100 ns. is added to the Offset value automatically. ♦ Initial Length of Test Bench: 1500 ns. Leave the default values in the remaining fields.

FIGURE 5.5 : Initialize Timing Page 37

8. Click Finish to complete the timing initialization. 9. The blue shaded areas that precede the rising edge of the CLOCK correspond to the Input Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION port to define the input stimulus for the counter design as follows : ♦ Click on the blue cell at approximately the 300 ns to assert DIRECTION high so that the counter will count up. ♦ Click on the blue cell at approximately the 900 ns to assert DIRECTION low so that the counter will count down. Note: For more accurate alignment, you can use the Zoom In and Zoom Out toolbar buttons.

FIGURE 5.6 : Test Bench Waveform 10. Save the waveform. 11. In the Sources window, select the Behavioral Simulation view to see that the test bench waveform file is automatically added to your project.

FIGURE 5.7 : Behavior Simulation Selection 12. Close the test bench waveform. Simulating Design Functionality Verify that the counter design functions as you expect by performing behavior simulation as follows: 1. Verify that Behavioral Simulation and counter_tbw are selected in the Sources window. 2. In the Processes tab, click the “+” to expand the Xilinx ISE Simulator process and double-click the Simulate Behavioral Model process.The ISE Simulator opens and runs the simulation to the end of the test bench. 3. To view your simulation results, select the Simulation tab and zoom in on the transitions. The simulation waveform results will look like the following: Note: You can ignore any rows that start with TX. 4. Verify that the counter is counting up and down as expected. Page 38

Figure 5.8 : Simulation Results 5. Close the simulation view. If you are prompted with the following message, “You have an active simulation open. Are you sure you want to close it?“, click Yes to continue. You have now completed simulation of your design using the ISE Simulator.

Create Timing Constraints Specify the timing between the FPGA and its surrounding logic as well as the frequency the design must operate at internal to the FPGA. The timing is specified by entering constraints that guide the placement and routing of the design. It is recommended that you enter global constraints. The clock period constraint specifies the clock frequency at which your design must operate inside the FPGA. The offset constraints specify when to expect valid data at the FPGA inputs and when valid data will be available at the FPGA outputs. Entering Timing Constraints To constrain the design do the following: 1. Select Synthesis/Implementation from the drop-down list in the Sources window. 2. Select the counter HDL source file. 3. Click the “+” sign next to the User Constraints processes group, and double-click the Create Timing Constraints process. ISE runs the Synthesis and Translate steps and automatically creates a User Constraints File (UCF). You will be prompted with the following message:

Figure 5.9 : Prompt to Add UCF File to Project 4. Click Yes to add the UCF file to your project. The counter.ucf file is added to your project and is visible in the Sources window. The Xilinx Constraints Editor opens automatically. Page 39

Note: You can also create a UCF file for your project by selecting Project → Create New Source. In the next step, enter values in the fields associated with CLOCK in the Constraints Editor Global tab. 5. Select CLOCK in the Clock Net Name field, then select the Period toolbar button or double-click the empty Period field to display the Clock Period dialog box. 6. Enter 40 ns in the Time field.

Figure 5.10 : Clock Period 7. Click OK. 8. Select the Pad to Setup toolbar button or double-click the empty Pad to Setup field to display the Pad to Setup dialog box. 9. Enter 10 ns in the OFFSET field to set the input offset constraint.

Figure 5.11 : Pad to Setup 10. Click OK. 11. Select the Clock to Pad toolbar button or double-click the empty Clock to Pad field to display the Clock to Pad dialog box.

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12. Enter 10 ns in the OFFSET field to set the output delay constraint.

FIGURE 5.12 : Clock to Pad 13. Click OK. The constraints are displayed in the Constraints (read-write) tab, as shown below:

FIGURE 5.13 : Timing Constraints 14. Save the timing constraints. If you are prompted to rerun the TRANSLATE or XST step, click OK to continue. 15. Close the Constraints Editor.

Implement Design and Verify Constraints Implement the design and verify that it meets the timing constraints specified in the previous section. Implementing the Design 1. Select the counter source file in the Sources window. 2.Open the Design Summary by double-clicking the View Design Summary process in the Processes tab. Page 41

3. Double-click the Implement Design process in the Processes tab. 4. Notice that after Implementation is complete, the Implementation processes have a green check mark next to them indicating that they completed successfully without Errors or Warnings.

Figure 5.14 : Post Implementation Design Summary 5. Locate the Performance Summary table near the bottom of the Design Summary. 6. Click the All Constraints Met link in the Timing Constraints field to view the Timing Constraints report. Verify that the design meets the specified timing requirements.

Figure 5.15 : All Constraints Met Report

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7. Close the Design Summary. Assigning Pin Location Constraints Specify the pin locations for the ports of the design so that they are connected correctly on the Spartan3 Startup Kit demo board. To constrain the design ports to package pins, do the following: 1. Verify that counter is selected in the Sources window. 2. Double-click the Assign Package Pins process found in the User Constraints process group. The Xilinx Pinout and Area Constraints Editor (PACE) opens. 3. Select the Package View tab. 4. In the Design Object List window, enter a pin location for each pin in the Loc column using the following information: ♦ CLOCK input port connects to FPGA pin T9 (GCK0 signal on board) ♦ COUNT_OUT<0> output port connects to FPGA pin K12 (LD0 signal on board) ♦ COUNT_OUT<1> output port connects to FPGA pin P14 (LD1 signal on board) ♦ COUNT_OUT<2> output port connects to FPGA pin L12 (LD2 signal on board) ♦ COUNT_OUT<3> output port connects to FPGA pin N14 (LD3 signal on board) ♦ DIRECTION input port connects to FPGA pin K13 (SW7 signal on board) Notice that the assigned pin locations are shown in blue: 5. Select File → Save. You are prompted to select the bus delimiter type based on the synthesis tool you are using. Select XST Default <> and click OK. 6. Close PACE. Notice that the Implement Design processes have an orange question mark next to them,indicating they are out-of-date with one or more of the design files. This is because the UCF file has been modified.

Reimplement Design and Verify Pin Locations Reimplement the design and verify that the ports of the counter design are routed to the package pins specified in the previous section. First, review the Pinout Report from the previous implementation by doing the following: 1. Open the Design Summary by double-clicking the View Design Summary process in the Processes window.

FIGURE 5.16 : Package Pin Locations Page 43

5. Select File → Save. You are prompted to select the bus delimiter type based on the synthesis tool you are using. Select XST Default <> and click OK. 6. Close PACE. Notice that the Implement Design processes have an orange question mark next to them, indicating they are out-of-date with one or more of the design files. This is because the UCF file has been modified. Reimplement Design and Verify Pin Locations Reimplement the design and verify that the ports of the counter design are routed to the package pins specified in the previous section. First, review the Pinout Report from the previous implementation by doing the following: 1. Open the Design Summary by double-clicking the View Design Summary process in the Processes window. 2. Select the Pinout Report and select the Signal Name column header to sort the signal names. Notice the Pin Numbers assigned to the design ports in the absence of location constraints.

FIGURE 5.17: Package Pin Locations Prior to Pin Location Constraints 3. Reimplement the design by double-clicking the Implement Design process. 4. Select the Pinout Report again and select the Signal Name column header to sort the signal names. 5. Verify that signals are now being routed to the correct package pins.

FIGURE 5.18 : Package Pin Locations After Pin Location Constraints 6. Close the Design Summary. Page 44

Download Design to the Spartan™-3 Demo Board This is the last step in the design verification process. This section provides simple instructions for downloading the counter design to the Spartan-3 Starter Kit demo board. 1. Connect the 5V DC power cable to the power input on the demo board (J4). 2. Connect the download cable between the PC and demo board (J7). 3. Select Synthesis/Implementation from the drop-down list in the Sources window. 4. Select counter in the Sources window. 5. In the Processes window, click the “+” sign to expand the Generate Programming File processes. 6. Double-click the Configure Device (iMPACT) process. 7. The Xilinx WebTalk Dialog box may open during this process. Click Decline. 8. Select Disable the collection of device usage statistics for this project only and click OK. iMPACT opens and the Configure Devices dialog box is displayed.

FIGURE 5.19 : iMPACT Welcome Dialog Box 9. In the Welcome dialog box, select Configure devices using Boundary-Scan (JTAG). 10. Verify that Automatically connect to a cable and identify Boundary-Scan chain is selected. 11. Click Finish. 12. If you get a message saying that there are two devices found, click OK to continue. The devices connected to the JTAG chain on the board will be detected and displayed in the iMPACT window. 13. The Assign New Configuration File dialog box appears. To assign a configuration file to the xc3s200 device in the JTAG chain, select the counter.bit file and click Open.

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FIGURE 5.20: Assign New Configuration File 14. If you get a Warning message, click OK. 15. Select Bypass to skip any remaining devices. 16. Right-click on the xc3s200 device image, and select Program... The Programming Properties dialog box opens. 17. Click OK to program the device. When programming is complete, the Program Succeeded message is displayed.

On the board, LEDs 0, 1, 2, and 3 are lit, indicating that the counter is running. 18. Close iMPACT without saving. You have completed the ISE Quick Start Tutorial. For an in-depth explanation of the ISE design tools, see the ISE In-Depth Tutorial on the Xilinx® web site at: http://www.xilinx.com/support/techsup/tutorials/

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CHAPTER 6 VHDL PROGRAM RESULTS All the VHDL programs have been implemented and tested on Xilinx Project Navigator Release ISE 8.2i.The detailed summary of outputs are given below. MAIN PROGRAM design summary in FPGA :

MAIN PROGRAM design summary in CPLD :

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CHAPTER 7 CONCLUSION We successfully designed a HD6402 UART IC for serial communication application and observed its output, both as test bench waveform and on Spartan kit. We study UART protocol and then datasheet of HD6402 UART IC and finally implementation in VHDL. The simulator used is Xilinx ISE9.2i and implemented on FPGA Hardware. The experiment/project/thesis can be classified into the following stages: Learning UART protocol and HD6402 UART IC datasheet.  Getting acquainted with VHDL-The various knowledge required for operating VHDL like knowing about its syntax, architecture components etc. was studied and practiced byperforming simpler examples.  Learning the required circuits: The various circuits of timers FF,MUX,etc was studied from various digital books and rough diagram of the circuit was prepared.  Writing the program code :Then the required code for the HD6402 UART was written using VHDL and its errors were checked for.  Simulating the code using Xilinx : Then using xilinx simulator, the written code was simulated.The various errors and warning were taken care of.And finally the test bench waveform was obtained and studied.  Burning the code on FPGA:Then the code was burned using the Spartan kit and various necessary methods were carried out till we get the required output on the FPGA board.

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CHAPTER 8 BIBLIOGRAPHY 8.1 BOOK REFERENCES 1.”Digital Logic Circuits using VHDL” by Stephen Brown.. 2. "VHDL for Programmable Logic" by Kevin Skahill, Addison-Wesley 3."A Designer's Guide to VHDL Synthesis" by Douglas E. Ott and Thomas J. Wilderotter,Kluwer Academic Publishers 4. "VHDL Made Easy" by David Pellerin and Douglas Taylor. 5. "The Student's Guide to VHDL" by Peter J. Ashenden, Morgan Kauffman. 6. "VHDL Starter's Guide" by Sudhakar Yalamanchili 7. ” VHDL Primer by J. Bhasker”

8.2 Web link http://www.wikipedia.org/uart http://esd.cs.ucr.edu/labs/tutorial/ http://esd.cs.ucr.edu/labs/uart/uart.html

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APPENDIX Main Source Code of UART.vhd ----------------------------------------------------------------------------- UART Package Declaration -- by Shah Ravi, 04/2011 ---------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; ---------------------------------------------------------------------------package my_package is FUNCTION parity(inputs: std_logic_vector(7 downto 0)) RETURN std_logic; end my_package; PACKAGE body my_package is FUNCTION parity(inputs: std_logic_vector(7 downto 0)) RETURN std_logic is variable temp: std_logic; begin temp:='0'; for i in 7 downto 0 loop temp:=temp xor inputs(i); end loop; return temp; end parity; end my_package; ----------------------------------------------------------------------------- Modeling UART: HD-6402 -- UART Receiver Model (behavior modeling) -- by Shah Ravi, 04/2011 ---------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.my_package.all; ---------------------------------------------------------------------------entity recei is port( RRC: in std_logic; MR: in std_logic; RRI: in std_logic; SFD: in std_logic; RRD: in std_logic; DRR: in std_logic; CRL: in std_logic; CTRLWORD: in std_logic_vector(4 downto 0); OE: out std_logic; PE: out std_logic; FE: out std_logic; DR: out std_logic; RBR: out std_logic_vector(7 downto 0) ); end recei; ---------------------------------------------------------------------------architecture behv of recei is constant reg_init: std_logic_vector(11 downto 0):="111111111111";

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signal ctrl_word: std_logic_vector(4 downto 0); signal recei_reg: std_logic_vector(11 downto 0); signal rri_temp: std_logic; signal dr_sig,pe_sig,oe_sig,fe_sig: std_logic; signal rx_empty: boolean; signal rbr_temp: std_logic_vector(7 downto 0); begin P1: process(CRL,CTRLWORD) begin if CRL='1' then trl_word <= CTRLWORD; end if; end process; rri_temp <= RRI; P2: process variable cnt16: integer range 0 to 15; begin wait until RRC'event and RRC='1'; if MR='1' then -- initialize and wait to receive data... cnt16 := 0 ; -- Original state... rx_empty <= true; oe_sig<='0'; recei_reg <= reg_init; elsif (rx_empty and rri_temp='0') then cnt16 := 0; -- start reading the bit come in... rx_empty <= false; if dr_sig/='0' then oe_sig<='1'; elsif dr_sig='0' then oe_sig<='0'; end if; recei_reg <= reg_init; elsif (cnt16=7 and (not rx_empty))then recei_reg <= rri_temp & recei_reg(11 downto 1); cnt16 := cnt16 +1; elsif cnt16 = 15 then -- finish reading 1-bit of receipt cnt16 := 0; -- ready to read next.. else cnt16 := cnt16 + 1; end if; case ctrl_word(4 downto 1) is when "0001" => if (not rx_empty) and recei_reg(5)='0' then rx_empty <= true; if DRR='1' then dr_sig <= '1'; elsif DRR='0' then dr_sig <='0'; end if; elsif recei_reg(5)/='0' then dr_sig <= '0'; elsif (rx_empty) then if DRR='0' then dr_sig <= '0'; end if; end if;

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when "0000"|"0011" => if (not rx_empty) and recei_reg(4)='0' then rx_empty <= true; if DRR='1' then dr_sig <= '1'; elsif DRR='0' then dr_sig <='0'; end if; elsif recei_reg(4)/='0' then dr_sig <= '0'; elsif (rx_empty) then if DRR='0' then dr_sig <= '0'; end if; end if; when "0010" => if (not rx_empty) and recei_reg(3)='0' then rx_empty <= true; if DRR='1' then dr_sig <= '1'; elsif DRR='0' then dr_sig <='0'; end if; elsif recei_reg(3)/='0' then dr_sig <= '0'; elsif (rx_empty) then if DRR='0' then dr_sig <= '0'; end if; end if; when "0101" => if (not rx_empty) and recei_reg(4)='0' then rx_empty <= true; if DRR='1' then dr_sig <= '1'; elsif DRR='0' then dr_sig <='0'; end if; elsif recei_reg(4)/='0' then dr_sig <= '0'; elsif (rx_empty) then if DRR='0' then dr_sig <= '0'; end if; end if; when "0100"|"0111" => if (not rx_empty) and recei_reg(3)='0' then rx_empty <= true; if DRR='1' then dr_sig <= '1'; elsif DRR='0' then dr_sig <='0'; end if; elsif recei_reg(3)/='0' then dr_sig <= '0'; elsif (rx_empty) then if DRR='0' then dr_sig <= '0'; end if; end if; when "0110" => if (not rx_empty) and recei_reg(2)='0' then rx_empty <= true; if DRR='1' then dr_sig <= '1'; elsif DRR='0' then dr_sig <='0'; end if; elsif recei_reg(2)/='0' then dr_sig <= '0'; elsif (rx_empty) then if DRR='0' then dr_sig <= '0'; end if; end if; when "1001" => if (not rx_empty) and recei_reg(3)='0' then rx_empty <= true; if DRR='1' then dr_sig <= '1'; elsif DRR='0' then dr_sig <='0';

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end if; elsif recei_reg(3)/='0' then dr_sig <= '0'; elsif (rx_empty) then if DRR='0' then dr_sig <= '0'; end if; end if; when "1000"|"1011" => if (not rx_empty) and recei_reg(2)='0' then rx_empty <= true; if DRR='1' then dr_sig <= '1'; elsif DRR='0' then dr_sig <='0'; end if; elsif recei_reg(2)/='0' then dr_sig <= '0'; elsif (rx_empty) then if DRR='0' then dr_sig <= '0'; end if; end if; when "1010" => if (not rx_empty) and recei_reg(1)='0' then rx_empty <= true; if DRR='1' then dr_sig <= '1'; elsif DRR='0' then dr_sig <='0'; end if; elsif recei_reg(1)/='0' then dr_sig <= '0'; elsif (rx_empty) then if DRR='0' then dr_sig <= '0'; end if; end if; when "1101" => if (not rx_empty) and recei_reg(2)='0' then rx_empty <= true; if DRR='1' then dr_sig <= '1'; elsif DRR='0' then dr_sig <='0'; end if; elsif recei_reg(2)/='0' then dr_sig <= '0'; elsif (rx_empty) then if DRR='0' then dr_sig <= '0'; end if; end if; when "1100"|"1111" => if (not rx_empty) and recei_reg(1)='0' then rx_empty <= true; if DRR='1' then dr_sig <= '1'; elsif DRR='0' then dr_sig <='0'; end if; elsif recei_reg(1)/='0' then dr_sig <= '0'; elsif (rx_empty) then if DRR='0' then dr_sig <= '0'; end if; end if; when others => if (not rx_empty) and recei_reg(0)='0' then rx_empty <= true; if DRR='1' then dr_sig <= '1'; elsif DRR='0' then dr_sig <='0'; end if; elsif recei_reg(0)/='0' then dr_sig <= '0'; elsif (rx_empty) then if DRR='0' then dr_sig <= '0';

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end if; end if; end case; end process; P3: process(RRC,recei_reg,ctrl_word) begin case ctrl_word(4 downto 1) is when "0001" => rbr_temp <= "000" & recei_reg(10 downto 6); when "0000"|"0011" => rbr_temp <= "000" & recei_reg(9 downto 5); when "0010" => rbr_temp <= "000" & recei_reg(8 downto 4); when "0101" => rbr_temp <= "00" & recei_reg(10 downto 5); when "0100"|"0111" => rbr_temp <= "00" & recei_reg(9 downto 4); when "0110" => rbr_temp <= "00" & recei_reg(8 downto 3); when "1001" => rbr_temp <= '0' & recei_reg(10 downto 4); when "1000"|"1011" => rbr_temp <= '0' & recei_reg(9 downto 3); when "1010" => rbr_temp <= '0' & recei_reg(8 downto 2); when "1101" => rbr_temp <= recei_reg(10 downto 3); when "1100"|"1111" => rbr_temp <= recei_reg(9 downto 2); when others => rbr_temp <= recei_reg(8 downto 1); end case; end process; P4: process(dr_sig,ctrl_word,rbr_temp,recei_reg) begin if dr_sig='1' then if ctrl_word(0)='1' then -- even parity case if ctrl_word(1)='0' then if ctrl_word(2)='1' then if (parity(rbr_temp) xor recei_reg(9))='0' then pe_sig <='0'; else pe_sig <= '1'; end if; elsif ctrl_word(2)='0' then if (parity(rbr_temp) xor recei_reg(10))='0' then pe_sig <='0'; else pe_sig <= '1'; end if; end if; elsif ctrl_word(1)='1' then pe_sig <= '0'; end if;

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elsif ctrl_word(0)='0' then -- odd parity case if ctrl_word(1)='0' then if ctrl_word(2)='1' then if (parity(rbr_temp) xor recei_reg(9))='1' then pe_sig <='0'; else pe_sig <= '1'; end if; elsif ctrl_word(2)='0' then if (parity(rbr_temp) xor recei_reg(10))='1' then pe_sig <='0'; else pe_sig <= '1'; end if; end if; elsif ctrl_word(1)='1' then pe_sig <= '0'; end if; end if; if ctrl_word(2)='0' then if recei_reg(11)/='1' then fe_sig<='1'; else fe_sig<='0'; end if; elsif ctrl_word(2)='1' then if recei_reg(11)/='1' or recei_reg(10)/='1' then fe_sig<='1'; else fe_sig<='0'; end if; end if; else pe_sig <= '0'; fe_sig <= '0'; end if; end process; P5: process(SFD,rbr_temp,RRD,dr_sig,pe_sig,fe_sig,oe_sig) begin if RRD='1' then RBR <= "ZZZZZZZZ"; elsif RRD='0' then RBR <= rbr_temp; end if; if SFD='1' then DR <= 'Z'; PE <= 'Z'; OE <= 'Z'; FE <= 'Z'; elsif SFD='0' then DR <= dr_sig; PE <= pe_sig; OE <= oe_sig; FE <= fe_sig; end if; end process;

-- tri-buffer for other outputs

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end behv; ----------------------------------------------------------------------------- Modeling UART: HD-6402 -- UART Transmitter Model (behavior modeling) -- by Shah Ravi, 04/2011 -------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.my_package.all; -------------------------------------------------------------------------entity trans is port( TRC: in std_logic; MR: in std_logic; TBRL: in std_logic; SFD: in std_logic; CRL: in std_logic; CTRLWORD: in std_logic_vector(4 downto 0); TBR: in std_logic_vector(7 downto 0); TRE: out std_logic; TBRE: out std_logic; TRO: out std_logic ); end trans; -----------------------------------------------------------------------architecture behv of trans is constant C0: unsigned(4 downto 0):="00001"; constant CI: unsigned(4 downto 0):="01000"; constant CM: unsigned(4 downto 0):="10000"; constant MM: unsigned(3 downto 0):="1111"; signal trans_reg: std_logic_vector(11 downto 0); signal trans_reg_temp: std_logic_vector(11 downto 0); signal TBR_sig: std_logic_vector(7 downto 0); signal old_tbr_sig: std_logic_vector(7 downto 0); signal delay: std_logic_vector(0 downto 0); signal go: std_logic; signal t_pari: std_logic; -- signal clk: std_logic; signal i: unsigned(3 downto 0); signal ctrl_word: std_logic_vector(4 downto 0); begin P1: process(CRL,CTRLWORD) begin if CRL='1' then ctrl_word<=CTRLWORD; end if; end process;

-- load control word here

-- this process make out the transmit register according to control word. P2: process(ctrl_word,MR,TBR,TBRL,TBR_sig,t_pari) begin if (MR='1') then TBR_sig<="11111111"; t_pari <= '0';

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trans_reg_temp <= "1111" & TBR_sig; else if TBRL='0' then TBR_sig <= TBR; t_pari <= parity(TBR); end if;

-- call function and compute the parity

case ctrl_word is when "00000"|"00001" => if t_pari='0' then -- odd parity trans_reg_temp <= "111" & "11" & '1' & TBR_sig(4 downto 0) & '0'; elsif t_pari='1' then -- even parity trans_reg_temp <= "111" & "11" & '0' & TBR_sig(4 downto 0) & '0'; end if; when "00010"|"00011" => if t_pari='0' then -- odd parity trans_reg_temp <= "111" & "11" & '0' & TBR_sig(4 downto 0) & '0'; elsif t_pari='1' then -- even parity trans_reg_temp <= "111" & "11" & '1' & TBR_sig(4 downto 0) & '0'; end if; when "00100"|"00110"|"00101"|"00111" => -- no parity trans_reg_temp <= "1111" & "11" & TBR_sig(4 downto 0) & '0'; when "01000"|"01001" => if t_pari='0' then -- odd parity trans_reg_temp <= "11" & "11" & '1' & TBR_sig(5 downto 0) & '0'; elsif t_pari='1' then -- even parity trans_reg_temp <= "11" & "11" & '0' & TBR_sig(5 downto 0) & '0'; end if; when "01010"|"01011" => if t_pari='0' then -- odd parity trans_reg_temp <= "11" & "11" & '0' & TBR_sig(5 downto 0) & '0'; elsif t_pari='1' then -- even parity trans_reg_temp <= "11" & "11" & '1' & TBR_sig(5 downto 0) & '0'; end if; when "01100"|"01110"|"01101"|"01111" => -- no parity trans_reg_temp <= "111" & "11" & TBR_sig(5 downto 0) & '0'; when "10000"|"10001" => if t_pari='0' then -- odd parity trans_reg_temp <= '1' & "11" & '1' & TBR_sig(6 downto 0) & '0'; elsif t_pari='1' then -- even parity trans_reg_temp <= '1' & "11" & '0' & TBR_sig(6 downto 0) & '0'; end if; when "10010"|"10011" => if t_pari='0' then -- odd parity trans_reg_temp <= '1' & "11" & '0' & TBR_sig(6 downto 0) & '0'; elsif t_pari='1' then -- even parity trans_reg_temp <= '1' & "11" & '1' & TBR_sig(6 downto 0) & '0'; end if; when "10100"|"10110"|"10101"|"10111" => -- no parity trans_reg_temp <= "11" & "11" & TBR_sig(6 downto 0) & '0'; when "11000"|"11001" => if t_pari='0' then -- odd parity trans_reg_temp <= "11" & '1' & TBR_sig(7 downto 0) & '0'; elsif t_pari='1' then -- even parity trans_reg_temp <= "11" & '0' & TBR_sig(7 downto 0) & '0'; end if; when "11010"|"11011" => if t_pari='0' then -- odd parity trans_reg_temp <= "11" & '0' & TBR_sig(7 downto 0) & '0';

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elsif t_pari='1' then -- even parity trans_reg_temp <= "11" & '1' & TBR_sig(7 downto 0) & '0'; end if; when others => -- no parity trans_reg_temp <= '1' & "11" & TBR_sig(7 downto 0) & '0'; end case; end if; end process; -- P1 describes the whole transmission procedure P3: process variable cnt: integer range 0 to 12; variable cnt_limit: integer range 0 to 12; begin wait until TRC'event and TRC='1'; if MR='1' then old_tbr_sig <= "11111111"; delay<="0"; go<='0'; i <= "1111"; tre<='0'; else if (i=MM) then i<="0000"; if(go='0') then delay<="0"; cnt := 12; TRE <= '1'; if (old_tbr_sig=TBR_sig) then go <= '0'; elsif (old_tbr_sig/=TBR_sig) then go <='1'; end if; trans_reg <= "111111111111"; elsif (go='1' and delay="0") then go<='1'; cnt:=0; delay<=delay+1; TRE <= '1'; trans_reg <= "111111111111"; elsif (go='1' and delay="1" and cnt=0) then go <= '1'; cnt:=cnt+1; delay<=delay+0; old_tbr_sig<=TBR_sig; TRE<='0'; trans_reg <= trans_reg_temp; elsif (go='1' and delay="1" and cnt/=0) then trans_reg <= '1' & trans_reg(11 downto 1); case ctrl_word(4 downto 2) is when "000" => if ctrl_word(0)='0' then cnt_limit := 8; elsif ctrl_word(0)='1' then cnt_limit :=9; end if; when "001" => if ctrl_word(0)='0' then cnt_limit := 7;

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when "010" =>

when "011" =>

when "100" =>

when "101" =>

when "110" =>

when "111" =>

elsif ctrl_word(0)='1' then cnt_limit :=8; end if; if ctrl_word(0)='0' then cnt_limit := 9; elsif ctrl_word(0)='1' then cnt_limit :=10; end if; if ctrl_word(0)='0' then cnt_limit := 8; elsif ctrl_word(0)='1' then cnt_limit :=9; end if; if ctrl_word(0)='0' then cnt_limit := 10; elsif ctrl_word(0)='1' then cnt_limit :=11; end if; if ctrl_word(0)='0' then cnt_limit := 9; elsif ctrl_word(0)='1' then cnt_limit :=10; end if; if ctrl_word(0)='0' then cnt_limit :=11; elsif ctrl_word(0)='1' then cnt_limit :=12; end if; if ctrl_word(0)='0' then cnt_limit :=10; elsif ctrl_word(0)='1' then cnt_limit :=11; end if;

when others => end case; if cnt/=cnt_limit then go <= '1'; delay<=delay+0; cnt:=cnt+1; TRE<='0'; elsif cnt=cnt_limit then go <= '0'; delay<="0"; TRE<='1'; end if; end if; if SFD='1' then TBRE <= '1'; elsif SFD='0' then if (cnt=0 or cnt=1) then TBRE <= '0'; else TBRE <= '1'; end if; end if; --

else

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--

i<=i+1;

end if; end if; end process; -- this cocurrent statement handle the serial output of Transmitter TRO <= trans_reg(0); end behv; ----------------------------------------------------------------------------- Modeling UART: HD-6402 -- Top Level Design -- by Shah Ravi, 04/2011 ---------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.my_package.all; ---------------------------------------------------------------------------entity UART_6402 is port( TRC: in std_logic; MR: in std_logic; TBRL: in std_logic; SFD: in std_logic; CRL: in std_logic; RRC: in std_logic; RRI: in std_logic; RRD: in std_logic; DRR: in std_logic; CLS2: in std_logic; CLS1: in std_logic; PI: in std_logic; EPE: in std_logic; SBS: in std_logic; TBR: in std_logic_vector(7 downto 0); TRE: out std_logic; TBRE: out std_logic; TRO: out std_logic; OE: out std_logic; PE: out std_logic; FE: out std_logic; DR: out std_logic; RBR: out std_logic_vector(7 downto 0) ); end UART_6402; ----------------------------------------------------------------------------architecture struct of UART_6402 is component trans port( TRC: MR: TBRL: SFD: CRL: CTRLWORD: TBR: TRE:

in std_logic; in std_logic; in std_logic; in std_logic; in std_logic; in std_logic_vector(4 downto 0); in std_logic_vector(7 downto 0); out std_logic;

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TBRE: TRO:

out std_logic; out std_logic

); end component; component recei port( RRC: MR: RRI: SFD: RRD: DRR: CRL: CTRLWORD: OE: PE: FE: DR: RBR: ); end component;

in std_logic; in std_logic; in std_logic; in std_logic; in std_logic; in std_logic; in std_logic; in std_logic_vector(4 downto 0); out std_logic; out std_logic; out std_logic; out std_logic; out std_logic_vector(7 downto 0)

signal ctrl_w1, ctrl_w2: std_logic_vector(4 downto 0); begin process(CLS2,CLS1,PI,EPE,SBS) begin ctrl_w1(4) <= CLS2; ctrl_w1(3) <= CLS1; ctrl_w1(2) <= PI; ctrl_w1(1) <= EPE; ctrl_w1(0) <= SBS; ctrl_w2(4) <= CLS2; ctrl_w2(3) <= CLS1; ctrl_w2(2) <= PI; ctrl_w2(1) <= EPE; ctrl_w2(0) <= SBS; end process; U1: U2:

trans port map(TRC,MR,TBRL,SFD,CRL,ctrl_w1,TBR,TRE,TBRE,TRO); recei port map(RRC,MR,RRI,SFD,RRD,DRR,CRL,ctrl_w2,OE,PE,FE,DR,RBR);

end struct;

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TEST BENCH OF UART.vhd -------------------------------------------------------------------- TestBench for UART6402 -- by Ravi shah, 05/2011 ------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.my_package.all; ------------------------------------------------------------------entity test_UART is end test_UART; ------------------------------------------------------------------architecture bench of test_UART is component UART_6402 is port( TRC: in std_logic; MR: in std_logic; TBRL: in std_logic; SFD: in std_logic; CRL: in std_logic; RRC: in std_logic; RRI: in std_logic; RRD: in std_logic; DRR: in std_logic; CLS2: in std_logic; CLS1: in std_logic; PI: in std_logic; EPE: in std_logic; SBS: in std_logic; TBR: in std_logic_vector(7 downto 0); TRE: out std_logic; TBRE: out std_logic; TRO: out std_logic; OE: out std_logic; PE: out std_logic; FE: out std_logic; DR: out std_logic; RBR: out std_logic_vector(7 downto 0) ); end component; signal T_CLK,T_MR,T_TBRL,T_SFD,T_CRL,T_RRD,T_DRR: std_logic; signal T_CLS2,T_CLS1,T_PI,T_EPE,T_SBS: std_logic; signal T_TBR: std_logic_vector(7 downto 0); signal T_RBR: std_logic_vector(7 downto 0); signal T_TRE,T_TBRE,T_data,T_OE,T_PE,T_FE,T_DR: std_logic; begin Unit: UART_6402 port map( T_CLK,T_MR,T_TBRL,T_SFD,T_CRL,T_CLK,T_data, T_RRD,T_DRR,T_CLS2,T_CLS1,T_PI,T_EPE,T_SBS, T_TBR,T_TRE,T_TBRE,T_data,T_OE,T_PE,T_FE, T_DR,T_RBR); clk_sig: process begin

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T_CLK <='1'; wait for 5 ns; T_CLK <= '0'; wait for 5 ns; end process; process begin T_MR <= '1'; -- initialization... T_CRL <= '1'; T_CLS2 <= '1'; T_CLS1 <= '1'; T_PI <= '0'; T_EPE <= '1'; T_SBS <= '1'; T_DRR <= '1'; T_RRD <= '0'; T_SFD <= '0'; T_TBR <= "10011101"; T_TBRL <= '1'; wait for 50 ns; T_CRL <= '0'; -- load ctrl word here wait for 50 ns; T_MR <= '0'; -- reset release here wait for 50 ns; T_TBRL <= '0'; -- load transmit word wait for 200 ns; T_TBRL <= '1'; wait for 500 ns; T_TBR <= "10100010"; wait for 100 ns; T_TBRL <= '0'; -- load transmit word wait for 4000 ns; -- set SFD to high level T_DRR <= '0'; wait for 100 ns; T_DRR <= '1'; wait for 200 ns; T_SFD <= '1'; wait for 50 ns; T_RRD <= '1'; wait for 300 ns; T_RRD <= '0'; wait; end process; end bench; ------------------------------------------------------------------configuration CFG_TB of test_UART is for bench end for; end CFG_TB; -------------------------------------------------------------------

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