Robust M-PSK Phase Detectors for Carrier Synchronization PLLs in Coherent Receivers: Theory and Simulations Yair Linn, Member, IEEE

Abstract—In this paper we present two new Non Data Aided (NDA) phase detectors (PDs) for carrier synchronization Phase Locked Loops (PLLs) in M-ary Phase Shift Keying (M-PSK) receivers. The first structure is a self-normalizing modification of the M-th order nonlinearity detector. We investigate this detector theoretically in order to predict its S-curve, self-noise, squaringloss, and phase-error variance performance. These theoretical predictions are then verified by computer simulations, and the results are contrasted with results obtained using other NDA and Decision Directed (DD) phase detectors. As those comparisons show, the proposed structure offers improved phaseerror variance performance that is robust to Automatic Gain Control (AGC) circuit imperfections. Moreover, the new detector has a compact hardware structure suitable for implementation within an FPGA or ASIC. The second phase detector structure presented is an adaptive detector whose principal novelty is that it dynamically adapts the phase detector’s gain to allow the PLL to perform optimally at any input Signal-to-Noise Ratio (SNR) at which it can lock. This detector is also robust vis-`a-vis the AGC and has a compact hardware implementation suitable for FPGAs and ASICs. Index Terms—AGC, automatic gain control, BPSK, carrier, coherent, detector, lock, loop filter, loop, MPSK, M-PSK, phase locked loop, phase shift keying, phase, phase, PLL, PSK, QPSK, receiver, signal to noise ratio, SNR, synchronization.



HIS paper discusses new practical phase detector structures for use in carrier synchronization PLLs in M-PSK receivers. Carrier phase error removal in M-PSK receivers is generally achieved via one of two techniques. The first method uses a feedforward phase estimator ([1 Chap. 5, 6], [2-11]) to estimate the phase error, and that estimate is then used to demodulate the received signal. The second method is the use of feedback ([1 Chap. 5, 6],[12],[13 Chap. 9], [14 Chap. 16], [15-22]) systems, which remove the carrier phase error using

Paper approved by C. Tepedelenlioglu, the Editor for Synchronization and Equalization of the IEEE Communications Society. Manuscript received July 18, 2007; revised November 14, 2007, April 22, 2008, and July 15, 2008. Y. Linn is currently a visiting professor on the Faculty of Electronic Engineering at the Universidad Pontificia Bolivariana, Km. 7 via a Piedecuesta, Bucaramanga, Santander, Colombia (e-mail: [email protected]). This paper was presented in part in Y. Linn, “A robust phase detection structure for M-PSK: theoretical derivations, simulation results, and system identification analysis,” in Proc. 18th Canadian Conference on Electrical and Computer Engineering (CCECE’05), Saskatoon, SK, Canada, May 2005, pp. 869-883. This work was supported by the National Sciences and Engineering Research Council of Canada (NSERC), and the Universidad Pontificia Bolivariana, Bucaramanga, Colombia. Digital Object Identifier 10.1109/TCOMM.2009.06.070342

a Phase Locked Loop (PLL) that ideally cancels the phase error between the local and received carriers. See [23 p. 7578] for a detailed discussion of the differences between the two approaches. In this paper we deal solely with coherent M-PSK receivers that utilize feedback in the form of a carrier synchronization PLL to remove the carrier phase error. MPSK carrier synchronization PLLs are tasked with eliminating the carrier phase error, an estimate of which is provided by a carrier Phase Detector (PD). There are two general categories of PDs: Non Data Aided (NDA) and Decision Directed (DD). The Mth -order nonlinearity detector and its modifications ([24 Chap. 6], [1 Chap. 5,6], [25 Chap. 5], [16]) and the multiphase NDA Costas loop and its modifications ([26], [25 Chap. 5], [15], [16]) are examples of NDA phase detectors. Examples of DD detectors can be found in [24 Chap. 6], [1 Chap. 5, 6], [27], [28], [29] and [30]. An inherent problem of DD detectors is that at low SNRs (and also during acquisition) they suffer from considerable self-noise due to erroneous decisions, which also affect their S-curves (see [1 Fig. 6-2], [27-29]). NDA detectors, while not vulnerable to decision errors, are nonetheless seldom used for higher order modulations since they have high self-noise (due to the high-order nonlinearities which they include) and their implementations are significantly more complicated than their DD counterparts (see [26 p. 74], [25 Fig. 5.54]). An additional problem afflicting the DD and NDA detectors just cited is that their gain is strongly linked to the AGC circuit’s operating point and performance. As we shall see, if the phase detector’s gain is not constant this implies that the carrier PLL’s characteristics will change accordingly, and hence a non-optimal AGC implies a similar lack of optimality of the carrier PLL. In this paper we shall present two new NDA phase detector structures for M-PSK carrier synchronization. The first structure will be a self-normalizing modification of the Mth -order nonlinearity detector which will allow the PLL to become independent of the AGC and also have improved phase-error variance performance. The second structure is an adaptive phase detector which will be shown to produce a constantgain detector during tracking, which allows the carrier PLL to maintain optimality at virtually any SNR at which it can lock. Unlike other NDA phase detectors, both the proposed structures have a compact implementation which is quite suitable for use within an FPGA or ASIC. This paper proceeds as follows. In Sec. II we outline the

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Fig. 1.

Simplified diagram of the M-PSK Receiver. Inset: equivalent nonlinear baseband model.

signal and receiver models. In Sec. III we define a family of self-normalizing NDA carrier phase detectors. In Sec. IV we review the accepted metrics and methods used in the evaluation of phase detector performance, which are then used in Sec. V in order to investigate the detectors which were presented in Sec. III. In Sec. VI we discuss why a constantgain phase detector is desirable, and in Sec. VII we present and investigate a family of adaptive M-PSK phase detectors which has such constant gain. In Sec. VIII we briefly discuss how the proposed phase detectors allow the requirements upon the AGC to be relaxed. Finally, Sec. IX is devoted to conclusions.




define the baseband signal as m(t) = a p(t − nT ), with p(t) being the baseband data n=−∞ n Δ ∞ Δ pulse (with energy Ep = −∞ p2 (t)dt) and an = exp (jφn ), We ∞




φn = 2π · mn /M , with mn ∈ {0, 1, ..., M − 1}. The Δ modulated signal is sm (t) = Re [m(t) exp(jωi t + jθi )] and that signal is corrupted by Additive White Gaussian Noise (AWGN). Fig. 1 shows a simplified diagram of the M-PSK receiver under discussion. In Fig. 1: 1) 1/T is both the symbol rate and the sampling rate. The signal is narrowband (i.e. ωi >> 1/T ), and the Nyquist criterion for zero-ISI [24 Sec. 9.2.1] is assumed to be obeyed regarding the output of the matched filters. 2) n(t) ∼ N (0, N0 W ) where W is the width of the bandpass IF filter (not shown). 3) K represents the physical gain associated with the circuit. In general, K is a slow function of time controlled by the AGC to achieve a desired signal level at the


sampler inputs. For a more detailed discussion see Appendix A. When the carrier loop is locked around a stable equilibrium point, we have Δω = 0 and (since M-PSK carrier synchronization has an inherent M-fold ambiguity [25 Sec. 5.7.6]) θo ∈ {θi + 2πk/M −θe | k = 0, 1, ..., M − 1}, where θe ∈ [−π/M, π/M ] is the phase error. Coherent M-PSK receivers overcome this ambiguity by precoding of the symbols [25 Sec. 5.7.6]. We thus assume without loss of generality that k = 0, i.e. we assume θe = θi − θo . Δ The matched filter h(t) is ideal (i.e. h(t) = p(−t)), and the sampling at the outputs of matched filters is considered to be at the ideal time (i.e. the symbol synchronization loop is assumed locked). Δ The ES =  ∞ symbol energy is2 [24 Sec. 4.1.1] ∞ 2 ≈ 1/2 −∞ p (t)dt = −∞ [p(t) cos (ωi t + θi )] dt 1/2E . Without loss of generality we assume for conp venience EP = 1 (implying ES = 1/2), and we use the notation χ to refer to the ES /N0 ratio (=SNR). We assume the carrier loop is a 2nd -order PLL, Δ with linearized response HP LL (s) = θo (s)/θi (s) = 2 2ζωn ·s+ωn where ζ is the damping ratio and ωn 2 s2 +2ζωn ·s+ωn (radians/sec) is the natural frequency [31 Sec. 2.2].

From Fig. 1 (see also [32 Sec. II]) we have that I(n) = K (2ES cos ( − Δω · nT + θi − θ0 + φn ) + nI (nT )) Q(n) = K (2ES sin ( − Δω · nT + θi − θ0 + φn ) + nQ (nT )) (1)

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where nI (nT ) and nQ (nT ) are white mutually uncorrelated white Gaussian processes distributed as follows: nI (nT ), nQ (nT ) ∼ N (0, 2N0 ES )


III. A S ELF - NORMALIZING NDA P HASE D ETECTOR – D EFINITION AND H ARDWARE S TRUCTURE A. Definition of Normalized Mth -Order Nonlinearity Detector The first of two new M-PSK phase detector structures presented in this paper can be thought of as a self-normalizing Δ modification of the Mth -order nonlinearity detector cM (n) = Im[(I(n) + j · Q(n))M ], defined as follows:

a dependence upon the dynamic range of K and the AGC still exists. For a more detailed discussion of the AGC and the parameter K, the reader is referred to Appendix A. See [23 p. 98-103] and [44] for a more detailed discussion of the advantages of the hardware implementation. Further analysis of dM requires some PLL modeling techniques, which are now presented. IV. P ERFORMANCE A NALYSIS OF PLL S – A B RIEF OVERVIEW A. Overview of Performance Metrics, the Nonlinear Model, and the Linearized Model

B. Preliminary Analysis of dM (n) and an Overview of its Hardware Realization

In this section we outline the PLL modeling techniques that we shall use to evaluate the proposed detectors. One of the most widely used PLL performance metrics [27 Sec I] is the phase-error variance var(θe ), or equivalently, the Δ loop-SNR ρ = 1/var(θe ) [34 eq. (3.3-7)]. This is because the phase-error variance has a crucial role in determining the cycle-slip rate of the PLL and the SER (Symbol Error Rate) degradation due to imperfect synchronization [25 p. 20-21, 210-211]. Determination of var(θe ) via simulations is easily done using nonlinear models (shown in inset of Fig. 1, Fig. 8), but the nonlinearity of the phase detector function presents great obstacles for theoretical analysis. To arrive at theoretical predictions, a standard approach adopted by synchronization texts (e.g. [1], [25]) is to assume that the PLL is locked and then analyze the linearized PLL model1 . In the following subsection, we briefly review this approach.

Rectangular-to-polar manipulations and DeMoivre’s theorem [33 eq. (6.9)] yields:

B. The Linearized PLL Model

dM (n)

M Δ ] = Im[(I(n)+j·Q(n)) 2 2 M/2 ⎛(I (n)+Q (n)) ⎞




M 2k + 1


⎠ (−1)k I M −2k−1 (n)Q2k+1 (n)


(I 2 (n)+Q2 (n))M/2


For example, for M=4 (QPSK) we have d4 (n) = (4I 3 (n)Q(n) − 4I(n)Q3 (n))/(I 2 (n) + Q2 (n))2 . To understand this detector intuitively, note that the denominator in (3) performs a normalization on the numerator (which is cM (n)). As we shall see, this normalization makes dM behave quite differently from cM , despite the notational similarity.






Im[(I(n) + j · Q(n)) ] = (I (n) + Q (n))

· sin (M ϕn ) (4) Δ where ϕn = tan−1 (Q(n)/I(n)) is the instantaneous received symbol phase. We then have: M

Im[(I(n)+j·Q(n))M ] (I 2 (n)+Q2 (n))M/2 (I 2 (n)+Q2 (n))M/2 sin(Mϕn ) = (I 2 (n)+Q2 (n))M/2


dM (n) = =

sin (M ϕn ) .


We see from inspection of (5) that dM ’s value is independent of K, and hence independent of the AGC. Moreover, dM (n) has an efficient fixed-point hardware implementation in the form of a lookup table; this is due to the small dynamic range that is needed to express dM (n) (since |dM (n)| = |sin (M ϕn )| ≤ 1). An example of such an implementation is shown in the bottom inset of Fig. 2. To see why the existence of such an implementation is significant, we note that other phase detectors suffer from a large dynamic range that often renders a similar implementation unfeasible. Consider cM (n): it is easily seen that cM (n) ∝ K M , so a phase detector lookup table and the ensuing datapath (in particular, the loopfilter) must all be able to handle the dynamic range of K M . This is often prohibitive to implement in fixed-point hardware. Moreover, the dependence on K M implies a nonlinear dependence upon the AGC. A similar conclusion applies to the DD Δ ˆ ˆ − Q(n) · I(n) detector, which is[27] DDM (n) = I(n) · Q(n) ˆ ˆ (where I(n) and Q(n) are the I and Q decisions). It is easy to show that DDM (n) ∝ K, so use of DDM (n) means that

To develop the linearized model, we define the following quantities for any phase detector P (n): Δ ∞ 1) BL = 0 |HP LL (j2πf )|2 df = 1/2ωn (ζ + 1/(4ζ)) is the loop’s noise bandwidth (see [31 p. 30-32]). Δ 2) The phase detector’s S-Curve [25 p. 206] is SP (θe ) = E[P (n) |θe ] , i.e. it is the average output of the phase detector given the phase error. 3) The linearized gain of P (n) (or simply the “gain” of P (n)) is defined as: Δ

gP (M, K, χ) = (∂SP (θe )/∂θe )|θe =0


Note in (6) that the gain generally depends on M, K, and χ (the SNR). It is common practice to normalize the gain so that it is unity at χ = ∞. Most synchronization texts also assume a constant K=1, whereupon the normalized gain is: Δ

αχ,P = gP (M, 1, χ)/gP (M, 1, ∞)


1 The SNR at which the nonlinear model results diverge from the linearmodel predictions is called the PLL’s lock threshold [34 Sec. 6.1]. Performance evaluation in the threshold region is beyond the scope of this paper and is not of interest for the following reasons : (a) the PLL performance in the threshold region is independent of the phase detector [1 p. 389] (although the location of the threshold is phase detector dependent); and (b) normal coherent receiver operation is always at least several dB above the threshold since this is a requirement for stable PLL lock to be achieved and for any error correction decoder to maintain lock for any useful amount of time.

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Fig. 2. S-curve of dM (n) for M=2 (BPSK), for various SNR ratios. ‘Predicted, Exact’ is Sd (θe ) = f2 (χ) · sin(2θe ), and ‘Predicted, Approx.’ is Sd (θe ) ≈ exp (−1/χ) sin(2θe ); see (20), (24). Bottom inset: efficient hardware generation of dM (n).

(note: since χ signifies the SNR (=ES /N0 ), we use the notations αSN R,P and αχ,P interchangeably). αSN R,P is called the amplitude suppression factor. However, as we show in Appendix A, despite its widespread use the assumption K=1 is usually not realistic. Hence, in this paper we assume that K is a function of the SNR, i.e. K = ΥAGC (χ) (see Appendix A), and we define the effective amplitude suppression factor, denoted βSN R,P , which (as we shall see later) is useful for incorporating AGC effects into the PLL model. Formally: Δ

βχ,P = gP (M, ΥAGC (χ), χ)/gP (M, 1, ∞)


(note: since χ signifies SNR, we use the notations βSN R,P and βχ,P interchangeably) 4) The normalized equivalent loop noise at θe ≈ 0 is defined as (using [1 eq. (6-73), p. 342] and normalizing): Δ

Ne,P (n) = lim (P (n) − SP (θe ))/gP (M, 1, ∞). (9) θe →0

5) The phase detector’s self noise is defined as (see [27 eq. (6)]) Δ (10) ξP = 2 · χ · var(Ne,P (n)). Note that when AGC effects are ignored then (9) and (10) are computed with K = 1 assumed. When AGC effects are modeled and βSN R,P is used as the gain in

the linear model, then (9) and (10) must be computed using K = ΥAGC (χ). 6) An important tool in evaluating a phase detector is its squaring loss [24 eq. (6.2-59)]. In terms of previous definitions, if we assume K = 1 the squaring loss is Δ Δ 2 ΩP = ξP /α2SN R,P , or ΩP = ξP /βSN R,P if modeling of the AGC’s effects is done via K = ΥAGC (χ) (the squaring loss is identical in both cases, since it is an inherent property of the phase detector). The linear model is shown in the lower left of Fig. 4. The phase-error variance is2 [28 eq. (21)] : var(θe ) = BL · T · ΩP /χ = 1/2ωn (ζ + 1/(4ζ)) · T · ΩP /χ


V. L INEAR -M ODEL AND N ONLINEAR -M ODEL A NALYSIS OF dM (n) We now investigate dM using the techniques presented in Sec. IV, with the aim of comparing dM to other phase detectors. Using the expressions for I(n) and Q(n) (given in 2 B in this paper contains a factor of 1/ w.r.t. its definition in [27]-[29]. 2 L This is to make the BL compatible with the more widely used definition, as used in [25], [34], [1], and [31]. However, note that (11) incorporates a compensating factor of 2 (w.r.t. [28 eq. (21)]).

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(1)) we define the instantaneous received symbol phase:  Δ ϕn = tan−1 Q(n) I(n)  (12) sin(−Δω·nT +θ +φ )+n (nT )/2E = tan−1 cos(−Δω·nT +θee +φnn )+nQI (nT )/2ESS

The S-curve is then3 :

Furthermore, we note that for any M-PSK constellation point φx = 2π · mx /M where mx ∈ {0, 1, ..., M − 1}:


sin(M (ϕn − φx )) = sin(M ϕn ) cos(2π · mx )


− cos(M ϕn ) sin(2π · mx ) = sin(M ϕn )



Hence, from (13) the value of dM (n) (which is sin(M ϕn ), see (5)) is not dependent upon the transmitted symbol but rather only on the phase difference between the instantaneous received symbol phase and the phase of any constellation point. Thus, we assume for simplicity φn = 0 for all n. When locked, Δω = 0, so we can reduce (12) to:   sin(θe ) + nQ (nT )/2ES ϕn = tan−1 . (14) cos(θe ) + nI (nT )/2ES Define the process: Δ

Δφn = ϕn − θe


where ϕn is given in (14). Now, from [35 Sec. 4.5] Δφn has a Rice phase probability density function (pdf): Δ

pR (Δφ|χ)   = p ( Δφn = Δφ| ES /N0 = χ) √ cos(Δφ)  2χ −y2 /2 √ e−χ χ·cos2 (Δφ) e dy = 2π 1 + 2χ cos (Δφ) e −∞

(16) where in (16) Δφ ∈ [−π, π]. Moreover, at high SNR we can arrive at an approximation for (16) that will be very useful later on. At high SNR, we have that Δφn is generally very small (i.e. pR (Δφ|χ) is non-negligibleonly for small Δφ),  2 ∞ and thus we can write (using (16) and 0 e−ax dx = 12 πa [33 eq. 15.72]): high SNR e−χ √   2 ≈ pR (Δφ|χ) 2π 2χ exp χ · cos (Δφ) ·  ∞ −y2 /2  2 dy ≈ χπ exp −χ (Δφ) −∞ e





fM (χ) = E[cos(M Δφn )] =

cos(M τ )pR (τ |χ)dτ . (21) In [36 eq. (7)] we evaluate fM (χ) where it is shown that √       π·χ I(M−1)/2 χ2 + I(M+1)/2 χ2 fM (χ) = 2 · exp −χ 2 (22) where Ik (•) is the k-th order modified Bessel function of the first kind [33 Chap. 24]. At high SNR, a useful approximation (21) in conjunction with (17) and  ∞ −axis2 attained using1  π −b2 /(4a) e cos(bx)dx = [33 eq. 15.73]: 2 ae 0 π fM (χ) = −π cos(M τ )pR (τ |χ)dτ high SNR  χ  ∞ (23) 2 ≈ π −∞cos (M τ ) exp(−χτ ) · dτ = exp −M 2 /(4χ) −π

Now, to arrive at the S-Curve, we substitute (22) into (20), which yields:    √   −χ  I(M−1)/2 χ π·χ 2  sin(M θe ) · exp 2 Sd (θe ) = 2 +I(M+1)/2 χ2 (24) We see from (24) that the S-Curve is sinusoidal in θe with, as is usual for M-PSK, M stable equilibrium points. We arrive at a useful approximation for the S-Curve by looking at high SNRs, and substituting (23) into (20), yielding: Sd (θe )

 high SNR  ≈ exp −M 2 /(4χ) sin(M θe )


S-Curve plots are shown in Fig. 2, where we see that the approximation of (25) is quite accurate (even at low SNR), hence making it a very useful tool for the designer for manually estimating the S-curve behavior. Linearized gain: The gain of dM is from (6), (20), and (24): gd (M, K, e )|θe =0 = M · fM (χ)  √χ) = (∂Sd (θe)/∂θ  χ  χ  π·χ −χ I + I =M· · exp (M−1)/2 (M+1)/2 2 2 2 2 (26) Moreover, a simple and useful engineering approximation for the gain is found by using (25) in (6), yielding: gd (M, K, χ)

high SNR ≈ M · exp(−M 2 /(4χ))


Amplitude suppression factors: the amplitude suppression factors are found from (7), (8), and (26):

A. Linear Model Parameters of dM S-curve: To arrive at the S-Curve of dM , recall from (15) Δ that Δφn = ϕn − θe so that ϕn = Δφn + θe and thus from (5): dM (n) = sin(M ϕn ) = sin(M (Δφn + θe )) = cos(M Δφn ) sin(M θe ) + sin(M Δφn ) cos(M θe ).



which means that for high SNR the process Δφn can be considered to be Gaussian with the following distribution: Δφn ∼ N (0, 1/(2χ))


Sd (θe ) = E[dM (n) |θe ] = E[cos(M Δφn )] sin(M θe ) + E[sin(M Δφn )] cos(M θe ) = fM (χ) sin(M θe )


βχ,d = αχ,d = fM (χ) √       π·χ I(M−1)/2 χ2 + I(M+1)/2 χ2 = 2 · exp −χ 2


3 Here and onwards we use subscript “d” for variables that pertain to dM (n). Similarly, subscript “c” is used for variables that pertain to cM (n), subscript “DD” for DDM (n), and “V” for variables that pertain to VM,N (n) (which is defined in Sec. VII).

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Fig. 3. Bottom part, right Y-axis: Squaring loss as a function of ES /N0 . Top part, left Y-axis: Simulated var(θe ) (and associated calculated CRB), simulated using nonlinear model in inset of Fig. 1. Also shown are linear-model theoretical predictions for dM (n) using the model in bottom left of Fig. 4 (”no AGC”). At each SNR the loop-filter’s gain Ka is selected such that ζ = 0.95. and ωn = 8.24 · 10−3 /T , which ensures that 2BL T = ωn (ζ + 1/(4ζ)) · T = 0.01 at each SNR. AGC effects are ignored (i.e. K = 1). The SNRs below which nonlinear model var(θe ) increases dramatically for M=8 and M=16 are the PLL lock thresholds.

Furthermore, we arrive at useful approximations for the amplitude suppression factors by using (7), (8), and (27): βχ,d = αχ,d

high SNR   ≈ exp −M 2 /(4χ)


Eq. (29) is a useful approximation for use by the engineer for quick manual computations when designing the PLL. The Loop noise, self noise, and squaring loss: loop noise is easily found from (19) and (9) to be Ne,d (n) = 1/M · sin(M Δφn ). Observe that Ne,d is not Gaussian, though it may be approximated by Gaussian noise at high SNR, since from (18) we have high χ χ→∞ Ne,d (n) → Δφn ∼ N (0, 1/(2χ)). The self noise of dM is from (10): ξd = 2χ · var(Ne,d (n)) π = 2χ −π (1/M sin(M τ ))2 pR (τ |χ) · dτ π 2χ =M (1/2 − 1/2 cos(2M τ )) pR (τ |χ) · dτ 2 −π χ = M 2 (1 2M (χ))  − f√   −χ χ χ π·χ χ 2 = M2 1 − 2 · e I 2M−1 2 + I 2M+1 2 2


(30) 2 and the squaring loss Ωd = ξd /α2SN R,d (= ξd /βSN R,d ) is readily found using (30) and (28). B. Quantitative Comparison of dM ’s Predicted Performance to that of Other Phase Detectors Having developed the linear model for dM , we can now predict dM ’s performance. The amplitude suppression factors are shown in Fig. 6 and Fig. 7 (which are discussed in depth in Secs. VI-VII). Squaring loss comparison vs. other detectors is shown in Fig. 3. Linear-model predictions of phase-error

variance performance can be made via (11) and are shown for dM in Fig. 3, with ζ = 0.95 and ωn = 8.24 · 10−3 /T fixed at all SNRs so that 2BL T = 0.01 at all SNRs. Finally, also plotted in Fig. 3 are nonlinear model simulation results and the Cram´er-Rao Bound (CRB) [1 eq. (6-108)]: CRB = BL · T /χ = 1/2ωn (ζ + 1/(4ζ)) · T /χ


As seen in Fig. 3, the predictions of the linear model are in excellent agreement with the nonlinear simulations anywhere above the PLL’s lock threshold, and dM provides excellent performance and hence is a very viable phase detector. VI. T HE C ASE FOR A C ONSTANT-G AIN P HASE D ETECTOR In Fig. 3 (top) we have 2BL T = ωn (ζ + 1/(4ζ)) · T = 0.01 at all SNRs. This is achieved by using a different loop-filter gain at each SNR so that ζ = 0.95 and ωn = 8.24 · 10−3 /T . Maintaining ζ and ωn constant at all SNRs is the practice adopted in most texts (e.g., [1], [25]) since it facilitates a meaningful comparison of var(θe ) achievable by the compared phase detectors when they are employed in PLLs that have identical parameters. However, it is important to note that constant ζ and ωn cannot be maintained by a PLL with a fixed (=non-adaptive) loop-filter gain and which uses either DDM , cM , or dM . Consider, for example, in Fig. 3 (top) the PLL for QPSK (M=4) which employs DDM . Let us use the notation Ka,DD (ρ) to refer to the loop-filter gain at ES /N0 = ρ. Now, from [27]-[29] we know that if the loop-filter gain needed to achieve ζ = 0.95 and ωn = 8.24 · 10−3 /T in noiseless conditions is Ka,DD (∞), then to maintain the same ζ and ωn at ES /N0 = χ we must have Ka,DD (χ) = Ka,DD (∞)/αχ,DD if AGC effects are ignored by assuming K = 1 (as done

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Fig. 4. Calculated var(θe ) using linearized model (shown in lower left of this figure) when AGC effects are ignored and when AGC effects are modeled. Modulation is QPSK (M=4). Optimization SNR is λ = 5 dB. Note that in the linearized model (lower left) the loop noise Ne is computed differently for the “w. AGC” and “no AGC” cases (see Sec. IV). Also, when AGC effects are ignored, then the loop-filter’s gain Ka is selected at each SNR such that ζ = ζopt = 0.95 and ωn = ωopt = 8.24 · 10−3 /T at each SNR. When AGC effects are modeled, Ka is constant and is selected so that at ES /N0 = 5 dB the PLL has ζ = ζopt = 0.95 and ωn = ωopt = 8.24 · 10−3 /T (since Ka is constant, this will not hold at other SNRs; rather, changes will occur as per (32)).

in [27]-[29]). Moreover, Appendix A shows that to assume K = 1 is unrealistic and AGC effects must be modeled, and it is easily shown that in practice at ES /N0 = χ actually we must have Ka,DD (χ) = Ka,DD (∞) · β∞,DD /βχ,DD . Thus, when inspecting Fig. 3 (top) it is important to realize that since the loop-filter’s gain is different at each SNR, the results for a given phase detector cannot be obtained using a single PLL with a fixed loop-filter gain. The correct way to interpret Fig. 3 (top) (and similar graphs in texts such as [1] and [25]) is hence by considering the results at each SNR as if they were obtained by measurements on PLLs unique to that SNR that were optimized for operation at that SNR to  yield ζ = 0.95 and ωn = 8.24 · 10−3 T . Indeed, as noted earlier, a single PLL with a fixed loop-filter gain and which uses cM , DDM or dM cannot maintain constant ζ and ωn over the entire SNR range; rather, the desired values will be attained only at a single SNR which we call the optimization SNR. When we are not operating at the optimization SNR the PLL will observe changes in ζ and ωn that will cause changes in all of the PLL’s parameters, e.g. the noise bandwidth BL = 1/2ωn (ζ + 1/(4ζ)), the settling time Tset ≈ 2π/ωn , the lock range ΔωL , the pull-out range ΔωP O , and the cycle-slip statistics ([37 Chap. 2],[1 Sec. 6.4],[34 Chap. 6],[27]-[29]). To quantify this effect, suppose we use a phase detector P (n) in a PLL that has a fixed-gain loop-filter, and that the PLL is designed for operation at ES /N0 = λ (the “optimization SNR”) with the optimal parameters ωopt and ζopt (e.g., λ might be the lowest SNR at which the error correction decoder

provides an acceptable coding gain). It can be shown [38 Sec. 9.1] that, accounting for AGC effects, at ES /N0 = χ the natural frequency ωnχ and damping ratio ζχ will be:

ωnχ = ωopt

  βχ,P /βλ,P and ζχ = ζopt βχ,P /βλ,P


Thus (assuming βχ,P increases monotonically vs. χ) we conclude from (32) that for χ > λ we have higher-thanoptimal ζ and ωn , and for χ < λ we have lower-thanoptimal ζ and ωn . Only at χ = λ does the PLL perform as desired. To illustrate this phenomenon and its effect upon the PLL we present in Fig. 4 phase-error variance results and CRBs, computed via (11) and (31). Clearly, the variation of ζ and ωn due to the AGC profoundly affects the PLL. Note that at low SNR the AGC appears to cause a reduction in var(θe ), but it would be fallacy to say that this is a positive effect, since this reduction is due to the reduction of ζ and ωn , which has a detrimental effect on the PLL’s stability, lock range, pull-out range, etc., as outlined in the previous paragraph. From (32) it follows that to achieve the parameters ωopt and ζopt at all SNR, the phase detector must have βSN R,P = 1 (implying constant gain vs. the SNR since from (8) gP (M, K, χ) = gP (M, 1, ∞)·βχ,P ). We now present such a detector.

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Fig. 5.


Fixed-point hardware implementation of VM,N (n).

VII. A N A DAPTIVE P HASE D ETECTOR A. Definition, Principle of Operation, and Hardware Implementation The second phase detector presented in this paper is an adaptive detector that will be shown to have unity gain during tracking, hence allowing for optimal4 loop parameters to be maintained at all SNRs where the PLL can lock (see discussion in Sec.VI). The idea behind this adaptive detector is simple: if we somehow estimate gd in real-time, and divide dM (n) by this estimate, we arrive at a constant-gain detector. Fortunately, this is easy to do. First, we define Δ Re[(I(n)+j·Q(n))M ] (I 2⎞ (n)+Q2 (n))M/2

xM (n) = M/2 



⎛ ⎝

M 2k

⎠ (−1)k I M −2k (n)Q2k (n)


(I 2 (n)+Q2 (n))M/2

Similar to the derivation of (5), it is easy to show that xM (n) = cos (M ϕn ). A carrier lock detector is defined simΔ 1 0 ilar to [32], [11 Sec. V] via ˆlM,N = 2N n=−2N +1 xM (n), and it is easily shown [32 Sec. IV] that when the PLL is locked: E[ˆlM,N ] = E[xM (n)] = E[cos(M ϕn )] = E[cos(M (Δφn + θe )] = E [cos (M Δφn )] E [cos (M θe )] − E [sin (M Δφn )] E [sin (M θe )] (34)



= E [cos (M Δφn )] E [cos (M θe )] = fM (χ)E [cos (M θe )] When in lock, to a very good approximation E[cos(M θe )] ≈ 1 (see [32 Sec. IV]), and hence from 4 In some systems, the optimal value of ω will be dependent upon the SNR n [38 Chaps. 7, 8]. Nonetheless, even in such systems the desired variation of ωn in general will not correspond to the variation caused by the changing phase detector gain. Hence, in this case as well, we would like to have a constant-gain phase detector, and the modification of ωn would be done via changing the loop filter coefficients as a function of the SNR (with the aid of an SNR estimation algorithm such as in [43]-[47]).

(34) and using the fact that any random variable is an unbiased estimate of its expectation we arrive at: ˆlM,N ≈ E[ˆlM,N ] = fM (χ) E [cos (M θe )] ≈ fM (χ)



Eq. (35) combined with (26) and (28) reveals that, when in lock, ˆlM,N ≈ fM (χ) = αχ,d = βχ,d = (1/M )gd . Thus, recalling the discussion at the beginning of this  Δ section, if we define VM,N (n) = dM (n) (M · ˆlM,N ), such a phase detector should have unity gain, i.e. it should have gV ≈ 1. When out of lock, ˆlM,N ≈ 0 (see [32]) so an appropriate value μ needs to be substituted for ˆ lM,N in the expression for VM,N (n) in order to achieve acceptable performance during acquisition (μ is discussed further in Sec. VII-D). We hence define the adaptive phase detector as follows: Δ

= dM (n)/(M · δ) VM,N (n)  ˆlM,N if carrier is locked with δ = μ if carrier is unlocked


A fixed-point hardware implementation structure for VM,N (n) is presented in Fig. 5. We now make several observations regarding the efficiency of such an implementation. First, observe how the division by 2N is avoided, where it is assumed that 2N is a power of 2 (see also [32 Sec. III-B]). Secondly, the Integrate-and-Dump averager is a very simple module [39 Fig. 18] that is little more than a carefully controlled accumulator [39 Sec. 9]. Finally, with regards to the LUTs (Lookup Tables): the implementation of LUT #1 was discussed in [32], and implementation of LUT #2 was discussed in Sec. III-B. There it was shown that LUTs #1 and #2 can be efficiently realized in fixed-point hardware. As for LUT #3, observe that the lowest value of ˆ lM,N that need be handled is the lock threshold value, since below this value μ is used. Hence the largest absolute value that LUT #3 needs to accommodate is (sup |dM (n)|)/(M · min{μ, γ}) = 1/(M · min{μ, γ}), with γ being the lock threshold. Typically, μ ≥ γ (see Sec. VII-D) and neither parameter would

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be less than about 0.04, since below that value the SNR is so low that there is scarcely hope of the PLL locking [32 Fig. 3]. This means that 1/(M · min{μ, γ}) ≤ 25/M , and thus the dynamic range of the data in LUT #3 can be sufficiently limited to allow for its compact fixed-point hardware implementation. To conclude this subsection, we have shown that VM,N (n) can be implemented compactly in fixed-point hardware.

B. Linear modeling of VM,N The linear model analysis of VM,N shall now be done by relying on the analysis in Sec. V regarding dM . S-curve, gain, and amplitude suppression factors: Assuming that the loop is locked, from (19) and (36): dM (n) n) = sin(Mϕ M·ˆ lM,N M·ˆ lM,N cos(MΔφn ) n) sin(M θe ) + sin(MΔφ M·ˆ lM,N M·ˆ lM,N

VM,N (n) = =

cos(M θe ).


Fig. 6. αSNR for the detectors discussed in this paper. Data pertaining to cM was obtained from [16, 25], and for DDM is taken from [27-30].

To find the linear-model parameters of VM,N , we choose to treat ˆlM,N as a constant. This is justified by noting that ˆlM,N changes significantly slower than dM (n) (slower by a factor of 2N, which typically would be at least in the order of 100 (Sec. VII-E, [32 Sec V])). With that assumption and since E[sin(M Δφn )] = 0, from (37) the S-curve is Δ

SV (θe ) = E[VM,N (n)|θe ] = E[cos(M Δφn )] sin(M θe )/(M · ˆ lM,N ) ˆ = (fM (χ)/(M · lM,N )) · sin(M θe )


and it is easy to show from (38) and (6)-(8) that gV (M, K, χ) = αχ,V = βχ,v = fM (χ)/ˆlM,N . The central idea is that ˆlM,N ≈ fM (χ) so that gV (M, K, χ) = αχ,V = βχ,v ≈ 1. It is stressed that for all M we have that gV , αSN R,V , and βSN R,V are approximately equal to 1 independent of (a) the value of K and the AGC’s performance, and (b) the SNR. Fig. 6 - Fig. 7 show αSN R and βSN R for the various phase detectors, where we see that the AGC’s effect upon DDM and cM is quite pronounced. Since only VM,N has a constant βSN R , only VM,N will be able to maintain optimal loop parameters at all SNRs. Loop noise, self noise, and squaring loss: Once again treating ˆ lM,N as a constant approximately equal to fM (χ), we see that the only random process in (36) is dM (n). Thus, the squaring loss of VM,N should be identical to that of dM . Formally, it is easily shown from (9), (10), (35)-(38) that Ne,V ≈ 2 Ne,d /fM (χ), ξV ≈ ξd /fM (χ), and (since αχ,V = βχ,v ≈ 1) 2 2 (χ) = Ωd . Hence, since that indeed ΩV ≈ ξV /1 ≈ ξd /fM ΩV ≈ Ωd from (11) we conclude that dM and VM,N have the same phase-error variance performance, but with the important difference that results for VM,N can be achieved using a fixed-gain loop-filter (see Sec. VI). Nonlinear-model simulations presented in the next subsection verify these predictions. As a caveat, we note that the delay 2N · T incurred during the computation of ˆ lM,N must not substantially impact the validity of the approximation ˆlM,N ≈ fM (χ) when that value is used to compute VM,N (n). In Sec. VII-E, it is shown that a

Fig. 7. βSNR for the detectors discussed in this paper. We assume that the AGC is as described in Appendix A. Also plotted is the AGC curve (i.e. K = ΥAGC (ES /N0 )). Data pertaining to cM was obtained from [16, 25], and for DDM is taken from [27-30].

relatively small N is required5 to achieve good performance over practical SNRs, so the delay is inconsequential for most systems. This is particularly true where the symbol rate is high compared to the channel fading rate, which is usually a good assumption if suppressed-carrier coherent M-PSK is the chosen modulation ([40], [41], [25 p. 250]), and an excellent assumption for geosynchronous microwave satellite links [42 Chap. 4]. Nonetheless, this constraint must be taken into account when deciding if usage of VM,N is appropriate. C. Nonlinear-model Simulations for VM,N To validate the linear-model predictions of the previous subsection regarding the performance of VM,N , simulations 5 Another constraint exists for N, namely that the lock and false-alarm probabilities are attained ([32 Sec. V]). If this constraint conflicts with Sec. VII-E, the Integrate-and-Dump module in Fig. 5 can be duplicated, with a different N being used in each module. One module would be used to generate ˆ lM,N for lock detection (and for the MUX “sel” input), while the other would be for the “1” input to the MUX.

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Fig. 8. var(θe ) for QPSK and 16-PSK obtained via nonlinear-model simulations including AGC effects. K behaves according to the AGC of Appendix A. For VM,N , N = 256 was chosen.

were conducted via the nonlinear equivalent baseband model, assuming the AGC of Appendix A. This is shown in Fig. 8. In Fig. 8, Ka is constant and is selected so that at the optimization SNRs (which are 5 dB, 17.5 dB for QPSK and 16-PSK, respectively) the PLLs have ζ = ζopt = 0.95 and ωn = ωopt = 8.24 · 10−3 /T . Since Ka is constant while βSN R,DD and βSN R,c vary (see Fig. 7), then ζ = ζopt and ωn = ωopt is not true at other SNRs for the loops employing DDM and cM ; rather, changes will occur as per (32). However, for the PLLs employing VM,N , since βSN R,V ≈ 1 at all SNR we do have ζ = ζopt and ωn = ωopt at all SNR. Note that DDM appears to outperform VM,N at low SNR; but this is a fallacy, since this is due to the reduction of ωn and ζ in the PLLs that use DDM . As predicted earlier, the results for VM,N agree with those in Fig. 3 (top) for dM (but with the crucial difference that VM,N achieves these results with a fixed-gain loop filter). By contrast, comparing Fig. 3 (top) to Fig. 8, the AGC affects cM and DDM profoundly, as per (32). D. Unlocked-state Operation of VM,N From (36), VM,N will exhibit behavior identical to that of dM during acquisition, as it is simply dM (n) multiplied by the constant 1/(M · μ). The gain of VM,N is then gV (M, K, χ) = gd /(M · μ) = fM (χ)/μ. To maintain the optimal loop parameters during acquisition, we strive to have gV = 1, implying that we should aspire for μ = fM (χ). An algorithm for deciding upon an appropriate μ would try, for example, to determine the latter either by: (a) using a worst case value (i.e. the value of fM (χ) for the lowest SNR for which operation is desired), (b) using the last measured value of ˆlM,N when

the receiver was locked (because E[ˆlM,N ] ≈ fM (χ), see (35)), or (c) using some carrier-independent SNR estimation technique (e.g., see [43], [44], [45], [46], [47]) to determine χ and then compute fM (χ). It is important to note that performance during acquisition is only partially addressed by using a constant μ, due to the fact that, since fM (χ) varies with the SNR yet μ is constant, gV = fM (χ)/μ will vary vs. the SNR. E. Bounds on N to Ensure Satisfactory Tolerances in PLL Parameters In previous subsections we found that to maintain optimal PLL parameters we desire βχ,V = 1 identically, which, since βχ,V = fM (χ)/ˆlM,N , means that we strive that ˆlM,N = fM (χ). The way to achieve acceptable accuracy of ˆlM,N ≈ E[ˆlM,N ] = fM (χ) is by ensuring that ˆlM,N ’s variance is low enough, which, using var(ˆlM,N ) ≤ 1/(2N ) [32 Sec. III-D] means choosing a high enough N . Denoting the optimal ωn and ζ as ωopt and ζopt , we want to achieve them at all χ ∈ [Γ, ∞] where Γ is some reasonable lowest SNR (e.g., lock threshold SNR). It can be shown [23 Sec. 3.6.8] that to ensure P (|ωnχ /ωopt − 1| < tol) > C and P (|ζχ /ζopt − 1| < tol) > C for χ ∈ [Γ, ∞] (tol=tolerance,C=confidence) it suffices that   2 N > 1/fM (Γ) · 2  erf −1 (C) min{|((1−tol)−2 −1)|, |((1+tol)−2 −1)|}

Thus, small N is needed to guarantee optimal parameters for reasonable SNRs (e.g., N=256 to ensure tol=20% C=85% for SNRs above –2, 4, 10, and 16 dB for M=2, 4, 8, 16).

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VIII. R ELAXATION OF R EQUIREMENTS UPON THE AGC C IRCUIT As another advantage of the proposed structures, we note that the requirements on the AGC for a PLL employing dM or VM,N can be relaxed, since there is no dependence of the phase detector’s gain upon K. The are two limitations on this. First, the AGC must ensure that the samplers and the preceding signal chains are not saturated. Secondly, the signal-levels must span enough sampler bits so that quantization noise does not cause unacceptable degradation. These loose constraints significantly relax the requirements imposed upon the AGC as compared to a PLL that uses cM or DDM , where to produce the planned phase detector gain K must be maintained within a tight range (see also Appendix A).

range and an infinite number of quantization bits. Clearly, the AGC discussed here (though still “ideal”) is a much closer approximation of reality. For more analysis see [44] and [23 Sec. 1.5]. ACKNOWLEDGMENT The author would like to thank the National Sciences and Engineering Research Council of Canada (NSERC) and the Universidad Pontificia Bolivariana (UPB), Bucaramanga, Colombia, for their financial support. In particular, the author thanks Prof. Alex A. Monclou and Prof. Sayra M. Cristancho from the UPB. Furthermore, the author would like to thank the editor Prof. Cihan Tepedelenlioglu for his diligent handling of the manuscript editorial process.

IX. C ONCLUSIONS In this paper we presented and investigated two new families of M-PSK NDA carrier phase detectors for operation in carrier synchronization PLLs. First, a new family of selfnormalizing phase detectors dM (n) was proposed, and its properties analyzed - first theoretically via linear modeling and then verified through simulations of the nonlinear model. Next, we investigated an adaptive phase detector structure for M-PSK, which we denoted VM,N (n). The major novelty of VM,N (n) is that it has a constant gain during tracking, which allows the carrier PLL to maintain optimal parameters at any SNR at which it can attain lock; it is emphasized that these optimal parameters are maintained even though the PLL has a fixed (i.e. non-adaptive) loop filter. Both new families of detectors were shown to possess self-normalizing qualities that simplify the receiver design by significantly decoupling the AGC circuit from the carrier synchronization PLL, and both have a compact fixed-point hardware implementation that is suitable for use within an FPGA or ASIC. X. A PPENDIX A: T HE AGC’ S O PERATION AGC circuits are strongly dependent upon the specific communications system, and so most texts ignore AGC effects (by assuming a constant K = 1). Yet, as this paper shows, the AGC has a profound interaction with the carrier PLL. To understand this interaction, we treat AGC effects in this paper through an example AGC. The AGC’s purpose is to control the signal levels at the samplers so that they are neither underdriven nor overdriven. Our example AGC attempts to control the pre-sampler signal level RMS (Root Mean Square) value to 80% of the samplers’ full-scale voltage range. It can be shown that the AGC curve K = ΥAGC (ES /N0 ) is as shown in Fig. 7. Moreover, if we were to plot ΥAGC (ES /N0 )/ΥAGC (∞) it can be shown that our AGC corresponds to the squarelaw AGC behavior given in [34 Fig. 7.2-5]. It is important to realize that we are still assuming an ideal AGC, i.e. our example AGC is assumed to be devoid of lag time and is assumed to control the RMS of the pre-sampler waveforms to precisely 80% of the samplers’ dynamic range. The assumption of K = 1, though undertaken in the vast majority of synchronization texts (e.g. [1], [25], [27]) describes not an ideal AGC, but rather an atrophied AGC which operates within a system whose samplers have an infinite dynamic

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[39] Y. Linn, “A methodical approach to hybrid PLL design for high-speed wireless communications,” in Proc. 8th IEEE Wireless and Microwave Technology Conf. (WAMICON 2006), Clearwater, FL, Dec. 2006. [40] B. Sklar, “Rayleigh fading channels in mobile digital communication systems—part I: characterization,” IEEE Commun. Mag., vol. 35, no. 9, pp. 136-146, Sept. 1997. [41] B. Sklar, “Rayleigh fading channels in mobile digital communication systems—part II: mitigation,” IEEE Commun. Mag., vol. 35, no. 9, pp. 148-155, Sept. 1997. [42] M. M. J. L. van de Kamp, “Climatic radiowave propagation models for the design of satellite communication systems,” Ph.D. thesis, Technische Universiteit Eindhoven, The Netherlands, 1999. [43] D. R. Pauluzzi and N. C. Beaulieu, “A comparison of SNR estimation techniques for the AWGN channel,” IEEE Trans. Commun., vol. 48, no. 10, pp. 1681-1691, Oct. 2000. [44] Y. Linn, Synchronization in Coherent M-PSK Receivers: Carrier Synchronization, Phase Detection, Lock Detection, and SNR Estimation, book, to be published. [45] G. Ping and C. Tepedelenlioglu, “SNR estimation for nonconstant modulus constellations,” IEEE Trans. Signal Processing, vol. 53, no. 3, pp. 865-870, Mar. 2005. [46] Y. Linn, “A real-time SNR estimator for D-MPSK over frequency-flat slow fading AWGN channels,” in Proc. 2006 IEEE Sarnoff Symposium, Princeton, NJ, Mar. 2006. [47] Y. Linn, “A carrier-independent non-data-aided real-time SNR estimator for M-PSK and D-MPSK suitable for FPGAs and ASICs,” IEEE Trans. Circuits and Systems I, in press. Yair Linn (M’01) received his B.Sc. (with honors) in computer engineering from the Technion Israel Institute of Technology, Haifa, Israel, in 1996. In the years 1996-2001 he was employed as an electrical engineer in the Israeli Ministry of Defense, where he worked with the development, implementation, and deployment of wireless communications systems. From January 2002-July 2007 he completed the Ph.D. degree in electrical engineering at the University of British Columbia, Canada. He is currently a visiting professor in the faculty of electronic engineering at the Universidad Pontificia Bolivariana, Bucaramanga, Colombia. Dr. Linn was awarded the Jean MacDonald Graduate Fellowship scholarship as a winner of the University Graduate Fellowship competition at UBC in 2002. In April 2003, he was awarded a postgraduate scholarship by the National Sciences and Engineering Research Council of Canada (NSERC), as a winner of the 2003/4 NSERC Postgraduate Scholarship Competition. In April 2005, he was awarded an NSERC Canadian Graduate Scholarship as a winner of the 2005/6 NSERC Postgraduate Scholarship Competition. In November 2005 he was awarded the Bell Canada 125th Anniversary Graduate Scholarship. In May 2007 he was awarded Best Paper prize at the Wireless Telecommunications Symposium, Pomona, CA. Dr. Linn’s research interests include synchronization in wireless receivers, estimation of wireless channel parameters, and implementation of real-time digital signal processing algorithms in FPGAs.

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Robust M-PSK Phase Detectors for Carrier ...

[15-22]) systems, which remove the carrier phase error using. Paper approved by C. ... gain detector during tracking, which allows the carrier PLL to maintain ... from IEEE Xplore. Restrictions apply. ...... Princeton, NJ, Mar. 2006. [47] Y. Linn, “A ...

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