Integrated Routing and Fill for Self-Aligned Double Patterning (SADP) Using Grid-Based Design Youngsoo Songa b , Jeemyung Leea , Seongmin Leeb , and Youngsoo Shinb a Samsung

b School

Electronics, Hwasung 445-701, Korea of Electrical Engineering, KAIST, Daejeon 34141, Korea

ABSTRACT Self-aligned double patterning (SADP) has been proposed as an alternative patterning solution for sub-10nm technology because of delay of advanced lithography beyond 193nm ArF. In conventional SADP, line and space style of dummy metal fills are inserted once main design is complete. A large buffer distance is required around the main design because no further verification of main design (in presence of fills) is performed. This causes irregular pattern density, which becomes a source of process variations. We propose integrated-fill, in which main design and dummy fill insertion are performed together. This requires a change in overall design flow, which we discuss. Integrated-fill is demonstrated in M2 layer of SADP process; M2 density increases by 15.7% with 2.3% reduction in standard deviation of density distribution; metal thickness variation is also reduced by 24%. More dummy fills cause increased coupling capacitance, which however is shown to be insignificant.

1. INTRODUCTION A shrinking feature size causes difficulty in manufacturing integrated circuits, particularly in lithography process. Multiple patterning technique, specifically litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP), has been proposed as a solution in sub 10nm and below.1–3 As shown in Figure 1(a), LELE prints metal patterns of very small pitch using two masks; each metal pattern now belongs to one of the two groups (through a process named coloring) with slight overlap, called stitch. Metal patterns of different colors are printed via different masks, and lithography and etch are performed independently. Pattern overlay problem occurs in LELE process when the second mask is misaligned from the first, which results in degradation of chip performance and yield. SADP is a more complex process by using mandrel, trim, and block masks. Conventional SADP process is illustrated in Figure 1(b). For a given main design, mandrel is determined without any conflicting point; selfaligned sidewall spacers are formed by mandrel etch-back; unnecessary spacers are removed by using a block mask; required area to wide patterning is filled by trim mask as a post process; finally, the remaining spacers are etched to the substrate, which leaves the final metal wires. Due to the advantage of self-aligned process, SADP can pattern pitch smaller than LELE can and is free from lithography limitations, forbidden pitch, and mask misalignment. In SADP, a conventional method of dummy fill insertion is to insert line and space style of dummy fills; it is performed once main design is complete just as in usual design process. Since main design has been completed and verified, the impact of dummy fills on main design cannot be further verified; hence, a large buffer distance is required. This causes irregular pattern density, which in turn results in metal thickness variation. We propose integrated-fill, in which main design and dummy fill insertion are performed together. This requires a change in overall design flow, which we discuss. Design-Process-Technology Co-optimization for Manufacturability X, edited by Luigi Capodieci and Jason Cain Proc. of SPIE Vol. 9781, 978105 © 2016 SPIE · CCC code: 0277-786X/16/$18 · doi: 10.1117/12.2219142 Proc. of SPIE Vol. 9781 978105-1 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 03/23/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

Main design

Coloring (Stitch)

Mask1 (Litho-Etch)

Mask2 (Litho-Etch)

Metal pattern

(a) Mandrel

Spacer

Block mask

Main design

Mask1 Mandrel & Spacer (Litho-Etch)

Mask2 Block mask (Litho-Etch)

Cut mask

Mask2 Trim mask (Litho-Etch)

Metal pattern

(b)

Figure 1. Comparison of (a) LELE and (b) SADP process.

The remainder of this paper is organized as follows. In Section 2, we propose a new design flow with integrated-fill. Evaluation of integrated-fill is presented in Section 3, in which we discuss the effectiveness of the proposed fill method in terms of metal density and total capacitance compared to conventional method. Conclusions are drawn in Section 4.

2. INTEGRATED-FILL 2.1 Motivation In CMP process, metal density affects metal thickness by dishing effect, which in turn changes coupling capacitances and circuit delay.4, 5 To avoid a large on-chip variation in circuit performance, dummy fill is used to make a uniform metal density in chip area. An example of conventional dummy fill, denoted by post-fill, is shown in Figure 2(a). Since fill insertion is performed after timing sign-off, designers cannot consider the effect of dummy fill on coupling capacitance in design stage. To avoid the change of timing, dummy fill needs large distance to main design (see A region), which degrades the uniformity of metal density. Some dummy fills cannot even be inserted between metals due to a large buffer distance (see B regions). If line-end of main pattern is misaligned from the other, trim or block process needs irregular shape that is not easily processed (see C region).

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C

B

Main design Dummy fill B

A

Main design (a)

Cut

1-D grid array

Main design (b)

Figure 2. Dummy fill insertion in (a) post-fill and (b) integrated-fill.

The proposed integrated-fill overcomes the limitations of post-fill, as shown in Figure 2(b). One dimensional layout is assumed, and cut is performed where main design and dummy fill are defined. Since dummy fill and main designs are formed concurrently, the effect of dummy fill on coupling capacitance can be reflected in circuit design, which implies that we can aggressively reduce buffer distance, which in turn brings about a uniform metal density.

2.2 Design Flow In post-fill design flow, layout of main design is completed without dummy fill; parasitic extraction (PEX), static timing analysis (STA), and engineering-change-order (ECO) are performed to check the timing and remove any timing violations. After timing sign-off, dummy fill is inserted to satisfy the density rule in design rule check (DRC). To minimize the impact of dummy fills on main design, post-fill sets a large buffer distance between main design and dummy fill as we mentioned in Section 2.1.

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Grid-based array

Layout design ECO

PEX, STA Yes

No Metal fill

Layout design

ECO

Array cut Density, PEX, STA Yes

No

DRC (density)

DRC (density)

Fabrication

Fabrication

(a)

(b)

Figure 3. Design flow of (a) post-fill and (b) integrated-fill.

In integrated-fill design flow, main design is imported and overlapped with the array after gridbased array of one dimensional layout is assumed. Grid-based array, which has no intersection with main design, will be defined as the area of dummy fill; this also allows us to define cut locations. Since dummy fill is identified in circuit design, we may reflect the effect of metal thickness variation from metal density in circuit design; we calculate coupling capacitances by considering the change of metal thickness from metal density, and analyze timing using the capacitance. If timing violation occurs, we perform ECO by modifying dummy fill as well as main design. The key difference between the two design flows is whether it considers the effect of dummy fill on main design or not.

2.3 Main Design Modification SADP process consists of mandrel, trim, and block masks; it prefers regular patterns, which are favorable to process. In two dimensional layout, undesirable patterns may happen in performing trim or block process, and the way to resolve these problem is introduction of coloring mask by decomposition tool or limitation by design rule for complex layout to be expected. This is the reason why one dimensional design layout is more suitable for SADP process. Less complicated one dimensional layout can reduce the degree of process difficulty and minimize the uncertainty in performance caused by SADP process. In one dimensional layout, if we simply use the original metal patterns, irregular shapes of trim or block mask may form as illustrated in Figure 4(b); we may extend some metal of main design in this case to have more regular ones as illustrated in blue bars of Figure 4(c).

3. EVALUATION OF INTEGRATED-FILL We assess integrated-fill with post-fill as a reference in pattern density and coupling capacitance. M2 layer is considered, which we assume as a target layer of SADP process.

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Main design

(a)

Metal fill

Metal extension

(b)

(c)

Figure 4. (a) Initial main design, (b) irregular shapes for trim or block mask, and (c) modifying main design for more regular.

3.1 Pattern Density We compile a set of test circuts,6 which are listed in Table 1. Each circuit, given as Verilog description, is synthesized using Design Compiler; its layout is obtained using IC Compiler;7, 8 a gate library in 28nm technology is used for whole design process. Pattern density in M2 layer is obtained with both post-fill and integrated-fill. Its average and standard deviation are presented in Table 1. On average of test circuits, integrated-fill achieves 15.7% higher pattern density; in addition, it achieves 2.3% lower standard deviation implying better pattern uniformity. This is due to smaller buffer distance in integrated-fill, which also allows some missing fills in post-fill to be introduced as discussed in Table 1. Average and standard deviation of pattern density in M2 layer Circuit ac97 aes cipher b16 b18 b19 des3 eth mc spi tv80 core usbf usfft4 2b vga enh wb dma Average

Post-fill Avg (%) Std 36.9 35.4 34.3 45.6 33.7 34.1 34.5 36.2 39.0 37.4 35.9 34.6 34.2 35.1 36.2

(%) 5.5 4.6 4.8 4.7 4.3 3.5 3.8 4.7 6.1 6.0 4.7 4.1 3.5 3.7 4.6

Integrated-fill Avg (%) Std (%) 52.0 2.5 52.1 2.4 52.2 2.1 50.6 1.7 52.4 1.6 52.7 1.9 52.6 2.2 51.5 3.0 50.3 4.1 51.4 2.6 51.7 2.4 52.7 1.9 52.8 1.5 51.3 2.7 51.9 2.3

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+

100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0%

(a)

(b)

Figure 5. Pattern density map from (a) post-fill and (b) integrated-fill.

Section 2.1. M2 density distribution is graphically shown in Figure 5, for circuit FFT. It is even more clear now that integrated-fill yields overall higher pattern density with more regularity (less roughness of surface). In Cu damascene process, pattern density affects metal thickness due to varying amount of erosion that it causes. We adopt an empirical equation9 to calculate M2 thickness from extracted M2 density distribution: M2 0.2 ≤ Mb ≤ 0.8 (1) TCu = α(1 − b ), β where TCu is thickness, Mb is density, and α and β are fitting parameters. Calculated M2 thickness with two fill methods is compared in Figure 6 using example circuit b18. Post-fill causes wide variation of M2 thickness, specifically 0.025 difference between maximum and minimum value. Variation is substantially reduced to 0.006 in integrated-fill, which is about 24% reduction. Post-fill

Integrated-fill

0.490 Post -fill

Metal thickness

0.485

Integrated -fill

0.480 0.475

0.006 (24% reduction)

0.025

0.470 0.465 0.460 0.30

0.35

0.40

0.45

0.50

0.55

Metal density

Figure 6. Comparison of integrated-fill and post-fill for metal2 thickness variation in circuit b18.

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Tatal coupling capacitance Post-fill (1)

Integrated-fill (2)

[(2)-(1)]/(1) (%)

140 120

ac97 acs cipher b16 b18 b19 des3 etch mc spi tv80_core usbf usfft64_2b vga_enh wb_dma

1.34 1.92 1.39 1.47 1.30 1.31 3.31 1.82 1.38 1.53 2.66 1.44 2.43 2.35

1.38 1.95 1.42 1.51 1.33 1.35 3.34 1.86 1.42 1.56 2.69 1.48 2.47 2.40

2.99 1.56 2.16 2.72 2.31 3.05 0.91 2.20 2.90 1.96 1.13 2.78 1.65 2.13

Average

1.86

1.90

2.15

Integrated-fill

Circuit

100 80 60 40 20 0

//

."

I

0

20

40

Integrated-fill 60

80

100

120

140

Post fill

Figure 7. Total coupling capacitance (pF) for various test circuits.

3.2 Total Coupling Capacitance Since the buffer distance is kept smaller in integrated-fill, it is easy to expect that coupling capacitance will increase. In the proposed design flow shown in Figure 3(b), if coupling capacitance increases too much and so affects the design too badly (e.g. signal noise or timing failure), we may adjust the buffer distance and iterate the design flow. Coupling capacitance in M2 layer is extracted after post-fill and integrated-fill are performed respectively. Integrated-fill causes 7% higher coupling capacitance in example circuit b18, but total coupling capacitance including all metal layers increases only by 2.72%. Total coupling capacitance with two fill methods is compared in Figure 7 for various test circuits, which also graphically shows how close the total coupling capacitance with two methods is in b18 circuit.

4. CONCLUSIONS We have proposed a new design flow of dummy insertion in SADP process; integrated-fill, in which main design (in particular, routing) and fill insertion are performed together. Since the effect of dummy fill on main design can be verified, fill insertion can be done in more aggressive fashion. This allows more uniform pattern density, which helps reduce metal thickness variation. Total capacitance increases in integrated-fill, but only marginally as demonstrated in experiments.

ACKNOWLEDGMENTS This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2015R1A2A2A01008037).

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