Selection of Airgap Layers for Circuit Timing Optimization Daijoon Hyun§‡ and Youngsoo Shin§ §School of Electrical Engineering, KAIST, Daejeon 34141, Korea ‡ Samsung Electronics, Hwasung 18448, Korea ABSTRACT Airgap refers to a void formed in place of some inter metal dielectric (IMD). It brings about the reduction in coupling capacitance, which may contribute to improvement in circuit performance. We introduce two problems in this context. First is to choose the layers, where airgap should be applied, in such a way that total negative slack (TNS) is minimized for a given circuit. This has been motivated by the fact that best choice of airgap layers is different for different circuits. An algorithm is proposed to solve the problem, and is assessed against a naive approach in which airgap layers are simply fixed; additional 8% TNS reduction, on average of a few test circuits, is demonstrated. In the second problem, some wires of critical paths that are on non-airgap layers are reassigned to airgap layers such that TNS is further reduced; additional 3 to 14% of TNS reduction is observed. Keyword: Airgap, layer re-assignment, total negative slack

1. INTRODUCTION Airgap refers to air being used together with some dielectric material as IMD. It brings about reduced IMD permittivity from 2.5 (porous SiOC:H) to below 2.0 (airgap with SiOC:H)1, 2 and corresponding reduction in coupling capacitance. It has been reported that total wire capacitance including coupling component is reduced by 17% to 28%.3, 4 Airgap has been employed in high-performance microprocessor design to reduce interconnect delay by 17%;3 another application of airgap is to reduce floating gate interference by 20% in NAND flash memory.5 Latest research shows 25% reduction in capacitance between gate fin and contact in Finfet technology.6 A process for airgap formation is shown in Figure 1.4, 7 After the formation of standard Cu interconnect (Figure 1(a)), IMD between metal lines is removed (Figure 1(b)). Two consecutive depositions are applied. Conformal dielectric deposition using atomic layer deposition (ALD) is first performed for sidewall passivation of metal lines (Figure 1(c)); this is to prevent Cu being oxidized by air. Non-conformal dielectric deposition using chemical vapor deposition (CVD) then follows to pinch off the top portion of dielectric layer (Figure 1(d)). Airgap formation is an expensive process, and is associated with more than 10 additional process steps.7 Therefore, the number of layers that employ airgap, called airgap layers, is usually limited.3, 8 Let two airgap layers be utilized. The choice of airgap layers affects circuit timing. Specifically, Figure 2(a) shows the improvements of TNS for various choice of airgap layers in two example circuits. There is a wide variation of TNS reduction in one circuit, e.g. 42% variation in usb funct. More importantly, the best choice is different for different circuit, i.e. M2+M3 is the best choice for usb funct but M3+M4 is the best for gfx. Systematic method is thus required to choose the best airgap layers, which is our first problem. Assume that airgap layers have been chosen for a given circuit, for instance M2 and M3 for circuit usb funct. As shown in Figure 2(b), the percentage of wires on timing critical paths that are on M2 and M3 are about 50%, while the remaining wires do not take advantage of airgap. This suggests us to re-assign some of those remaining wires to M2 or M3 so that we can take best advantage of airgap, which is our second problem. The percentage of wires on M2 and M3 greatly increases after re-assignment, by 20%, which offers further TNS reduction by 9%. For the first problem, we identify critical path by choosing the paths of negative timing slack. We visit each net in critical paths one by one. For each net, we estimate potential delay reduction if airgap is assumed in particular layer; once we identify potential delay reduction for each candidate layer for each net, we calculate the whole TNS reduction for all combinations of airgap layers; finally, we select the best airgap layers that Design-Process-Technology Co-optimization for Manufacturability XI, edited by Luigi Capodieci, Jason P. Cain, Proc. of SPIE Vol. 10148, 101480O · © 2017 SPIE CCC code: 0277-786X/17/$18 · doi: 10.1117/12.2258034 Proc. of SPIE Vol. 10148 101480O-1 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/02/2017 Terms of Use: http://spiedigitallibrary.org/ss/termsofuse.aspx

Cu

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Figure 1. Airgap process steps: (a) formation of standard Cu interconnect, (b) IMD etch, (c) conformal dielectric deposition for sidewall passivation, (d) non-conformal dielectric deposition and airgap formation.

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Figure 2. (a) TNS reduction ratio for each candidate of airgap layers in usb funct and gfx, and (b) metal usage of critical paths for each metal layer in usb funct.

maximally reduce TNS. For layer re-assignment, we apply our algorithm to each timing critical net one by one, with a net of worst negative slack first. We first partition a net into multiple paths of wire segments based on slack continuity. Layer re-assignment is applied to each path, and corresponding problem can be formulated as shortest path problem of directed acyclic graph; we update the layer of each wire segment from the solution. The remainder of this paper is organized as follows. Section 2 introduces constraints on airgap formation process and then defines two problems. The first problem, selection of airgap layers, is presented in Section 3; an efficient and accurate method is addressed as a means of choosing best airgap layers; its application to 28nm commercial library is demonstrated. In Section 4, we present an algorithm of re-assignment on layer of timing critical paths and its application to a few circuits. Conclusions are drawn in Section 5.

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Upper via space

Airgap

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Wire segment

Upper metal (a)

(b)

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Figure 3. Constraints on airgap formation process: (a) upper via spacing rule, (b) minimum metal spacing rule, and (c) line-end spacing rule.

2. PRELIMINARIES 2.1 Constraints on Airgap Formation Process There are three constraints of airgap formation process. First, airgap is not allowed near vias connecting to upper metal layers as illustrated in Figure 3(a), because otherwise IMD may be broke down during high stress process such as chemical mechanical planarization.9 Airgap cannot be formed between wires that are widely spaced since non-conformal dielectric deposition (see Figure 1(d)) is not possible.4 A typical rule requires adjacent wires to be spaced in minimum metal pitch as shown in Figure 3(b). Finally, proper line-end space is required to avoid unintentional airgap formation (see Figure 3(c)) due to process variation, such as mask misalignment. These constraints affect the amount of airgap, i.e. reduction of coupling capacitance; thus, they should be considered in circuit timing optimization.

2.2 Problem Formulation Let a circuit layout be given after place and route. All metal layers use one-dimension metal routing for selfaligned double patterning (SADP),10 where dummy wires are inserted between signal wires in minimum metal pitch; thus, most signal wires observe minimum metal spacing rule. The number of airgap layers is limited to two. The problem of selecting airgap layers is to determine a set of metal layers with objective of minimizing TNS. After airgap layers are determined, second problem is to re-assign some wires of critical paths on non-airgap layers to airgap layers such that TNS is further reduced.

3. SELECTION OF AIRGAP LAYERS To maximize the effect of airgap on circuit timing, we select airgap layers which cause largest TNS reduction. Exact approach is to perform timing analysis for all candidates of airgap layers, but it takes much time for parasitic extraction and timing analysis; in addition, the runtime largely increases with the number of metal layers and airgap layers.

3.1 Algorithm Our goal is to find the best airgap layers that maximize TNS improvement of a circuit in an efficient way. Given a circuit layout and corresponding timing analysis results without airgap, we first identify critical paths, by choosing the paths of negative timing slack. We visit each net in critical paths one by one. For each net, we assume airgap formation for each layer, for instance, airgap is assumed in M2 (see Figure 4(b)), and airgap is assumed in M3 (see Figure 4(c)). Note that airgap can only be assumed in the wires which have adjacent wires in minimum distance which are indicated as red colors in the figures. Potential delay reduction from airgap is calculated for each assumption; wire capacitance is reduced as a rate of λ, capacitance reduction ratio from airgap, only for the portion of wires that are associated with airgap; the wire capacitance reduction is then

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Adjacent wire

Wire

Airgap M3 M2

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M3 M2

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Figure 4. (a) Example circuit and its airgap formation when airgap is assumed (b) in M2 and (c) in M3.

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Figure 5. Estimation of TNS reduction for each candidate of airgap layers.

applied to obtain cell and wire delay reductions, where cell delay reduction is referred from timing library. Once we identify potential delay reduction for each candidate layer for each net, we calculate whole TNS reductions for all combinations of airgap layers. For instance, when we choose M4 and M5, delay reductions corresponding to grey and black boxes are added to calculate TNS reduction as illustrated in Figure 5. Also for M2 and M3, we sum up the delay reductions of white and brown boxes, which results in TNS reduction of 29ps. Finally, we select the best airgap layers that maximally reduce TNS. This method only uses given timing analysis results without airgap, and the delay reduction is calculated once for each critical net, regardless of the number of airgap layers; thus, complexity is O(n), where n is the number of critical nets in a circuit.

3.2 Experiments Experiments are carried out on a set of sequential circuits from ITC, ISCAS, and OpenCores benchmarks. Each circuit is synthesized by Design Compiler with 28-nm commercial library. IC Compiler is used for place and route, where we use three metal layers (M2, M4, and M6) for horizontal routing and two metal layers (M3 and M5) for vertical routing. Dummy wires are inserted in minimum metal pitch to consider SADP, and λ is set to 23%.4 We assess the airgap layers selected in proposed method using 48 test circuits; the number of cells after place and route ranges from 0.2k (s444) to 338k (jpegencode). For a reference, all candidates of airgap layers are checked in timing anlaysis, and airgap layers that maximally reduce TNS are chosen; this is an exact solution. As a result, proposed method correctly selects best airgap layers for 92% of test circuits, which corresponds to those of reference. For the remainders, the selected airgap layers show very small difference below 2% in TNS

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Circuits s400 s713 s832 s15850 s9234_1 s13207 spi usb_funct fft_64 b19 b21 ac97_ctrl rc4-prbs vga_lcd gfx

Circuits (b)

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Figure 6. (a) Choice of airgap layers in proposed method, and (b) comparison of TNS reduction ratios between proposed method and naive approach.

reduction compared to the best airgap layers of reference, for instance of b18, proposed method chooses M3 and M4 which bring TNS reduction of 35%, while the reference selects M2 and M3 with that of 36%; this proves that our approach is very accurate. It comes from the reliable estimation of TNS reduction from airgap layers, which has small error of 3% on average and up to 11%; Our method in turn yields the runtime decrease of 110 times, from 1,990 to 18 seconds, for gfx circuit at the cost of a little accruacy. The effectiveness of the proposed algorithm is assessed by comparing it to a simple naive approach, in which airgap layers are just fixed to M3 and M4, given that they show the largest metal usage in our test circuits. In Figure 6(a), the choice of airgap layers is shown in second column for a few circuits listed in first column. There is not much dramatic variation over the circuits; M2 and M3 are chosen for the first 10 circuits, but for the remainders, there is still an option, M3 and M5 or M3 and M4. The selected airgap layers can be changed even for one circuit according to chip size that limits metal resource. For example, M2 and M3 are chosen for usb funct, but if we decrease chip area 12%, the best airgap layers are changed to M3 and M4. Resulting TNS reduction ratios are presented in Figure 6(b), where circuits without airgap serve as references. If we compare the proposed algorithm and naive approach, the former achieves 8% more TNS reduction on average and up to 15%. When we compare the circuits which select M2 and M3, four left most circuits show relatively large TNS reductions over 12%. It is because that they have a large metal usage for M2 and M3 in critical paths, for instance s15850 shows 78% metal usage in M2 and M3 while fft 64 represents 52% one.

4. RE-ASSIGNMENT OF LAYERS ON CRITICAL PATHS Suppose that airgap layers are selected, and some wires on critical paths are not included in airgap layers. If we move the wires into airgap layers, the more negative slack can be reduced due to decrease of coupling capacitance; thus, the goal is to move some wires on critical paths, if they are not on airgap layers, to airgap layers so that we can take best advantage of airgaps.

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Figure 7. Re-assignment of layers on critical paths: (a) partitioning a net into multiple paths, (b) weight assignment in graph modeling, and (c) final graph for shortest path problem.

4.1 Algorithm Our optimization is applied to each critical net one by one from largest negative slack to smallest one. For a net, we divide the tree structure of wire segments into multiple paths as illustrated in Figure 7(a), where we consider slack continuity. For example in the figure, path1 in blue is more critical and so slack on this path is continuous. Path2 is then identified as a second path. Let n wire segments in path1 be noted by w1 , w2 , ..., wn . We want to determine the layer of each wire segment in a way that TNS reduction is maximized without any design rule violations. Layer re-assignment in one path can be modeled as shortest path problem. Each wire segment corresponds to vertex, wij , where superscript j indicates that the wire segment is assigned to j-th layer. Let five metal layers are available for routing, in which three layers (M2, M4, and M6) are used for horizontal direction, and vertical routing is available in M3 and M5. Adjacent wire segments with different directions are connected in 6 configurations that are represented by edges. Each edge has a weight, and it is zero as a default. If an edge is associated with metal or via conflict, corresponding weight is set to positive infinite. Let airgap layers be M3 and M4, and w2 and w3 are connected as shown in Figure 7(b). w3 cannot be assigned to M4 because it can be overlapped with wother on M4. w3 on M6 has no metal conflict, but it requires stacked vias from M3 to M6, where the vias are overlapped by wother on M4. The weights of edges to w34 and w36 are thus set to infinite. Otherwise, if the layer of next vertex belongs to airgap layers, the weight is set to delay reduction from airgap. Also, the increased or decreased number of vias is considered in a weight, in terms of delay change. The edge to w32 has a weight of zero, because there is no delay change from airgap and the number of via. Once a graph is constructed from a path, two virtual vertices, s and t, are added to the graph as source and target, respectively. Graph model for layer re-assignment is finally shown in Figure 7(c). Let the shortest path from s to wij , P(wij ), be denoted by a sequence of consecutive vertices. At each vertex j we compare the sum of weights for P(wil )∪wi+1 , l ∈ L, where L denotes a set of available layers that wi j can be assigned, and pick the path of smallest one for P(wi+1 ). Resulting shortest path can be obtained at t,

j wi+1 ,

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Circuits Figure 8. TNS reduction ratios before and after re-assignment of layer on critical paths.

and the layer of each wire segment is updated following the solution. This process is repeated for the other paths in the critical net.

4.2 Experiments The proposed method is implemented in Tcl script, which runs on IC Compiler whose timing engine is also used for assessment of TNS reduction. In calculating weights, delay changes from airgap and the number of vias, are estimated by using the method in Section 3.1. The test circuits in Section 3.2 are reused. Our algorithm is assessed by comparing its TNS reduction to the solution of first problem, i.e. choice of best airgap layers but without layer re-assignment. The result is shown in Figure 8, where TNS reduction ratios before and after layer re-assignment are represented in white square and black circle, respectively; circuits without airgap serve as references. On average, layer re-assignment achieves 7% further TNS reduction, as small as 3 to 4% when airgaps are applied to M3 and M4 or M3 and M5, and as large as 6 to 14% when airgaps are applied to M2 and M3. M3 and M4 require more number of vias to connect to M1 pin; thus, TNS reduction from airgap becomes relatively smaller. In other words, the delay reduction from airgap is cancelled by increased number of vias in using higher metal layers. For b21, M3 and M5 are selected as best airgap layers, but there is no other vertical metal layers in non-airgap layers. Therefore, corresponding 3% TNS reduction comes not from advantage of airgap, but from the reduced vias in our algorithm.

5. CONCLUSION Airgap offers a possibility of circuit timing optimization; we have addressed two problems in this context. The first problem is to choose the best airgap layers such that TNS is minimized. We have proposed an algorithm that estimates TNS reduction from each candidate of airgap layers, and the airgap layers that maximize TNS reduction are selected. The experiment shows 8% more TNS reduction compared to naive approach, in which airgap layers are simply given. Once best airgap layers have been chosen, in the second problem, we move some wires on critical paths, if they are not on airgap layers, to airgap layers for further timing optimization, which allows additional 3 to 14% of TNS reduction.

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ACKNOWLEDGMENTS This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2015R1A2A2A01008037).

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