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STUDY OF MICROCONTROLLERS A dissertation submitted in partial fulfillment for the requirement of awarding the degree of Bachelor of Engineering in
Electronics and Communication Engg. Submitted by Harsh Pradhan 2k3/ECE/625
Under the guidance of
Prof. I.P Singh
Instrument Design and Development Center Indian Institute of Technology Delhi
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CERTIFICATE This is to certify that the dissertation entitled, “Study of Microcontrollers” is a bona fide record of the project work carried out by Mr. Harsh Pradhan (2k3/ECE/625) from 10th June 2005-31st July 2005 under my supervision and guidance in partial fulfillment of the requirement for the award of the degree of BACHELOR OF ENGINEERING. Further to the best of our knowledge this report has not been submitted to any other University or Institute for the award of any degree or diploma. I also sincerely thank Mr. Sewa Singh and Mr. Harpal Singh but for whose cooperation and support the present form of this project would not have materialized. I would also like to thank with pleasure all my friends for their cooperation and motivation.
Prof. I.P Singh Instrument Design and Development Centre Indian Institute of Technology New Delhi (India) Date: Place:
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ACKNOWLEDGMENT The completion of any project work depends upon the cooperation, co-ordination and combined effects of several resources of knowledge, energy and time. Therefore I approach this important matter of acknowledgement through these lines trying my best to give full credits where it deserves. I am extremely grateful to my guide Prof. I.P Singh, for his expert guidance, constant encouragement, valuable suggestions, constructive criticism and sustained interest in the project that tremendously enhanced my perseverance towards my project work. I am thankful to Dr. A. L. Vyas, Head of the Department, IDDC, for his guidance throughout my course of study & work. Finally, I would like to thank all those who helped me directly or indirectly to make this project a success.
Harsh Pradhan
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CONTENTS 1. Introduction to IDDC
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2. 8085 Microprocessor:
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2.1. I/O Interfacing 2.2. Stepper Motor Control 2.3. Interfacing with A/D Converter 3. Introduction to Microcontrollers- Overview and Applications
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4. 8751 Microcontroller
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4.1. Functional Diagram 4.2. Architecture 4.3. Programming of 8751 4.4. Experiments: i) Sinusoidal to Square Wave Conversion ii) Calculation of Frequency of input Square Waveform iii) Frequency Display using LCD 5. PIC Microcontroller 5.1. Introduction to PIC- Pin out Description and Architecture 5.2. Programming the PIC 16F877 5.3. Experiment: Interfacing with Temperature Sensor LM35 and display the temperature using LEDs
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Information on the Venue Indian Institute of Technology ,Delhi is one of the six Institutes of Technology created as centres of excellence for higher training, research and development in science, engineering and technology in India, the others being at Kanpur, Kharagpur, Madras Bombay and Guwahati. Established as College of Engineering in 1961, the Institute was later declared an Institution of National Importance under the "Institutes of Technology (Amendment) Act, 1963" and was renamed "Indian Institute of Technology Delhi". It was then accorded the status of a deemed university with powers to decide its own academic policy, to conduct its own examinations, and to award its own degrees.
HRH Prince Philip, the Duke of Edinburgh, laid the foundation stone of the Institute on January 27,1959.The institute was inaugurated by Prof Humayun Kablr, the then Union Minister for Scientic Research and Cultural Affairs on August 21,1961.. The Institute buildings were formally opened by Dr.Zakir Hussain, the then President of India, on March 02,1968.
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Information on the Venue The facilities at the center are enlisted as follows.
. Electronic laboratories having facilities for Analog and digital design, Microprocessor System Development , electron instrumentation
. Manpower training in Instrument Technology Laboratory . Industrial Design Laboratory and Model making Workshop . Holographic Laboratory . Photo-Mechanical Engineering Laboratory . Optics Laboratory and workshop. It has also a Mechanical workshop to assist to assist in research activities of the center. It also has MAC laboratory for CAD and Multimedia.
Projects of IDDC A selected list of the projects are enlisted below:
. Condition Monitoring of Joint using Digital Laser Speckle Pattern Interferometer. . Development of Teaching Material for Engineering and Polytechnics in the country. . Resource Center in Electronics(IMPACT) . Development of Interferometric techniques by using Semiconductor Lasers and its application in Entouring of Optical Components and Optical Testing
. Design and Development of Electromagnetic Proximity Fuse. . Design and Development of the Automatic Measurement System for Telecom Cables. . Design and Development of Instruments and Devices for Passive Solar Architecture Applications
. Thrust Area Project for setting up an Industrial Design. . Fire Control Systems for Defence Vehicles . Monitoring of Vibrations using DSPI
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8085 MICROPROCESSOR INTEL 8085 MICROPROCESSOR ARCHITECTURE REGISTERS Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store operations. Flag is an 8-bit register containing 5 1-bit flags: •
Sign - set if the most significant bit of the result is set.
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Zero - set if the result is zero.
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Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result.
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Parity - set if the parity (the number of set bits in the result) is even.
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Carry - set if there was a carry during addition, or borrow during subtraction/comparison.
General registers: •
8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a pair the C register contains low-order byte. Some instructions may use BC register as a data pointer.
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8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a pair the E register contains low-order byte. Some instructions may use DE register as a data pointer.
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8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a pair the L register contains low-order byte. HL register usually contains a data pointer used to reference memory addresses.
Stack pointer is a 16 bit register. This register is always incremented/decremented by 2. Program counter is a 16-bit register. IO PORTS 256 Input ports 256 Output ports
MEMORY Program, data and stack memories occupy the same memory space. The total addressable memory size is 64 KB. Program memory - program can be located anywhere in memory. Jump, branch and call instructions use 16-bit addresses, i.e. they can be used to jump/branch anywhere within 64 KB. All jump/branch instructions use absolute addressing.
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Data memory - the processor always uses 16-bit addresses so that data can be placed anywhere. Stack memory is limited only by the size of memory. Stack grows downward.First 64 bytes in a zero memory page should be reserved for vectors used by RST instructions.
INTERRUPTS The processor has 5 interrupts. They are presented below in the order of their priority (from lowest to highest): INTR is maskable 8080A compatible interrupt. When the interrupt occurs the processor fetches from the bus one instruction, usually one of these instructions: •
One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into stack and branches to memory location N * 8 (where N is a 3-bit number from 0 to 7 supplied with the RST instruction).
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CALL instruction (3 byte instruction). The processor calls the subroutine, address of which is specified in the second and third bytes of the instruction.
RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 2Ch (hexadecimal) address. RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 34h (hexadecimal) address. RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 3Ch (hexadecimal) address. Trap is a non-maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 24h (hexadecimal) address. All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM instruction.
INSTRUCTION SET 8085 instruction set consists of the following instructions: • Data moving instructions. • Arithmetic - add, subtract, increment and decrement. • Logic - AND, OR, XOR and rotate. • Control transfer - conditional, unconditional, call subroutine, return from subroutine and restarts. • Input/Output instructions. • Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations, etc.
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[Frame3]
PROGRAMMING THE 8085 MICROPROCESSOR 8085 KIT DESCRIPTION VMC-ICE8085 is an 8-bit Microprocessor Training kit cum In circuit Emulator for 8085 Microprocessor. The VMC_ICE8085 provides the Engineer, a complete microprocessor design tool set working with 8085 - in a cost effective package that sets a new industry standard. The monitor enables one to use VMC-ICE8085 through keyboard and display having 28 keys Hexadecimal keyboard and 6 Seven Segment Display. The 28 keys consist of 16 Hexadecimal keys, 11 Functional keys & 1 Hardware Reset key. The kit provides 48K bytes of RAM (0000 to BFFF) with onboard battery backup for preserving data stored in this address range even after power is removed. VMC_ICE8085 is also a Stand Alone In-Circuit Emulator that connects to the Serial port of the PC via RS-232 cable provided with the kit.
SPECIFICATIONS •
Based on 8085 Microprocessor operating at 6.144 MHz clock frequency
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VMC-ICE8085 comprises three components: o
Microprocessor Kit
o
In-circuit Emulator
o
Cross Assembler
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48K Emulation Memory, RAM area starting from0000H
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8K bytes of EPROM with powerful monitor program.
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48 I/O lines using 2 nos. of 8255.
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Three nos. of 16 bit Timer/Counter using 8253.
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28 keys Hexadecimal keyboard & 6 Seven Segment display.
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On board battery backup for Emulation memory.
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40 Pin Header with cable for connecting the target.
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RS-232C port for serial communication with PC.
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Uploading/Downloading facility to/from PC.
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Powerful software commands like Break point, Single Stepping, Auto Single Stepping, Go, Fill, Compare, Examine Memory, Assemble etc. •
User's Manual, cable & connectors.
AIM: •
Display binary counting sequence on 8 LEDs connected to Port A {0.5 see duration each step}. r Supply requirements: +5V/1.2A, +/-12V/250mA, +24V/100mA. Objective To demonstrate the concepts of: a) Different methods of saving a register. b) Transparent subroutine c) Conditional output ON BOARD d) Reading of latched output in 8255 ICE8085
CROSS ASSEMBLER: •
VMC-ICE8085 has its own fast & efficient built-in Cross Assembler that can assemble a source file and produce a modified Hex file which can be downloaded to VMC-ICE8085.
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The 40 pin POD and flat cable are use to connect the VMC-ICE8085 to the target system.
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The Input/Output Structure provides 48 I/O lines using 8255. It has got 16 bit programmable
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Timer/Counter for generation of accurate time delay under software control.
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Ram area from 0000H location onwards, so all software & Hardware interrupts can be taught as per 8085 Instructions.
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Target program development & debugging starts from 0000H location and when development is over, can be directly loaded in the EPROM.
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The VMC-ICE8085 kit can be directly connected to the CPU of the target board to test software & Hardware by writing small programs for enabling students/users to understand the techniques of hardware and software testing.
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P o w e
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I/O INTERFACING WITH THE 8085 EXPERIMENT-1 Inputs: Nil Outputs: Method:
Binary counting sequence on LEDs on Port A with a 0.5 duration between steps. begin Initialize stack; Initialize 8255; Initialize a counter, {say Reg A} loop Output counter, Increment counter, save counter, call delay for 0.5 sec; restore counter forever end
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PROGRAM
AGAIN:
DELAY:
MVI SP,21FFH MVI A,90H OUT 03H MVI A,00H OUT 01H LXI D,0000H CALL DELAY INR A JMP AGAIN DCX D MOV A,E ORA D JNZ DELAY RET END
; initialize stack pointer ; control word for 8255 ; output to control word register of 8255 ; clear accumalator ; output to port B ; delay= 0.5s ; increment accumalator ; loop ;delay routine
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EXPERIMENT-2
AIM: Display the switch data on switches connected to Port B continuously in a Loop.
Objective: To demonstrate the concepts of: a) Combined Input Output b) Loop forever. c) Real time output corresponding to input d) Break the loop on a particular condition of input (e) Continuous looping to detect change in input. Input:
Current switch data X on Port B
Output: LEDs on port A lit according to the switch data X. _ Method: begin Initialize 8255 with A as output & B,C as input; loop Input switch data X to accumulator; Output X to LEDs loop end
PROGRAM
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AGAIN:
MVI SP,21FFH MVI A,90H OUT 03H IN 00H OUT PORTB JMP AGAIN
; initialize stack pointer ; control word for 8255 ; output to control word register of 8255 ; input from port A ; output to port B ; loop END
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EXPERIMENT-3
begin Initialize stack; {define stack pointer} Initialize 8255 for A as output, B,C as input; loop Output 55H to Port A; Delay of 0.5 sec; Output AAH to Port A; Delay for 0.5 sec
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PROGRAM
MVI SP,21FFH MVI A,90H OUT 03H AIM:
; initialize stack pointer ; control word for 8255 ; output to control word register of 8255
Display LEDs 0,2,4,6 for 0.5 sec and then display LEDs 1,3,5,7 for 0.5 sec and repeat.
MVI A, 55H
Objective: To demonstrate the concepts of: a) b) ; load c) accumulator d) with 55H e) AGAIN: OUT registers. f)
PORTB ; output to Inputs:
Nil
Outputs:
I D,0000H Method:
DELAY:
end
Use of monitor subroutines Making and using subroutine Display refreshing. Checking for a condition with a loop. Use of subroutine may lead to destruction of data in some Use of another register to save a register whose value gets destroyed.
port B
LEDs 0,2,4,6 ON for 0.5 sec and then LEDs 1,3,5,7 ON for 0.5 sec and then repeat.
; delay = 0.5s CALL DELAY RRC ; rotate accumulator without carry JMP AGAIN ; loop DCX D ; delay routine MOV A,E ORA D JNZ DELAY RET END
LX
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STEPPER MOTOR INTERFACING AIM To run a stepper motor using the 8085 kit . A stepper motor is interfaced to the ports of 8255 on the kit through a stepper motor driver. The stepper motor is to be driven at 10 rpm. EQUIPMENT REQUIRED 8085 microprocessor kit Power supply for the kit A 12V, 5A power supply for stepper motor driver Stepper motor Stepper motor driver THEORY A stepper motor has four coils, which are to be energised in a particular sequence (two coils at a time). The sequences can be outputted from the microprocessor as TTL output. This is converted to the required power outputs by a stepper motor driver card. The four drivers on this card for the four coils can be turned 'off or 'on' depending on whether the four bits from the 8255 port are '0' or ' 1'. This 8255 is on the microprocessor kit and is a peripheral of microprocessor. The stepper motor rotates when a series of steps are given to it. The sequence for running the stepper motor are : A, 9, 5, 6 using the diagram shown in Figure 2.18.1. The stepper rotation sequences are indicated in Figure 2.18.2. If this sequence is given in a cyclic fashion the stepper motor takes a step for each output. If the direction of the sequence is reversed the direction of rotation of the stepper motor is also reversed. The time period between the steps determines the speed of rotation. This delay can be generated either by a software loop or through the timer.
Stepper motor control circuit
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In software the delay can be generated by counting down of a register pair using the DCX instruction. For this register pair DE is counted down using the DCX instruction in a loop till it becomes zero. The register pair DE is found to be zero if the logical OR of register D and register E is zero. The time can be calculated as each loop takes 24 clock cycles. In case of a crystal frequency of 6.144 MHz, the System Clock is of 3.07 MHz. The machine cycle T is therefore of 0.65 microsecond. Delay Time = (24 x N + 17) x T If a word AS is formed in a byte ( a register or accumulator) and the LS Nibble or MS Nibble is connected to the four inputs to the Stepper Motor Driver, the required sequences can be easily derived. The next following sequences can be found by shifting twice consequetively to the right for rotation in one direction, or twice to the left for the other direction.
Stepper motor driver circuit
EXPERIMENTAL PROCEDURE AIM:
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The stepper motor driver card is connected to the 8085 kit through one of the connectors labeled as 8255-1. These connections from the kit to the card are made via an interface cable provided. The following program may be used: Method: begin Initialize the stack; Initialize the 8255 port to all outputs; Form the word A5 in the Accumulator A; Loop Output the Accumulator A; Call delay for 100ms; Rotate Accumulator twice (left or right); forever; end Subroutine Delay begin do decrement count N in DE register pair while (DE register pair is no zero); end
PROGRAM
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HERE:
DELAY:
MVI SP,21FFH MVI A,80H OUT 03H MVI A,A5 OUT 00H LXI D,1000H CALL DELAY IN 00H RLC RLC JNZ HERE DCX D MOV A,E ORA D JNZ DELAY RET END
; initialize stack pointer ; control word for 8255 ; output to control word register of 8255 ; load accumulator with start sequence ; output to port A ; delay =0.5s ; input from port A ; rotate accumulator left for ; anticlockwise rotation of motor ; loop ; delay routine
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CALCULATION OF STEP ANGLE AND SPEED OF STEPPER MOTOR CRYSTAL FREQUENCY: 6.14 MHZ CLOCK FREQUENCY : 3.07 MHZ
LP:
DELAY ROUTINE
CLOCK CYCLES
LXID N DCX D MOV A,E ORA D JNZ LP RET
10 6 4 4 10/7 10
COUNT= 10+N (6+4+4+10) +10-3 = 24N+17 DELAY TIME= (24N+17)/3.07 OBSERVATIONS: TIME TAKEN FOR 5 REVOLUTIONS: 27 sec. TIME PER REVOLUTION: 27/5 = 5.4 sec. SPEED IN RPM = 60/5.4 = 11.11 RPM N= 16^3 DELAY TIME= 24* (16^3)*(0.000006)/ 3.07 = 0.032768 sec. HENCE WE HAVE, TIME FOR 1 STEP = 0.032768 sec. THERFORE, IN 1 REVOLUTION = 5.4/ 0.032768 STEPS IN 360 DEGREES, STEPS TAKEN = 164.8 NO. OF DEGREES PER STEP = 360/164.8 = 2.14
RESULT: STEP ANGLE FOR GIVEN STEPPER MOTOR IS CALCULATED TO BE 2.14 DEGREES PER STEP, WITH SPEED OF 11.11 RPM. EXPERIMENT-5
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AIM To implement ADC converter using Counter Method INPUT Analog Input, Depression of SOC switch OUTPUT Digital equivalent of Analog Input on LEDs in a continuous loop. (Start of conversion switch (SOC) to be pressed for next output). METHOD begin Initialize stack; Initialize 8255; loop Call Debounce Key Initialize DA counter (Register A) Call Convert forever Subroutine convert begin repeat Output DA counter to LED’s; Delay for 2ms appear;(DA converter to settle) Check comparator output; If comparator is ‘1’ then Increment DA counter; Until comparator output is ‘0’; end
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ADC CARD
PROGRAM
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MVI SP,21FFH MVI A,80H OUT 03H LP1:
LP2:
CONV:
AGAIN: DELAY:
IN 02H ANI 01H JZ LP1 LXI D,0800H CALL DELAY IN 02H ANI 01H JZ LP1 IN 02H ANI 01H JNZ LP2 LXI D,0800H CALL DELAY IN 02H ANI 01H JNZ LP2 MVI A,00H CALL CONV JMP LP1 OUT 00H LXI D,150H CALL DELAY IN 02H ANI 02H JNZ AGAIN RET IN 00H INR A JMP CONV DCX D MOV A,E ORA D JNZ DELAY RET END
; initialize stack pointer ; control word for 8255 ; output to control word register of 8255 ; debounce routine ; check for key depression-input from port C ; mask bit PC1 ; loop ; delay = 16ms ; input from port C ; mask bit PC1 ; loop ; check for key release ; mask bit PC1 ; loop ; delay = 16ms ; check for key release ; mask bit PC1 ; loop ; clear accumalator ; call conversion routine ; loop ; routine to obtain digital equivalent of analog input
; delay routine
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MICRO CONTROLLERS AND THEIR APPLICATIONS A computer system has mainly three components; they are the Central Processing Unit (CPU), the memory and the Input/output interface. Apart from these it has a clock and a reset circuit. The memory is of two types i.e. the read only memory (ROM) and Read Write Memory (RAM). With miniaturization the CPU was fabricated on a single silicon chip and this was known as a Micro Controller Further miniaturization leads to integration of RAM, ROM and the I/O interface with the CPU, on a single silicon chip. These microcomputers on a single chip are known as Micro Controllers.The compactness of these micro controllers has made it possible to be used in small and low cost systems. More powerful microcomputers are available for sophisticated control applications. Some of the facilities found on Micro Controllers •
The CPU- It may be 8 or 16 bits.
• The on-board RAM- This is usually of 64 to 256 bytes. It includes the SFR's (Special Function Registers), which serve to program and control the I/O interface. • The on-board ROM- This may be EPROM (Erasable Programmable Read Only Memory). They usually range in size from IK to 8K. • Parallel I/O ports- They are used to send and receive data from other external peripherals. Usually three I/O ports are typically available on Micro Controllers. • Timer/Counter- There is usually one counter timer available in microcontrollers. • Interrupts-Usually two or more interrupts are available on Micro Controllers. • Clock Generator- This is present in all micro controllers. Only a crystal and a few capacitors are needed to ensure proper operation. Many of the microcontrollers are available in the ROM less version. These contain all the resources of the microcontroller family-except the EPROM. In order to use these ROM has to be interfaced to it. These are much cheaper than the EPROM version of the microcontroller, but one loses some of the I/O ports, as the microcontroller has to be used in the expanded mode.
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APPLICATIONS OF MICROCONTROLLERS Most control applications require a number of I/O functions, but the memory requirements are not large. In highly integrated microcontrollers, these requirements are easily met. Moreover since most I/O functions are available on a single chip, automation can easily be provided even to very small system. For more sophisticated control application more' powerful microcontrollers with fast calculations and fast I/O operations are available. Some of the areas of application of microcontrollers are discussed.: a). Hand-Held instruments: Low power CMOS microcontrollers working on Ni-Cd cells. provide the computing power, I/O operations and display functions for hand-held instruments: The glucose level meter for diabetics is an example from medical electronics. Other examples of these are the Electronic planimeter and the digital level meter. b). Peripheral Devices: Microcontrollers used in many peripheral devices attached to a main system. For example, the IBM PC keyboard is based on the 8048 microcontroller. It performs a number of functions such as keyboard debouncing and N-key-rollover, serializing the key data and sending it to the PC is done by the microcontroller.Other examples of these are the modems used to interface the computer to the telephone lines. The printer buffer is another example. c). Stand-Alone Devices: Some of the standalone devices use the microcontroller to control its functions. The paper copier, the electronic typewriter and the plotters are examples of these. Precision weighing scales usually have a microcontroller to acquire the data through ADC, process it and display the weight. d). Instrument Sub-Functions: In a number of modern instruments the front panel functions are done by microcontrollers. These functions are usually handling key inputs and displaying the data. CRT displays and touch screen displays use a microcontroller. e). Automotive Applications: Microcontrollers are now being employed in ignition control, transmission control, Antiskid brakes and pollution control in automobiles. f). Industrial Applications: The industrial applications of microcontrollers are generally concerned with automation and process instrumentation. Examples are Motion control, robotics, Numerical control, intelligent transducers etc.
g). Guidance command Control: The more sophisticated high end microcontrollers are used for missile control, torpedo guidance, and control intelligent ammunition etc.
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ARCHITECTURE OF 8751
PINOUT OF 8751 MICROCONTROLLER
Thee Central Processing Unit (CPU) is responsible for fetching and executing the Accumulator A, the Multiplication Register B, the Program Status Word (PSW), the Stack Pointer (SP), the 16-bit Program Counter PC (PCH & PCL) for program memory and Data Pointer DPTR (DPH & DPL) for External Data Memory. The registers A, B, PSW, SP, DPH and DPL are some of the Special Function Registers (SFRs) and are mapped on to the internal data memory. The I/O ports PO and P2 are connected to the Program Counter and the Data Pointer. The latches of PO, PI, P2, P3 of all the ports are associated with SFRs, which form a part of Internal Data Memory. The eight pins of Port P3 are also having alternate functions. Similarly all the alternate functions of Port P3 are also associated with SFRs. These include Serial Port Register SCON, Serial Port Buffer SBUF, Interrupt Enable Register IE, Interrupts Priority Register IP, Timer Register TCON, Timer Mode Register TMOD and the Timer 0 and Timer 1 high and low count bytes-TLO, THO, TLI AND THI.
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MEMORY ORGANIZATION IN 8751 The 8751 has separate address spaces for program memory and the data memory. Both these address spaces can be expanded through External memories. Therefore the Total .Memory Space in the 8751 can be divided into four distinct parts. These are the Internal Data Memory, the External Data Memory, the Internal Program Memory and the External Program Memory. The 8751 can be expanded for up to 64K of external data memory (RAM) and 64K of external code memory (ROM/EPROM).
THE PROGRAM MEMORY: The program counter starts at 0000H on RESET and therefore the first instruction to be executed lies at this location. Normally, this location lies in the internal ROM, but if EA /Vpp is
grounded the program fetches are made from the external memory. THE INTERNAL DATA MEMORY This is a 256 byte memory on the chip itself. The first 1,28 bytes from the internal RAM space. The other. 128 bytes from 80H to FFH are registers concerned with the hardware known as SFRs. The first 128 bytes can be divided into three segments: The register banks 0 to 3: a). These are four register banks each containing 8 registers. Only one of these banks can be active at a time and this is defined by setting of the two "Dank select bits" in the PSW (Program Status Word). b). The Bit Address Space: RAM addresses 20H through 2FH are designated as bit addressable memory locations. These 128 bits can be directly addressed. c). The Scratch Pad Area: The last 80 bytes are available to the user as RAM for general-purpose data storage as well as stack operations.
THE SPECIAL FUNCTION REGISTERS: The SFRs are contained in the next 128 bytes of the internal data memory corresponding to address 80H to FFH. The SFRs are registers required for software execution as well as for controlling special hardware features. These SFRs can either be addressed by their hexadecimal or by their symbolic names. Some of these registers are: a) The Accumulator and Register B: The 8751 is also an accumulator based processor, like many other microprocessors, it contains one of the operands as well as the result
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of an arithmetic operation. In the instructions the _cc. is referred to as A. The register B is used together with the A in multiplications and divide instructions. b) The Program Status Word: Most of the arithmetic and logical operations affects the status flags. These flags are grouped together to form the Program Status W_)fd, PSW. The PSW also contains information about which is the active register bank of four register bank. Details are given below: c).CY: This is the carry flag. It is used by the addition, subtraction and rotate instructions. Apart from that it is used as a Boolean Accumulator for the one bit logical and bit manipulation instructions. d).AC: This bit is used for BCD operations and denotes carry or borrows out of 3 of accumulator. e).OV: This indicates whether an overflow has occurred. This makes signed arithmetic possible. f).P: This is the parity flag. It is set/cleared depending upon whether the no. of 1’s in A is odd or even. g).FO: This is the user defined flag. This can be set, cleared or tested through software. h).RSI & RSO: These two bits indicate which one of the four register banks is active. '00' indicates bank 0, '01' indicates bank I, '10' indicates bank 2 and "11' indicates bank 3. The PO, PI, P2, P3 are the SFR latches registers of the respective ports. The SP is 8 bit wide and can point to data anywhere in the Internal RAM. This is initialised to 07 after reset; the stack starts from 08H. The Data Pointer DPTR (DPH & DPL) is a 16-bit register and holds a external data address. It can also be manipulated as two separate 8-bit registers. i).Timer/Counters 0 and 1: The 8751 microcontroller has two Timer/Counters which are 16-bit registers. These are THO,TLO,THI and TLI. Apart from these _ere are two register TMOD, the Mode Control Registers, and TCON, the Control Register. TMOD register determines for both the timer/counters whether they are to be used as a timer or a counter, selects one of the four modes of the timer/counter operations & defines the gating controls. The TCON on the other hand contains the four bits to turn the two timer/counters on/off as well as to specify whether the interrupts are falling edge triggered or low level. There are two flags to indicate the overflow of the two timer/counter. There are two other flags which indicates whether an external interrupt edge was detected at INTO and INTI.
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j).INTERRUPTS: There are 5 sources of interrupts in 8751. There are two external interrupts, INTO & INTI, the two timer interrupts TFO & TFI and the Serial interrupt, which is an OR of the transmit and receive interrupts. The external interrupts can be either falling edge or low level triggered, but these are programmed by the TCON as associated with the timer/counters. The interrupts are enabled or disabled through the IE special function registers. Each of these interrupt has a priority attached. This is determined by the Interrupt Priority Register, the IP Within each priority, the interrupts are serviced in the following sequence: External Interrupt 0 (INTO) Timer Interrupt 0 (TFO) External Interrupt I (INTI) Timer Interrupt I (TF I) Serial Interrupt (RI & TI)
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Block Diagram
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External Clock Drive Waveforms
AC Testing Input/Output Waveforms
Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.
DC Characteristics
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TA = -40°C to 85°C, VCC = 5.0V ± 20% (unless otherwise noted)
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power-down is 2V.
PROGRAMMING THE 8751 MICROCONTROLLER
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SOFTWARE SPECIFICATIONS 8051 CROSS ASSEMBLER The 8051 Cross Assembler takes an assembly language source file created with a text editor and translates it into a machine language object file. This translation process is done in two passes over the source file. During the first pass, the Cross Assembler builds a symbol table from the symbols and labels used in the source file. It's during the second pass that the Cross Assembler actually translates the source file into the machine language object file. It is also during the second pass that the listing is generated. 8051 CROSS ASSEMBLER DIRECTIVES The 8051 Cross Assembler Directives are used to define symbols, reserve memory space, store values in program memory, select various memory spaces, set the current segment's location counter and identify the end of the source file. Only one directive per line is allowed, however comments may be included. The remaining part of this chapter details the function of each directive. Symbol Definition Directives
EQU Directive The EQUate directive is used to assign a value to a symbol. It can also be used to specify user defined names for the implicit operand symbols predefined for the Accumulator (i.e.,A) and the eight General Purpose Registers (i.e., R0 thru R7). The format for the EQU directive is: symbol, followed by one or more spaces or tabs, followed by EQU, followed by one or more spaces or tabs, followed by a number, arithmetic expression, previously defined symbol (no forward references allowed) or one of the allowed implicit operand symbols (e.g., A, R0, R1, R2, R3, R4, R5, R6, R7), followed by an optional comment. RUNNING THE 8051 CROSS ASSEMBLER Once the program is assembled and an output hex file generated, we move to progmr sub-directory within the cross directory. Here, the hex file is loaded onto the buffer area, the required device is selected, the requisite voltage levels for burning the program into the chip’s memory are applied. Device programming: 1.Erase the previous memory contents 2.Verify if device is blank 3.Load the hex file into device’s RAM 4.Check whether program has been successfully loaded
35
EXPERIMENT 1
Circuit for sinusoidal to square wave conversion
36
CALCULATE FREQUENCY OF GIVEN SQUARE WAVEFORM ;****************************************************** ; File Name:DMSD1 Dated: 29/06/05 ; Name: TO MEASURE FREQUENCY OF INPUT SQUARE WAVE ; ; ; ; ; ;****************************************************** ;INCLUDED, IS A LIST OF THE REGISTER AND BIT NAMES ;WITH THEIR CORRESPONDING ADDRESSES. THESE MAY ;BE SPECIFIED AS PART OF THE ASSEMBLER CODE, OR ;MOVED TO THE END OF THE 8051 TABLE FOR GREATER ;TRANSPARENCY. ;***************************************************** CPU "8051.TBL" HOF "INT8" ;****************************************************** ; ;MCS-51 INTERNAL REGISTERS ; B: EQU 0F0H ;B REGISTER ACC: EQU 0E0H `;ACCUMULATOR A: EQU 0E0H ;ACCUMULATOR PSW: EQU 0D0H ;PROGRAM STATUS WORD IPC: EQU 0B8H ;INTERRUPT PRIORITY P3: EQU 0B0H ;PORT 3 IEC: EQU 0A8H ;INTERRUPT ENABLE P2: EQU 0A0H ;PORT 2 SBUF: EQU 99H ;SEND BUFFER SCON: EQU 98H ;SERIAL CONTROL P1: EQU 90H ;PORT 1 TH1: EQU 8DH ;TIMER 1 HIGH TH0: EQU 8CH ;TIMER 0 HIGH TL1: EQU 8BH ;TIMER 1 LOW TL0: EQU 8AH ;TIMER 0 LOW TMOD: EQU 89H ;TIMER MODE TCON: EQU 88H ;TIMER CONTROL PCON: EQU 87H ;POWER CONTROL REGISTER DPH: EQU 83H ;DATA POINTER HIGH DPL: EQU 82H ;DATA POINTER LOW SP: EQU 81H ;STACK POINTER P0: EQU 80H ;PORT 0 ; ;MCS-51 INTERNAL BIT ADDRESSES ; CY: EQU 0D7H ;CARRY FLAG AC: EQU 0D6H ;AUXILIARY-CARRY FLAG F0: EQU 0D5H ;USER FLAG 0 RS1: EQU 0D4H ;REGISTER SELECT MSB RS0: EQU 0D3H ;REGISTER SELECT LSB OV: EQU 0D2H ;OVERFLOW FLAG P: EQU 0D0H ;PARITY FLAG
37
PS: PT1: PX1: PT0: PX0: EA: ES: ET1: EX1: ET0: EX0: SM0: SM1: SM2: REN: TB8: RB8: TI: RI: TF1: TR1: TF0: TR0: IE1: IT1: IE0: IT0:
EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU
0BCH 0BBH 0BAH 0B9H 0B8H 0AFH 0ACH 0ABH 0AAH 0A9H 0A8H 09FH 09EH 09DH 09CH 09BH 09AH 099H 098H 08FH 08EH 08DH 08CH 08BH 08AH 089H 088H
;PRIORITY SERIAL PORT ;PRIORITY TIMER 1 ;PRIORITY EXTERNAL 1 ;PRIORITY TIMER 0 ;PRIORITY EXTERNAL 0 ;ENABLE ALL INTERRUPT ;ENABLE SERIAL INTERRUPT ;ENABLE TIMER 1 INTERRUPT ;ENABLE EXTERNAL 1 INTERR ;ENABLE TIMER 0 INTERRUPT ;ENABLE EXTERNAL 0 INTERR ;SERIAL MODE 0 ;SERIAL MODE 1 ;SERIAL MODE 2 ;SERIAL RECEPTION ENABLE ;TRANSMITT BIT 8 ;RECEIVE BIT 8 ;TRANSMIT INTERRUPT FLAG ;RECEIVE INTERRUPT FLAG ;TIMER 1 OVERFLOW FLAG ;TIMER 1 RUN CONTROL BIT ;TIMER 0 OVERFLOW FLAG ;TIMER 0 RUN CONTROL BIT ;EXT INTERR. 1 EDGE FLAG ;EXT INTERR. 1 TYPE FLAG ;EXT INTERR. 0 EDGE FLAG ;EXT INTERR. 0 TYPE FLAG
; Port Addresses ; Port P3 P30: P31: P32: P33: P34: P35: P36: P37:
EQU EQU EQU EQU EQU EQU EQU EQU
0B0H 0B1H 0B2H 0B3H 0B4H 0B5H 0B6H 0B7H
; RxD ; TxD ; ; ; ; ; WR* for mem mapped I/O (X-Data Space) ; RD* for mem mapped I/O (X-Data Space)
0A0H 0A1H 0A2H 0A3H 0A4H 0A5H 0A6H 0A7H
; ; ; ; ; ; ; ;
; Port P2 P20: P21: P22: P23: P24: P25: P26: P27:
EQU EQU EQU EQU EQU EQU EQU EQU
; Port P1 P10: P11:
EQU EQU
90H 91H
; ;
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P12: P13: P14: P15: P16: P17:
EQU EQU EQU EQU EQU EQU
; Port P0 P00: P01: P02: P03: P04: P05: P06: P07:
92H 93H 94H 95H 96H 97H
; ; ; ; ; ;
80H 81H 82H 83H 84H 85H 86H 87H
; ; ; ; ; ; ; ;
(AD Bus)
EQU EQU EQU EQU EQU EQU EQU EQU
; Bits of ACCUMULATOR A 0E0H A0: A1: A2: A3: A4: A5: A6: A7:
EQU EQU EQU EQU EQU EQU EQU EQU
0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0E7H
; ; ; ; ; ; ; ;
0F0H 0F1H 0F2H 0F3H 0F4H 0F5H 0F6H 0F7H
; ; ; ; ; ; ; ;
; Bits of B Register 0F0H B0: B1: B2: B3: B4: B5: B6: B7:
EQU EQU EQU EQU EQU EQU EQU EQU
; End of the Internal Register and Bits definition ; ;****************************************************** ;DEFINITIONS OF RAM BYTE ADDRESS LOCATIONS for program ;****************************************************** LCDDAT: KEYCOD:
EQU EQU
30H 31H
;****************************************************** ;DEFINITIONS OF RAM BIT ADDRESS LOCATIONS for program ;****************************************************** ;**************************
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GFLGS: EQU ; Bit Definitions of LCDSTA LP27: EQU
20H
; General flags
00H
; Latch data of port bit P27
;************************** ;****************************************************** ;DEFINITION OF CONSTANTS ;****************************************************** ; ;LCW: EQU 00H ; ;****************************************************** ;DEFINITION OF EXTERNAL DATA LOCATIONS ;****************************************************** P8255A: EQU
0E0H
;
;****************************************************** ;PIN-OUT DEFINITION OF 8255 PORT PINS ;****************************************************** ;****************************************************** ; MAIN PROGRAMS AND SUBROUTINES BANK 00 ;****************************************************** ; ; Register Definitions for BANK 00 ; ;****************************************************** ; ; Initializations: RST:
ORG
0000H
; Reset vector AJMP STRT
; Beginning of Main Program
INTEX1: ORG 0013H AJMP ISREX1
; The External Interrupt '0' Vector ; jump to ISR for external interrupt 0
;INT0:
; The Timer '0' Interrupt Vector ;AJMP ISRT0 ; Jump to ISR for timer 0
ORG
000BH
; ****************** ; Subroutine ;Name : INIT ;Org : ;Funct : This is the main program ; ;Calls : This subroutine calls all the other subroutines ; ;Input : ;Output :
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;Description: ; ; ****************** ; ORG 100H ISREX1: CPL F0 JB F0,THERE SETB TR0 RETI THERE: CLR TR0 CLR EA CLR EX1 CLR P10 RETI STRT:
MOV SP,#60 MOV TMOD,#11H SETB EA SETB EX1 SETB IT1 MOV TH0,#00H MOV TL0,#00H SETB F0 SETB P10
;TIMER IN MODE 1 ;TO ENABLE NEGATIVE EDGE TRIGGERED EXTERNAL INTERRUPT ;USER FLAG IN PSW
YY: EXIT:
JNB P10,EXIT SJMP YY MOV P1,TL0 MOV P2,TH0 END
;WAIT FOR INTERUPT
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OBSERVATIONS
FREQUENCY
COUNT IN HEX
DECIMAL
CALCULATED FREQUENCY
PERCENTAGE ERROR
25
9007
36871
24.99
0.0208
500
0734
1844
499.77
0.0452
1000
0398
920
1001.720
0.172098
2000
01EC
492
1873.1367
6.34316
4000
0E6
230
4006.88
0.172098
5000
0B8
184
5008.60
0.172098
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ORIOLE DISPLAY MODULE 1.INTRODUCTION The Oriole's Display Module (ODM) is a dot matrix liquid crystal display that displays alphanumerics , Kana (Japanese) characters and symbols. The built-in controller & driver LSl 's provide convenient connectivity between a dot matrix LCD and most 4 or 8 bit microprocessors or microcontrollers. All the functions required for dot matrix liquid crystal display drive are internally provided. Internal refresh is provided by the ODM. The CMOS technology makes the device ideal for applications in hand held, portable and other battery powered instruments with low power consumption. 2.FEATURES • Easy interface with a 4-bit or 8-bit MPU. • Built-in Dot Matrix LCD controller with font 5x7 or with font 5x10 dots. • Display Data RAM for 80 characters (80 x 8 bits). • Character generator ROM, which provides 160 characters with font 5x7 dots and 32 characters with font 5x1 0 dots. • Both display data and character generator RAMs can be read from the MPU. • Internal automatic reset circuit at power ON. • Built-in Oscillator circuit. (No external clock required) • Wide range of instruction functions: Clear Display, Cursor Home, Display ON/OFF, Cursor ON/OFF, Cursor Shift, Display Shift. .
'"
3.OPERATIONAL OVERVIEW 3.1 Busy Flag (BF) When the busy flag is HIGH level. it indicates that controller is in the internal operation mode and the next instruction will not be accepted. When R/W is HIGH and RS is LOW, the busy flag is output from DB7. After the busy flag is set to LOW, the next instruction must be written. 3.2 Address Counter (AC) The address counter (AC) generates the address for the DD RAM, the CG RAM and for the cursor display. When an instruction code for DD or CG RAM address is written to the controller, after deciding whether it is DD RAM or CG RAM, the address information is transferred to AC. After writing into (or reading from) DO or CG RAM display data, AC is , automatically incremented (or decremented ). The data of the AC is output to DB0-DB6 when RS is LOW and R/W is HIGH 3.3 Character Generator ROM (CG ROM) The character generator ROM generates 5x7 dot or 5x1 0 dot character patterns from 8-bit character codes. It can generate 160 types of 5x7 dot character patterns and 32 types of 5x10 dot character patterns. When the 8-bit character code of a CG ROM is written to the DD RAM, the character pattern of the CG ROM corresponding to the code is displayed on the LCD display position corresponding to the DD RAM. 3.4 Character Generator RAM(CG RAM)
The character generator RAM (CG RAM) is the RAM with which the user can rewrite character patterns by program. The CG RAM has the capacity to store a kinds of 5x7 dots or 4 kinds for 5x10 dots. Programming of these character patterns is explained in CG RAM programming.
43
4.INTERFACING ODM TO MPU The data bus with MPU is available either once for 8 bits 1- operation or 4 bit 2-operation allowing the ODM to be interfaced with either an 8 bit or 4 bit MPU. When the interface data is 8 bits long ,data bits DB0 to DB7(8) are all used and data input/output is carried out simultaneously. When the interface data is 4 bits long, the data is transferred using only 4 bits (DB4-DB7) while DB0-DB3 are not used. Data transfer between the ODM and the MPU is completed when 4-bit data is transferred twice. Data of the higher order 4 bits is transferred first, then the lower order 4 bits is transferred. Check the busy flag after 4-bit data has been transferred twice (one instruction). A 4 bit 2operation will then transfer the busy flag and address counter data. The latched data controls the driver for generating drive waveform outputs, Send of serial data always starts at the display data character pattern, corresponding to the last address of the display data RAM (DD RAM).
5.DETAIL DESCRIPTION OF INSTRUCTION 5.1 Clear Display RS R/W DB7 DBs DBs DB4 DB3 DB2 DB1 DB0 Code 0 0 0 0 0 0 0 0 0 0 When this instruction is executed, the LCD display is cleared. Returns display to its original status if it was shifted. The cursor or blink go to the left edge of the display (the left end of the first line if 2-line mode). Writes space code "20" (hexadecimal) (character pattern for character code "20" is blank pattern) into all DD RAM addresses. Sets DD RAM address 0 in address counter (AC). Set I/D = 1 (Increment Mode) of Entry Mode. S of Entry Mode doesn't change. 5.2 Return home RS RNJ DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 0 0 0 0 0 0 0 0 1 1 The cursor or blink go to the left edge of the display (to the left end of the first line in the 2 line display mode). Returns display to its original status if it was shifted. DD RAM contents do not change. Sets the DD RAM address 0 in address counter. 5.3 Entry mode set RS RNJ DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 0 0 0 0 0 0 0 1 I/D S I/D : When the I/D is set, the 8-bit character code is written or read to and from the DO RAM, the cursor and blink shift to the right by 1 character position (I/D = high; increment) or to the left by 1 character position ( I/D = low; decrement). The address counter is incremented (I/D = High) or decremented (I/D = Low) by 1 at this time. Even after the character pattern code is written or read to and from the CG RAM, the address counter (AC) is the incremented (I/D = High) or decremented (I/D = Low) by 1. S: Shifts the entire display either to the right or to the left when S is 1; to the left when I/D = 1 and to the right when I/O = O. Thus it looks as if the cursor stands still and the display moves. The display does not shift when reading from the CG RAM when S=0.
44
PIN CONNECTIONS Symbol
Pin No.
Function
Level __
1.
0V
Vss __
2.
Vdd __
5V __
Power Supply
3
Vl
4.
RS
H/L
H: Data input L: Instruction data input
5.
R/W
H/L
H: Data read L: Data write
6.
E
H.H/L
7.
D0
H/L
8.
D1
H/L
9.
D2
H/L
10.
D3
H/L
11.
D4
H/L
12
D5
H/L
13.
D6
H/L
14.
D7
H/L
Enable signal
Data Bus Line
45
46
EXPERIMENT 2 INTERFACING LCD WITH 8051
47
;****************************************************** ; File Name: LPD Dated: 12/07/05 ; Name: TO MEASURE FREQUENCY OF INPUT SQUARE WAVE AND DISPLAY ; ON LCD ; ; ; ; ;****************************************************** ;INCLUDED, IS A LIST OF THE REGISTER AND BIT NAMES ;WITH THEIR CORRESPONDING ADDRESSES. THESE MAY ;BE SPECIFIED AS PART OF THE ASSEMBLER CODE, OR ;MOVED TO THE END OF THE 8051 TABLE FOR GREATER ;TRANSPARENCY. ;***************************************************** CPU "8051.TBL" HOF "INT8" ;****************************************************** ; ;MCS-51 INTERNAL REGISTERS ; B: EQU 0F0H ;B REGISTER ACC: EQU 0E0H ;ACCUMULATOR A: EQU 0E0H ;ACCUMULATOR PSW: EQU 0D0H ;PROGRAM STATUS WORD IPC: EQU 0B8H ;INTERRUPT PRIORITY P3: EQU 0B0H ;PORT 3 IEC: EQU 0A8H ;INTERRUPT ENABLE P2: EQU 0A0H ;PORT 2 SBUF: EQU 99H ;SEND BUFFER SCON: EQU 98H ;SERIAL CONTROL P1: EQU 90H ;PORT 1 TH1: EQU 8DH ;TIMER 1 HIGH TH0: EQU 8CH ;TIMER 0 HIGH TL1: EQU 8BH ;TIMER 1 LOW TL0: EQU 8AH ;TIMER 0 LOW TMOD: EQU 89H ;TIMER MODE TCON: EQU 88H ;TIMER CONTROL PCON: EQU 87H ;POWER CONTROL REGISTER DPH: EQU 83H ;DATA POINTER HIGH DPL: EQU 82H ;DATA POINTER LOW SP: EQU 81H ;STACK POINTER P0: EQU 80H ;PORT 0 ; ;MCS-51 INTERNAL BIT ADDRESSES ; CY: EQU 0D7H ;CARRY FLAG AC: EQU 0D6H ;AUXILIARY-CARRY FLAG F0: EQU 0D5H ;USER FLAG 0 RS1: EQU 0D4H ;REGISTER SELECT MSB RS0: EQU 0D3H ;REGISTER SELECT LSB OV: EQU 0D2H ;OVERFLOW FLAG P: EQU 0D0H ;PARITY FLAG PS: EQU 0BCH ;PRIORITY SERIAL PORT
48
PT1: PX1: PT0: PX0: EA: ES: ET1: EX1: ET0: EX0: SM0: SM1: SM2: REN: TB8: RB8: TI: RI: TF1: TR1: TF0: TR0: IE1: IT1: IE0: IT0:
EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU
0BBH 0BAH 0B9H 0B8H 0AFH 0ACH 0ABH 0AAH 0A9H 0A8H 09FH 09EH 09DH 09CH 09BH 09AH 099H 098H 08FH 08EH 08DH 08CH 08BH 08AH 089H 088H
;PRIORITY TIMER 1 ;PRIORITY EXTERNAL 1 ;PRIORITY TIMER 0 ;PRIORITY EXTERNAL 0 ;ENABLE ALL INTERRUPT ;ENABLE SERIAL INTERRUPT ;ENABLE TIMER 1 INTERRUPT ;ENABLE EXTERNAL 1 INTERR ;ENABLE TIMER 0 INTERRUPT ;ENABLE EXTERNAL 0 INTERR ;SERIAL MODE 0 ;SERIAL MODE 1 ;SERIAL MODE 2 ;SERIAL RECEPTION ENABLE ;TRANSMITT BIT 8 ;RECEIVE BIT 8 ;TRANSMIT INTERRUPT FLAG ;RECEIVE INTERRUPT FLAG ;TIMER 1 OVERFLOW FLAG ;TIMER 1 RUN CONTROL BIT ;TIMER 0 OVERFLOW FLAG ;TIMER 0 RUN CONTROL BIT ;EXT INTERR. 1 EDGE FLAG ;EXT INTERR. 1 TYPE FLAG ;EXT INTERR. 0 EDGE FLAG ;EXT INTERR. 0 TYPE FLAG
; Port Addresses ; Port P3 P30: P31: P32: P33: P34: P35: P36: P37:
EQU EQU EQU EQU EQU EQU EQU EQU
0B0H 0B1H 0B2H 0B3H 0B4H 0B5H 0B6H 0B7H
; RxD ; TxD ; ; ; ; ; WR* for mem mapped I/O (X-Data Space) ; RD* for mem mapped I/O (X-Data Space)
EQU EQU EQU EQU EQU EQU EQU EQU
0A0H 0A1H 0A2H 0A3H 0A4H 0A5H 0A6H 0A7H
; ; ; ; ; ; ; ;
; Port P2 P20: P21: P22: P23: P24: P25: P26: P27: ; Port P1 P10: P11: P12:
EQU EQU EQU
90H 91H 92H
; ; ;
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P13: P14: P15: P16: P17:
EQU EQU EQU EQU EQU
; Port P0 P00: P01: P02: P03: P04: P05: P06: P07:
93H 94H 95H 96H 97H
; ; ; ; ;
(AD Bus) EQU EQU EQU EQU EQU EQU EQU EQU
80H 81H 82H 83H 84H 85H 86H 87H
; ; ; ; ; ; ; ;
; Bits of ACCUMULATOR A 0E0H A0: A1: A2: A3: A4: A5: A6: A7:
EQU EQU EQU EQU EQU EQU EQU EQU
0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0E7H
; ; ; ; ; ; ; ;
; Bits of B Register 0F0H B0: B1: B2: B3: B4: B5: B6: B7:
EQU EQU EQU EQU EQU EQU EQU EQU
0F0H 0F1H 0F2H 0F3H 0F4H 0F5H 0F6H 0F7H
; ; ; ; ; ; ; ;
; End of the Internal Register and Bits definition ; ;****************************************************** ;DEFINITIONS OF RAM BYTE ADDRESS LOCATIONS for program ;****************************************************** Load_LSB16: Load_MSB16:
EQU EQU
30H 31H
; ;
Load_0B32: Load_1B32: Load_2B32: Load_3B32:
EQU EQU EQU EQU
32H 33H 34H 35H
; ; ;
Mul_LSB16: Mul_MSB16:
EQU EQU
36H 37H
; ;
50
Div_LSB16: Div_MSB16:
EQU EQU
38H 39H
; ;
Add_LSB16: Add_MSB16:
EQU EQU
3AH 3BH
; ;
Sub_LSB16: Sub_MSB16:
EQU EQU
3CH 3DH
; ;
Add_0B32: Add_1B32: Add_2B32: Add_3B32:
EQU EQU EQU EQU
3EH 3FH 40H 41H
; ; ; ;
Sub_0B32: Sub_1B32: Sub_2B32: Sub_3B32:
EQU EQU EQU EQU
42H 43H 44H 45H
; ; ; ;
OP_0: OP_1: OP_2: OP_3:
EQU EQU EQU EQU
46H 47H 48H 49H
; ; ; ;
TMP_0: TMP_1: TMP_2: TMP_3:
EQU EQU EQU EQU
4AH 4BH 4CH 4DH
; ; ; ;
CNT_3: CNT_2: CNT_1: CNT_0:
EQU EQU EQU EQU
4EH 4FH 50H 51H
; ; ; ;
NBH: EQU 52H; NBL: EQU 53H; ;****************************************************** ;DEFINITIONS OF RAM BIT ADDRESS LOCATIONS for program ;****************************************************** ;************************** GFLGS: EQU ; Bit Definitions of LCDSTA LP27: EQU
20H
; General flags
00H
; Latch data of port bit P27
;************************** ;****************************************************** ;DEFINITION OF CONSTANTS ;****************************************************** ; ;LCW: EQU 00H ; ;******************************************************
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;DEFINITION OF EXTERNAL DATA LOCATIONS ;****************************************************** P8255A:
EQU
0E0H
;
;****************************************************** ;PIN-OUT DEFINITION OF 8255 PORT PINS ;****************************************************** ;****************************************************** ; MAIN PROGRAMS AND SUBROUTINES BANK 00 ;****************************************************** ; ; Register Definitions for BANK 00 ; ;****************************************************** ; ; Initializations: RST:
ORG 0000H AJMP STRT
INTEX1: ORG 0013H AJMP ISREX1
; Reset vector ; Beginning of Main Program ; The External Interrupt '0' Vector ; jump to ISR for external interrupt 0
; ****************** ; Subroutine ;Name : INIT ;Org : ;Funct : This is the main program ; ;Calls : This subroutine calls all the other subroutines ; ;Input : ;Output : ;Description: ; ; ****************** ; ;************************************************************** ORG 100H ISREX1:
THERE:
PULSE:
CPL F0 JB F0,THERE SETB TR0 RETI CLR TR0 CLR EA CLR EX1 CLR P10 RETI
52
MOV TMOD,#11H SETB EA SETB EX1 SETB IT1
;TIMER IN MODE 1 ;TO ENABLE NEGATIVE EDGE TRIGGERED EXTERNAL
INTERRUPT MOV TH0,#00H MOV TL0,#00H SETB F0 SETB P10
;USER FLAG IN PSW
YY: JNB P10,CONV SJMP YY CONV:
;WAIT FOR INTERUPT
MOV OP_0,TL0 ;COUNT SENT TO MOV OP_1,TH0 ;OPERAND LOCATION MOV Div_LSB16,#0E8H ; DIVISOR=1000D MOV Div_MSB16,#03H ACALL DIV_16 MOV CNT_3,OP_0 ;THOUSAND DIGIT MOV OP_0,R6 ; MOV OP_1,R7 ; MOV Div_LSB16,#64H ; DIVISOR=100D MOV Div_MSB16,#00H ACALL DIV_16 MOV CNT_2,OP_0 ;HUNDRED DIGIT MOV OP_0,R6 ; MOV OP_1,R7 ; MOV Div_LSB16,#0AH ; DIVISOR=10D MOV Div_MSB16,#00H ACALL DIV_16 MOV CNT_1,OP_0 ;TENTH DIGIT MOV CNT_0,R6 ;UNIT DIGIT RET
;*******************************************************************************
;MAIN PROGRAM STRT: MOV SP, #68H ACALL INITAL ACALL PULSE PERIOD OF INPUT SIGNAL ACALL DCNT LJMP EXIT
; Redefine Stack ; Initialize all the chips. ; MEASURE NUMBER OF PULSES IN ONE TIME
;*************************************************************** INITAL:
ACALL INIT1 ACALL INIT2 RET
; Initialize LCD-Function set ; initialize LCD
53
;Liquid Crystal Display ;********************************************************* ; Here are some of the commands to be written ; ; Clear Display = 01h ; Return Home = 02h ; Entry Mode = 06h with increment and no shift. ; Cursor ON = 0Fh with cursor blinking ; Cursor OFF = 0Ch ; Cursor or display shift: ; Cursor Display Shift = 10h left ; = 14h right ; Display Shift (Cursor follows) = 16 left ; = 18 right. ; Function Set =38h for 8 bits, 2 lines and 5x7 dots. ; Set DD RAM = 80h for first line first place (00h to 0Fh) ; = C0h for second line first place (40h to 4Fh) ; ;*************************************** ;**************************************** ; ;
This subroutine gets into function set command by giving large delays without checking the BUSY status.
INIT1:
MOV R7,#03H ; Delay of 15 ms minimum ?? ACALL LDLY ; after power on. SETB LP27 ; Make P27 port bit - input (1) ;-------------------------------------------------------------------------MOV R2, #28H ; Set Function, 4 data lines, ACALL LD_CM1 ; 2 disp lines & 5x7 dots.- command MOV R7,#50H ; delay of 40 ms ACALL DLY ; MOV R2, #28H ; Set function again ACALL LD_CM1 ; MOV R7,#50H ; wait for 40 ms ACALL DLY ; MOV R2, #28H ; Set function again. ACALL LD_CM1 ; RET ; return. ;
subroutine actually initializes the LCD
INIT2:
;
MOV R2, #28H ; Function set, data of 4-bits, ACALL LD_CMD ; 2-lines, 5x7 dots - checks busy MOV R2, #06H ; Entry mode - increment , no shift ACALL LD_CMD ; busy checked MOV R2, #01H ; Clear display ACALL LD_CMD ; busy checked MOV R2, #03H ; Cursor - return home ACALL LD_CMD ; busy checked MOV R2, #0EH ; Display cursor - no blinking ACALL LD_CMD ; busy checked RET ; subroutine for checking busy flag.
54
CHK_BF: MOV CHK_B1:
; ;
; clear user flag F0 ; P20-23 input, RS=0, R/W =1, E=0 ; also P27 is an input. ; for reading E is toggled, ie. ; E=1 for MS Nibble ; Status busy bit into C ; and F0 ; make E low for MS Nibble ; E=1 for LS Nibble ; E=0 for LS Nibble ; if busy = 1 then recheck ; else if busy = 0, return
subroutine for loading command to LCD R2 contains command byte. LD_CM1 used if busy is not to be checked
LD_CMD: LD_CM1:
; ;
CLR F0 MOV A, #0AFH P2, A NOP SETB P26 MOV C, P23 MOV F0, C CLR P26 NOP SETB P26 NOP CLR P26 JB F0, CHK_B1 RET
ACALL CHK_BF MOV A, R2 MOV B, #10H DIV AB MOV NBH, A MOV NBL, B MOV A, #80H MOV R0, #NBH XCHD A, @R0 MOV P2, A SETB P26 CLR P26 DEC R0 XCHD A, @R0 MOV P2,A SETB P26 CLR P26 RET
; Check Status for busy flag ; move command byte in R2 to A ; and make two nibbles and ; store them in memory ; ; ; command R/W=0, E=0, RS=0, P27=1 ?? ; put MS Nibble address in R0 and ; exchange nibbles with A ; and output to P2 ; Toggle E ; ; R0 points to LS Nibble ; same for LS Nibble ; ; ; ;
subroutine for loading data to LCD R2 contains data byte. LD_DA1 used if busy is not to be checked
LD_DAT: LD_DA1:
ACALL CHK_BF MOV A, R2 MOV B, #10H DIV AB MOV NBH, A MOV NBL, B MOV A, #80H SETB A4 MOV R0, #NBH XCHD A, @R0 MOV P2, A SETB P26 CLR P26 DEC R0 XCHD A, @R0 MOV P2,A
; Check Status for busy flag ; move data byte to A ; and make two nibbles and ; store them in memory ; ; ; data R/W=0, E=0, RS=0, P27=1 ; make RS=1, for data ; rest same as LD_CMD ; ; ; ; ; ; ;
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SETB P26 CLR P26 RET ;
subroutine displays 'CNT' on LCD
DCNT:
; ; ; ;
; ; ;
MOV R2, #89H ACALL LD_CMD MOV DPTR, #4EH MOV R4, #00H MOV R3, #04H ACALL MESDSP RET
; set position on LCD ; 9th position, 1st line ; point to table for frequency count ; start of Table for frequency count ; number of bytes ; display message ;
subroutine for displaying messagesDPTR points to the relevant Table. R4 contains start of message from Table, = 0 initially R3 contains the number of bytes.
MESDSP:
MOV A, R4 MOVC A, @A+DPTR ADD A,#30H MOV R2, A ACALL LD_DAT INC R4 DJNZ R3, MESDSP RET
DELAY: DLY: LP1:
MOV R7, #05H MOV R6, #00H DJNZ R6, LP1 DJNZ R7, LP1 RET
LDELAY: LDLY:
MOV MOV MOV DJNZ DJNZ DJNZ RET
LP2:
R7, #05H R6, #00H R5, #00H R5, LP2 R6, LP2 R7, LP2
; ; get required byte from Table and put it in A ; ; ; display the byte ; get next byte ; till R3 is zero. ;
; Short Delay with Data in R7 ; Delay = 0.5 * R7 millisec
;Long Delay with data in R7 ;.131 * R7 sec.
;****************************************************************** ;**************************************************** ;***************************************************** ; no pos. TCNT: DFB 43H, 6EH, 74H, 20H ;'Cnt ' (4), 09 ;*************************************************** ; File Name : MATH.ASM
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Load_16: MOV MOV MOV MOV RET
; Loads lower 16 bits of OP registers bytes with value supplied. OP_3, #00H ; OP_2, #00H ; OP_1, Load_MSB16 ; OP_0, Load_LSB16 ; ;
Load_32: ; Loads all OP register bytes with values supplied. MOV OP_3, Load_3B32 ; MOV OP_2, Load_2B32 ; MOV OP_1, Load_1B32 ; MOV OP_0, Load_0B32 ; RET ; Low_16: ; Returns the lower 16 bits of the OP Registers MOV R6, OP_1 ; MOV R7, OP_0 ; RET ; Mid_16: ; Returns the middle 16 bits of the OP Registers MOV R6, OP_2 ; MOV R7, OP_1 ; RET ; High_16: ; Returns the high 16 bits of the OP Registers MOV R6, OP_3 ; MOV R7, OP_2 ; RET ; Div_16: ; This divides the 32 bit OP register by the value supplied. MOV R7,#00H ; MSB MOV R6,#00H ; LSB zero partial remainder MOV TMP_0, #00H ; LSB of Temprary mem MOV TMP_1, #00H ; MOV TMP_2, #00H ; MOV TMP_3, #00H ; MSB MOV R1, Div_MSB16 ; load divisor MOV R0, Div_LSB16 ; MOV R5, #32H ; loop count ; This begins the loop Div_loop: LCALL Shift_D ; shift divedend and return MSB in C MOV A, R6 ; shift carry into LSB of partial REM RLC A ; MOV R6, A ; MOV A, R7 ; RLC A ; MOV R7, A ;
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; Test to see if R7:R6 >= R1:R0 JC Can_sub ; Carry out of R7 shift means R7:R6 > R1:R0 CLR C MOV A, R7 ; Subtract R1 from R7 to see if R1 < R7 SUBB A, R1 ; A = R7-R1, carry set if R7 < R1 JC Cant_sub ; ; at this point R7 > R or R7 = R1 JNZ Can_sub ; jump if R7 > R1 ; if R7 = R1, test for R6 >= R0 CLR C ; MOV A, R6 ; SUBB A, R0 ; A = R6 - R0, Carry Set if R6 < R0 JC Cant_sub ; Can_sub: ; Substracts the divisor from the partial remainder CLR C ; MOV A, R6 ; SUBB A, R0 ; A = R6 - R0 MOV R6, A ; MOV A, R7 ; SUBB A, R1 ; A = R7 - R1 - Borrow MOV R7, A ; SETB C ; to shift 1 into quotient. SJMP Quot ; Cant_sub: ; Shifts a zero into quotient CLR C ; Quot: ; shifts the carry into the quoteient LCALL Shift_Q ; ; Test for completion DJNZ R5, Div_loop ; ; Now we are all done, move the TMP values back int OP MOV OP_0, TMP_0 ; MOV OP_1, TMP_1 ; MOV OP_2, TMP_2 ; MOV OP_3, TMP_3 ; RET Shift_D: ; Shifts the dividend one-bit to the left and returns the MSB in C CLR C ; MOV A, OP_0 ; RLC A ; MOV OP_0, A ; MOV A, OP_1 ; RLC A ; MOV OP_1, A ; MOV A, OP_2 ; RLC A ; MOV OP_2, A ; MOV A, OP_3 ; RLC A ; MOV OP_3, A ; RET ;
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Shift_Q: ; Shift the quotient one bit to the left and shift the C into LSB MOV A, TMP_0 ; RLC A ; MOV TMP_0, A ; MOV A, TMP_1 ; RLC A ; MOV TMP_1, A ; MOV A, TMP_2 ; RLC A ; MOV TMP_2, A ; MOV A, TMP_3 ; RLC A ; MOV TMP_3, A ; RET ; EXIT: NOP END
The LM34 is a versatile device which may be used for a wide variety of applications, including oven controllers and remote temperature sensing. The device is easy to use (there are only three terminals) and will be within 0.02°F of a surface to which it is either glued or cemented. The TO-46 package allows the user to solder the sensor to a metal surface, but in doing so, the GND pin will be at the same potential as that metal. For applications where a steady reading is desired despite small changes in temperature, the user can solder the TO-46 package to a thermal mass. Conversely, the thermal time constant may be decreased to speed up response time by soldering the sensor to a small heat fin.
