Synthesis of Lithography Test Patterns through Topology-Oriented Pattern Extraction and Classification Seongbo Shim, Woohyun Chung, and Youngsoo Shin Department of Electrical Engineering KAIST, Daejeon 305-701, Korea
ABSTRACT Comprehensive and compact test patterns are crucial to the development of new semiconductor technology. In particular, the random nature of routing layers tends to create many hotspots, corresponding to patterns which are difficult to predict. Conventional group of test patterns consists of parametric typical patterns and real layout clips, which contain a lot of redundancy. The paper addresses a problem of generating comprehensive yet compact group of test patterns for random routing layers. A new method of pattern extraction and classification is proposed to solve the problem. Keywords: Lithography, test pattern, pattern extraction, pattern classification
1. INTRODUCTION When a new semiconductor technology is being developed, the design restrictions and lithography options have to be optimized, with the aim of achieving defect-free images during mass production. Test patterns are used for this purpose, and they should exhibit correspondence to a large proportion of the patterns encountered in actual circuits.1 Dense line and space (DLS) patterns, isolated (ISO) patterns, and line-end to line-end (E2E) patterns, shown in Figure 1(a), are some of the parametric patterns, which are commonly used for lithography and design rule optimization.2 These patterns are configured by a few geometric parameters to produce a diverse set of patterns. The patterns in metal routing layers tend to be random as shown in Figure 1(b). So, test pattern for these layers cannot be generated parametrically as too many parameters would be required. Clips from actual layouts, which contain various complicated 2D patterns, as shown in Figure 1(c), can be used instead,3 but these usually contain many uninteresting and duplicate patterns. We propose a new method of generating comprehensive yet compact test patterns, particularly for metal routing layers. This is done through pattern extraction and classification as outlined in Figure 2. A number of clips from layouts are decomposed into a large set of patterns, from which the significant patterns, the patterns that are likely to create hotspots, are extracted. These are classified and grouped into small sets of geometrically similar patterns; from each group we then select a small set of representative patterns. By comparing these sets of representative patterns across layouts, we can quantify the similarity of layouts, and we finally create a test pattern group from the set of representative patterns. Further author information: (Send correspondence to Seongbo Shim) Seongbo Shim: E-mail:
[email protected], Mobile: +82 10 7136 7738
Design-Process-Technology Co-optimization for Manufacturability VIII, edited by John L. Sturtevant, Luigi Capodieci, Proc. of SPIE Vol. 9053, 905305 · © 2014 SPIE CCC code: 0277-786X/14/$18 · doi: 10.1117/12.2046142 Proc. of SPIE Vol. 9053 905305-1 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 07/02/2014 Terms of Use: http://spiedl.org/terms
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Figure 1. Example of (a) a parametric pattern, (b) a 2D random pattern, and (c) a clip from an actual layout. Pattern extraction Pattern extraction
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Figure 2. Proposed method of synthesizing lithography test patterns.
The remainder of this paper is organized as follows. In Section 2, we propose a topology-oriented method of extracting significant patterns from layouts. New methods of classifying these patterns are presented in Section 3. In Section 4, we apply these methods to several test layouts, and explore ways of increasing the variety of patterns; and we eventually propose a procedure for synthesizing high-coverage test patterns. In Section 5, we draw conclusions and suggest directions for future work.
2. TOPOLOGY-ORIENTED PATTERN EXTRACTION To obtain a set of representative patterns for a given layout, we need to decompose that layout into small patterns. Our aim is to extract patterns corresponding to all the hotspots in the layout, while keeping the total number of patterns as small as possible, to limit complexity of pattern classification, which increases as the square of the number of patterns. The requirements for the pattern extraction can be summarized as follows: • All hotspots in a given layout should be represented by the captured patterns. • Only complicated patterns should be captured, because simple patterns should be presented in parametric test patterns.
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Conventional pattern extraction Conventional pattern extraction
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Figure 3. Comparison of (a) conventional and (b) proposed pattern extraction methods.
• A single hotspot should not be represented by multiple patterns. The conventional approach to pattern extraction does not satisfy these requirements because it captures patterns at regular geometric intervals, as shown in Figure 3(a). In this example, the conventional approach yields 24 patterns, which include redundant ones: we would expect patterns 2, 5, 6, 8, 9, 19, 20, 21, 22 in Figure 3(a) to appear in a set of parametric patterns; and the pairs of patterns 1 and 10, 7 and 12, 13 and 15, and 23 and 24 overlap each other too much, and one pattern in each pair is therefore redundant. Our topology-oriented pattern extraction procedure is shown in Figure 3(b). First, the regions which satisfy the following conditions are identified: • Projections: locations where a line-end can be projected on to a neighboring line (such as these marked 1, 3, 4, 5, 7). • Close ends: a location between two close line-ends in close proximity (such as the location marked 2). Locations satisfying these two conditions are subjected to further procedures as follows: • Adjacency: locations that are close together are merged (such as the locations marked 6). • Sandwich: only locations sandwiched between two or more lines are selected (such as these marked 3, 4, 6, 7). Patterns are then extracted centered on each location, with the aim of having a hotspot near the center of every pattern. Each captured region should span over more than five lines (or spaces) of minimumpitch design rule; polygons are taken into account in a subsequent retargeting process. In the example of Figure 3(b), this method yields just 4 patterns; we see that insignificant and redundant patterns have been excluded, and there is little overlap between the captured regions. We verified that the small number of patterns extracted by our technique contain all the lithography hotspots in a layout clip. Figure 4 shows that hotspots occur near the locations that our technique identified, and thus lie within a captured region.
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PVB Design layout
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Figure 4. Verifying that the locations for topology-oriented pattern extraction correspond to lithography hotspots. Tolerance
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Figure 5. Examples of pattern classification methods: (a) overlapping area classification, (b) pattern matching classification, and (c) image-based classification.
3. PATTERN CLASSIFICATION After extraction, the patterns are classified into a small number of groups based on geometric similarity. Representative patterns are then identified in each group, and the similarity of two layouts can then be observed in terms of the representative patterns which they have in common. The quality of this assessment strongly depends on the quality of pattern classification. If each group were to contain only identical patterns, then similarity would be underestimated, which implies that a diversity of patterns is overestimated. Therefore we classify patterns using a similarity tolerance, in a process called fuzzy classification. We considered several well-known pattern classification techniques: • Overlapping area classification: the proportion of the area of two overlapping patterns is taken as a measure of their similarity. This is vulnerable to shifting, as shown in Figure 5(a), leading to similarity being underestimated. • Pattern matching (PM) classification: the corresponding edges in two patterns are compared, using some tolerance, as shown in Figure 5(b). However, if the patterns have different number of edges, this method fails, even if two patterns are actually very similar. In addition, it is practically impossible to allocate tolerances to all the edges of every captured pattern. • Image-based classification: each pattern is rasterized, and then the pixels of the resulting images are compared, as shown in Figure 5(c). This approach allows us to use many image processing
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Figure 6. Comparison between (a) the overlapping area classification and (b) the proposed method.
techniques, such as image blurring, weighting, and filtering, but quantization errors due to grid snapping cause shifted patterns to appear dissimilar. We need a pattern classification method which overcomes the limitations of these methods. To avoid problems with shifted patterns, we perform pattern classification in the Fourier domain. It is well known that a shift in space corresponds to a phase shift in the Fourier domain, and the phase term can be eliminated from a Fourier spectrum by taking the square of its absolute value: e F[g(x − x0 )](u) = e−j2πx0 ·u G(u),
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e is the Fourier transforms of g(x), where g(x) is the rasterized image of a pattern, x0 is the shift, G and u is an angular spectrum in the Fourier domain. This allows us to compare patterns regardless of a shift. An example is shown in Figure 6: pattern A is compared to the identical pattern B, which has been shifted along the x- and y-axes. If similarity is calculated in terms of the overlapping area, then it varies with the extent of the shift, as shown in Figure 6(a). Conversely, as shown in Figure 6(b), the similarity determined by the proposed method is almost independent of the shift. Figure 7 shows how geometrically different patterns are clearly distinguished by this method. e 2 for each pattern is converted to a multiWe measure similarity as follows: an image of |G| dimensional vector, and a distance between vectors is obtained. Similarity as a percentage is then √ obtained by dividing this distance by the maximum distance n, where n is the dimension of the vector. Vectors corresponding to patterns are classified using CLARANS,4 which allows similarity tolerances to be defined. This classification method is illustrated in Figure 8.
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Figure 7. Similarity between pattern A and patterns B–D, measured in terms of overlapping area and our method, with results shown below the layouts and spectra, respectively.
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Figure 8. Illustration of our classification method.
4. EXPERIMENTS AND RESULTS 4.1 Layout Similarity Analysis Figure 9 shows the process of layout similarity analysis. Patterns of interest, shown as black dots in Figure 9(b), are captured by our topology-oriented pattern extraction technique. A small number of representative patterns, indicated by the red dots in Figure 9(c), are obtained by our pattern classification method. We now can compute a measure of similarity between two layouts as the ratio between the intersection and the union of the sets of representative patterns from each layout as shown in Figure 9(d). Figure 10(a) shows the similarities of the metal 2 layers in layouts generated using 7 different circuits from Opencores,5 with the same synthesis options, including the core utilization factor, the floorplan aspect ratio, and the via scheme. Interestingly, although these layouts originated from different circuits, they have almost the same kinds of representative patterns (86.1% on average). This suggests preparing many layouts using different circuits is not an efficient way to get a variety of test patterns. However, we found that the core utilization factor, which is the ratio of the sum area of cells to the chip area, affects the variety of patterns in the layout. Figure 10(b) shows average similarities between layouts generated from the same circuit using different core utilization factors. Layouts become less similar as the difference in core utilization factor between the layouts increases, as we see for layout
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Pattern extraction Pattern extraction Pattern extraction Pattern extraction Pattern Classification Layout A
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Figure 9. Our layout similarity analysis process: (a) given layout, (b) pattern of interest (black dots) captured by pattern extraction, (c) representative patterns (red dots) obtained by pattern classification, and (d) layout similarity is the ratio of the number of patterns in the intersection and union of the sets of representative patterns. Layout B Metal 2 100
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Figure 10. Experimental results from layout similarity analysis: layout similarity with respect to (a) type of circuit, (b) core utilization factor, (c) aspect ratio of floorplan, and (d) via scheme.
A in Figure 10(b). In addition, layouts become similar if the core utilization factors of the layouts are small. Similarity between the layouts of 60% and 75% core utilization factors is higher than that between the layouts of 70% and 85% core utilization factors, as shown in Figure 10(b). This suggests that a smaller utilization factor will yield simpler patterns, because there is more area to play with, whereas in a small area the circuit paths have to be more bent or cut off during routing process. Thus, the number of representative patterns from a layout of 90% core utilization factor is about twice of that of 70% core utilization factor. The aspect ratio of circuit floorplan, which is a ratio of a height and width of chip area, increases
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Figure 11. Process of generating a comprehensive set of test patterns: (a) layout inputs listed in Table 1 and patterns of interest (black dots), (b) the test pattern group generated by our process, and an example of a captured pattern; a hotspot is detected at the center of this pattern, and the corresponding hotspots in the input layout are marked by red dots in (a).
the variety of patterns. Figure 10(c) shows the average similarities of 7 layouts with different aspect ratios. Layout similarity is reduced to 51.3%, averaged over all aspect ratios, which is about 35% less than the result of Figure 10(a). We found that the patterns in metal 2 and 3 layers are not affected in the same way by aspect ratio. As the aspect ratio increases, which means the chip height increases but the width decreases, the similarity of patterns in metal 2 layers increases, but in metal 3 layers it decreases. This result is because metal 2 wires mostly run horizontally, so their layer is less strongly affected by increase in aspect ratio. If we introduce redundant vias, which is a common way of improving chip yield, then we obtain substantially different patterns than we get from layouts with singe vias. We compare two layouts, which are generated with single and double via schemes, respectively, from the same circuit. This comparison is performed for 7 different circuits, and Figure 10(d) shows the average similarity for different core utilization factor. When the utilization factor is in the range 60 to 80%, the average layout similarity is less than 27%. But when the core utilization factor becomes very high, layout similarity increases because there is not much space remains to insert redundant vias.
4.2 Synthesis of a Comprehensive Set of Test Patterns The layouts that are input to our process for generating test patterns, shown in Figure 2, determine the quality of those patterns. The results presented in the previous section allow us to focus on synthesis options that improve the variety of patterns: varying the type of circuit and aspect ratio is not effective; but varying the core utilization factor and via scheme is.
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Table 1. Experimental result of test pattern generation
Layout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Circuit A A A A A A B B B B B B C C C C C C
Utilization 0.7 0.8 0.9 0.7 0.8 0.9 0.7 0.8 0.9 0.7 0.8 0.9 0.7 0.8 0.9 0.7 0.8 0.9 Average
Via scheme Single Single Single Double Double Double Single Single Single Double Double Double Single Single Single Double Double Double
# patterns 1862 1959 2167 2139 2340 2639 1781 1999 2100 1815 2392 2460 1778 2089 2276 2329 2639 2798 1987.8
# rep. patterns 125 150 210 201 210 387 175 198 253 219 391 448 189 248 297 439 544 689 287.3
Percentage [%] 6.7 7.7 9.7 9.4 9.0 14.7 9.8 9.9 12.0 12.1 16.3 18.2 10.6 11.9 13.0 18.8 20.6 24.6 13.6
Process of the test pattern generation is illustrated in Figure 11, and experimental results are summarized in Table 1. We prepared 18 layouts by combining the following options: 3 different circuits, 3 core utilization factors (0.7, 0.8, 0.9), and 2 via schemes (single, double redundant vias) as listed in the first 4 columns of Table 1. The patterns of interest are then identified by our topology-oriented method of pattern extraction. The number of patterns obtained is given in Table 1. We then select a set of representative patterns, marked by red dots in Figure 11(a), from each layout by grouping the patterns of interest using our classification method. The number of representative pattern for each layout is given in the sixth column in Table 1. The percentage of representative patterns to the total number of patterns, given in the last column of Table 1, measures the variety of patterns: increasing the utilization factor and the use of double redundant vias both make the layout more complicated, and so a greater variety of patterns is generated. The representative patterns from all the layouts are aggregated and grouped using our classification method, resulting in a set of unique significant patterns. The geometry corresponding to each pattern is then clipped out of the appropriate layout with its context, which is the geometry within twice the optical interaction range (2µm) from the center of the pattern. The clipped patterns are arranged as shown in Figure 11(b), and there is a thick boarder at the boundary of each pattern to prevent geometric artifacts due to clipping. As shown in Figure 11(a) and (b), the proposed method yields a compact test pattern group, containing just 2034 different patterns, an area of which is only 9.6% of the total area of the input layouts. To assess the coverage of the hotspots achieved by our test pattern group, we performed lithography
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verification on both the input layouts and the test pattern group. We then visited all the hotspots in the layout inputs, to see whether they are covered by our test pattern group, shown in Figure 11(b). Black dots in Figure 11(a) are the corresponding patterns to our test patterns, and 97% of hotspots were covered by those patterns. The other 3% of hotspots occur at simple geometries with design rule violation, so we can ignore them although they are not covered by our process; they will not appear in real design. Many hotspots correspond to a single test pattern: for example, the 1367 hotspots, indicated by red dots in Figure 11(a), can be covered by the test pattern shown in Figure 11(b).
5. CONCLUSION We have proposed a new method of generating compact and comprehensive lithography test patterns, aimed especially at metal routing layers, which exhibit hotspots that are difficult to predict using parametric patterns and a few actual layout clips. A topology-oriented method of pattern extraction selects significant patterns from a number of layouts, and spectrum-based pattern classification allows us to identify a small or representative patterns from the selected patterns, without redundancy, and without the issues related to shifting which limit existing classification methods. We demonstrated that all the lithography hotspots in the layouts, from which the patterns were derived, can be identified by the test patterns, even though their area is only 9.6% of that of the layouts. The method that we have proposed could be used to generate a robust hotspot library, which would allow lithography-unfriendly patterns to be prevented during the ECO process. Our method could also be used to select appropriate test patterns for OPC model calibration.
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