Term Project Guide SKEE2263 Sistem Digit Table of Contents Objectives .......................................................................................................................................... 2 Project Scheduling .......................................................................................................................... 2 Option 1: Serial Multiplier ........................................................................................................... 3 Option 2 : Serial Divider ............................................................................................................... 7 Option 3 : GCD Calculator .......................................................................................................... 11 Option 4 : Binary to BCD Converter ....................................................................................... 15
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Term Project Guide
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Objectives • • • •
To build a complete digital design containing a datapath unit and control unit using Schematic Capture To perform top-down design and bottom-up with emphasis on hierarchy, modularity and regularity To implement and test the design on the EPM240 board with all relevant input/output devices To manage a project with the aid of a Gantt Chart
Project Scheduling The term project contributes 30% of your overall marks. At the end of term, you must implement a complete digital system an Altera CPLD board. The titles avalable for the project are listed in this document. To ensure you successfully complete the project, the term project has 6 different tasks, so that you build the complete system incrementally. The following Gantt Chart outlines the tasks. # 1 2 3 4 5 6
Week 1 2 3
Task
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Quartus familiarization Altera built-in module familiarization Construction of combinational modules Construction of sequential modules Datapath unit integration Control unit implementation
The end of each task is a milestone, and you are to deliver the following: Milestone 1 2 3 4 5 6
Date Early week 3 Early week 5 Before break Early week 11 Early week 13 During week 15
Deliverable Multi-bit adder 4-bit to 7-segment decoder Combinational modules of your chosen circuit Sequential modules of your chosen circuit Datapath unit combining all previously designed modules Completed system combining datapath unit and control unit
Completion of each milestone is worth 5% of the overall grade. You have done Milestones 1 and 2. This document describes Milestones 3 and 4 only since the descriptions for Milestones 5 and 6 are the same. If you are interested in pursuing other interesting titles, discuss with your lecturer concerning the specific deliverables for Milestones 3 and 4. Option # 1 2 3 4
Title Serial Multiplier Serial Divider Greatest Common Denominator (GCD) Calculator Binary to BCD Converter
TIP: You can simplify your work by creating a module in Verilog and inserting it in your schematic. You will need to save the circuit as a module by selecting (on the design window) “File|Create/Update|Create Symbol File for Current File”. This generates a .bdf file. In Verilog, you cannot insert a Pre-design Symbol Module (.bdf). You can only insert a verilog file (.v) to use a pre-designed module.
Option 1: Serial Multiplier
Option 1: Serial Multiplier Algorithm Serial multiplication is performed using the shift-and-add algorithm as shown in Figure 1-1.
Figure 1-1: Multiplication using Shift-and-Add algorithm
Datapath
Figure 1-2: Serial Multiplier datapath.
Deliverables Milestone 3 4 5 6
Deliverable 4 bit Carry Look ahead Full Adder 4 bit Parallel Load Shift Register and 9 bit Parallel Load Shift Register Datapath unit combining all previously designed Full Adder & Shift Register Completed system combining datapath unit and control unit
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Milestone 3: 4-bit Carry Lookahead Adder
Figure 1-3: CLA.
Milestone 3a: Create 1- Bit Partial Full Adder
Figure 1-4: PFA. Step 1. Implement a 1-bit binary half adder based on Figure 2. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional simulation show proof that the waveform conform to the Boolean expression of the PFA.
Milestone 3b: 4 bit Carry Look Ahead Generator (CLG)
Step 1. Implement a 4 bit Carry Look Ahead Generator based on the expression given Figure 2.
Option 1: Serial Multiplier
Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional simulation show proof that the waveform conform to the Boolean expression of the CLG by giving 4 test cases. .
Milestone 3c: 4 bit Carry Look Ahead Adder (CLA4) Step 1. Using the four Half Full Adders and a 4 bit Carry look Ahead modules, implement the 4 bit Carry Look Ahead Adder based on Figure 1. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional simulation. Show proof that the waveform conform to the Function of a 4-bit Full Adder giving 4 test cases Step 3: Simulate your circuit using functional and timing simulation. Step 4: Give a snapshot of functional and timing simulation for the following inputs: Cin 0 1 0 1
A[3..0] 0011 0111 1101 1111
B[3..0]
S[3..0]
C4
S3
Gate Delay S2 S1
S0
0100 1001 1000 1111
Note: You will need to determine the period of 1 gate delay.
Milestone 4: 9-bit Shift Register Refer to Figure 1-1. There a two registers located below the adder: one 1 bit register and two 4-bit registers. Each bit must be able to perform 3 functions: hold, load from adder and shift right. We can use the universal shift register as the foundation. It can perform 4 functions. We are not going to use the shift left function.
Figure 1-5: USR.
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Milestone 4a: 1 bit of Universal Shift Register (USR)
Figure 1-6: 1 bit of USR. Step 1. Implement one bit of the USR. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional simulation show proof that the bit cell does what it is supposed to be doing.
Milestone 4b: 4 bit Universal Shift Register (USR) Step 1. Implement the complete 4 bit USR. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional simulation show proof that the bit cell does what it is supposed to be doing i.e. it can do a parallel load (D à Q+) right shift (Q>>1 à Q+), and hold (Q à Q+) .
Milestone 4c: Linked FF and USRs Step 1. Combine 1 FF, and 2 USRs according to Figure 1-2. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional and timing simulation show proof that the whole 9-bit register does what it is supposed to be doing.
Milestone 5: The Datapath Combine the circuits in Milestones 3 through 4 to build the datapath as shown in Fig. 1-2. Simulate using sensible data combinations.
Milestone 6: The Complete System Draw the Algorithmic State Machine (ASM) Chart to control the whole datapath. Build the control unit to implement the ASM chart. Test the system using sensible data combinations. The data set you choose will reveal your knowledge. Choose wisely.
Option 2 : Serial Divider
Option 2 : Serial Divider Algorithm Division in hardware can be done using several methods. One of them is the non-restoring algorithm in Figure 2-1.
Figure 2-1: Non-restoring division.
Datapath
Figure 2-2 Serial Divider
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Deliverables Milestone 3 4 5 6
Deliverable 5 bit Adder/Subtractor 5 bit and 4 bit Parallel Load Shift Registers Datapath unit combining all previously designed Full Adder Shift Register Completed system combining datapath unit and control unit
Milestone 3: 5-bit Ripple Carry Adder/Subtractor
Figure 2-3: 5-bit Ripple Carry Adder/Subtractor.
Milestone 3a: Create 1- Bit Full Adder
Figure 2-4: PFA. Step 1. Implement a 1-bit Full adder based on Figure 2.4. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional simulation show proof that the waveform conform to the Boolean expression of the 1-bit Full adder.
Option 2 : Serial Divider
Milestone 3b: Ex-Or implementation using 2-1 Multiplexer
Figure 2-5: Ex-Or implementation using 2-1 Multiplexer Step 1. Implement a Ex-OR expression based Figure 2. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional simulation show proof that the waveform conform to the Boolean expression of the X = f (A,B) =
.
Milestone 3c: 5 bit Adder/Subtractor Step 1. Using the Full Adders and Ex-Or modules, implement the 5 bit Adder/Subtractor based on Figure 1. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional simulation. Show proof that the waveform conform to the Function of a 4-bit Full Adder giving 4 test cases Step 3: Simulate your circuit using functional and timing simulation. Step 4: Give a snapshot of functional and timing simulation for the following inputs: Add/Sub
A[4..0]
B[4..0]
0 1 0 1
0011 0111 1101 1111
0100 1001 1000 1111
S[4..0]
Note: You will need to determine the period of 1 gate delay.
C5
S4
Gate Delay S3 S2
S1
S0
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Milestone 4: 9-bit Shift Register Refer to Figure 2-1. There a two registers located below the 5-bit adder/subtractor: one 5 bit register and one 4bit registers. Each bit must be able to perform 3 functions: hold, load from adder and shift left. We can use the universal shift register as the foundation. It can perform 4 functions. We are not going to use the shift right function.
Figure 2-5: USR.
Milestone 4a: 5 bit of Universal Shift Register (USR) Step 1. Implement the 5 bit USR. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional simulation show proof that the bit cell does what it is supposed to be doing i.e. it can do a parallel load (D à Q+), left shift (Q<<1 à Q+) and hold (Q à Q+) .
Milestone 4b: 4 bit Universal Shift Register (USR) Step 1. Implement the complete 4 bit USR. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional simulation show proof that the bit cell does what it is supposed to be doing i.e. it can do a parallel load (D à Q+), left shift (D<<1 à Q+) and hold (Q à Q+).
Milestone 5: The Datapath Combine the circuits in Milestones 3 through 4 to build the datapath as shown in Fig 2-2. Simulate using sensible data combinations.
Milestone 6: The Complete System Draw the Algorithmic State Machine (ASM) Chart to control the whole datapath. Build the control unit to implement the ASM chart. Test the system using sensible data combinations. The data set you choose will reveal your knowledge. Choose wisely.
Option 3 : GCD Calculator
Option 3 : GCD Calculator Algorithm The greatest common divisor (GCD) of two numbers is the largest number that divides both of them without leaving a remainder. The GCD of 54 and 24 is 6 as shown below: The number 54 can be expressed as a product of two integers in several different ways: 54 x 1 = 27 x 2 = 18 x 3 = 9 x 6 Thus the divisors of 54 are: 1,2,3,6,9,18,27,54 Similarly, the divisors of 24 are: 1,2,3,4,6,8,12,24 The numbers that these two lists share in common are the common divisors of 54 and 24: 1,2,3,6
The greatest of these is 6. That is, the greatest common divisor of 54 and 24. One writes: gcd(54,24) = 6. GCD is popularly solved using Euclid’s algorithm. The pseudocode: function gcd(x, y) while x ≠ y if x > y x := x − y; else y := y − x; return x;
Datapath To make the circuit useful but still simple enough, data size of 6 bits is chosen.
Figure 3-1 GCD Engine (http://www.gstitt.ece.ufl.edu/courses/spring13/eel4712/labs/lab5/lab5Spring13.pdf)
Deliverables Milestone 3 4 5 6
Deliverable 6-bit 2:1 mux, 6-bit subtractor (lpm_addsub), 3 6-bit registers, 6-bit comparator (iterative) Datapath unit combining all modules shown in Fig. 3-1 Completed system combining datapath unit and control unit
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Milestone 3: 6-bit Ripple Subtractor & Mux Milestone 3a: 6 bit Mux Step 1. Based on the mux you used in Milestone 2, expand it to 6 bits. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional simulation. Show proof that the waveform conform to the function of a 6-bit mux using 4 test cases.
Milestone 3b: 6 bit Subtractor
Figure 3-3 lpm_add_sub Step 1. Pick the lpm_add_sub symbol from the Altera MegaWizard. Configure it as a 6-bit subtractor. Disable the adder function. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional and timing simulation. Show proof that the waveform conform to the function of a 6-bit mux using 4 test cases. X[5..0]
Y[4..0]
54 24 0 63 1 31 0
24 54 63 0 2 31 0
D[4..0]
Option 3 : GCD Calculator
Milestone 4: Registers and Comparator
Milestone 4a: DFFE
Figure 3-3 DFFE Step 1. Build the DFF with enable as shown in Figure 3-3. Refer to your textbook for explanation on how it works. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional and timing simulation. Show proof that you understand how to use the DFFE. Step 3: Save the circuit as an Altera module called DFFE.
Milestone 4a: 6 bit Register with Enable Step 1. Combine 6 units of the DFFE to build a 6-bit register with 6-bit data input, 6-bit data output, one clock input and one enable input. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional simulation. Show proof that you understand how a register with enable works.
Milestone 4c: One Bit Comparator
Step 1. Build one slice of the iterative comparator. Refer to the textbook for more details. Step 2.
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Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional simulation. Show proof that you understand how the comparator worksl. Step 3: Save the circuit as an Altera module called comp1bit.
Milestone 4d: Six Bit Comparator
Step 1. Combine 6 comp1bit modules to build a 6-bit comparator. Add the necessary gates to produce the x_lt_y and x_ne_y signals as shown in Figure 3-1. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional and timing simulation. Use the following test data. X[5..0]
Y[4..0]
54 24 0 63 1 31 0
24 54 63 0 2 31 0
x_lt_y
x_ne_y
Step 3: Save the circuit as an Altera module called DFFE.
Milestone 5: The Datapath Combine the circuits in Milestones 3 through 4 to build the datapath in Figure 3-1. Simulate using sensible data combinations.
Milestone 6: The Complete System Draw the Algorithmic State Machine (ASM) Chart to control the whole datapath. Build the control unit to implement the ASM chart. Test the system using sensible data combinations. The data set you choose will reveal your knowledge. Choose wisely.
Option 4 : Binary to BCD Converter
Option 4 : Binary to BCD Converter Algorithm Converting 255 from binary to BCD: // Double-dabble algorithm Hundreds = 0; Tens = 0; Ones = 0; for (i=0; i<8; i++ { // check all columns >= 5 if (Hundreds >= 5) Hundreds += 3; if (Tens >= 5) Tens += 3; if (Ones >= 5) Ones += 3; // shift all bits left Hundreds <<- 1; Hundreds[0] = Tens[3]; Tens <<= 1; Tens[0] = Ones[3]; Ones <<= 1; Ones[0] = Binary[7] Binary <<= 1; }
Hundreds
Tens
1
1
11 110 1001 0010
10
0101
Datapath
Figure 4-1 Binary to BCD Engine
Deliverables Milestone 3 4 5 6
Deliverables Custom add-by-3-if-greater-than-4 circuit & 8-bit PISO 2+4+4 bit Universal Shift Register Datapath unit combining all modules shown in Fig. 3-1 Completed system combining datapath unit and control unit
Ones 1 11 111 1010 0101 1000 0001 0011 0111 1010 0101
Binary 1111 1111 111 1111 11 1111 1 1111 1111 111 11 1
Oper. Load << #1 << #2 << #3 +3 << #4 +3 << #5 << #6 +3 << #7 +3 << #8
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Milestone 3: Custom adder and register cell Milestone 3a: Add-3-if-greater-than-4 circuit
Figure 4-2: Custom adder circuit. Step 1. Based on the truth table in Figure 4-2, build the simplest and fastest circuit. Justify your design. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional and functional simulation. Test using all 16 input combinations. Find the worst case delay.
Milestone 3b: PISO register
Figure 4-3: Simplified PISO. Details have been left out. Step 1. Based on 4-bit shift right PISO in Figure 4-3, modify it to shift left and expand it to 8 bits. The 8-bit PISO must have 2 control signals: LD (parallel load) and SH (left shift). LD has higher priority than SH. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional and timing simulation. Prove that you understand how a PISO works. Prove that you understand how to use the LD and SH signals.
Option 4 : Binary to BCD Converter
Milestone 4: 2+4+4 bit Shift Register Refer to the universal shift register in Figure 4-4. Use this register as the foundation for the 2+4+4 Shift Register. First build a module to implement a single bit. Then use it to build the 2-bit Hundreds register and the 4-bit Tens and Ones registers. Note: The Hundreds register is not required to parallel load. You may find a simpler circuit for it later if you like.
Figure 4-4: USR.
Milestone 4a: 1 bit of Universal Shift Register (USR)
Figure 4-5: 1 bit of USR. Step 1. Implement one bit of the USR. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional simulation show proof that the bit cell does what it is supposed to be doing.
Milestone 4b: 4 bit Universal Shift Register (USR) Step 1. Implement the complete 4 bit USR. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional simulation show proof that the bit cell does what it is supposed to be doing i.e. it can do a parallel load (D à Q+) right shift (Q>>1 à Q+), and hold (Q à Q+) .
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Milestone 4c: 2 bit SIPO Step 1. Simplify the 1-bit USR cell in Figure 4-5 so that it can shift left or hold only. Step 2. Compile your circuit until there are no errors. Step 3: Simulate your circuit using functional and timing simulation show proof that the whole 9-bit register does what it is supposed to be doing.
Milestone 5: The Datapath Combine the circuits in Milestones 3 through 4 to build the datapath as shown in Fig. 1-2. Simulate using sensible data combinations.
Milestone 6: The Complete System Draw the Algorithmic State Machine (ASM) Chart to control the whole datapath. Build the control unit to implement the ASM chart. Test the system using sensible data combinations. The data set you choose will reveal your knowledge. Choose wisely.
Option 4 : Binary to BCD Converter
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