Thapar University, Patiala UEC 621: CMOS Circuit Design Tutorial Sheet #9 Instructor: Dr. Alpana Agarwal 1. For a CMOS inverter with (W/L)p=8 and (W/L)n=6 in a process where process transconductance kn =150 µA/V2, kp=60 µA/V2, Vt0,n=+0.7 V, Vt0,p=−0.7 V and uses VDD=3.3 V and total output capacitance is estimated to be 150 fF. Find rise time and fall time by average current method. 2. Find fall time τf in a CMOS inverter with VDD = 3.3 V, CL = 1 pF, µn.COX = 20 µA/V2, (W/L)n = 10, VT0,n = 0.8 V, µp.COX = 9 µA/V2, (W/L)p = 20, VT0,p = − 0.8 V. (Compare the results by average current method and integration method) 3. Find τPHL using the average current method for a load of 1 pF driven by a 10 kΩ resistive-load inverter circuit, where µn.COX = 25 µA/V2, W/L = 10, VT0 = 1 V. Assume input to be ideal rectangular pulse switching between 0 V & 5 V. 4. A CMOS inverter is characterized by the switching times tr = 430 + 3.68 CL ps and tf = 300 + 2.56 CL ps with external load capacitance CL in units of fF. • Plot the rise and fall times for the range CL = 0 to CL = 200 fF. • A three inverter cascade is built using identical circuits. Find the worst-case delay through the chain if the output capacitance to each NOT gate is CL = 45 fF. 5. A 1 pf load is driven by a 10-kΩ resistive load inverter circuit. Given µn.COX = 25 µA/V2, W/L = 10, VT0 = 1.0 V. Find τPHL and τPLH by using the average current method. Assume input switches from 0 to 5 V with zero rise/fall times. 6. A CMOS inverter has the following device parameters: nMOS: VT0,n = 0.8 V, µn.COX = 50 µA/V2 pMOS: VT0,p = − 1.0 V, µp.COX = 20 µA/V2 The VDD = 5 V, Ln = Lp = 1 µm, CL = 2 pf. a. Determine the channel width of the nMOS and pMOS transistors such that the switching threshold voltage is equal to 2.2 V and the output rise time is 5 ns. b. Calculate the average propagation delay for the designed circuit. c. How dothe switching threshold and the delay times change if the power supply voltage is dropped from 5 V to 3.3 V. Provide an interpretation of the results. 7. A CMOS inverter has the following parameters: nMOS: VT0,n = 1.0 V, µn.COX = 45 µA/V2 (W/L)n = 10 pMOS: VT0,p = − 1.0 V, µp.COX = 20 µA/V2 (W/L)p = 20 The VDD = 5 V and CL = 1.5 pf. a. Calculate the rise time and fall times of the output signal using i. Average current method ii. Integral method b. Determine the maximum frequency of a periodic square wave input signal so that the output voltage can still exhibit a full logic swing from 0 V to 5V in each cycle. -------------