THE ARCHITECTURE OF THE SPERRY UNIVAC 11OO SERIES SYSTEMS

B.R. Borgerson, M.D. Godfrey, P.E. Hagerty, T.R. Rykken

~I=Er~v.~,,UNIVAC Blue Bell, PA.

Abstract

Main Storage (up to 4M words)

This paper presents an overview of the architecture of the SPERRY UNIVAC® 1100 Series systems. The principal topics are instruction and data formats, main storage and addressing, process management, and I/O.

Cache (8K to 16K words)

Introduction The SPERRY UNIVAC® 1100 Series architecture was introduced in the early i960's. The basic architectural features common to all models of the 1100 Series are binary arithmetic, a fixed-length 36-bit word, a fixed-length single-address instruction, and a large set of general and special-purpose registers. Since the introduction of the 11 O0 Series, its architecture has changed in several major respects. Process management features have been added, along with features to support multiprogramming and multiprocessing. Other additions include address relocation and storage protection registers, the extension of data types to include double-precision binary numbers and 9-bit characters, and expanded addressing capability. Evolution of the architecture of the 1100 Series has had four steps which occured chronologically in models 1107, 1108 (1106, 1100/10, 1100/20), 1110 (11OO/40), and 1100/80. The models-shown in parentheses are technology enhancements of the respective original models. This paper gives an overview of the architecture which is common to all models of the SPERRY UNIVAC 1100 Series and points out architectural differences among models. Although this Series has existed for many years, no concise description of the architecture has existed. The only previously published paper 1 traces the evolution of the 1100 Series from the introduction of the 1107 in 1962 to the present. Since many other aspects of the Series were discussed in that paper, only a cursory description of the architecture could be given there. A simplified block diagram of a two-processor 11G0/80 system is shown in Figure 1. The 1100/80 is used here as the principal representative of the 11OO Series; where other models differ significantly, these differences are described specifically. The 1100 Series is characterized as a family because model dependencies are generally hidden from applications programs. The same operating system has been used on all 1100 Series models subsequent to the 1107. Since the introduction of the 1108, changes in the nonprivileged instructions have been upward compatible, and differences in the privileged instructions are resolved by the operating system.

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The requirement for upward compatibility has strongly influenced the evolution of the 1100 Series. Some architectural features with roots in the 1107 probably would not appear in a contemporary machine such as the 11OO/80 if upward compatibility were not required. The basis for full user-level upward compatibility is the 1100 Operating System. Since this system was first made available on the 1108, the 1107 will be excluded from further discussion in this article. System Structure The major architectural components of an 1100 Series system are Instruction Processors (tPs), Input-Output Units (IOUs), and Main Storage Units (MSUs). Additional processing capability is frequently included in an 1100 Series system to enhance such functions as communications processing or on-line maintenance, but these specialized processors are not essential components from an architectural standpoint and hence will not be discussed here.

CH1394-6/79.0000-0137 $00.75~1979 IEEE IB7

The 1100 Series IPs perform all general computational functions within the system. IOUs perform a limited set of functions for the purpose of controlling data flow into and out of main storage. An 1100 Series system normally is configured as a tightly coupled multiprocessor system containing multiple IPs and multiple IOUs. All IPs and IOUs can address all of main storage. Thus, only a single copy of operating system code is maintained in storage. Shared code and data is accessible to all processors, and any user or system code may be executed on any or all of the processors at any time. Usually, multiprocessor configurations are symmetric; since symmetry implies multiple paths between components, this leads to an improvement in system availability and throughput.

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The instructions use a single-address format with an operand register specifier as part of the instruction. Operand registers are of three types: A registers are used for arithmetic, X registers are used as index registers, and R registers are used for special functions such as masking. Four registers are usable as either A or X registers, and not all R registers have assigned functions. Some arithmetic can be done in the X registers. In addition to being usable as register operands, the registers are assigned addresses in the storage address space. Although the instruction set appears to be register-storage operations, register-register operations are done by specifying the storage address associated with a register. Indirect addressing is permitted to an arbitrary depth, and indexing may be independently specified at each step in an indirect addressing chain.

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The SPERRY UNIVAC 1100 Series is a word-oriented family of information processing systems. Main storage is word addressable and all instructions are one 36-bit word long. Some instructions can operate on fields within words and others can operate on multiple words.

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The 1100 Series IPs are two-~mode machines and run in either user or privileged mode. Only the operating system may use privileged mode. There are two complete sets of A, X, and R registers. Program segmentation, dynamic relocation, and storage protection are implemented by segment descriptor registers.

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Figure 2 shows the architecturally defined arithmetic data formats. The most important of these are the single-precision (36-bit) integer and floating-point formats and the double-precision (72-bit) floating-point format. Ones complement notation is used throughout to represent negative values. This simplifies the imp!ementation of logical operations (the logical and arithmetic complements of a number are the same), but gives rise to the problem of two representations of zero. The arithmetic hardware generates negative zero for zero in only a few special cases. Negative and positive zeroes are usually treated alike when used as inputs to arithmetic or comparison operations.

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Most arithmetic operations are carried out on full words, but many instructions have a field that can be used to reference part of a word. if an instruction that fetches an operand from main storage specifies a partial word, the partial word is extracted, right justified, and filled to full word length with either zeroes or sign bits before being used. When register data is stored in a partial word, the full-word value is truncated on the left to the required number of bits and then packed into the appropriate part of the .word in storage.

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138

where the meanings of the fields are:

Floating-point numbers are binary normalized. The binary exponent field is biased. The single-precision and double-precision floating-point formats differ not only in the number of fraction bits, but also in the size of the exponent field. The single-precision format has a sign bit, an 8-bit exponent field and a 27-bit fraction field. This gives an exponent range of approximately 10 -38 to 1038 and a precision of about eight decimal digits. The double-precision format has a sign bit, an 1 t - b i t exponent field, and a 60-bit fraction field. This gives an exponent range of approximately 10 -3o8 to 103°8 and a precision of approximately eighteen decimal digits. The 6 0 - b i t fraction format was chosen because it provided more bits in both the fraction and the exponent than the main competitive systems which duplicated the 9-bit sign and exponent field in the second 36-bit word.

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For many values of f, the j field specifies the operand reformatting that occurs in step 5 or 7 of the instruction execution; the specific fields that may be selected from within a word are shown in Figure 3. Although these instructions can use the contents of the j field to generate immediate operands or select partial words, the basic addressable unit of storage is still a full word. The partial-word selection is part of the operation code, not the address, and hence cannot be modified by indexing.

The results of a floating-point operation (either precision) are always normalized. A word of all zero bits is treated as a normalized floating-point zero. The floating-point representation (sign bit, biased exponent, fraction) allows the same comparison instructions to be used on both integer and floating-point data. Instructions are provided that convert between the various integer and floating-point formats.

A limited form of byte addressing was introduced in the 1110 and carried forward into the 1 1 0 0 / 8 0 . Some of the instructions introduced at that time use the j field as a register selector, and addressing functions were assigned to some of the previously unused R registers.

The half- and third-word integer data formats are historical remnants of an applications requirement for very fast arithmetic to be done on integers of limited range. To satisfy this requirement, half- and third-word arithmetic instructions were added to the repertoire of the 1107. These instructions operate on the halves (or thirds) of a single word in parallel, thus gaining a speed increase of two (or three) over full-word arithmetic. This feature has been retained in all subsequent models of the 1100 Series for compatibility.

When the j field is not used as above, it is usually concatenated with the f field to form a l O - b i t operation code. For those values of f for which this is done, the meaning of j varies from instruction to instruction. One major function code concatenates the j field and the a field to form a single 8-bit quantity the value of which is used as a register designator for a loop count instruction that makes no functional distinction between A , X , and R registers.

Instruction Execution

The a field specifies an operand register in register storage. This may be an A , X , or R register depending on the major function code. The organization of the register store is described below. The x , h, i, and u fields control jointly the formation of operand addresses. The x field specifies an index register and u is an offset value. An index register is treated as two 18-bit halves: the increment, X i, and the modifier, X m. Address formation is done with 18-bit quantities; the 16-bit u field is extended with two leading zeroes. The contents of the modifier half of the specified index register is added to the (extended) u field of the instruction to form an operand address; if the value of the x field of the instruction is zero, no index addition takes place and the content of the u field alone is used as an operand address. The 16-bit u field allows direct addressing of up to 64K words, while up to 256K words can be addressed with indexing. For generated addresses for which the value of u + Xrn is less than 2008, the operand is obtained from register storage instead of main storage. A simpiified diagram of the 1100 Series addressing structure is given in Figure 4.

Instruction execution generally proceeds by the following steps: 1. 2. 3. 4. 5. 6. 7. 8.

Fetch and decode the instruction Generate the storage operand address Fetch the register operand Fetch the storage operand Reformat the storage operand Perform the specified operation Reformat the result Store the result

For simple instructions, the instruction word fields and the processor state determine the arguments for these eight steps. More complex or specialized instructions may require additional data obtained from or pointed to by registers and may cause iteration of instruction execution steps. All instructions occupy one word; the instruction format below gives the width in bits of each field and the letter designation for each field:

Width (bits)

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major function code minor function code or partial word designator operand register designation index register designation index incrementation indicator indirect addressing indicator operand address offset or immediate operand field

The i bit indicates indirection. If this bit is set, the low order 22 bits (x through u fields) of the current instruction are logically replaced by the corresponding bits of the addressed word, and the standard address formation sequence is repeated. This indirect chain continues until it encounters a word with its i bit clear. The final address developed at the end of the chain is then used as the operand address.

16

The j field values of 168 and 178 specify immediate operand addressing. In this case if x = 0 , then the contents of the low--order 18 bits of the instruction is transferred. If x;¢O, (after applying h and i in the normal way) u + X m is transferred. If

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The A registers may be used for both floating-point and integer arithmetic. Some instructions require two adjacent A registers; integer multiply produces a double-word result, for example. A f e w instructions (e.g., conversion from double-precision floating-point to integer) require three adjacent A registers. Any adjacent A registers may be used in these instructions; there are no odd-even boundary requirements. While not addressable as registers, A 16 and A 17 exist in the hardware. Thus, all arithmetic instructions operate normally using A 15. A 16 and A 17 may be addressed as storage.

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The X registers are used in address generation as noted in the previous discussion of the instruction format. They are also used for subroutine linkage. Integer addition and subtraction can be done in the X registers.

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The R registers are used for special functions. RO is the real-time clock and cannot be altered by a nonprivileged program. R I is used as a counter by move and search instructions, and R2 is used as a mask register by some instructions. R3 through R9 are used as parameter registers by various byte manipulation and editing instructions. No special functions are assigned to the remaining R registers.

Operand 2 No

The A , X , and R registers are implemented in a special processor-local store called the General Register Set (GRS). Figure 5 is a diagram of the GRS. There are 2008 words of GRS, and they are mapped into the address space of a process in locations 0 through 1778 . By software convention, program relative main storage addresses start at relative location 10008 to avoid conflict with GRS addresses. No main storage needs to be allocated to that portion of the address space hidden by the GRS because the base registers used for program relocation provide the appropriate relative address offset.

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To reduce register saves and restores, a separate set of A , X , and R registers is provided for the operating system. These registers are mapped to GRS locations different from those of the user set. When the system is operating in user mode, register designators in the a field and x field of instructions select registers from the user set. A status bit allows operating system code to use either set. When the operating system set is selected, the a and x fields of the instructions select registers from that set and GRS relative addresses (u + Xm) must be used to refer to the user set.

Figure 4. Operand Addressing j is 178 , the resulting 18-bit sum is sign extended with the contents of the high-order bit of the final operand. Operand addresses generated as above are called relative addresses. Relative addresses are the only addresses visible to a user program. After a relative address is developed, the contents of a base register are added to form what is called an absolute address, and the absolute address is used by the hardware to reference main storage. Available to the operating system is an addressing mode which bypasses base register relocation; in this mode, relative addresses are used as absolute addresses and used to reference main storage directly.

Because the GRS is addressable, register-register operations are effected by specifying one register in the operand register field (a field) of an instruction, and the second register by its GRS address (u -f- Xm). The two sets of A , X , and R registers do not occupy all 128 GRS locations; most of the remaining words of the GRS are special-purpose registers used by the operating system and a few are unassigned. GRS locations other than those used f o r t h e user A , X , and R registers are protected from user modification.

The h field selects incrementation of the register indicated by x. This feature facilitates access to tables and arrays. When h is set, the modifier portion, X m, is incremented by the value of X i after the sum u + X m has been developed. This addition treats X i and X m as signed ones complement values.

Each IP contains a 36-bit, nonaddressable processor state register called the designator (D) register. Typical bits indicate the protection state of the segments of the program, the system state (user or privileged mode), and the register set. Some bits are used for the status of arithmetic operations (e.g., divide check, overflow). External events may or may not cause an interrupt, depending on the status bits. If arithmetic interrupts are not specified, a process must test the status bits to determine exception conditions; special instructions are provided for this.

Registers and Status Bits User mode provides 16 A and R register addresses and 15 X register addresses ( X I through X I 5 ) . Not all addresses identify unique registers; the last four X registers are the same as the first four A registers. These four overlapped registers may be used for either indexing or arithmetic.

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Register Designators (decimal) or-"

Segment Selection and Relocation. A segment descriptor exists for each segment. Up to four segment descriptors may be held in segment descriptor registers. These registers determine the current addressing capability of the process.

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Each descriptor register contains a pair of storage limits and a base value. The limits specify the upper and lower relative addresses occupied by the segment. The base value defines the origin of the segment in real storage. A real storage address is the sum of a relative address and the base value.

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Segments are bound to relative addresses when they are created. Since the values in the segment descriptor registers for all segments are distinct, the segments need not be contiguous in relative nor absolute address space. For search purposes, the segment descriptor registers are paired into an even (0 and 2) and an odd (1 and 3) pair, and one pair is treated as primary. If the even pair is primary, the search order is O, 2, 1, 3, otherwise, it is 1, 3, O, 2. The primary pair is determined by the most recent jump target address; i.e., whenever a jump target falls in one of the secondary segments, the search order inverts and the secondary pair becomes primary. A schematic diagram of the algorithm used to translate relative address to absolute address is given in Figure 6.

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Two pointer registers in the GRS locate segment descriptor tables. The descriptor for a segment contains its relative address limits, its base value (if it is in main storage), a use count, and flag bits indicating residency and protection. Figure 7 shows the use of a segment descriptor table. The instruction that activates a new segment specifies the table to be used, the index in that table, and the segment descriptor registers to be used for the new segment. If the new segment is not in storage (the residency fault bit in the descriptor is set), then an interrupt occurs to allow the operating system to load the segment.

154

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Segment Activation. At most four segments can be simultaneously addressable by a program; although a much larger address space of named segments is available. Instructions are provided which allow a program to activate a new segment by changing segment descriptor register contents under controlled circumstances.

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Addressing and Protection

One of the two descriptor tables is dedicated to segn,ents local to the executing program, while the other is used for segments that are known s y s t e m - w i d e and hence sharable among programs. Typical shared segments are the instruction segments of utilities, such as compilers ond the editor, and instruction and data areas used by the data management system (DMS 1100). Each of the tables may contain up to 4 0 9 6 entries, thereby providing programs with two billion words of address space. Although hardware segment names are indices into these tables, system software allows the segments to be symbolically named and resolves the symbolic names to the correct table indices.

The address space as seen by an executing process is a linear address space partitioned into the addressable GRS (locations 0 through 1778) and up to four main storage segments. An instruction may address directly up to 64K words, while 256K words are addressable with indexing. The four segments are of variable length and may start on any 5 1 2 - w o r d boundary in the user address space. The address value in the user space is the sum u + X m. This relative address is then mapped to a real storage (absolute) address by a segment descriptor register. Segment descriptor registers allow segments to be relocated dynamically on any 6 4 - w o r d boundary in real storage.

The segment activation instructions can be used as subroutine call instructions. The parameters that describe the segment to be activated are taken from an index register. After the specified segment has been activated, the program branches to the operand address of the activat,on instruction. The contents of the parameter register is set to the parameters of the segment containing the activation instruction, and the return address also is stored in the register. This enables a called subroutine to return directly to the point from which it was called; it does so by executing a segment activation instruction using the parameters set by the original call.

The 128 words of the GRS are local to e t c h IP. The registers used by a particular process are saved and restored at process switch time and hence are local to the process itself. The address space seen by the process is thus partially local (the register address space) and partially sh~rable with other processes and processors in the system (the main storage address space).

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or underflows. This facilitates storage management for shared segments. Since some programs (i.e., those with stringent response time requirements) may need to keep a s e g m e n t resident even when not in use, the interrupt on zero can be disabled.

Figure 6. Re/ative~To-Absolute Address Translation

S e g m e n t s may be p o s i t i o n e d a n y w h e r e in real storage starting on a 6 4 - w o r d boundary, and a segment may occupy any number of 6 4 - w o r d blocks to a total of 2 5 6 K words. The first word of a segment must fall on a 5 1 2 - w o r d boundary in the relative address space of the program. An individual program has an 18-bit (256K words) address space directly available to it; absolute storage addresses (represented in the various base and pointer registers) are 24 bits, allowing a system to address up to 16 million words of main storage.

Main Storage Management. Main storage is managed on a segment basis. Whole segments are swapped in and out by the operating system as required; there is no paging underneath the segment structure. The segment descriptors in the two tables contain residency fault bits indicating the absence of a segment in main storage. An attempt to activate a nonresident segment causes an interrupt for o p e r a t i n g system intervention. Part of each s e g m e n t descriptor is a use-count field that is incremented by one at each activation and d e c r e m e n t e d by one at each deactivation. Interrupts may be specified to occur when the use count is decremented to zero and always occur when the count overflows

Protection. Since all user-program generated addresses are checked against storage limits and relocated by the base values, a user p r o g r a m c a n n o t address storage that has not been assigned to it. A bit in the descriptor for each segment indicates if the segment can be written into. All write operations into the segment are checked to ensure their validity.

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Process Synchronization. The primary mechanism for process synchronization is the Test-And-Set instruction. The T e s t - A n d - S e t instruction examines the rightmost bit of the leftmost sixth of the addressed storage location. If the bit is zero, the next instruction is executed; if not, an interrupt occurs. In either case, the addressed sixth word is set to one. For this instruction to be effective in synchronizing processes on several processors, it is indivisible; i.e., it is not possible for processor to modify the contents of the sixth word between the time that processor A reads it (for testing) and writes back the resulting value of one.

The code of a segment may be protected against unauthorized use by marking its descriptor as "guaranteed entry point'. A segment so marked cannot be activated except by an activation instruction that simultaneously transfers control to the first word of the segment itself. Model Dependencies. The addressing mechanism above is that of the 1 1 0 0 / 8 0 . Other models exhibit minor differences. The 1110 requires use counts to be maintained by operating system software. The 1108 may have at most t w o active segments. The t w o - s e g m e n t structure was introduced on the 1108 to increase speed by overlapping of instruction and operand references.

T e s t - A n d - S e t instructions are used by the software to provide locks. A process claims the lock by executing a Test and Set. If the bit is zero, the process continues and the bit is set to prevent other processes from successfully claiming the lock. If the bit is set, then the process is interrupted and queued by the operating system. A process clears the lock by storing zero in i(.

Besides these architectural differences, minor implementation differences exist between models. On the 1108, for example, the segment descriptor registers contain absolute instead of relative limit values.

Because a Test-And-Set lock can be cleared by storing zeroes in it, the operating system normally has no way of knowing when such a lock is cleared. Consequently, when a Test and Set causes an interrupt, the interrupted process is put on a queue and periodically reactivated to perform the Test and Set again. This mechanism amounts to having the program periodically poll the lock until some other process clears it. A software interface convention (called T e s t - A n d - S e t Queuing) exists that allows programs to notify the operating system when a Test-And-Set lock has been cleared. If this feature is used, the polling is unnecessary.

On 1108 and 1110 systems, the selection algorithm used for basing restricts certain segments (e.g., those described by bas.e registers 0 and 1 on the 1110) to no more than 64K words. Further, these systems require that segments be positioned to start on 5 1 2 - w o r d boundaries in real storage, rather than the 6 4 - w o r d boundaries of the 1 1 0 0 / 8 0 . Of the differences above, only the 64K segment-size limit and the two (rather than four) active segments of the 1108 are visible to user programs. The remaining differences are handled by the operating system and are invisible to the user.

Interprocessor Signaling. Since all processors share the same storage, a pro~,ess may communicate with another process by sharing storage. A privileged instruction exists to allow a processor to gain the attention of another processor in the system by causing an interrupt on the target processor.

Process Management Although all 1100 Series systems are able to operate with only one IP, the system architecture and s o f t w a r e support multiprocessor configurations of up to four IPs (in the case of the 1110, up to six) all sharing the same main storage. The operating system allows any process to create other processes. The processes that result from the execution of a single program are coequal and share the same local segment descriptor table. Therefore, they can c o m m u n i c a t e by using shared local segments. Different programs executing on behalf of different users can communicate by sharing segments that are described by the system-wide shared segment descriptor table.

Interrupt Structure. Interrupt handling uses a transfer vector. Specific locations in the transfer vector are reserved for different kinds of interrupts; these locations contain jump instructions that transfer to the required interrupt handling routine. The location of the transfer vector in main storage is determined by a register called the Module Select Register. This mechanism allows easy removal of any storage unit from the system for maintenance, and allows the partitioning of a multiprocessor system into isolated systems. The following events occur as the result of an interrupt:

Process Switching. Since all processors are identical, the operating system dispatcher can activate any process on any processor, and a given process will execute typically on several processors during its lifetime. As noted previously, register storage is processor local; tables associated with each process' are used to preserve the register contents when the process is inactive. A process is activated by loading its user registers, segment descriptor register, and designator register, then transferring to its entry address. The process runs until an interrupt of some kind causes control to pass back to the operating system. In this context, the Executive Request instruction (used by programs to request system intervention) can be viewed as causing an interrupt. A user process cannot lock out interrupts. If the process does not voluntarily relinquish control (by an Executive Request instruction or an error interrupt) or is not interrupted by an external event (I/O completion or a signal from another processor), eventually it will lose control by a timer interrupt. Once the operating system gains control, it can deactivate the process by copying the registers and status bits back into the process local tables reserved for this purpose. These tables reside in a Program Control Segment associated with the program.

1.

Program status (i.e., the program address register and D register) is saved in the G R S . ' If there is status information associated with the interrupt, it too is stored.

2.

The D register is set to privileged mode: absolute addressing is enabled, the operating system register set is selected, and privileged instructions are allowed.

3.

Deferable interrupts are locked out.

4.

Control is transferred to the transfer vector location specific to the type of interrupt. The instruction at this location is normally an unconditional jump to the address of the required interrupt handling routine.

Interrupts can be locked out in several ways. Some interrupts, such as Test-And-Set and Executive Request, can never be locked out. Others can be locked out by clearing their

143

register contents. Intrasegment calls are effected by an instruction that deposits a return address in an X register and transfers control to the instruction at the operand address.

enable bits in the D register. In addition, the privileged Prevent-All-Interrupts-And-Jump instruction locks out deferable interrupts until a corresponding AIIow-All-lnterrrupts-and-Jump instruction is executed.

A Block Transfer instruction exists for storage-to-sto-age moves. This instruction uses the j field as a partial word specifier, allowing parts of words to be moved. The word addresses of the source and destination fields are developed using index registers. The use of incrementation on these registers allows this instruction to broadcast constants, reverse the order of stored data, or do a simple move. The repetition count is taken from the R I register.

The Instruction Set The complete instruction set of the 1100 Series is rich - over 2 0 0 distinct instructions. The usual c o m p l e m e n t of arithmetic and logical instructions is provided for all data types, as are instructions for converting data types (e.g., floating point to integer and vice versa). Logical, arithmetic, and circular shifts in both double and single precision are provided. The synchronization and segment manipulation instructions have been discussed. A few further distinctive instructions are noted here.

Privileged Instructions. The privileged instructions vary somewhat from model to model in the 11OO Series. All I/O instructions are privileged, as are those that manipulate the clocks, modify privileged state, disable interrupts, and modify segment descriptor register contents. The capabilities one normally associates with "privileged mode" operation of a system are controlled by distinct bits in the D register. Absolute addressing enable, register set selection, and the ability to execute privileged instructions are controlled by three distinct bits. Mixtures of the settings of these bits allow the system to operate in states of partial privilege.

Conditional Tests. The conditional tests are of two basic types: jumps and skips. The conditional jumps test arithmetic register conditions and status bits and branch to their operand address if the condition is satisfied. The skip instructions test storage locations for specific conditions or compare register contents with storage. If the test succeeds, the instruction immediately after the test is skipped; otherwise, it is executed. The skip instructions admit partial word operands. Immediate data specification is used to test registers against constant values.

Diagnostic Features The 1110 and 11OO/80 systems provide t w o hardware features to aid in program analysis: the p r o g r a m m a b l e breakpoint and the jump history buffer.

Search Instructions. Several instructions are provided for table searching. In effect, the search instructions are equivalent to the conditional test instructions executed in a hardware-controlled loop. A parameter register ( R I ) is set to the loop count prior to execution of the search. The search instruction is repeatedly executed until ~i;her ":he test succeeds or the loop count is reduced to zero. If the test succeeds, the action is like that of a skip instruction: the loop terminates and instruction execution continues after skipping the next instruction. If the loop count is reduced to zero, then the next instruction in sequence is executed. One iteration of a search instruction performs the same comparison as the corresponding skip instruction. Indirection, if specified, takes place prior to the first iteration of the search instruction. Incrementation, if specified, takes place on each iteration. Thus, use of index incrementation allows a program to search every Nth (with N arbitrary) location in a table either forward or backward.

The breakpoint register contains a 2 4 - b i t absolute address and a number of flag bits. The address is compared with the addresses developed by the processor during instruction execution, and an interrupt occurs on a match. This interrupt occurs after completion of the instruction causing the match. Bits in the breakpoint register specify whether the comparison should be done for instruction fetches, data fetches, or data stores. Any combination is allowed. Breakpoint checking is disabled by clearing all three of these bits. Flags in the breakpoint register also control the jump history buffer which occupies eight GRS locations. These locations contain the last eight absolute addresses used as jump targets by the processor. When the buffer fills, updating is inhibited and an interrupt occurs. If the interrupt is disabled (by a bit in the breakpoint register), the eight GRS locations are treated as a circular buffer, and storage of jump target addresses wraps around. A bit in each entry indicates whether it was stored on an even or odd pass through the buffer. An enable bit in the breakpoint register controls jump history buffer updating.

Masking. Several instructions allow the use of bit masks to select arbitrary bits from words. Some search instructions and some conditional skips allow masking. There are, for example, conditional skips that test the parity of a collection of bits selected by a mask. There is also a "register load" instruction that forms a word by a mask-controlled selection of bits from either of two operand data words. The mask value must be set in register R2.

The 1110 jump history buffer occupies only four words. The 1108 has no jump history buffer. It has a breakpoint register that can be set only by panel switches, and the processor halts on a successful comparison.

Byte Instructions. Several instructions a l l o w decimal arithmetic and operations on byte strings. These instructions include byte moves, comparisons, translation, and conversion from the binary to decimal and byte data formats and vice versa. An EDIT instruction contained in this set performs the same function as the COBOL EDIT verb. Parameters describing string lengths, byte addressing , sign convention, and fill bytes are obtained from registers R3 through R9.

Input/Output The most substantial differences between members of the 11OO Series family concern the handling of I/O. Since all I/O is done by the operating system, these differences are invisible to user programs.

Miscellaneous User Instructions. Intersegment subroutine calls (and returns) are accomplished by using the instructions discussed earlier that activate segments and change base

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I/O on the 1 1 0 0 / 8 0 device-control functions (such as disk seek or magnetic tape rewind) can proceed simultaneously on the same channel. The channel has priority rules that are used to decide w h i c h subchannel has control (i.e., which channel program is to be executed) at any given time.

The connection between the central complex (IP and MSU) of an 1 1 0 0 / 8 0 system and the outside world is the I n p u t / O u t p u t Unit (IOU). An IOU may be coupled to one or t w o IPs in a system. The IOU may contain a number of channel modules; each channel module supervises the transfer of data over one to four data paths to the outside world. The term "channel" will be used to refer to both the data path and the associated hardware that controls it.

Byte and block multiplexer channels differ primarily in the length of time that the channel is devoted to data transfer for a particular device. On byte channel input, for example, a device uses the channel to send one byte at a time. The byte is tagged with an identifier that indicates the subchannel, and the channel uses this identification to determine which channel program (i.e., subchannel) is controlling the disposition of the data. Once the byte has been processed, the channel is free to service another device. On a block multiplexer channel, the channel remains in use by a device for the entire duration of a data transfer (e.g., a tape or disk record). While a block m u l t i p l e x e r channel is transferring data from one I / 0 device, operations not involving data transfer (e.g., a disk seek or tape rewind) may be taking place on other I/O devices on the channel.

The channels of an 1 1 0 0 / 8 0 IOU can be either w o r d oriented or byte oriented. These t w o t y p e s of channels exist for compatibility between Sperry Univac's t w o mainframe Droduct lines: the w o r d - o r i e n t e d 1 1 0 0 Series and the byte-oriented 9 0 Series. The t w o kinds of channels allow w o r d - o r i e n t e d or byte-oriented peripherals to be attached to an 1 1 0 0 / 8 0 system. The t w o main channel types are further broken d o w n into channels d e s i g n e d for l o w - s p e e d peripherals and those designed for h i g h - s p e e d peripherals. In the byte case, the low-speed and high-speed types are called byte multiplexer and block multiplexer channels, respectively. In the w o r d case, the corresponding capabilities are the Internally Specified Indexing (ISI) and Externally Specified Indexing (ESI) modes of a word channel.

A w o r d channel operating in the ISI mode is similar to a block multiplexer channel; data transfers over the channel take place in large blocks. The channel internally computes the main storage addresses used for the data transfer, hence the name Internally Specified Indexing. ESI w o r d channels are used for certain c o m m u n i c a t i o n s peripherals. A communications line index is used to access a main storage table which, in turn, points to the w o r d or partial w o r d in main storage to be used for the data. These are called Externally Specified Indexing channels because the storage addresses are generated external to the channel.

A channel may be thought of as a specialized processor with a limited instruction set tailored to i n p u t / o u t p u t The instructions executed by a channel are called commands, and a channel p r o g r a m is a list of ( 7 2 - b i t ) d o u b l e w o r d s called Channel Command Words (CCWs). Channel programs reside in main storage. When an I / 0 operation is to be done, operating system software executing in an IP constructs a channel program in main storage and then executes an I / O instruction. The I / 0 instructions initiate and m o n i t o r the e x e c u t i o n of channel programs by the IOU. Once informed by the IP of the existence of a channel program to be executed, the IOU executes this program while the IP continues asynchronously. When the channel program is finished, the IOU usually informs the IP by interrupting it. In some channel types, the interrupt is optional; if channel program completion does not cause an interrupt, the IP checks IOU status.

I/O on the 1 1 0 8 and 1 1 1 0 Byte and b l o c k m u l t i p l e x e r c h a n n e l s exist o n l y on the 1 1 0 0 / 8 0 . Byte-oriented peripherals can be connected to 1 1 0 8 and 1 1 1 0 systems through an intermediate controller called a Multisubsystem Adapter. The Multisubsystem Adapter adjusts the data formats from byte oriented (on the device side) to w o r d oriented (on the IP side).

IP and IOU Interaction. Reserved locations in main storage are used for communication between IPs and IOUs. There are six I/O instructions that an IP can execute. They initiate channel programs, test channel status, halt channel programs, and set parameter values. All I/O instructions specify a device address (the sum u -I- X m is used), and those that start channel programs specify a register containing the address of the channel program. Device addresses are an e n c o d i n g of the IOU number, the channel on the IOU, and the device on the channel. When an I / 0 instruction is executed, the IP places the information from the instruction (e.g., type of instruction, device address, address of channel program) in a t w o - w o r d reserved area in main storage; the IOU takes the information from there. If status information is to be sent from the IOU to the IP, the status information is placed by the IOU in a fixed area of main storage also. The I / 0 instructions are dual purpose; not only do they communicate information to a channel, they also test w h e t h e r the channel can process the information. If it can, they skip the next instruction. If not, they deposit an error status in an X register and execute the next instruction.

The 1 1 1 0 has a unit called an I n p u t / O u t p u t Access Unit. Its role in the system is much the same as that of the 1 1 0 0 / 8 0 IOU, but its command structure is unique. On most 1 1 0 8 systems, i n p u t / o u t p u t is done wholly by the IP; 1 1 0 8 channels are much simpler than those of the other systems. An 1 1 0 8 channel p r o g r a m consists of a single commanC (called an access word) that specifies a word count, storage address, and direction of transfer in storage. When the count for a data transfer goes to zero, the instruction processor may be interrupted. Main Storage Main storage on all 1 1 0 0 Series systems is w o r d addressed. The detailed organization (such as interleaving and error correction) differs from model to model in the 1 1 0 0 Series. 1 1 0 0 / 8 0 Main Storage Main storage on the 1 1 0 0 / 8 0 may consist of up to four million words of MOS storage. This storage is interfaced to the IPs and IOUs of an 1 1 0 0 / 8 0 system through a cache which is invisible to executing programs. In a two-processor 1 1 0 0 / 8 0 , both processors interface to the same cache, to obviate

S u b c h a n n e l s a n d Channel Types. A channel can supervise the execution of several different channel programs (lists of CCWs) at once. Each of these programs is controlled by a subchannel and is devoted to a different I/O device. Only one device at a time can transfer data over a channel, but several

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multiprocessor synchronization problems that would arise if each processor had an independent cache. A three- or four-processor system uses two caches, one for each pair of processors. In this case, the caches are interconnected; when data is written in one cache, a signal is sent to the other to invalidate its local copy of the data if any exists.

Conclusion The 1100 Series continues under active architectural development. This development is guided by the requirement of upward compatibility. Future systems will provide substantial new capabilities visible in both system and user modes. These capabilities may be used as new software is developed while current software may be operated unchanged.

An 1100/80 cache may have a capacity of from 4K to 16K words. The cache is set associative. It is organized in four-word blocks, and there are four such blocks per set. The addresses presented to the cache by an IP are 24-bit absolute addresses. The low order two bits of an address select the word in a block, the next bits (the number depends on cache size) select the set, and the remaining (high order) bits are the associative argument that selects one of the four blocks in the set. The replacement algorithm is least-recently-used within a set. Data modification by an IP is handled by a write-through mechanism; the copy of the data in the Cache is modified immediate!y, and a write cycle to modify the copy in backup main storage is initiated. The write through to main storage takes place asynchronously with execution of succeeding IP instructions.

Acknowledgement It is impossible to give credit to all the architects who contributed to the development of the 11 O0 Series systems over the many years of the existence of this Series. Our thanks to the many people who reviewed this paper especially three experts on the architecture of the 1100 Series systems, A.F. Boehm, E.H. Moulton, and R.Q. Smith for their contributions. Reference [1] Borgerson, B. R., Hanson, M. L., and Hartley, P. A., "The Evolution of the Sperry Univac 1100 Series", Communications of the ACM, January 1978, Vol. 21, Number 1, pp. 25-43.

1110 and 1108 Main Storage Main storage capacity on the 1110 can be up to 1.25 million words and is partitioned into two types: primary (fast) and secondary (slow). The absolute address space is partitioned with primary storage assigned to the low addresses and secondary to the high. Main storage on the 1108 system is limited to 256K words of core storage.

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