To avoid unintended latch in VHDL Synthesis Pages collected by Achut Giree Tribhuvan University Institute of Engineering, Pulchowk Campus, Nepal [***********First page***********] VHDL Latch example [inferred Latch]: process (enable, data_in) begin if enable = '1' then q <= data_in; end if; end process; Latches are inferred by "if" statements which are not be completely specified. A Latch is inferred when an "else" statement is omitted, when values are not assigned a value, or when the "event" statement is missing. To avoid a Latch being developed assign an output for all possible input conditions. Use an "else" statement instead of an "elsif" statement in the final branch of an "if" statement to avoid a latch. Be sure to assign default values at the beginning of a process to avoid an inferred latch. Two ways to avoid a Latch are provided below, the first one represents a 2-to-1 latch, and second is a normal D-type flip flop. VHDL 2-1 Mux process (enable, data_in) begin if enable = '1' then data_out <= data_in; else data_out <= '0'; end if; end process; VHDL code for a D Flip Flop with Reset and Clear if reset = ‘0’ then output <= ‘0’; elsif set = ‘0’ then output <= ‘1’; elsif (clock’event and clock = ‘1’) then output <= data; end if;

[************second page*************] HDL Coding Guidelines for Synthesis (Sequential Logic) The number one rule for synthesis coding is this: When writing HDL code, keep in mind the hardware intent. This article gives guidelines, considerations, and examples for HDL coding for latches and flip-flops.

Latches 1. If possible, avoid using latches in your design. Latches can make it more difficult for you to design correctly and to verify. 2. If you do use latches, partition the logic in a separate module. 3. You can avoid inferred latches by using any of the following coding techniques: - Assign default values at the beginning of a process. - Assign outputs for all input conditions. - Use else (instead of elsif) for the final priority branch. 4. In VHDL, a latch is inferred during synthesis whenever an if statement satisfies all of the following conditions: - Conditional expressions are not completely specified. An else clause is omitted. - Objects conditionally assigned in an if statement are not assigned a value before this if statement. - The VHDL 'event attribute is not present in the conditional if expression. VHDL examples: a. VHDL latch inferred example process (enable, data_in) begin if enable = '1' then q <= data_in; end if; end process; b. VHDL latch avoidance example process (enable, data_in) begin if enable = '1' then data_out <= data_in; else data_out <= '0'; end if; end process; 5. In VHDL, latches are synthesized whenever a case statement satisfies both of the following conditions: - An expression is not assigned to a VHDL object (signal or variable) in every branch of the case statement. - VHDL objects assigned an expression in any case branch are not assigned a value before the case statement is entered.

VHDL examples: a. VHDL latch inferred example process (data_in) begin case data _in is when 0 => when 1 | 3 => when 4 to 7 | 2 => when others => end case; end process; b. VHDL latch avoidance example process (data_in) begin out_1 <= '0'; out_2 <= '0'; out_3 <= '0'; out_4 <= '0'; case data _in is when 0 => when 1 | 3=> when 4 to 7 | 2 => when others => end case; end process;

out_1 <= '1'; out_2 <= '1'; out_3 <= '1'; out_4 <= '1';

out_1 <= '1'; out_2 <= '1'; out_3 <= '1'; out_4 <= '1';

Flip-Flops 1. In VHDL, flip-flops are inferred when an if statement contains an 'event attribute, a wait until statement is used, or the rising_edge function is used. Choose one and document it to produce uniform and professional-looking code. VHDL flip-flop inferred example: process (clock) begin if (clock'event and clock = '1') then data_out <= data_in; end if; end process;

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