J $ ' ' O ! -' * -' * =* & & ( * & ' --' ' ' * '6 - - * '& . . ' > ?% E -3 O . ' > ?% E -3 O 5 & ' '& 8 -3 O %S? >J D -3 O ( (#/" 3 O: 7

'

,

'

& 8 DEH & ' !' ' @ & -' ' & '? . ' : ' = * & ' $ '&' & !

'

'& *

& !'

"

7

88

( ( '

' * & '

--'

-'

&'

&

!

"

): G . ' " , ,- ' " ' ' * . ' " > ? ' , @' & " & ' #' ,G#5 ' F4" H '& / ' " #5. @ " #5. -'6 - - '' # ! 5 " - ' * . . ' - ' . . . ' " > ' "

7 LL E > * #. L 5. * F4 ' (' ' ! 2

1 D P<;

"

P / E -3 O

P< / - 8 DEH 5.

! ?H '& # ' & ' '&

& '

-

) #! '& # ! ?@' - '- . @' " % ! '- @' " - ' * . " - ' . . " > ' "

= 8 O

-3

- 8 DEH 5.

' ' ' ! ? - '= -' F4 = , '! #5. ''' ' ' ' - ? ''' ' ' ?' ?* ' & ' ? '

) 5' ' , '6 >,> #! '& > '

' " - 5' ' ( ' @' " 3 " >,> . = @' " ' * . " ' . . " "

!

'

'

H

89 D D O

F4 1 Q . ' -3 - 8 DEH 5. @

! '' & ' ? '& ' '' - ' '

2

' --

8E

*' > ( ' (

'

-

' - ' ' & '*' ! -*' $ '

*

B

* ' 3 * ' ! -*' * %S? >J + 9 E $* * & B ' " 2 > ! + & ' & >,> - - $ ,L $ - ' ! ' 2 ! ' - ' $ -*' ' ' * '= $ & ) 1 ' & * '' $' ! & -' * '' ! ? 3 * # ' ( 3 * ' ' *' ! * & & '- " 2 # & '- ' * ' -' '' ' && ' 2 #5 > (' -' ' ' * ' '' B -' 2 # ' -' & '- ' - ' -' ' ' - ' & # & '- * ' ' '' -' & ' ' , ' 1 ,2 & '- ' * = & --' ' & > ?% '' ! . -' * -' & '- ' & '* - ' ! '& & '- * ' * ' ' ( & '- * * & * - ' " 2 = * ' * ' ' * ' '$ * ' & '' && & '! ( * ' 8 2 # $ '' ! ' $ * ' & * ' && *' ! %! '& * -' * ' '' & ' *' ! * ' & ( 5>( ' ' & '- * ' ' & ' - ' %' & '' '' ! $* * ' '$ ' 5>( ( -* ( ' -' & '- * * - ' &! %6'& '- * B * $ & * & ! " 2 # 6 ' & ' $ ' ' , ' 1 , 2 $* ' ! ' B ( & ' * ' 2 5' ' * ' ! ' ' B -' > B * ' $ *' ' '&' 8D

(

& & '-$

*

'

&

*' ' %S?

'

-*' "

>J

-'

,

Graphical User Interface Program Controls

Display Function

Display Process

Oscilloscope Program

Circular Buffer

DFT Program

Automatic Test Program

Scanning Process

GPIBClass

USBControlClass

Pipe 0

USB 2.0

Pipe 1

Endpoint 1 (OUT)

Endpoint 2 (IN)

Common Serial Bus Output Function

EZ-USB FX2

16

Port C

FIFO Input

Common Serial Bus to Front-Ends

Data from Digital Stage 1

* ! 1 ' ' !

AUTO IN

>& ' ! -

,

* $ ' & !

'' ' ' & !

' $

' ( ' ( *' 3 7 & ( ' *

GPIB to Signal Generator

-

' ! & ' ' ' = ! -' * * ' , ' *'

! 8:

<

'

&

'

- ' -' -' ? '

& *' ' ' + ! $' ' '!' ' - *'

' *' 6 ' *' *'

-

' '! '& ' * = ( = ' '- *' ' & ' & & ' ' ' *' & $ *' '= & ( ' = $' ! " + % + * E' + * E' $ $ $ " E' ! ' & ?' ? ,>@ # 6 A / $ 6 A * & '

- ! ' ' *' & & ' B ' ' #( $ % * $ $ C #( $ $ * $ C #) $ $ + $ #& ' * ' ' *' ' + ' + & ! ,>@ # ' -' ' + ! - " 2 @ & ' ' * & ' 2 - ' + . & *' 1( ' 2 2 ( ? ' ' . & !2 # ' . !2 B - $ & ! ' 3 ' & ' * ' * * B ' = ' ! $ *' ' ' & ' & ?' ? ( -' ' & *' 1$ ' ' = * = ? $ ' + '!' ' L + * =L& * & ' * - ! ' *' ' ' ' ! = 1> ?% $ 5 & ' ? '& ' %S? >J 2$ *' '' = ' ' & ' * = -'= & ' ' ? & ( & ' & ' ! ! ' ' ' !' ' > ?% '& + -' $ ! & ' ? '& ' %S? '& * '!' ' ( *' ' ' ' * ? ' & ' ? '& ,>@ # 6 < % ' B & ( ' ' #5. '' DE 9 $ * ' ' ' $ ' ' ' ' '' ' &' ' ' G' ' , 1G,?5#K2 ( ' ' ' ! 6 * = &* - $ ' ! ' *' B * ' * ( < %+ #5. ' ' D / * H '& 5 ' & ' 1/H5 2 ' $* ' ' & ? '& ' & ' ? '& 3 ' ! $ '& -' & *' ' & ' '& ' & %S? >J ! ( ! + '' *

-' C

89

6 '

' ' '

'

. ' ' !

'

! ' ' ' & ! *' '!' ' $ & - ' &' . * & ( * ! - ' ' & O8 # ' ! ' ' ' *' '= *' ' ' ' ! ' ' ' ' *' #7 * ' ! ! ' ' ' * 6 ! $' ' '' *' & ' ' * ! ' $ ' ' ' %S? >J ! ' ' -' ' *' ' $' B ' - *' ' D* = $' & *' *' & ' ' ( -' ' & & & > ?% ' 5 & ' ? '& ' ! ' = ! , *' ' ' ' ' * 5 & ' ? '& ' %S? >J '& ' ' < % - ' /H5 ' $' * ' * 5& ' '& & * ' %S? >J ! ' ' ! & , *' ' *' ' !' '& ' & > ? % ' & ' . & ' ='& $ * *' - ' * = ( *' -' * ' > ?% ' * ' - ' & . ' ' . -' ' ' ( ' & - & & $ &' & ' *' -'= ' ' !' '=$ &+ ! ' * & '& ' ' ' # ' 6 ' & $ '! * '' ! ' ' * ! * - ' & & , ' ! ' -' ' & * ' ' '! ' ' ! * ! ' C ( * & * = ' *' ! " 5' : 5 ' . 8 ' ' F' *' 5 & ' . 9 > ' . /' ' ' ' ' ( ( ' ' & ' *' & *' -' & $ ' ' ' & > ?% '& $ ' ' = *' -' & 3 ' ' ' ' & *' * ' ' *' & -

8

Task Name Final Year Project

08

15

22

Nov '0 1 29 05

12

19

26

Dec '0 1 03

10

17

24

Jan '0 2 31 07

14

21

28

Feb '0 2 04

11

18

25

Mar '02 04

11

18

25

Preliminary Research Evaluation of Current Oscilloscopes Evaluation of High-Speed Serial Technology Cost & Power Budget Analysis Solution Development Requirement Specification Development Requirement Specification Completed

02/11

Solution Development Solution Chosen

23/11

Block-Level Specification Front-End Specification Dither Generator Specification Digital Stage Specification Power Supply Specification Top-Level Specification Completed

07/12

Front-End Design Evaluation of Available Technology Sub-Block Definition Initial Front-End Design Front-End Deisgn Appraisal Front-End Design Finalisation

04/01

Dither Generator Design Research into the Use of Additive Dither Initial Dither Generator Design Dither Generator Deisgn Appraisal Dither Generator Design Finalisation

04/01

Digital-Stage Design Research into Non-Uniform Sampling Methods Evaluation of Available FPGA Technology Initial Digital-Stage Design Digital-Stage Deisgn Appraisal Digital-Stage Design Finalisation

04/01

Device Prototyping Order Component

11/01

Lead Time for Ordered Component PCB Layout Submit PCB Design for Manufacture

08/02

PCB Lead Time Build Prototype Prototype Built

01/03

Device Testing Front-End Testing Digital Stage Testing Hardware Tested

22/03

Software Development Microsoft Windows Driver Model Research Software Architecture Specification Development Software Architecture Specification Completed

28/12

Software Development Using Keil Emulator Order Development Board

09/01

Development Board Lead Time

E

Software Development using Development Board Software Written

23/03

Exam Period Interim Report Writing Interim Report Writing Interim Report Deadline Final Report Writing Final Report Writing Final Report Deadline

22/01

Apr '02 01

08

15

22

May '02 29 06

13

20

27

Jun '0 2 03

10

8

-?/ ! 5 ( '

. B B

& ' ' & ' /H5 ' ' ' $ * ' 6

'

! ' * *

' *

&

-

*' ' ! & $ *' ' ' $ F * ! -* EH 5 & & ' * ' ' * & !' ' & 5

' '

'&

8

,

'

'

& &

'

& ' *' & * = & & & # & @ ! * '&

'

- * * -? ! =$ ' & , ' ' ' $ ' ' & ' & *

&

-+

-

'

-5

( & -

' '

- '& '' & > ' ' * ' ' ' * B ' ' * ' * & ( - ' ' 6 ' * ! $ * > ?% ' 5 & ' ? *' ' ' 6 * * & ' & & ' * '& * -

! '

' (

*

& * &

-? ! '& '-

'

'

'

'

& To Host Computer Common Serial Bus Power In In

DS LV

Channel 0 Front-End Board 1MΩ Signal Input

Common Serial Bus Out

Dither Clock In In Common Serial Bus In Power In Channel 1 Front-End Board 1MΩ Signal Input

Digital-Stage Board Power In

LVDS Receiver Daughter Board

LVDS

DS LV

Clocks Dither Out Out

EZ-USB FX2 Development Board

Clock Generator Dither Clock In In

!

# '&

%

'

' ' *

!

-

)5 1

'& '' & ' * ' > ? !' < % - ' /H5 ' 5 & ' ? '& $ ' ! . ' ( %S? >J ! ' ! ! + . ' # ' & ' = ' & ! ' + ' E

(

5 & ' ? '& * ' ' '

8

. -(

* %S? -& '

&

'

'

/H5

'

' .

-* >J '

( -- ' * & &

' & '

' * 9 ' *' !

*' ' ' ( *' '! & !

'

' '

-' , L 1,L 2 '' * ,L 9 $ *' ( * ?* $ * ' -'' * > ?% & B ( ' '

" EZ-USB FX2 I/O Port

Bus Assignments 1 (Brown):

SCLK

2 (Red):

CH_SEL

3 (Orange):

DCLK

4 (Yellow):

DATA

Front-End Channel 0

5 (Green): Reserved 6 (Blue):

Reserved

7 (Purple): Reserved 8 (Grey):

Reserved

9 (White):

N.C.

Front-End Channel 1

10 (Black): Ground

Bus-Line Filtering 100Ω

Front-End Common Serial Bus Input Pin

To Front-End Serial Decoder 10nF

!

( ? ' ' ' &

B & '

> ' -

(

?% ' * E =F4 1 8& %S? >J

'

& ' @. E 1)D 2 & * >

*

'

?%

E

( & ' ./A ' . .FZ %/ . ' 5./A 5#(# @ ! G.

'

* ' *" ' '' 5#(# & ' B > ?% ' * . ' $F& . ' 2 = ' ''* ' & ' ' ' '' & '

= . # 1/ 5' ' . = . 5' ' & ' ( @ ! & ' # G . 7

!

=

(

( > ?% & B * & . ' ( ' * *' ! - $ *" ( B

& ' $ ' $ ' & ' *' '

6 '

! D (

'

& '

'

& &

7 # ' . # ' # ' . # ' 8 # ' . 8 # ' 5. . #. . ' '& $ 6 E ' '& $ 6 ' '& $ 6 ' '& $ 6 @ ! @ ! @ ! @ !

< 8 E D : 9

< 8 E 7

( ( --

'

!

):

' * ' * & '& '- ' ' &

6 ' "

' -

>

'

'' -' $

?%

} !

):

(

To Front-End Level-Control

(

E<

( -5' ' .

* ' ' :8F.E E 9 & ' /E ( G#G5 & &' ' ' = & ' & . ' & ' ( ' * & $ * & ! ? G#G5 &' @ E' @ D

*

8

(

F4 >' .

( ' ! ?' *' ' @ ' ! + '' = & ' 6 ' & '-/ = /

8 <(

!

*

F4

'& ' = , ' & ' & ' ? '& ' & $' . ( ' D. - ' -' = ' - * ' ' ?

'

, ' & ' ' * > ?% 5 & ' ? '& ' - ' /H5 ' ,>@ # 6 < % ' B & ( * ' > ?% ' * *' & ! ' ' ! ' & ' ? '& ' ( ' ' ' ' E ?*' E * ' . , 5? * * & & ' " G & ' $ D Y./A$ ?./A 9$ < @ ! $@ ! E$ Y <$ ? <1 2 < $D Y $? 9$ < Y $? <8$ Y $? $
'

=

' ' - -' ! - ' & B ' F4 = & ' *' =& .). < < ! *' ' ' ' ! & ' & & -9 F4$ ! ' ( ! + ?! ' ' & ' ' ' $ 1 // 2 ' = !

/H5 ,

!

5C

):

7

' & & '

8:

)

( ' * -' ' Y , G#/$? , G#/$ & ' ' G '

' & ' G5$V -

8

''

& ' !

'

D'

/H5 ' ' ( ' Y , G#/$? , G#/$ G5$ ' * ' ' '= E8

! & & #

' > '

' ?%

'& #5. *' *

' /H5

8 8

B !'

'

(

' $'

$

- ' *

' '

&

7

!!

1

=

& ' ! '& $ ' '& ! -'

-5 ! * . ' ( -'

' ' (

7-

& *?

' ' * & $

'

'& * B * & &' ! $ & F * ! $' *' & B ( > ?% ' B ! '& * &. '

YEH P EH Y
):

'

! '& * ' ! '& & ' *

'

& ' ' ' -'

* ! 6 ,H

#

& @ ! *

' *' &

* 8

*

, *' ' ' ' & ' . $ * & ' > ?% ' 5 & ' ? '& . ( - *' EH $ ' ! '& B * '! ! ' ' ' ' $ *' ' ' * ! '& * & ' ' ' 5 & ' '& & ' ' ! ' * (' 88 ( ' ' * ' > ?% # ' @ ' " > ?% #" > ?% #5. # ' & " > ?% #5. 5 & ' " 5 & ' ? '& /5 , '" 5 & ' ? '& /5 , L " %S? >J "

8

'

*

*

( $ ' ' & ' &' ! ! -

*

(

&

' '

-

*'

'

!

-'

-

'

*' ' ' = ' ' & ' *' ' & $ *' -' '= ' ' & ' & & ' '& ' ' & ' - ' *

' ' # & ' < % ' ( > ?% . & ' ( - *' ' ' ! *' ' ' 6 ' & ' & = & ' ( ' * ' * 2 , ! ' ! * ' 2 (- * ! ! ' ! 2 ( = ! & $ & '& * ' *'

. . ' " $

&

=& '&

* & '

' ' '

' '

'

'& '

-' '*

& '-- & *

.). '

'

&

$

'

< <

$ =

' & '?

EE

!2

, * & '

' 6 ' & ' & ( ! ' *'! & ' ' . - ' - *' ' ' ?# '* & &' ( * ' *' &' ! ' $ ' *' -' ' * ' B F4 ( * * & ( -' -? ! *' ' ' ' ' 5 & ' ? '& *' - ' ' ( *' * & ' " 2 , *' ' * ' ' . , . $ /H5 ' * 5 & ' ? '& ' %S? >J ! ' $ ' & ' * ! = ( *' ' & ? ' & ' * ? . , 2

//

-'

'

!

&

( - *' 6 & 5' &

2 ( ' 5 & ' ? '&

& $ ' & & ' 6 ' . ' ? ' * ' ' ! = ' ' ! ' *' = * ' '' ' * ' !' 5& '? '& '' ! ' *' = *' ' & ' '& ' * ! ' ( * '! ' -'= & & ' $' /H5 ' *' B

8< > ' ( * &

=

$*

-5

&

-' -? !

-

&

! *-

' ! $

'

& " Common Serial Bus Power In In

To Host Computer

Channel 0 Front-End Board

DS LV

1MΩ Signal Input Dither Clock In In Common Serial Bus In Power In

Channel 1 Front-End Board

Clock Clocks In Out

Common Serial Bus Out

EZ-USB FX2 Development Board

Dither Clock In In

(

Power In

S

D LV

1MΩ Signal Input

! !

Digital-Stage Board

-

)5 1

' ?# '& ' '. - ' & ' -' ' G G ' * ' ' B D F4 ' * & ! '& '&' ' ' ' ' '

! ( '

*' ' ' * ' & &'

ED

To ADC and LVDS Interface

External Signal Generator Clock Input

! "

)

1

7

(;D

7

E:

E >

?%

5

&

(

'& & & ' *' $ *' & > ?% '& , ! ' ! ' ' 6 $ ' ' ? * -' ' ?* ' ' '= ( & ' ! ' $ ' ' -' ' 3 ' =? ! *' ! $ 6 '& *' - -' = ' ' ! ' * ' ' ! * &' '-- ' ' ' B ! '& & & ' + YEH$ ! & -' *' ' ' ' ( ' * -' & * -' '&' B ' ' $ ' ' * ' & !' ( * '! ' '&' $ & ' ? -' ' ' * ? -' ' ( . ' =?/ ! -' $ ' & & & * = '= ' > ?% =

E

=/ ! 5

&

( B ' ' > ?% ' *' ' *" , ,- ' " 7 LL E > * #. L 5. * ' ' * . ' " F4 > ? ' , @' & " (' E * & ' #' ,G#5 ' F4" D H '& / ' " P<; #5. @ " '6 - - #5. '& ' " # ! 5 " P / P< / - ' * . . ' " E -3 - 8 DEH 5. - ' . . . ' " O > ' " ! ?H '& # ' & ' & ' '& 7

"

):

-H 1PE-H 5.2 -H 1PE -H5.2 H 1PE -H5.2 H 1PEH 5.2 H 1PE H 5.2

-H 1P -H 5.2 -H 1P -H5.2 H 1P H 5.2 H 1P H 5.2 7

(* 2

2

"

-

7

E -H 1P E-H5.2 E -H 1P E -H5.2 EH 1P EH 5.2 E H 1P EH 5.2

)

* ! =? *' ' ' & ' ' * ' & $* & ' !' -- & ( *' ' = 6

! ' ' $ = 6 *' ' ! ' -

-$ *

!

' ' ' '& *

& ' $*

' E9

& ' !'

'

! '& * * -- & *' ' ' -* ' # ' !' '& & ! '& $ -'6 - * ' & ? @ ' -' '!' ' -' = $ * ' ' !

' (

' !' '& 6 ' ' '& * & ' B ' B

' ' ! ' -'

* * ! ' !

' '

# ! ' 2

- & '

'

'

'

*'

" ( ' G

& * ! ' 2 -' ' ' * B # - *' #5. '& ( ' E: ( =? ! ' =+ '

' -

-

6

'

& ?

'' ! * * ' $ ' & ? & ' #5. * ' * >& * (' E<

Over-Voltage Protection +V

& '

'

E

#

LVDS Output to Digital-Stage

1MΩ Analogue Input Front-End Buffer

Attenuator

'

Amplifier Stage

Anti-Alias Filter

ADC Driver

LVDS Interface

ADC

-V

"

#

$B '

! ?H >

#-

, ('= ' '& ' H

?%

'&

7

-

$) 1

'

7 LL E > & ' ' ! ' ' & ' ' '& * ! #. L 5. & '&' ! '& & ' ' , &

):

- ' $ * B ' * ' &! *? ' & ! ' ? *? ' F4 D ' F4

F& & EH ' ,G#5 # &' / * ! '& ' - ' E 7 F& , ,- ' ' ' $ $ E$ $ $ E ' * F4 &' ' ,G#5 ' D ' F4 - ' E 7

$ & ?

-

'

+ '

* -

' &

E

#

?# ' >

. '' . ? B ? ' ' ' ' ? ' # ' ' ' * (* E 7 - ' ( *

#5. 5 !

' '

#5.

' '

/ * F& (

'&

' -

-

/H5 ,

'

7

& ' -' ! EH

- '

$' ! -' * ' &' &

-

-'

& ? '

& '

' ' *? '

& ' '6 - - '. . /H5 . -& '

F4 ' ' ?D 2 ' ' ? D -'6 -

1 '

' ,

E 7

'

$

&

'

'

- ' -

& - & E ?*' ,>@ <

/H5

*' & '

%

"

- '

7)7

'&

. ,

$ ,

):

-' ' (' E< &! * & ' (' E8 ' ? ' ! '& ' & * ' = > ?% '& - - - ' -'6 - ? ' ' & ( - - ? ' ' & * ' ' ! 1 2' '1Y8 2 ( -'6 - ? ' ' & * ' ' ! 1?8 2' '&' 1 2 G ' ' ' '= ' ? ' # ?# ' > ' $* ' ' ? ( * '! ' & & ? ' ' & ' #5.$ & = & , * & ' ' ' '- ' - '= *' -' & ' > ?% & * =$ * *' ! * & '& , *' & ' ' ' 7 '' - ' $ ' ' ' 7 6 - $' ' *" Oscilloscope Probe 1MΩ R

Signal Source

R

1MΩ Impedance Transmission Line approx. 1.5meters long

"

, -' B

'

6 ' ( *'

$ * !

'! ' &

7

%

'!

!

Input 1MΩ Termination of Oscilloscope

0

&

%

$' ' ' ( '

;E

! ' -

' & '

D

' ' & ' *' 6

* - ' '

' '- ' '*$ ' '&

% G

'

7

"!

*' '

( '

'

&

- -> & -H E-H E-H -H EH H

-

# ' , > ?% #, #5. 5 ! , #5. ,

7

,

& !

' '

!

' &

? '

1

' # &

7 (' &'

'6 - - > & H E H EH H EH H

E8 ( >

?

? '

):

%

)

( ' =? ! ' ' * ' ! ! *' ' & '' & * =$ ' ! '& ( & * = ' = - ' 1' -F2 ' ' '' - ' ' ' & !' ' ' 1' M>2 * ' -' ' ' 1' >2 /' & !' ' ' '! ' ! ' & B $ * -' !' ' ' $ '' - ' ' ' !' '& ' '& ' ' ' ' ' 5. ' ' ' * - ' ' & B

E

#

'

5

( & '

& '

*

EH ' * P EH '! ' - ' -'!' ' & 2 # * B ' ' ! * &* 5. ( ' ' & ( *' ' ! ( -'

' ?

*? ' ! '& 7 !

&

' ! &'

'

= -

'' &

> ?% , *'

$

' ' & '' * E > -' 1( ' ' ' *' ' '? ! ' ' *' '= &! 1 2$ 1? 2' 1?8 2 ( ' * 6 ! '& ' & PE H - ' * & * #. ' 5. ' * ' & ' ' ' *"

50Ω BNC Input

To Front-End Buffer 0dB

AC / DC

-20dB

-40dB

"

(

D

@ '! B 5

' *' -' $ ' $ * F4 ' *

# ? $5 - ' 1 & & ' $ ' '

' ?(

& * $'

' * !'

& '

7

' $ '! ' & * '

E< ( * * * *" ( @>< E 8E

( @> E 8E 9

""

* !

* *' ' *

' (

'!

' '

'

' (K E 8

9 F4

' =$

*

$ * -'

'

* & H '& 1H2 . * 1-32 . ' @ ' 1-72 . ' H '& @' &1H 5.2 ' * * [ E , ' ' F4 1 2 /' &H \ & 1O2

'

E

< F4

F4

E

DE

8

G < 8

G : D

) <9

-

' ' ! & -' ! $ ' ' * & & ' F * ! ' ! * B * & E H 5. ( ' ' ! 6 ! C 1# & ' ? B ' 2 ( (K !' ' ' ' *' * *' ! ' ' -' ' -' ' ! * $ ' ' & * & & *' ! & ' ' * *' B ' ' ' ( & ' & ! * * & ' ' <- $ ' * ' ' '* & * ( (K #?/ ?EH ' *' ' * 6 -# ' * ' $' - &' ' * * ' '- - $ 6 & ' * ( *' ' ! * & - -' '& M> ' ' '& & ' 8: 7 ( - ' ' ' '& ' ' ' *' B * * & !

( & ' B

&

# * >& ' &

* &

'

' ' &

1 '

-

E< > (

( B

?% !

' &- ' 9 *' ! & & ? > ?% & '-' = ( *' $

5

&

'

-

&

@

- ,. * ' ! & *'

&'

& '& *' ! -' ' ! ' ' $ ' & ' ( ' * ' ! ' '& ' * '! '

' '

D

* '

B ,

-

-$

' '!' ' -'

! ?

* * $

' * '

* '

* ( 6'

" #DEE P8 :E

- ! '& 1H2 '6 - 1-#2 , - ' 1 72 ' ' * 1 F42 ? ' 1HLM 2 * G 1 HL]F42 ' F4 ,G#5 1 2 ' F4 7

"#

)

/ = &' ! '

' $

( '

*

'

'

' '

*'

' !' '& #
F4 ( !

#DEE >

?%

-* &' F4 > '

!' D -

*


' ''

E

8

, 1 -

'

#
#
> ' &! !' ! *? ' * -'6 - ' * Peak Amplitude (V) Without Slew-Rate Distortion

1 0.8 0.6

0.4 0.2 0 10

6

10

7

10

8

10

6

Frequency (Hz) " !

%

$

,)

1

8&C*F

, *' & ' ' ' ! ' ' -' - ' *' '! ' ( ' #
( &'

&

* & '

'& '-

*

-' = !

'

> ?% & "

To Gain Stage

From Attenuator Circuit

" "

E 8 #(

'

'& 5

B F& ' ' ' * ,G#5

' -

):

(

& '-

'

'& *' '

' $ $ E$ $ $ E F4 &' ' ' D ' F4 - ' E 7 ( B ' ' ' F4 ' * ' &' - ' ' * ' ! ' ' * ' &' ? ' * F4C 3 * F4 ' ' '& * '! ' '#&' *' -' & ' - '' $ ' * - & , ' & ? ! B ' ' ?'-' = # '' ! *' $ # #59 $ ' * *" #59 - ! '& 1H2 YEH '6 - 1-#2 8 /' & & ' ' * 1 F42 ' N < &' ' * 1 F42 *? ' 1HLM 2 EE G 1 HL]F42 ' F4 ,G#5 1 2 ' E F4 :8 ,G#5 1 2 ' E F4 88 7

3 ' & ' &' ' ? EH (

*'

&' ' -' '

"

1

'

*

$ ' *' ' * P EH *'

$

*"

' & ' '

$ $

! '& ' '& '

& *'

' & 5 !

+&&8

F4 ' ' !

'& '

' B

'

-' * ' B ( - *' '- - ! '& ' ' & D8

' ' ' &' ' * * ' 1YD 2$ E 1Y 8 2$ 1Y 2$ 1Y D 2$ E 1Y<8 2 1Y8 2 ( ' ' & * &' '& $ * '& ! & &' ' $E' $' ! & $ ' ( * & * &' & *' ' & #59 ! &' '& $ ' * ' 6 ' = ( ' &' $ ' &' $ + ! & & ( * -' ' & 1 ' 6'* & ' C2" 1Y

( 2$

Gain Stage 1

Gain Stage 2

From Front-End Buffer

To Anti-Alias Filter

Gain Stage 1, 14dB (x 5)

Gain Stage 1, 20dB (x 10)

Gain Stage 2, 6dB (x 2)

Gain Stage 2, 20dB (x 10)

" #

* &B ' ' ! ' " * & @ '

'

@ ' . * '# >%( * 5

:

(

,

' 5

-

, / %6 %6

--' %

- '

%6 -

%6 %6

%6 -

* ' '

-' = . *'

) ,

&'

'

=

-

9

'

%6

"+

#5 : *

&

' &

-' '

*

' ' ' '

! ! ! 7

,

* &

,

&-' -

*'

- * ' ( # ' &5 ! $ ' *' ' ! 6

$' *' & &' DE

1/' '-

& '

& '& 2

'

EE #

?# ' >

*'

5

'

'# >%( *

( ' ' ' ' ' & #' '& ' ' ' * 6 ' F * ! ! '- ' *' F4$ ' ? * F4 ! ' # ?# ' > , *' ' '! ' ' ' $' * ' ' ' ' ( ' ' # 5 & 1.#52 ' ='& *' > ' : - -' '' E 7 *' 3 ' ? ' ' ' ' ! F4 ' ' ' 1 ' ' ? ' ( *' ' ' ? ' ' '

G 6$ D ' ! -

:

,

1

' - *' ' ? ' $ ' * ' ? B F4 *'

'!

& '

(

"

*

& '

* '

'-

? ' ' ' & (

&' ' - ''& -

' % ' & $

4

* . '

*? ' B ->&

E: 2 '

! '

: - ! 9 F4 (

*

@ B

?

&

'!

4 8&;3?

' '

F4

*

& ? ' ? '

$ * F4 ' D ' -' & 1 E

)

0 )#&

'

2

&;3?

B ' '

' '

( *' *' :

DD

" +:

,

, *' & D

,

, ' ' ( '

*' ''

-' '

1

&

*

? '

?

!' ' , *' ' * ? ' ' ' ' ' '

" 8:

*'

4 + ;3?

' '

&

6 $'

1

' '

' ' :

9 F4 ' # -' F4 ? B *' ' !' *

8

4 8 ;3?

$ & *' $

0) &

B F4

- ' $ ! ' '' &

)

6

*' ? ' ' ' *

' *

8;3?

! &! ' '-

'

)

*' *' ' ' ? '

0) &

&+;3?

' ' & * '

'

' !

' B

' *' * ! , D D:

( * &

-

"

( ' ->& < 8 ( + (

-' ?

*? '

*'

&

-

8

+ B

' ''

'

E $ 8< <: D E: 9 D< 8 E B

F4 F4 F4 F4

'

-

'

)

,)

4

' '

B

4

*

' !'

'

' ' ' '"

'

& '

'& 5

'

&

'

*

* &

-' "

To ADC Driver Stage

"

E D #5. 5 !

,

'

From Amplifier Stage

(

-

* ="

)

&

& = (

& > ?% '& ' ' ' & ? #5. 5 ! + ' '= * ! ? & ? & '$ * & * ' & ' ,>@ # 6 < %$ ' ! ' & ' & #5. ( ' ' ' ' #5. *' * ! * & ( ! & -' = ' ' * B ' = &! ! '& *' # ' & 5 ! #59 <9$ * ' ' *" #59 <9 - ! '& 1H2 P 8 '6 - 1-#2 < /' & & ' ' * 1 F42 H DE &' ' * 1 F42 < ? ' 1HLM 2 * E G 1 HL]F42 ' 8 F4 E ,G#5 1 2 ' E F4 8 ,G#5 1 2 ' : F4 D 7

( ' -

! *

'

"8

1

' * G E 7 # ?# ' > $'

+

+

B - ' -

-

( & '

-' - ' ' ( &' D9

&

'

ED 7 E E7 ' - ' - '

& ?

&' 2 G ' !'

& - ' ' ' ' ? !

1(

' ' &' 8$ ! & ' '' - ' 9 =7 ' E 87 ' ! & $* *' ' ' * ( ' !' -'= '- $ '- ' E 7 Y E 7 LL E 7

&

ADC Driver

To ADC From Anti-Alias Filter

Dither Filter

Dither Signal Input

Dither Attenuator "

( 5 & ' '

(

1

0

-

& * = * ' >& E * & ' *? ' ' ' ' ' & * &' E 7 ( & ' *' ' ? * F4 &'8 ? ' * * $ ? ' & B & ' & ' & ' & ( & ' ' ' * ' ' ' -' $ * !' * & & '& ( ' ' ! B '* 'P / P< / # & ' ! & ' ,>@ # 6 < % *' = * $ '' ' ' ' *' ' & G *? ' & #5. '& $ ' ' ' ( ? B *' ' 8 F4 1 E 8 2)D 2 ' * & ' ' * & & & '

E : #5.

'& 5

&

# '

'

> ?% ' "' *'

# -' = '

'

-' = ' 6 #5. * & *' '=

(

'& ' ' ' & ?? & ' ! ( #5. * ' -'6 - - '' 6'& '!' ' ! ' ' ' ' ' ' ' - ' ' ' --' * &

"

D

( 6' , #5 @ 1 2 5 ! ' ='& & ?% 5 '6 - - '& @' 1 2 # ' & , ' * 1 F42 ,G#5 1 2 H '& 1H2 '6 - - * . 1-32 A 1O2

'

&

&

# ' & 5 ! #5 <

E8 < D

D <

&

5

<

8

8

E8 <

E < 98

ED < D

E <

8 E<

8

< E8

'

*

< 8D

< %

#5

'6 - L 5' ' #J 98

<

" &

# ' &5 !

G' ' #5. 5

5 8

8

, '

# ' & 5 ! #5

&

7

*

( 6' , (F 8

< *'

E

(

" 2

, ' ' ? ' ,G#5 ' $ 2 ( '' *' * = &* < % 6 ' -' '' ( #5 < ' ' *' B ! # ?# ' ' #59< 9 ! #5. 5 ! ( #5. -' * ' ' /H5 '& ( & ' ' * H '' &

* &!

'*

' -$

*'

' $' ' & ' * #5. * & ' -' - + DE 9

#5. ' ' &
Sample Clock

}

From ADC Driver Stage

"

To LVDS Output Stage

(

:

E 9 /H5 (

'& 5

* & -' 6 < %+ /H5 -- ?'& %' - ' *? '

,>@ # 5& ' ' '

' ' '!

& /H5 ! G -- & ' = /H5 ' -- ?' - & LVDS Line Common-Mode Drivers Filtering

& ' '

*

>

50 Pin SCSI Connector

Sample Clock

From ADC

{ 4 Least Significant Bits Set to Ground

"

E

* ( (

& '

'

' ' &

! ' YEH

5

5 !

1

5

)

&

--

(

(

5C

* & * #5 : . ' ! ' ' &

' * B

!

' ' ' & ' =-

*

' * . - ' * # ' ' $ &' * ' ?. ' >%($ * ' ? - ! & ' & . & ( ' ' ! ? ? ! ' ( ' ' !' '& ! '& ' ' ( & ' ' ' ' ?'' ! '& ? EH ' H $ Y EH

:

From Common Serial Bus Decoder

From Common Serial Bus Decoder

To Gain Switch

Example Gain Switch Driver

Example Relay Circuit "

"

1

.5

/

9

) ,

1

.

/

:

D 5 & ' ? '& 5 (

B

&

'

#! '& # ! ?@' '- . = @' " % ! '- @' " - ' * . " > ' "

7

& '

8

-3

'&

*

*"

- 8 DEH 5.

' ' ' ! ?' - '= -' F4 = , '! #5. ''' ' ' ' - ? '''

#

)-

,

1 ,

)

B

? - '& & ' '& * & '--' / & 5 ! 1 /52 @ ' *' /5 '!' ' -' = ( ' ' *' B = B F4 F4 ' =* * * ' '=$ ! * ' ' ' * ' F4 = ! '*' ' ! B -'6 - = ' B $ *' # '+ #J: . %% @ ' /5 ( ' ' & ? -' '' ' EH ! '& $ * ' ' EH ' < B 1 F42" '

'

7

> B

#

'

'

F4 6' ! 3 ' ' -

' ' '' ( $'

' *

' % *

'& 9 # '

('5

!

'

' ' &

' *

' ' $

' ' ! & ' &* . /5 ' & ' '& * !'& & & ' ( ' *' & '& F * !

*

! 2 2 2 !2

; @ &&&

*' & & & ! '

" 6 6 D

#5. 5' ' %S? @ ' L3

>J >,> - %S?

>J >,>

6 /%5 :<

!2 6 '= !2 F4 = # *' & *' ' & $ ( *' ' & ' '' ! ' ' ' $ ! & ? # ' ' =& '

' & &' ' ' ! & '& - -

' ' & > ?% '& ' *' ' !' ' - *' * ' ? -

:8

: 5

& @ ! *

( &

& ' '

*

:

' *' - ' '& ' &

G

* '

'

' &

&

--' 5 & ( *' ! -' 2 ( # ' ' & ' ' 5 & ' ? '& %S? >J ! 5 & ' ? '& ( ' ( ' !

!

'

!

'

* &

'

*

&

* & '&

!

:< 5 ( ' -

( '

& *' !' '

' ' ' 1 6 & -'6 - ' & 'R:< 98

& @ ! *. & $

' *

# ' ! '

& *

&

' *' $ ' *' ' , 6 > ' ' , ' ' -'6 - - 6 ! * /H5 ' 2 D3$ * * B * E3 ' ( OE< 8E$ ' ' ' ' !'

' $'

'

5 & ' ? '& *' =& ' *' $ ' ' & ' = & ' - ' *'! ' 6 ' & ' & ' " ?# ' > ' *' & ' > ' ' ' ? F4 & ' * & ' , ' *' & ' ' ( *' ' ! & . ' & ' ' &! '& :E -' ' ! * # 6 ,H

. ' &

*

-

' F4

> ' (

' ' '

"

2 2

:

'

'!

*

! ! & & *' ' -' & = ' * *

. ' &

& ' (

$

' ' $ *' - $' '

' -

&

& -

'

! *

'

! ' ! ' '

' *' & # ! $'

-

- & ! $ ' -'

& ' *'

' '

& -

&* =

' '

:E

USB2Scope Budget Front End: S upp ly Voltage (V)

Component

Manufacturer

Device

0dB Attenuator Relay 20dB Attenuator Relay 40dB Attenuator Relay AC / DC Relay Front End Buffer Variable Gain Stage 1 Variable Gain Switches 1 Variable Gain Stage 2 Variable Gain Switches 2 ADC Driver ADC

Matsushita (Aromat) Matsushita (Aromat) Matsushita (Aromat) Matsushita (Aromat) TI (Burr Brown) Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices

TQ2SA-L2-5V TQ2SA-L2-5V TQ2SA-L2-5V TQ2SA-L2-5V OPA355 AD8009 ADG702 AD8009 ADG702 AD8138 AD9203

5 5 5 5 ±2.5 ±2.5 ±2.5 ±2.5 ±2.5 3 3

Supply Power (mW) Load Power (mW) Total Power (mW) 1KU Min Typ Max Min Typ Max Min Typ Max Price (US$) Supplier 0 0 0 0 0 0 0 0 0 1.8 Avnet Website 0 0 0 0 0 0 0 0 0 1.8 Avnet Website 0 0 0 0 0 0 0 0 0 1.8 Avnet Website 0 0 0 0 0 0 0 0 0 1.8 Avnet Website 41.5 41. 5 55 0 2.8 5 .6 41.5 44.3 60. 6 1 .25 T I Website 70 70 80 0 12.8 25. 6 70 82.8 105. 6 1 .87 Analog Devices Website 0 0 0 0 0 0 0 0 0 1.02 Analog Devices Website 70 70 80 0 44.1 88. 1 70 114.1 168. 1 1 .87 Analog Devices Website 0 0 0 0 0 0 0 0 0 1.02 Analog Devices Website 54 60 69 0 0 0 54 60 69 4.25 Analog Devices Website 60.3 60. 3 6 6 13.2 13. 2 18 73.5 73. 5 84 6 .34 Analog Devices Website

296

302

350 13.2

72.9

137

309

374.7

487.3

$24.8 2

Single Channel Front End Power Consumption (mW) Min Typ Max 309 374.7 487.3

Price (US$)

Dual Channel Front End Power Consumption (mW) Min Typ Max 618 749.4 974.6

Price (US$)

$24.82

$49.64

Digital: Component

Manufacturer

Device

FPGA USB 2.0 Microcontroller Programable Clock

Altera Cypress Cypress

EPM7064B CY7C68013 CY22393

Supply Voltage (V)

Supply Power (mW) Load Power (mW) Total Power (mW) 1KU Min Typ Max Min Typ Max Min Typ Max Price (US$) Supplier 2.5 188 188 188 65.5 65.5 130.7 253.5 253.5 318. 7 5 Avnet Website 3.3 422.4 422.4 422. 4 92 92 165 514.4 514.4 587.4 16.28 Avnet Website 3.3 39.6 79.2 79. 2 0 0 0 39.6 79.2 79. 2 2 .92 Avnet Website

650

690

690

158

158

296

807.5

847.1

985.3

$24.2 0

:D

Digital Stage Power Consumption (mW) Min Typ Max 807.5 847.1 985.3

Price (US$)

Device Total Power Consumption (mW) Min Typ Max 1426 1597 1960

Price (US$)

$24.20

$73.84

:8 > '

F' *'

'

): G . ' " , ,- ' " ' ' * . ' " > ? ' , @' & " & ' #' ,G#5 ' F4" H '& / ' " #5. @ " #5. -'6 - - '' # ! 5 " * . . ' 1 '6 - -2" . . . ' " > ' "

7 LL E > * #. L 5. * F4 ' (' : *2

1 D P<;

8 P / E -3 O : :<

P< / - 8 DEH 5.

! ?H '& # ' & ' ,>@ # 6 < %

-

) #! '& # ! ?@' - '- . @' " % ! '- @' " * . 1 '6 - -2" . . " > ' "

= 8 -3 OE DD

- 8 DEH 5.

' ' ' ! ? - '= -' F4 = , '! #5. ''' ' ' ' - ? ''' '

) 5' ' , ' " '6 - - 5' ' ( ' @' " >,> 3 " #! '& >,> . = @' " * . 1 '6 - -2" . . " > ' "

!

'

'

H

89 D D O

F4 1 Q . ' 2 -3 - 8 DEH 5. D @ ! '' & ' ? '& ' ' '' - ' -'

7

-H 1PE-H 5.2 -H 1PE -H5.2 H 1PE -H5.2 H 1PEH 5.2 H 1PE H 5.2

-H 1P -H 5.2 -H 1P -H5.2 H 1P H 5.2 H 1P H 5.2 7

E -H 1P E-H5.2 E -H 1P E -H5.2 EH 1P EH 5.2 E H 1P EH 5.2

)

::

9

& (

& '& *' ' ,>@ # 6 ! '& $ F ( . * ! ' ' . ! ' - 2 !!! ( ' '' ' & ' ? - $ -' - $ ? -' ' . ' B ! . & - ' ( -& ' ' ' & -' . ' * & -' $ & '' ' # ' -' . ' & '' ' . ' ' $ 3 * ' 6 ' &' - ' . ' -' = ' ' ' ( . ' ' ' & ? ' &!' * ' + ' ( ' * ' & -' = &! -' ' & $ -'= & ' # *' & ' $ ' ' *' -' & * ' ' & # -' ' ' . ' *' = * !' ' ' ' & * =' ' ' ! B

9

>

?%

'

(

' B & ' ' > ?% '& #5. ! '& *' & ' ' ' * '' - ' E 7 ( * ' = *' ' ' ' *" #' * '' ' ( * = * ' * ' & ' $ ' ' 6 -' ' ' ' 6 & ( ( % -'& * ' ' -' ' * * ' ' & ' ' 9 * @ 2 B9 @2C *'! # (% *'! ' '&' ' & ' ' ' & ' - & - ( ' * ' &' , ' - ! ' 6 -' ' ' & * & 3 !' '' - ' ' ' ' ' ' *$ * ( "

A

"( $ &

< <

DD:

( =

## 888 % % ''

"( $ &

.

: --$

!'

*' E 7 ( ' - - & ' ' - '

'' + &

' ' ' ! ' ' & !

! ! !' ' 1<2 ' , *' (

1<2 *'

3 '

> ' = *

* ' ?% &

1 83 !!0 $ * ' < E< 3 * ' = 8<-- * ' *' ' - ' ' ' *' ' ' :9

* & ' & ' $ ' ' = ' & - ' - * ' < 8 # = '& '> ?% . ' * ( ' * & & ' ' ' ' $ '' ' & '& $ * & ' ' & & #5. ! '& # & ' /H5 ! ' & ' & ' ( ' * ' ' & ' - ' & 6$ * ' & /H5 ' &

Analogue Power Regulation

Attenuator

Gain Stage 1

* & '& & * #5. . , -' ' *

Power Input

AC / DC Switch

Front-End Buffer

50W BNC Input

' ' &

Gain Switch Drivers

Anti-Alias Filter

Dither Input

Dither Dither Filter Attenuator

Relay Drivers

ADC Driver

Common Serial-Bus Decoder

Gain Stage 2

Common Serial-Bus Input

Clock Input

ADC

LVDS Line Drivers ADC Power Regulation

LVDS Common-Mode Filtering

50-Way SCSI Connector +

9

5 & ' ? '&

7

$

'(

-

'

6' * & . ' >& 9 * ' = '& ' %S? >J ! ! + > 6' ' '& -' # 6 ,H

*

):

( -'

& -'= & ' '

' .

' *

' $

'

& ' '& ' ' /H5 ! % : 9 /5 5& '? :

JTAG Interface LVDS 1

LVDS 0

P4: CPU Clock

E D F C MAX7128B

P1: FIFO Interface

G

P2: FIFO Control

H

A

B

P5: Interface Clock Clock Output Circuitry

Clock Input Circuitry

P6: Port E and Timers Common Serial Bus Output

P3: Port C

+

9< (

7

Power Supply

$

)

'( 5 -

> '

( 2

& (

2

' ( - '

2

!2 !2

!2

'' * & * > ?% '& ' & ' / = * & ? ' '

* * ='

& '

'& * " ' & ' * * & & * ' ' !'& 5 & ' ? '& ' * ' ' . ( & ? ' ( ' = $' & ' &

*' *' ' ! ' ( / 8 ! ! '& & ' > ?% '& $ * & Y EH ' Y ?% ' ( ' ' 6 ' &' ! * *' ' ( ' ?# '& ! ' ' ' . - ' = & ' 6 F4 , ' * = F4 # * ' B !' *' ' & ' :8#. 8 ' !' . ! *' ' ' E F4 ( & ' *' ' & ' 5. ' ! #5. # & ' ' *' ' * - ' @E ' &' @E8 ' @E: > ?% ' 9

! 2

! 2 62

( ! '& ' &' ? * ? & ' ' ?'1,. ' ,. 82 *' ' & - Y E Y EH & * ! + * ' & ( *' ' & & ' @D ' @: $ ' @:< ' @:E ( ' *' & & ? * * & ' & ' '& *' , ' / < :( ' & ' ! * / ' & ?' ' ?# '& > ?% '& ' 5 & ' ? '& $ ' #59D F4 ' - ' ' *' ' !' -# ' &5 ! 5 & ' ? '& & ( ! * = ' 6 $ * ! - ' ' B F4 = $ ' ' 5 & ' ? '& $ !' ' ' ' ? '&! $ F4 = & ' *' ' ' B ' - '&

9

98

&' (

* & & & '& "

+

'

&'

' *'

&

-

9

,

(

( ' =$ &

6 '

'& '

&

*' =$

'' * & ' '' '

( ! &! '

" . . . .

> ?% ( & 5 & ' ? '& ( & > ?% ,- ! < ! *' ! '= * 5 ! , &' . ' 8* ' * ( '& *' &' ' > ?% '& + -' ( & *' '= & * = & ' ( & ' D ' $* 5 & ' ? '& $ ' *' -' ' - ! > ?% '& $ ' * 6 ' * = *' '

' ' ' '

> '

%' & & '

(

& '& *'

?%

(

( ' * ' ' ' - ' ' * ' &

&

$

' '

' '

< +

'

'

-' * & '

$' 6'& (

&

-

# ?# ' $ ' = & & ' , > ?% '& & & ,>@ < % --' & &

' > ?% '& ' '' '& - ! 6 ' & ,>@ < % ( ' ' ' $ 6

& , &' '

9<

## ( <9

' ' # ?# ' - ' '

'

*' - ' ' = & & '

& ' ' ?

'

,

-$

*

*"

&

)

=

-

.

/

' B !' ' !' * '!' ' 1 8 F$ 9 8 F$ : < F ' 99 F2 & & '& $ '!' ' !' F P ; *' ( ' ' B & ' - ' B ( ' ' * ' ? ' ' ? ' ' ' $' *' ' ' - * * ( ' & & ' ? ' $' ' '& ' ' B $ &' D ? & ( ? B ' F4 B ? F4 ( ? ' ' ' * ! ' D B ' @ & ' *' & ' H G * = # ' 1HG#2$ * * '! ! ' 1 2 ''

98

>

?%

'

-

( - ' ' + ' = & & ' *' B > ?% -' ( ' = && *' ? -$ ' *' - ' * ' - ' ' - ' # 6 *' - ' ' > ?% '& ( 'E 7 ' ' = -' ' $* 'E 7 Spectrum Analyser

' ? *'

Marconi 2382

Terminated Tracking Generator 50Ω Output Measured with Oscilloscope Probe on x1

RF Input 50Ω

Attenuator Stage

Buffer Stage 50Ω

%' *

'

'

'

&

):

& *'

'

=

-

): .

( ' ? <

(

*"

&

'

'- & '

' *

-' ' ! ( ?

-' -

)

'$* ' '

1

/

* * '! F4 (

'

4

' ?

' $* ? 9E

' '-

' * ( ? ' ' & F4$ * ' ' '&' , ' D - - - !' F4 ( ?8 ' ' & ' ' ? ' ' ? &$ E ' 8 F4 '' -'& ' ? &$ ' & ' -' ' , ' F4 , ' *' & ' * -' > ?% ( - *' & ' - '& ' & ' ' ' ' + ' = ( *'

'

F4 - '

'

D

'!' #

'

- *'

-* = & /' $ ' , ' 7$ '

-

& ' 6

& $ '

'

$ &

*'

* *'

& ' - ' &' ' ' ' - ' *' ' 7

$

&

*'

* !

6 '

' & *'

' "

Oscilloscope Probe 1MΩ R

Signal Source

R

1MΩ Impedance Transmission Line approx. 1.5meters long

& !

,

( ' 6 -'

$' ' ' ! - ' ' & *'! ' '&' ' - ! ' ! ( 7 ! $

;E

'

B -'

'

Input 1MΩ Termination of Oscilloscope

&'

*' E-

7

6 '

* +

$ ' ,

&

& ' - ' ! ( ' !' ' * B !' ' ( * -'& &' ' & '- - - , ? B F4$ ' &' *' F4 * ' ' '= &? &' ' 6 & ' $ ' * + ' # *' $ *' ' * ' & 6 & 7

- ' ' '! '

'

' '

9D

< #-

'

, *' ' > ?% '& $ ' & * (

!

- ' * #59 --'

$ ' ( 6 $ *

-

& '&

! *" Spectrum Analyser

&' *' '#5 : .

Marconi 2382

Tracking Generator Output 50Ω

RF Input 50Ω

Amplifer Stage

50Ω

50Ω & "

( & & '+ '&'

' = & & ' *' ?E - ' *' ''& & ' E 7 ' $ ' *' - ' $' * ' ! ( *' ' = -' ' &'E 7 ' * E 7 ' ( ''& *' ' &' & ' * '- & ' *

*"

& # .

= )

1

, /

9:

# ' $ * ! ' ! *' $ * '

' B 8

'

$

' $ <8 &$

6

'

' # 5. &' ' $D ' 8 &' ! * *' ( D '- &' !'

D '

& & & '

<< #

= & ' ' ' B *' & (

' '

' ' B

8

' (

' '

'

- ' %'

&

- - * #5 : . & *'

#-

'

&

*' ' &

=

' ' '3 *' '

? '& '

-

>

'

&& ' = F ' ! > ?% -

' &! ! -

&

-

' *' *"

-

): ,

'

' '

-

&

#&'

$ '

' ''& * & ' = & & ' ?E -$ ' - ' &' ?- ' ' - ' ( *' &' 6 $' # ' ''& *' '- & '

,

6 '&

-'=

*' * , *' ! * ' . '

*' ' ?%

- ' ' #5. '& ' ' %S?

>J

.

!

( '

!

)

*' ' ! & &

' ' & '& > ?% # ' '

1

/

''

'

'= $ 5& '?

99

$ * '! ,>@ # 6 < %

*

E ( ( 5& ' ( '& '

''

& I>#(+ '

*

,>@ < *' #5.

& > ?% '& '& ' %S? & ' %S? >J ( > ' < % ( ' > ?% *' B ' &

- '

% @' >

*

> B

'& ' 5& ' ,>@ < % & '& ( #5. -' ' $* & *' ' 5& '? >J & ' - ' ! , *' ' ' ' 5 & ' ? '& -' $ ! ' ' ! ?% '& ' < % & ' - *' ' ' ' -' ! ' & -' - *' '>' # -' ( 1>#(2 & - ' * < %$ ' * < %+ ' *' # ' >#( -$ > ?% '& * *" *'

'

'

- ' ' *'

2026 Signal Generator

?%

*

GPIB Control

Host Computer IFR 2026

A: 10MHz B: OFF C: 40MHz A

B

Σ

C

40MHz Sinusoid

Input Signal

74AC04 Based Clock Generator

Front-End Stage Dither In

National Instruments NI-DAQ Interface

40MHz Sample Clock

2319 RF Digitiser

LVDS Out

IFR 2319E

(Used as data capture device) & +

.

/ -

9

# 2

'

->& 9 * & - " # & ' & ' $ ' ' ,>@ D- ? & ' & ' ( ' $' ' ' & & ' 2 # , - ' .$ >#( *' 2 # ,>@ < % @> 5 & ( ' ' '' ' ' * /H5 ' ' G,?5#K ' ' . !2 ( > ?% < % !' /H5 ' , ' ' '= ' & ' < % ( ' = ' & ' & ' ' 6 ' :8#. 8 ' ? ? = & ' 1( *' & ' 2 ( & ' '= ,>@ D$ * , >#( *' & . 3 >#( & '$ ' & * $' 1 ' B - ' & ' ( & '' * & ' '! " 2 ( B & ' B ' ! & ' & ' & , ' 2 5' ' ' < % & G,?5#K ' 2 ( '' ' B -' ' B B -' = ' - ' $' ' ( * &- ' * ' & >#( -" ' < 2 ( B #5. '& $ & '$' 2 ( ! ' #5. '& $ & ' < '$' 2 ( ' < ' #5. '& * ' * ? ! $* ' * !2 ( B * > ?% '& $ & ' < '$' !2 ( ! ' * > ?% '& $ & ' < '$' ( B ' & - ' *' =F4 F4$ ' ! ' & - ' *' ? - Y9 - ( 6 '& * * &' >#( $' B ! ' 6 -

D

&'

>

& 8

?%

'

0 0

8:

&

&

,

<

, & #

%

"

7

,

):

: #5. > B

@

( B #59 <9 ' #5 <$ ' = ' #5. '& $ *' - ' & >#( ( '- ' B $ ' < '' * - ' =F4 F4 * ' #5. '' 8 F4 ( ! *' ? '! '& * '= ' - ' ( & * '' " -10 Fundamental -20

-30

Measured Level (dBm)

-40

-50

-60

Second Harmonic

-70

-80 Third Harmonic -90 Noise Floor (32768 Sample DFTs) -100

0

20

40

60

80

100

120

140

160

180

200

Input Frequency (MHz)

&

=

-

(

0

-

( B #5. '& * ' ?< ' * ' F4$ * ' ? $* * E F4 ( ' ' & ' * #5. < F4$ ? = #59 <9 #5. ! ( 6'& B B ! + '' ' &' 8 ( ' * *' ' ' F4$ ' ' * ( ' < '' ' D * & ' ! * ?< ' * ( & ' ' ' ' ' * D ,G#5 > ?% '& ( ' ? D < :D9 5>( ( ? ' ! #5. *' ' ' ! ! -$ *' - ' ' ? D > 1 > ? ' 2 ( ' * ' 5>( - ' ' ' &! ' ' * G B ' * ( ' * = * ' G ' ?3 G 3$ ' /2 , ' ' @ ' ?3 @ 31 * * '' ' -' = * ' 1 " '

/ (

1

/ ''

* ! - ' ' *

$

! *

' *

& I

1

' & 1 ' '

3

G 31

1

( * *

/ 1 *

' '

'

'-

'=

' * * ' ( ' *

* G B = * ' G B

2"

'

/

*

>#(

1

< :D9

3

* - ' ' '

-

/

' ' ' 5>( 2 ' B '

2'

/ %

'

/ %

3

'* *' "

B

& '-

(

'

' =-' ?F' & &'

* ** 5>(

:88: < ( <9 :

G@ ' B #5 < '! ?E ?<9 : N ? : : > ( & ( ' - ' 6 !

9 #5. / ! /

?E *

> $

6 ? D > *' '

'

'

( #5. ' ? ' ( - (

- ' - -' & >#( - *' ' ! ' '& ( *' ' *' ' ' ' * ! ' '- ' & ( * ' ! ' ! ! ' ' * ! ' & ' ' *' ' F4$ * ! ' & & -? ' < '$ ' * Y9 '- ' $ - ' & < :D9 5>( '! '& - ' ( ' * 6 '& >& ( ! ' ' ' ' ' ! $ ' '- ' - ' ' ' '- ' ' '-' ' $ ' & & ( - -- ' ' ? $' -'6 - - ,& ' G # 5 1 ,G#52 ' ' & !' ' 6 -' D ( * ' ' #5. '& & ' & ' '' & $ * ' ! ' - ' ' - - ' ? - ( & ' ' ' ' -' ' ' *' ' & '

5

%!' '

( T 8U ' ' *' B B ' ' '

-

' ! ' 5 '- @' & 1 >5@2 & ' -' ? ' - ' >5@ ' ( ' -

B

>

# & '

' '

& 4' & ' ' ' * ? * * <

' ' >&

'

'

'

'

-

& '

(

'

'

<

10 0 -10

Measured Level (dBm)

-20 -30 -40 -50 -60

Fundamental

-70 Third Harmonic

Second Harmonic

-80 -90

Noise Floor (32768 Sample DFTs)

-100 -90

-80

-70

Relative Amplitude (Not to Scale)

&

-60

1

ω1

-50

-40 -30 Input Level (dBm)

-

-20

-10

(

0

10

-

ω2

Key: : Fundamental Tones ω 1 + ω2

ω 1 − ω2

: Second Order Harmonic Distortion : Second Order Intermodulation Distortion

ω1 − 2ω 2

2ω1 − ω2

2ω1 2ω 2

: Third Order Intermodulation Distortion

Relative Frequency

&

$

(

1

'

' * &

* ' -$ ' &

, *' * >#( - ' '

$* ' ( * ? &

=

*

-

' ' ' ' * ' & '

'

' & '

,

- & * ? ' & ' * * ? ' - ' *' , ' '

, )

< & ' $ ' -

' & ' *' ' * '! '

, '

> '

- ' &

>5@ > &

-

,>@ ,>@ ?%

?% &

D$ ' D ' $ ' & ' & ' 8

*' ' * ' ?D -'6 - '- ' & -' ' ( B * & ' >5@ *' * ! ' & & * - ' ' -'6 - ' ' * & *"

- ' * ? '

$ *

Y9 -

F4 ' - ( !

*' F4 ( >5@ *' (

0 -10 -20

Measured Level (dBm)

-30 -40 -50 -60

Two-Tone Level

-70 SFDR With Dither -80 -90

SFDR Without Dither

-100 -90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

Input Level (dBm)

&

!

(

#

& '

>5@ & ' *' !'

' $ -' ? ' B ' ' * & -

' ! $' *'

,

,

0

' # '

-

'

- ! >5@ ' - * ' ! &' *

! ( '

'

( ' >

?%

@

( ' ' >#( > ?% '& -' ( B - ' ' ' *' #5. '& ( & ' ?- ' ' - ' $ '&' & & ( # ' ' &' '& * D * B $' ! '

-

' ! ' ! ' *' & ' *' - ' 6 >& E ' >& ! '

E

-10 Fundamental -20

-30

Measured Level (dBm)

-40

-50

Second Harmonic

-60

-70

-80 Third Harmonic -90 Noise Floor (32768 Sample DFTs) -100

0

20

40

60

80

100

120

140

160

180

200

Input Frequency (MHz)

&

"

):

=

-

0

-

-10 -0 -10 -20

Measured Level (dBm)

Third Harmonic -30 -40 -50 Fundamental

-60

Second Harmonic

-70 -80 -90 -100 -90

-80

-70

-60

-50

-40

-30

-20

Noise Floor (32768 Sample DFTs) -10 0 10

Input Level (dBm)

&

'

#

, - ' ' * (

):

1

-0

' -&

'!

6

$

-

#5. * &

'& $

-'

D

- ' * B '-

! 5. ' '' -$ *

& ' #5. '' ' ' ' '&

& F4 $ 6 (

' ' (

'& ' ' * F4 ( $ '

( ! - *' - ' - ' 6 ' *

- ' '

* ' !

'&

> '

?%

( & # --' #5. ' * #5. G@ 1 2 #5. ,G#5 1 > ?% '& > ?% '& > ?% '& 7

(

- ' ' & ' F4

&

'

E: < D GL# 1H E < < 13

' '& + !

* &

'-

! ? ' ! F4$ * * &'

' &

&* * *"

!

' * = &

'&

'$

' ? ' 2

' 2 .

)

1

* = *' B -' (*

/

!

* -

"

+ ' '

*' < - &

!

):

(

' '

(

*

1

'

? '= ' '

B

> ?% - '

*'

' !' * ' ' *

&.

2 ' * 1 F42 G@ 1 2 ,G#5 1 2

-' ' B ' ' &- ' 2 ( 2

'& & (

& '

?%

* *

-

(

*

-

'=

' - ' 1 F42

'

- '

*

(

'

> ' ' '$ B ' ? > ( > ?% ' D * ! & ' ' '$ * & ,G#5 ' ' - ' & ' & *

G ! *

(

' $ ' & '-

# ' ? ' $ * !

B & '&

&

& 6 *' ' &' * ' F4 ' * #5 : . &' * -'= ' * =

& '

*' &

'

'

B -'

( & 5 & ' ? '& & - *

' '

,

6''= *' * * & - ! >

' -$ ?%

*' '& +

' -'

:

5 & ' ? '& (

&

>'

! ! =

'

!

& .

3

' *' #

& ' '& ' $* ' '

' &

& B

?

E--

-

# '

*'

$

*' & '! ( *' ' ='& '+ '6 ,, ' ='& $ ! $ ' ' ' ! - ' *' & '-- & ! B ' ' 2 - ' ' *' $' '' . (# ' 5 & ' ? '& , *' & ' ' ' ?# '& $ ' *' & & & ' = & '$ ' & , ' ' # ' &5 ! #59D F4 ' - ' ' *' ( ! ' 9 ! *' & '6 ,, ' * ' /%5 $ ' F4 ' & & ( * = ' 6 # *' ' - - ' ? '= & ' $ -' & * = 5 & ' ? '& ! ! ' & &' 6 '' ' '>,> - ( * = *' ' ' $ * &'! - ! -' > ?% '&

9

>

?%

, *' D$ *' = , *'

! '

' & ?

&&

6 *' '= * ' *'

'

,>

-' ' '

'

): % &

( & <

' ( ' -"

>& ' -

?%

&$ '

- '

' -

( ' = && & *'

' "

,

'&' $ ?

& * & - (

&

%

7

' * ' 6 & '! *? ' 6 & ( 6 & '! ' & ? *' - ! - ' -' ! 6 & !' ' -' 6 &$ ' ' ' ! * * & & & ' = & & '

' *' ?

1

( '

):

= 1

' ' ' ' ' & ' B ' ' ' 6 - ' , *' ' #5 : ' &' * ! ' ! '&! B & ' ! &' ! ' -' ''& ( * & ' ' &' D '* ' * ' & ( ' ' B ' # '* &' * ' ' * ' - '' ' '-

-

7

?

!

$

F4 ' -'

% &,

&$ ! -

! -

> ?% ' ' * * ' ' ' , *' &* *' ' & ' ' ' *' , &' * ' $ ' ' &' ' ' & B ' ' ' & =

F ' *

( ' =

=

9 & 9

( #5 : *' *' ' "

!

( * &' *

&

=

# (

# & *' '

'

*

&& 9

,

' * &' &' * &' ?E

* ! ' -"

9 0

,

0 2D 6

' #

' #>

9

'

2D 6

0 , 2D 6

' -

! -

0

*'! '

$

' & *

' * &

, 2D 6

! ' *

#> '-

9

,

'# >%( *

9

! F4 ! -

,

#5 : !

$' '&

,

$'

,

. ! #5 : ! &' ' ' = &

"

1

9

=

-

&& 9

( ! & &' ! $ %' &' ! ' & ' ' ' F4$ * ! ! ' ( * & * & * '& $ ' ' ' & & ' '

#

1

= 0,

* )

' ' ' >

?% &#

1

-

): &

0

:

'

,

$ ' ' &' & - ! -

' ?# '

#2"

1

=

-

) &

( * D ( # ?# ' '' '! ' ! - ! -

>

?%

'

#-

' + &$ !

' ! >& &'6 ' $ ' & ' ' &

0,

0

'& * * ' F4$ * ' : ( ' B ' ' -# ' ' 8 '&' $

' '

- ' ! >& -' = ' &$ ' ' -

<

<

*' (

( '= '' ' ( ' @ '

,

<

5 !

-

&

' *' & $ &' - *' ! ( * '' & '- $ ! -*' ' ! -*' 9 E & ! + & 5 & ' ? '& $' -' $ ! ' ' ' '' ''' & + B !' * * = ' "LL& -

(

5 !

& '& $

*' *'

'

'

%S? -' '

'

>J '

1 !

$

'

&

* & 6$ ' ! "

> -*'

( -*' & ' ! ( & '9 E ?H ( -' * ' & *

%S? *

>J + 9 E 1 & '#G , .+ ' '- ?* =

*' * . & A

--'

* I...+

!'

void main(void) { ... // Initialize user device TD_Init(&pollStatus); ... // Task Dispatcher while(TRUE) // { if(GotSUD) // { SetupCommand(); // GotSUD = FALSE; // }

Main Loop Wait for SUDAV Implement setup command Clear SUDAV flag

// Poll User Device if (Sleep) { if(TD_Suspend()) { Sleep = FALSE; do { EZUSB_Susp(); // Place processor in idle mode. } while(!Rwuen && EZUSB_EXTWAKEUP()); // 8051 activity will resume here due to USB bus or // Wakeup# pin activity. EZUSB_Resume(); // If source is the Wakeup# pin, // signal the host to Resume. TD_Resume(); } } TD_Poll(&pollStatus); } }

8

( !

+

& '& '

' 1if (GotSUD)2$ 1if (Sleep)2$ status

' &

'

'

TD_Init()

--

* = *

= ' &

=

''

'

' # '

' ,

'

TD_Poll()

TPollStatus

' -

*

'

( --

'

*"

struct TPollStatus { // Boolean value denoting whether the TD_Poll() function is // currently sending data across the common serial bus: BYTE bSendingData; // The channel to which the data is currently being sent: // (Either 0 or 1) BYTE channel; // The data being sent a bit at a time across the bus: WORD serialData; // The current bit being sent: WORD currentBit; };

(

TD_Init()

*"

void TD_Init(struct TPollStatus *status) { // Set the CPU clock to 48MHz CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1); // Set up the strobes and flags for active high: FIFOPINPOLAR = 0x3F; SYNCDELAY; PINFLAGSAB = 0x00; SYNCDELAY; PINFLAGSCD = 0x40; SYNCDELAY; // Set up the FIFO interface for an external clock: IFCONFIG = bmIFCFG0 | bmIFCFG1; SYNCDELAY; // Set up EP2 FIFO: EP2FIFOCFG = bmAUTOIN | bmZEROLENIN | bmWORDWIDE; SYNCDELAY; // Configure EP2 (IN, BULK, 1024) EP2CFG = 0xE8;

SYNCDELAY;

// Set up EP2 FIFO for 1024 byte packets: EP2AUTOINLENH = 0x04; SYNCDELAY; EP2AUTOINLENL = 0x00; SYNCDELAY; // Configure EP1OUT (OUT, BULK, 512) EP1OUTCFG = 0xA0;

SYNCDELAY;

// Reset the FIFOs: FIFORESET = 0x80; FIFORESET = 0x02; FIFORESET = 0x00;

SYNCDELAY; SYNCDELAY; SYNCDELAY;

// Arm EP1OUT: EP1OUTBC = 0x00;

SYNCDELAY;

// Enable remote-wakeup Rwuen = TRUE;

E

// Initiate the serial bus: // -----------------------// Enable the output port: OEC = 0xFF; // Use Timer 2 for timing the serial clock period // Disable the timer: T2CON = 0x00; // Reset the timer: TH2 = 0x00; TL2 = 0x00; // Reset the bus: IOC = 0x00; // N.B. Both relay enables are low // Initialise CH0: status->channel = 0x00; status->serialData = 0xFF00; status->currentBit = 0; status->bSendingData = TRUE; IOC &= ~bmSERIAL_CHANNEL; while (status->bSendingData) serialTransmit(status); // Enable the CH0 relays: IOC |= bmSERIAL_CH0_RELAY_EN; // Initialise CH1: status->channel = 0x01; status->serialData = 0xFF00; status->currentBit = 0; status->bSendingData = TRUE; // Set serial bus to CH1: IOC |= bmSERIAL_CHANNEL; while (status->bSendingData) serialTransmit(status); // Enable the CH1 relays: IOC |= bmSERIAL_CH1_RELAY_EN; }

( >,> *'

&

= 89 F4 ' & ' 6 ' = # ' ' ' D * 4 7/ & 8 ' = ( & & ' ' '' % 1% 2 ' ' F ' $ >,> ' # % ' ( $ ! '' $ 4 '' ' ' ( ' * ' -' '- SYNCDELAY$ ' ' ' <. ' * & ' & ' ' &* ( -' ' 9 E + ' $ ' = ' ' ' ' '' (( serialTransmit() ' ' & !' status$ * ' TD_Poll() ( TD_Poll() ' * ! & , ' -$ ' B ! -' * ' '' ' ' ! % ( *" '

&

' !

%$&

. + & ' *

D

void TD_Poll(struct TPollStatus *status) { // If we are waiting for new data: if (!status->bSendingData) { // If new data has arrived: if (EP1OUTCS == 0) { // Check there's at least three bytes of data // in the buffer: if (EP1OUTBC >=3) { // Read in the channel (1 byte): status->channel = *EP1OUTBUF; // Read in serial data (2 bytes): status->serialData = *(WORD *)(EP1OUTBUF+1); // Re-arm the endpoint: EP1OUTBC = 0x00; // Set SERIAL_CHANNEL: if (status->channel == 1) IOC |= bmSERIAL_CHANNEL; else IOC &= ~bmSERIAL_CHANNEL; // Set the current bit to 0: status->currentBit = 0; // Set the sending data flag high: status->bSendingData = TRUE; } // Else an incorrect amount of data was sent, rearm // the endpoint: else EP1OUTBC = 0x00; } } // Otherwise, we are still sending the last data to the // serial bus: else serialTransmit(status); }

( TD_Poll() ' * ' ' & ' '' bSendingData ' ' !' % * !' channel ' $ '- & % ' serialTransmit() ' ! '' ( serialTransmit()

'

$

*' & * '' ' ( ' 3 * '' ' ! serialData ' ' ' & bSendingData TRUE '& ' = ' ' *"

void serialTransmit(struct TPollStatus *status) { WORD timer; timer = ((WORD)TH2 << 4) | (WORD)TL2; // If the current bit is less than 16: if (status->currentBit < 16) { // If SERIAL_SCLK is low and the timer is not running: if (((IOC & bmSERIAL_SCLK) == 0x00) && (timer == 0)) { // Write the current bit to SERIAL_DATA: if (((0x0001 << status->currentBit) & status->serialData) == 0x00) IOC &= ~bmSERIAL_DATA; else IOC |= bmSERIAL_DATA; // Enable the timer: T2CON = 0x04;

:

} // If SERIAL_SCLK and SERIAL_SCLK2 are low and more // than SERIAL_HALF_PERIOD has passed: else if (((IOC & (bmSERIAL_SCLK | bmSERIAL_SCLK2)) == 0x00) && (timer >= SERIAL_HALF_PERIOD)) { // Set SERIAL_SCLK2 high: IOC |= bmSERIAL_SCLK2; // Disable the timer: T2CON = 0x00; // Reset the timer: TH2 = 0x00; TL2 = 0x00; // Enable the timer: T2CON = 0x04; } // If SERIAL_SCLK2 is high and more than // SERIAL_HALF_PERIOD has passed: else if (((IOC & bmSERIAL_SCLK2) == bmSERIAL_SCLK2) && (timer >= SERIAL_HALF_PERIOD)) { // Set SERIAL_SCLK2 low: IOC &= ~bmSERIAL_SCLK2; // Set SERIAL_SCLK high: IOC |= bmSERIAL_SCLK; // Disable the timer: T2CON = 0x00; // Reset the timer: TH2 = 0x00; TL2 = 0x00; // Enable the timer: T2CON = 0x04; } // If SERIAL_SCLK is high and more than // SERIAL_HALF_PERIOD has passed: else if (((IOC & bmSERIAL_SCLK) == bmSERIAL_SCLK) && (timer >= 1)) { // Set SERIAL_SCLK2 low: IOC &= ~bmSERIAL_SCLK; // Increment the current bit: status->currentBit++; // Disable the timer: T2CON = 0x00; // Reset the timer: TH2 = 0x00; TL2 = 0x00; } } else { // If SERIAL_DCLK is low and the timer is not running: if (((IOC & bmSERIAL_DCLK) == 0x00) && (timer == 0)) { // Set SERIAL_DCLK high: IOC |= bmSERIAL_DCLK; // Enable the timer: T2CON = 0x04; } // If SERIAL_DCLK is high and more than SERIAL_HALF // period has passed: else if (((IOC & bmSERIAL_DCLK) == bmSERIAL_DCLK) && (timer >= SERIAL_HALF_PERIOD)) { // Set SERIAL_DCLK low: IOC &= ~bmSERIAL_DCLK; // Disable the timer: T2CON = 0x00; // Reset the timer: TH2 = 0x00; TL2 = 0x00; status->bSendingData = FALSE; } } }

9

( ' serialTransmit() ' & SDATA SCLK * 2 & 6 !' 2 3' & ' ' SCLK 2 & SCLK & !2 3' & ' ' SCLK !2 & SCLK * , currentBit ' D !2 & DCLK & ! 2 3' & ' ' SCLK ! 2 & DCLK ' bSendingData * # ! $ ' ./A = ' ' * & 9 E + -

<

(

F

#

(

"

'

*

2

'

'

( 3 * # .YY ' ='& F * ! $ ' ' *' - !

'

*' *' &

*'

'

& ' ' .YY

!

!

* ''

'

' ' ' ' ' & '- *' -' '!' ' - *' ! & *' ( ' ' ! & ' ' ' '' & ' & ' , ' $ ' & ' ' ' 6 *' ( ' '' *' ( && & '' & ' ' # 6 *' ! '= ' '' ' '! *' * = ' !' B 3 * 5 ! 5 ! ! ! ( ! * ' * '' ' 4 *

'

$ *

' '

+ H ' $ &'

*' ' '- F * ! ' * &' -' '=$ ' *' ' ' '' ' $ ' *' * & & '-+ ! $ ' 6 ' ' ' ' '

*'

D8A #

. ' & $' A 155A2 ' '

& ' -

&

8 5 ! ( *'

,

&' *'

& !' ' % : 9 & ' '& *' > ?% '& ( -*' %S? >J $ ' 3 *

-' ' ( & '-? & '' * *' * ' ' ' * * $ ! * = ! * C ( * & '& ' ? 3 * ' ' ' ( -' ' = -' ' * & * ' 6 '' ' ' ' ! & ' $* 3 * ' ! # *' ' %S? >J ! ' * ' ! ' '' , *' ' '' 1 Q 8Q 8Q9 N 9<99D 9 2 =' '' 8 < ?% F * ! $ - ' ' 3 * ' ' ' ; B $ '

8

#

!

'

B

!

$

-

E

%!' ' '

'

* ! ' '- ' ' ' ! $' & 2 2 2 !2 !2 !2 ! 2 2

&

$* ' *

$

-

'

* $* '

= ' =' * ' '

$'

2

& ! * 3 ' '! ' *' ' ' & $* =' * = ' ( '- & &' * $ *' ' *' ' ' & *' ( ! -' * ' ' & ' * * ' $ &" . & & ' & ' ' ? > -*' & 5 ! ! '& ' ' & '--' & ! 6 > & ' ' ' & ' '! " ( ' + ' ? * ' ' & & ' # ! ' ' 6 ' * & '

2

>

# 2

6 '

( & '

'

2

&

2

(- = ' &

( ' '

'

B &'

'! &

'!

'! *' &

' ' ' *' ( * ' - * '!' ' " 2 ( ' -' &! >#( 2 ( ' ' 2 !2

' & - !

!

'

"

-

'

!'

& ' !' '

- ' & - ' ( *' '

&

'

*' & '

'! '*

'

* !

' -

'

$

-

- '

&'

' ' & ? ? & ' $ * *'

' ' - ! >5@ ! ( ? - '&.' ' 5& ' # ' & . ! * '= *' 5. ' &! # -' ' ' *

-

!

* =

D . (

+ '= ' ' # $ $ $ !' & *' ' ' -$ * ! '= ' - ' ' ! ' *? ' ' '

( ' ' 6 -' = ' ' # ' " '' ' (

'

*' & $

'

' '

' -'

' (

'

$* *' '

!' *' B -

&' $ '

! & *'

'-

' # !' '& -

' ' ?

- '-

'= &

&

' &'

*' *' -

' & ' ' * '

' !

& $ &! & ' =

* & ' *

> & '?

' ' -

'

* -? ! & $ * & ' *' & 6 ' ' ' ' -' *' & ! $ & ' ' & ' -' & ' ' ( ' *' & - ' ' & ! * ' ' ! ' & * B ( & ' & '& * ' '' ' ! ( ' > ?% '& ' *' ' - ' ( ' & '- * 6 &' & ' ' ' &' * , & ' * * ' ! ' ! + -' ( - ! -' 6 & *' $' . &' * * ' '# >%( * $ ' ' -' * '= & -' ' ( *' - '!' ' ! ' -' *' B ' ! ' -' '' ( *' 6 ' $ ' ' ! -' - ' '* $* ' *' 6 * ' * < $ ' ' 6 89 ( + !' ' ' ' ' ! * - & $ ' -' ' - ' ! &' & ! ' ' ! # & 6 ' &' $ ' &' - = & -' ' & 6 ' - - ' ? - '& $' ' -' ' ' & ' ' -

?

& = (

*' "

&

- ' ' ' '

-

& -

!

* $ '

' (

' %

&

<

: # :

# (

6,

G

?

- '-

&

-

(

5 '

'

-

1 2

$ '

!

,

&

'

)

12

1

1

' '-

&

'"

'

'"

2

1

*

' ' -

! '-

- ' * & ' 1 2$

1

& *1 2

*1 2 12

12

)

12

&!

1

1

' & ' &

'-

"

2

1

(

-

> *1 2

'*1 2

'

12

* '

>

) &!

# % '

"

1E2

12 >1 2

* >1 2 &' , ' '& B ( '

)

'-

&

'

$

-$ '

12

"

1E2

$'

*

182 '

"

" 12 $ &

> *1 2

-"

"

'

&

! 6 '

" $ &

)

12

'

"

* '&

6

>

182

3 1

&!

"

12 1

& '

)

"

)

"

>T

"

1

B

1

&

"

"

12

2U > QT

> ' ' > *1 2 6 '

# % '

'-

1

2

"

1

2

2U

-

12 ' B

'

> Q1 2 * -

'-

- 6 ? & ' 8

F * ! - '

*

1

'

1

!

'-

1

'

1

1

'

1

'

(

12

- !' '

1@H 2$ *

'

'

'

!'

$

1

B '

"

1

1 2$

1 2"

! 12

12

12

1 2Q 1 2

12

1 2Q 1 2

(

-

> *1 2

' 12

)

-

"

1 12 6

+1 2

+1 2

& '$

1

1

@T+ 1 2U

'-

"

12

(

* (

*

*"

* !

-

@T+ 1 2U

'

"

12

' ' ' 6 '

)

@T > *1 2U

&!

' "

12

1

- !' ' ' ' - '-

& '

"

12

1

"

12

* , '

)

1

12

" $) &1

# 1 2% '

'

1

* 1

1

<

'"

12

1

( " * @T > 1 2U

:

#

>1 2

6 ,, 5 - 5

5

- '

!'

@'

B '

'

- H' '

& '"

1 2 ' B ' Y L ' ? L "

* %

%

1% 2

!'

%

$ '

%

- &

%

@H - %< , <

" < $$ &< 9

# % < 9 %' <

<

E

:< # G

6 ,,, 5 !' @' ' #5.

5

& '

9/8

B '

2

"

'

B '

'

9/8 1 2 2

%

'

2

2

<

# % 9 ' ' 2

& '

"

' 2

' 2

9/8 1 2 2

'

'

"1 $ &

12

-'6

& '

B ' % *'!

%

'

'6 - -

B '

2

*

B '

'

2

2

9

B '

"

2

9 " <# &$ % & '

&1 2

2

:D

D

2

D

:8 # ( .

< 8 E D : 9

( ( ( ( ( ( ( ( (

&

6 ,H 5 ! * & (

'& '

-' ' *&!

-' '

& ' '& +

> ?% '& # ' $ $ #' ' # ?# ' > '& > #5. 5 ! $ #5. ' /H5 / ?5 ! '& > ?% . -' 5 ' ' * 5 ! > ?% * 5 & ' ? '& & ' % : 9 ! 5 & ' '& ,L ' = % : 9 ! 5 & ' '& /H5 ! $ ' >,> ' ' 5 & ' ? '& -' 5 & ' '&

&

*

?%

:

9

<

8

E

D

9

' # ,

#

' -' * ? !

?

& '- , ' * ' & '-

?# ' ? !

19 Q % ' >,> > -*'

/

. &?'

@. @> ,G#5

2

# >

'# >%( F ? *'

? '

& ' -' , > *' ' ! $* -' - ' ' ' -# > % # ' -* ' ' ' ' - ! * / ' & ' ?( ' ' B ' ' ! &' '. ' # ' && ' ( ' ' -' ' ' ' !' ! !

' ' & '- '

@ ?.' ' @' > B ,& ' G #

5

^ -' %& (' ' *

' ! *

& *

' #5.

' -

& ' * ! ' ' '

! ' '

'

9

&' #6 F

$W $W

. -

$X 6

&

%6'-

5

.

- .

#

' '

$ W%S? A .

*

8

$X 7

$

*

>J

-

$ ' $

#$

%

+3

'

. -

$

-' ' $X @ !

$W

.

$X F

$ *

$

9 A 7 $

'$ W5 & '

, 5 @ +

'

4 $

4' $ W

'

'= ' 5 ' $X

-

'

$ W@>,. ' <$

*'! % &

&$X G $ (

$@ F $X

(

'

' )

7

/ $D % $

# ( -' $ W% -

$W 9

' & '

H

$

)

& $X 7@@ % $

&$

9 $'&

-

D

' ,

' $X 2 3

,.

' '= $ W5 & ' & ' ) 7 @ $< % $

@ % 3' ' . !

&$ '

/

*

5 '

& '

' -'

' (

% & $X (

$ / F # ' $X

' 5 # &' A' -'

' ,

$ W. % $ $

# D

' K '

' !

<

@

T U% ( 3 ' T U,

'= $ W $X

= '

# +

4 T
' $

7 T8U , 7

* 8 =

$ W@'


-4

$

9 ? 8$

& '

6 ' E

&$X

)

7

$

' @ # ! -' $ W# ' ? $ ,(?9 8E?E8$ D =$ W

'-

&

' ' '

@

TEU F

' $$ !

@

' -

&

-

$X 78@

'-

& ' $X

+6 *

>

ED$ '&

& $ .. = $ ' F -' $ W@ ? - '' ? & ' $X -I J432 & E ?D $ '

TDU F

>

& $ .. = $ ' F $ W>' & ' '&$X & 7&4

'& + J&3+ ! -

' ! ' K<-+ 2 +

?

' ! +

::
3 *$ W ' 47@@ B4

T9U G

' ' ' & ' $X

& & ' .

T U % / =' $ W. ' ' T U ( A'*' '$ W> G)$ :

T 8U & '

$X

?'

$ W( $

/ 4$ $X 7@@@ ' *

' $

-

$X 78@ B '

$/

'

(

H'

=

'

B ' :

?# &

$

A$

$X 7@@@ D

$X 4 $ '

G $!

4' 7

4' D8

D ? DE$ 5

$X 3

# '

T

' ? $

>

? '' - $X 2$ EEE?ED9

'

& D

8E? E8$ >

-' $ W5 $ $!

&

'?B ' 4 'C$ ! : $ D 1 ' +D

/ @ @' $ W( ' $ G$! E

T U/ @ $W $ $ ! ,(?9$ T U /

' ' ' 7

$ G * ) =$

89$ '

3 & $ W# $> B

<

T EU . A == + 0 @ # ' '

$ W,-

! & #5. & @

T DU @ # 3' '-'= $ W( 0 4 2 $+ * (

$ 3'

-' + '- .

$

' =

B ' 4' $ .' ' '$

& !

$X G

K

$ ' $

$X $ 0 :

+

<