VENUS INTERNATIONAL COLLEGE OF TECHNOLOGY Bhoyan Rathod, Gandhinagar

Index BRANCH: SUBJECT: DIGITAL LOGIC DESIGN SEMESTER: 3RD Sr. No

ENROLLMENT NO:

Topics

01

To practice converting data from decimal to binary and hexadecimal systems.

02

To study the basic logic gates which are used in digital circuits.

03

To study NAND and NOR gates as Universal Gates.

04

To study the arithmetic function of addition by building Half Adder and Full Adder circuit using logic gates.

05

To Design Half-Subtractor and Full-Subtractor.

06

To study the operation of multiplexer circuit.

07

Page No.

Date

Signatur e

To study the operation of de-multiplexer circuit.

08

To study R-S Flip flop circuit.

09

To study D Flip-Flop circuit.

10

To study JK Flip flop circuit.

11

To study Master-Slave JK Flip flop circuit.

12

Study of different modes of Shift Register.

13

To study the function of Decade Counter.

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EXPERIMENT NO.: - 1 AIM: To practice converting data from decimal to binary and hexadecimal systems. PRACTICE 1: Perform the following conversions and verify your results using Scientific Calculator. (a) Base-10 63 256 10 512 255

Base-2

Base-16

Base-2 11010 10000 11110 101010 1111

Base-16

Base-10

Base-16 3BC 10A 20 FFF FA BAD

Base-2

Base-10

(b)

(c)

Give the answer of the following Questions. 1. Give the highest single digit for each of the number systems: decimal, binary, and hex.

2. Which of the following cannot be a number in base-2? Give the reason. (a) 11001

(b) 113

(c) 10001

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3. What is the highest 8-bit number? (a) In binary:

(b) In hex:

4. What is the highest 16-bit number? (a) In binary:

(b) In hex:

5. Convert binary 100000 to decimal and hex. (a) Decimal:

(b) Hex:

6. Convert hex number BAAD to binary and decimal. (a) Binary:

(b) Decimal:

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EXPERIMENT NO.: - 2 AIM: To study the basic logic gates which are used in digital circuits. THEORY: Any Gate is a logic circuit with one output and one or more inputs. The output signal of any gate occurs only for certain combination of input signals. Different types of gates are used in the digital circuit like AND gate, OR gate, NOR gate, NAND gate, NOT gate are the basic logic gates. Some gates are the combination of above basic gates. Such gates can be prepared by using discrete components like diodes, transistors, and resisters but nowadays, different ICs are used to have different gates. A power supply of +5 V is used to give input. This supply is also used to drive ICs. When power supply to the input is 'ON' we can say that logic level is at '1' and when power supply to the input is 'OFF' the logic level is said to be at '0' level. AND GATE: AND gate is a gate which gives output (output at '1' level) only when all inputs are present (i.e. all inputs are at '1' level). Here IC 7408 is used which has 2-inputs AND gate which are four in numbers. Here only one gate is used. The truth table of AND gate is given in the table. A 0 0 1 1

B 0 1 0 1

OUTPUT 0 0 0 1

OR GATE: OR gate is a gate which gives output (output at '1' level) when any ONE of the input is present (any ONE out of all input must be at '1' level). Here IC 7432 is used which has two input OR gates which are four in numbers. The truth table of OR gate is given in the table. A 0 0 1 1

B 0 1 0 1

OUTPUT 0 1 1 1

NOT GATE: This is also known as INVERTER gate. This gate has one input and one output. All it does is invert the input signal i.e. if the input is at high level, the output will be at low level and vice versa. ICs 7404 or 7406 can be used to get NOT gates, which are six in numbers. The truth table of NOT gate is given in the table. A OUTPUT 0 1 1 0

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EQUIPMENTS REQUIRED: Trainer kit or Bread Board, Power Supply and LEDs. COMPONENTS REQUIRED: -ICs 7408, 7432, 7404. -Hook up wires. PROCEDURE: 1. Pull all switches at „0‟ position. 2. Switch ON the power supply. 3. Test the truth table of different gates by changing the position of inputs (i.e. „1‟ level means switch is ON & „0‟ level means switch is OFF) and check the level of output (if LED glows it is at level „1‟ and if LED doesn‟t glow output is at level „0‟). OBSERVATIONS:

CONCLUSION:

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EXPERIMENT NO.: - 3 AIM: To study NAND and NOR gates as Universal Gates. THEORY: Any Gate is a logic circuit with one output and one or more inputs. The output signal of any gate occurs only for certain combination of input signals. Different types of gates are used in the digital circuit. AND neither gate, OR gate, NOR gate, NAND gate, NOT gate are the basic logic gates. Some gates are the combination of above basic gates. Such gates can be prepared by using discrete components like diodes, transistors, and resisters but nowadays, different ICs are used to have different gates. A power supply of +5 V is used to give input. This supply is also used to drive ICs. When power supply to the input is 'ON' we can say that logic level is at '1' and when power supply to the input is 'OFF' the logic level is said to be at '0' level. NAND GATE: It is a sequence of series combination of AND gate and NOT gate, known as NAND gate. The output of NAND gate is at „0‟ level only when all the inputs are „1‟ level. In rest of all the conditions of inputs the output will be at level „1‟. IC 7400 can be used to get NAND gate. This IC has two input NAND gates, which are four in numbers. The truth table of NAND gate is given in the table. A

A'

A 0 0 1 1

NOT GATE USING NAND GATE

A

AB

(AB)' B AND GATE USING NAND GATE

A

OUTPUT 1 1 1 0

A+B

A' B

B 0 1 0 1

B'

OR GATE USING NAND GATE

NOR GATE: It is a sequence of series combination of OR gate and NOT gate. The output of NOR gate is at level „1‟ when all the inputs are at „0‟ level. In rest of all the conditions of inputs the output is at „0‟ level. IC 7402 can be used to get NOR gate. It neither has two input NOR gates, which are four in numbers. The truth table of NOR gate is given in table. A

A

A' NOT GATE USING NAND GATE

A+B

(A+B)' B OR GATE USING NAND GATE

A A' B

AB

A 0 0 1 1

B 0 1 0 1

OUTPUT 1 0 0 1

B'

AND GATE USING NAND GATE

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EQUIPMENTS REQUIRED: Trainer kit or Bread Board, Power Supply and LED‟s. COMPONENTS REQUIRED: -ICs 7400, 7402 -Hook up wires PROCEDURE: 1. Pull all switches at „0‟ position. 2. Switch ON the power supply. 3. Test the truth table of different gates by changing the position of inputs (i.e. „1‟ level means switch is ON & „0‟ level means switch is OFF) and check the level of output (if LED glows it is at level „1‟ and if LED doesn‟t glow output is at level „0‟). OBSERVATIONS:

CONCLUSION:

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EXPERIMENT NO.: - 4(A) AIM: To study the arithmetic function of addition by building Half Adder circuit using logic gates. THEORY: This experiment gives how computer does the function of addition. The addition of two numbers in binary which does no have “carry” is done by half adder circuit and the addition of two numbers in binary which have “carry” is done by full adder circuit. The half adder adds two-binary digit at a time. Fig. given below shows how to make half adder by using two logic gates namely AND gate and EX-OR gate. The truth table of EX-OR gate is as below: EX-OR Gate: A 0 0 1 1

B 0 1 0 1

OUTPUT 0 1 1 0

As shown in the following figure the output of AND gate is used as “carry” bit and the output of EX-OR gate is used as “sum” bit. There will be four distinct cases which are shown in following truth table.

A

Carry = A*B

B Sum = A+B

A 0 1 0 1

B Sum Carry 0 0 0 0 0 1 1 0 1 1 1 0

EQUIPMENT REQUIRED: -Trainer kit COMPONENTS REQUIRED: -ICs 7486, 7408. -Hook up wires. PROCEDURE: 1. Connect 5V DC power supply to input terminals. 2. Change the state of A & B (0 & 1) to get four states at output by changing the position of micro switch. Check the truth table of half adder. ( If LED glows it is High state and if it does not glow then it is Low state)

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OBSERVATIONS:

CONCLUSION:

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EXPERIMENT NO.: - 4(B) AIM: To study the arithmetic function of addition by building Full Adder circuit using logic gates. THEORY: This experiment gives how computer does the function of addition. The addition of two numbers in binary which does no have “carry” is done by half adder circuit and the addition of two numbers in binary which have “carry” is done by full adder circuit. Sometimes in addition of two binary numbers you may have a carry from one column to the next. So in the next column we have to add three digits. This is not possible by half adder circuit. This is carried by a circuit as shown in fig.1 which consists of two half adder circuits and an OR-gate. This is known as full adder circuit.

Figure: 1 : Full Adder As shown in figure.1 the output of AND gate is used at “carry” bit and the output of EX-OR gate is used as “sum” bit. There will be four distinct cases which are shown in following truth table. A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

CARRY 0 0 0 1 0 1 1 1

SUM 0 1 1 0 1 0 0 1

EQUIPMENT REQUIRED: -Trainer kit COMPONENTS REQUIRED: -ICs 7408, 7432, 7486. -Hook up wires.

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PROCEDURE: 1. Connect 5V DC power supply to input terminals. 2. Change the state of A & B (0 & 1) to get four states at output by changing the position of micro switch. Check the truth table of half adder. ( If LED glows it is High state and if it does not glow then it is Low state) OBSERVATIONS:

CONCLUSION:

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EXPERIMENT NO.: - 5(A) AIM: To Design Half-subtractor. THEORY: A combination circuit that performs the arithmetic subtraction of two bits is called half subtractor. In figure we assigns two symbols X and Y are two input variables and D (difference) and B (borrow) are two output variables. The truth table for half subtractor is shown in figure. D = x‟y + xy‟ =xy B = x y‟ The half subtractor consists of an X-OR gate and AND gate.

Figure: Half Subtractor EQUIPMENTS REQUIRED: -Trainer kit COMPONENTS REQUIRED:    

Connecting wires IC 7408 (AND gate) IC 7486 (X-OR gate) IC 7432 (OR gate)

PROCEDURE 1. Join the circuit as per circuit diagram. 2. Verify the truth-table.

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OBSERVATIONS:

CONCLUSION:

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EXPERIMENT NO.: - 5(B) AIM: To design Full-subtractor. THEORY: A combination circuit that performs the arithmetic subtraction of three bits is called full subtractor. In figure we assigns three symbols X, Y and Z are three input variables and D (difference) and B(borrow) are two output variables. The truth table for full subtractor is shown in figure. D=xyz B = x‟y + x‟z + yz The full subtractor consists of two half-subtractor and one OR gate.

Figure: Full Subtractor EQUIPMENTS REQUIRED: -Trainer kit COMPONENTS REQUIRED:    

Connecting wires IC 7408 (AND gate) IC 7486 (X-OR gate) IC 7432 (OR gate)

PROCEDURE: 1.Join the circuit as per circuit diagram. 2.Verify the truth table for full-subtractor.

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OBSERVATION:

CONCLUSION:

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EXPERIMENT NO.: - 6 AIM: To study the operation of multiplexer circuit. THEORY: A multiplexer is a MSI logic circuit capable of selecting single input bit from a number of different inputs and routing the selected bit to a single output. The bit selected is determined by the appropriate input address lines. For instant a multiplexer having three data select lines A, B, C is capable of selecting one of the eight possible input bits (i.e. D0 to D7). Here IC 74151 is used which is eight bit multiplexer. The connection diagram and truth table are shown in respective figures.

A

B

C Vcc

9 Strobe GND

10

11

7 8

Y

74LS151 5

Y'

16 12 13 14 15 1 2

6

3 4

I7 I6 I5 I4 I3 I2 I1 I0

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C X L L L L H H H H

INPUTS SELECT B A X X L L L H H L H H L L L H H L H H

OUTPUTS STROBE S H L L L L L L L L

Y L D0 D1 D2 D3 D4 D5 D6 D7

EQUIPMENT REQUIRED: -Trainer kit COMPONENTS REQUIRED: -ICs 74151. -Hook up wires. PROCEDURE: 1. 3. 4. 5.

Switch ON the power supply. Set inputs (D0 to D7) at high level or at low level as desired. Set STR to low level. Set three data select lines A, B, C at any value as per truth table ( say A = Low, B= High , C= Low i.e. 010 i.e. decimal 2 as per column no. 4) 6. Multiplexer will select D2 input at Y output terminal. 7. Check the truth table for different value of data select lines A, B, C mentioned in the truth table and checks the selected input Y appears at output. 8. If the level of strobe is changed to high level at any point, Y output will be only at low level irrespective of any position of A, B, C.

OBSERVATIONS:

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CONCLUSION:

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EXPERIMENT NO.: - 7 AIM: To study the operation of de-multiplexer circuit. THEORY: A demultiplexer is a MSI logic circuit capable of routing data from a single source to one of a number of possible destinations the data bits are applied at the enable inputs and they appear at an output specified by the address inputs A, B, C.

Here IC 74138 is used which decodes one of eight lines based upon the conditions at the three binary select inputs and the three enable inputs. The connection diagram and function table are shown below.

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A

B

1

16 15 14 13

74LS138

12 11 10 9

3 G2A

C

2

4

G2B

5

G1

6 8

ENABLE G1 G2 X H L X H L H L H L H L H L H L H L H L

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

7

INPUTS SELECT C B X X X X L L L L L H L H H L H L H H H H

Vcc

OUTPUTS A X X L H L H L H L H

Y0 H H L H H H H H H H

Y1 H H H L H H H H H H

Y2 H H H H L H H H H H

Y3 H H H H H L H H H H

Y4 H H H H H H L H H H

Y5 H H H H H H H L H H

Y6 H H H H H H H H L H

Y7 H H H H H H H H H L

EQUIPMENT REQUIRED: -Trainer kit COMPONENTS REQUIRED: -ICs 74138. -Hook up wires. PROCEDURE: 1. 2. 3. 4. 5. 6. 7. 8.

Switch ON the power supply. Set G1, G2A and G2B at low level. Set inputs C, B, A at low level. All output must be at high level ( i.e. all LED should glow - condition no.2) Set G1, G2A and G2B at high level & inputs C, B, A as it is i.e. at low level. All output must be at high level (i.e. all LED should glow – condition no.1) Set G1 at high level and G2A and G2B at low level. Set C, B, A at any different levels and check the outputs as per truth table, for example, if you adjust C, B, A to 0 1 0 , the output Y2 only will be low, others will be at high level – condition no.5.

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OBSERVATION:

CONCLUSION:

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EXPERIMENT NO.: - 8 AIM: To study R-S Flip flop circuit. THEORY: A multivibrator is a regenerative circuit with two active devices, designed so that one device conducts while the cuts off. Multivibrator can store binary numbers. So, it can perform essential functions like counting of pulsed, synchronizing arithmetic operations etc. Such type of circuit is known as Flip-Flop circuits.

R

R

Q

Q'

S

Q

Q'

S

The R-S Flip-Flop is another name of bi-stable multivibrator, one whose output is low or high, 0 or 1. This output can be changed to other state only with the help of an external input called „TRIGGER‟. Until the external input is applied, the original state of output remains unchanged indefinitely fig. no. 1 shows the circuit diagram of R-S flip-flop, which of two NOT gates and two NAND gates. This flip-flop has two inputs namely R and S (R=reset & S=set) and has outputs namely Q and Q‟, where Q‟ is always the complement of Q. The truth-table of this R-S flip-flop is as under. R

R Q

Q

Clock

Clock Q'

S

Q' S

R 0 0 1 1

S 0 1 0 1

Q Last state 1(Set) 0(Reset) 1 Forbidden

The first input condition in the truth-table is R=0 & S=0. Since 0 input has no effect on its output, the flipflop simply remains on its previous state i.e. Q remains unchanged. The second input condition of the truth-table is R=0 & S=1 forces the output to switch over to 1 i.e. at high level. Thus input at 1 level is said that the flip-flop has SET i.e. Q=1(naturally Q‟=0). The third input condition of the truth-table is R=1 & S=0 forces the output to switch over to 0 i.e. at low level. Thus input at 0 level is said that the flip-flop has RESET i.e. Q=0(naturally Q‟=1).

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The fourth input condition of the truth-table is R=1 & S=1 forces the output of both NAND gates to switch over to 0 i.e. at low level. In other words Q=Q‟+0 at the same time. This is nothing but violation of the basic definition of flip-flop that Q must complement of Q‟. This state is known as forbidden state. Generally it is agreed upon never to impose this input condition. EQUIPMENT REQUIRED: -Trainer kit COMPONENTS REQUIRED: -IC 7432 -Hook up wires. PROCEDURE: 1. Connect circuit as per the ckt. Diagram and give 5V DC power supply to input terminals. 2. Switch ON the power supply. 3. Change the state of R & S as per truth-table and note down the status of output at every stage as per truth-table. 4. Closely watch the output when R=S=1. OBSERVATIONS:

CONCLUSION:

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EXPERIMENT NO.: - 9 AIM: To study D Flip-Flop circuit. THEORY: A multivibrator is a regenerative circuit with two active devices, designed so that one device conducts while the cuts off. Multivibrator can store binary numbers. So, it can perform essential functions like counting of pulsed, synchronizing arithmetic operations etc. Such type of circuit is known as Flip-Flop circuits.

D

R Q Clock Q' S

The R-S Flip-Flop has two data input R & S. To store a high bit you need a high S. To store a low bit you need a high R. Generation of two signals to drive a Flip-Flop is a disadvantage in many applications. Further more the forbidden condition of both R=S=1 may occur inadvertently. This had led to change R-S Flip-Flop i.e. a Flip-Flop that needs only a single data input. This Flip-Flop is shown in figure. The truth-table of D Flip-Flop is as under: CLK 0 1 1

D X 0 1

Qn+1 On(Last state) 0(Reset) 1(Set)

This kind of Flip-Flop prevents the value of D from reaching the Q output until a clock occurs. In general D Flip-Flop is a bi-stable circuit whose D input is transferred to the output only after clock pulse is received.

EQUIPMENT REQUIRED: -Trainer kit COMPONENTS REQUIRED: -ICs 7400, 7432, 7408 -Hook up wires.

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PROCEDURE: 1. Connect circuit as per the circuit diagram. 2. Switch ON the power supplies for any condition of D and analyze the condition of output Q as per truth-table. 3. Set D=0 and apply clock pulse. Analyze the condition of output Q and verify with truth-table. 4. Set D=1 and apply clock pulse. Analyze the condition of output Q and verify with truth-table.

OBSERVATIONS:

CONCLUSION:

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EXPERIMENT NO.: - 10 AIM: To study JK Flip flop circuit. THEORY: A multivibrator is a regenerative circuit with two active devices, designed so that one device conducts while the cuts off. Multivibrator can store binary numbers. So, it can perform essential functions like counting of pulsed, synchronizing arithmetic operations etc. Such type of circuit is known as Flip-Flop circuits. JK flip-flop can be used to build a counter that counts the number of positive or negative clock edges driving its clock input. For the purpose of counting, the JK flip-flop is the ideal element to use. The fig. shows circuit diagram of JK flip-flop. The truth table is as under.

CLK X ↑ ↑ ↑

J 0 0 1 1

K 0 1 0 1

Q n+1 On (Last state) 0 (Reset) 1(Set) On‟(toggle)

When J & K both are at low state, both AND gate are disabled and so clock pulse has no effect i.e. Q retains its last value. When J=0 & K=1 upper gate is disable so there is no way to set the flip-flop. The only possibility is RESET. When Q is high, the power gate passes a RESET triggers as soon as the next positive clock edge arrives. This forces Q to become low. When J=1 & K=0, lower gate is disable so it is impossible to RESET the flip-flop. We can SET the flip-flop. When Q is low Q bar is high. Therefore the upper gate passes a SET trigger on the next positive clock edge. This drives Q into high state i.e. Q=1.When J=1 & K=1 then there is a forbidden state with RS flip flop i.e. it is impossible to SET or RESET the flip flop. If Q is high, the lower gate passes a RESET trigger on the next positive clock edge. On the other hand when Q is low the upper gate passes a SET trigger on the next positive clock edge. Either way Q changes to the complement of the last state. Therefore J=1 & K=1 means the flip flop will toggle on the next positive clock edge. The toggle means to switch to the opposite state. Thus by addition of clock and getting propagation delay, racing problem can be eliminated in JK flip flop.

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EQUIPMENT REQUIRED: -Trainer kit COMPONENTS REQUIRED: -IC 7400 (for clock) -IC 7432 (for RS flip flop) -IC 7486 (3- input AND gate) -Hook up wires. PROCEDURE: 1. Connect circuit as per the circuit diagram and give 5V DC power supply to input terminals. 2. Switch ON the power supply. 3. Change the state of J & K as per truth-table and note down the status of output at every stage as per truth-table. 4. Closely watch the output.

OBSERVATIONS:

CONCLUSION:

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EXPERIMENT NO.: - 11 AIM: To study Master-Slave JK Flip flop circuit. THEORY: One way to solve racing problem in JK flip flop is to use Master/slave JK flip flop circuit. This type of flipflop circuit is used mostly in counting devices. As shown in the figure there are two JK flip-flop one is Master and other is slave. Master is positively edge triggered and the slave is negatively edge triggered. Therefore the master responds to its J & K inputs before the slave. For example if J=1 & K=0 the master flip-flop SETS on positive edge of the applied clock pulse. The high output of master (y=1) drives the J input of slave. As slave is negative triggered flip-flop, on the negative edge of the clock pulse the slave flip-flop sets i.e. it follows master. Thus by any state of master will be copied by slave on negative edge of clock pulse. The change in output of master will be according to the level of J, K and positive edge of clock pulse applied. In short, if master Sets, the slave Sets and if Master Resets, the slave Resets. The 54LS74 and 74LS76 is a dual JK master/slave flip-flops widely used.

EQUIPMENT REQUIRED: -Trainer kit COMPONENTS REQUIRED: -IC 7473 (JK flip flop) -IC 7400 (for clock) -Hook up wires. PROCEDURE: 1. Connect circuit as per the circuit diagram and give 5V DC power supply to input terminals. 2. Switch ON the power supply. 3. Set J=1 & K=0 of master and press clock micro switch (keep on pressing so that only positive edge is applied). Observe the output of master Y=1 and Y bar =0. _____________________________________________________________________________________ VICT / EC DEPARTMENT Digital Logic Design PAGE : 28

4. Now release the micro switch so that negative edge of the clock is applied to slave. Observe that outputs of slave, they will be as per the outputs of master. 5. With different value of J & K of master repeat the above procedure and see that slave always follows master.

OBSERVATIONS:

CONCLUSION:

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EXPERIMENT NO.: - 12 AIM: Study of different modes of Shift Register. THEORY: A Register is a very important logical block in most of the digital systems. Registers are often used to store (momentarily) binary information which appears at the output of an encoding matrix. Similarly, they are often used to store (momentarily) binary data which are being decoded. Thus, registers form a very important link between the main digital system and the input/output channels. A register is nothing more than a group of flip-flops which can be used to store a binary number. There must be one flip-flop for each bit in the binary number. Naturally the flip-flop must be wired so that the binary number can be entered (shifted) into the register and possibly shifted out. A group of flip-flops wired to provide either or both of these functions is called a shift register. There are two methods for shifting binary information into a register. 1. Shifting the information into a register one bit at a time in a series fashion and leads to the development of a serial shift register. 2. Shifting all the bits into the register at the same time and leads to the development of a parallel shift register. Here we have used, IC74AS194. It is a Four-bit Bidirectional Universal Shift Register. These bi-directional shift register has four distinct modes of operation. 1. Parallel load. 2. Shift right. (In the direction Qa towards Qd) 3. Shift left. (In the direction Qd towards Qa) 4. Inhibit clock. (do nothing) Parallel shift mode: Synchronous parallel loading is accomplished by applying the four bits of data and taking both the control inputs, S0 and S1 high. The data are loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift Right mode: Shift right is accomplished synchronously with the rising edge of the clock pulse when S 0 is high and S1 is low. Serial data in this mode is entered at the shift right data input. Shift Left mode: When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the serial left input. Inhibiting mode: Clocking of the flip-flops is inhibited when both mode control inputs are low.

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EQUIPMENT REQUIRED: -Trainer kit PROCEDURE: A. Parallel in Parallel out: 1. 2. 3. 4.

Connect circuit as per the ckt. diagram and give 5V DC power supply to input terminals. Switch ON the power supply. As per the function table, first clear all the outputs, by keeping clear switch to low position. Now put the clear switch to high. Put S 0 and S1 switches both high. Set the input A,B,C,D to desire level a,b,c,d [i.e. 1010] and then give a clock; all the outputs are a,b,c,d [i.e. 1010, same as input] means this is a parallel shift register. 5. Check for other inputs.

B. Serial Right (SISO): 1. Switch ON the power supply. 2. As per the function table, first clear all the outputs, by keeping clear switch to low position. 3. Now put switch S1 to low, S0 to high and serial Right input switch to High position. 4. Then apply a clock pulse. 5. Data will shift from Qa to Qd i.e. serial right.

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C. Serial Left (SISO): 1. As per the function table, first clear all the outputs, by keeping clear switch to low position. 2. Now put switch S1 to high, S0 to low and serial Left input switch to High position. 3. Then apply a clock pulse. 4. Check for other inputs. 5. Data will shift from Qd to Qa i.e. serial left. D. Inhibiting Mode: 1. Put switch S1 and S0 to low, observe that now clock is inhibited. i.e. applying the clock pulse does not change the ouptput. OBSERVATIONS:

CONCLUSION:

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EXPERIMENT NO.: - 13 AIM: To study the function of Decade Counter. THEORY: A counter is probably one of the most useful and versatile subsystems in a digital system. A counter driven by a clock can be used to count the number of clock cycles. Since the clock pulse occurs at known interval the counter can be used as an instrument to measure time and frequency. Any counter consists of a number of Flip-Flops. Each flip-flop is triggered by the previous flip-flop is and thus the time has a cumulative settling time. A decade counter can be constructed by using the MOD-5 and Mod-2 counters. This still has ten discrete states. The counter counts in a straight binary sequence from 0000 to 0001 and then back to 0000. Decade counter IC 74LS90 is used for this purpose. A switch circuit is used to give clock pulse to this IC. The pin diagram of IC 74LS90 is given. The truth table of decade counter is shown as below. To display the output we have used seven segments display. So to convert the Binary output of 74LS90 to seven segments, a BCD to seven segment decoder IC 7447 is used. Seven segment display LT-542A is used, which is a common anode LED type display.

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Truth Table: Count 0 1 2 3 4 5 6 7 8 9

Qa L L L L L L L L H H

OUTPUT VOLTAGE Qb Qc Qd L L L L L H L H L L H H H L L H L H H H L H H H L L L L L H

Equipment Required: -Trainer kit COMPONENTS REQUIRED: -IC 7400 (for switching circuit with socket) -IC 7490 (Decade counter with socket) -IC 7447 (BCD to seven segment with socket) -Seven segment display LT 542 A. PROCEDURE: 1. Connect circuit as per the circuit diagram and give 5v dc power supply to input terminals. 2. Switch ON the power supply. 3. Apply clock pulse one by one and check the output on the display. 4. At the end of every clock pulse, check the output Qa, Qb, Qc and Qd of IC 7490 it should be as per the truth table. OBSERVATIONS:

CONCLUSION:

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