8

6

7

5

4

2

3

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

C

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

B

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

9 10 12 13 14 15 16 18 19 20 22 23 25 27 28 29 30 32 33 34 35 37 39 40 46 48 49 50 51 52 53 54 55 56 58 60 61

TABLE_TABLEOFCONTENTS_ITEM

A

01/03/2013

TABLE_TABLEOFCONTENTS_ITEM

J44 08/12/2013

TABLE_TABLEOFCONTENTS_ITEM

J44 08/12/2013

TABLE_TABLEOFCONTENTS_ITEM

J44 08/12/2013

TABLE_TABLEOFCONTENTS_ITEM

J44 08/12/2013

TABLE_TABLEOFCONTENTS_ITEM

J44 08/12/2013

TABLE_TABLEOFCONTENTS_ITEM

J44 08/12/2013

TABLE_TABLEOFCONTENTS_ITEM

J44 08/12/2013

TABLE_TABLEOFCONTENTS_ITEM

J44 08/12/2013

TABLE_TABLEOFCONTENTS_ITEM

J44 08/12/2013

TABLE_TABLEOFCONTENTS_ITEM

J44 08/12/2013

TABLE_TABLEOFCONTENTS_ITEM

J44 08/12/2013

TABLE_TABLEOFCONTENTS_ITEM

J44 08/12/2013

TABLE_TABLEOFCONTENTS_ITEM

J44 08/12/2013

TABLE_TABLEOFCONTENTS_ITEM

J44 08/12/2013

TABLE_TABLEOFCONTENTS_ITEM

J44 08/12/2013

TABLE_TABLEOFCONTENTS_ITEM

J44 08/12/2013

TABLE_TABLEOFCONTENTS_ITEM

J44 MASTER

TABLE_TABLEOFCONTENTS_ITEM

MASTER MASTER

TABLE_TABLEOFCONTENTS_ITEM

MASTER 04/02/2013 J44_YONAS-4GB 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

64 65 66 70 71 72 73 74 75 76 77 78 80 81 83 95 97 100

m

8

J44

62 63

o

TABLE_TABLEOFCONTENTS_ITEM

7

TABLE_TABLEOFCONTENTS_ITEM

.c

TABLE_TABLEOFCONTENTS_ITEM





DESCRIPTION OF REVISION

CK APPD

102 103 104 110 111 112 113 114 115 116 117 118

120





D

Date

Contents AUDIO:CODEC, ANALOG AUDIO:CODEC, DIGITAL AUDIO: SPEAKER AMP AUDIO: JACK AUDIO: JACK TRANSLATORS DC-In & Battery Connectors PBus Supply & Battery Charger CPU VR12.6 VCC Regulator IC CPU VR12.5 VCC Power Stage 1.35V DDR3 SUPPLY 5V / 3.3V Power Supply 1.05V S0 Power Supply LCD AND KBD BKLT DRIVER Misc Power Supplies Power FETs Power Control eDP Display Connector RIO Connector Display Mux: HDMI vs DP Power Aliases Signal Aliases Memory Bit/Byte Swizzle Functional / ICT Test PCB Rule Definitions CPU & PCIe Constraints USB Constraints PCH Constraints Memory Constraints TBT,DP,HDMI Constraints Camera Constraints SMC Constraints Project Specific Constraints Reference

x

TABLE_TABLEOFCONTENTS_ITEM

6

TABLE_TABLEOFCONTENTS_HEAD

Page 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

a

TABLE_TABLEOFCONTENTS_ITEM

5

08/20/2013

in

TABLE_TABLEOFCONTENTS_ITEM

4

01/13/2012 D2_KEPLER

h

TABLE_TABLEOFCONTENTS_ITEM

ECN

Sync 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44

C

08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 MASTER MASTER 01/03/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 01/03/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44

TABLE_TABLEOFCONTENTS_ITEM

B

.c

TABLE_TABLEOFCONTENTS_ITEM

3

(.csa)

Sync

w

TABLE_TABLEOFCONTENTS_ITEM

2

w

TABLE_TABLEOFCONTENTS_ITEM

1

Date

Contents Table of Contents BOM Configuration BOM Configuration PD Parts CPU GFX/NCTF/RSVD CPU Misc/JTAG/CFG/RSVD CPU DDR3/LPDDR3 Interfaces CPU/PCH POWER CPU/PCH GROUNDS CPU Decoupling PCH Decoupling PCH Audio/JTAG/SATA/CLK PCH PM/PCI/GFX PCH PCIe/USB/LPC/SPI/SMBus PCH GPIO/MISC/LPIO CPU/PCH Merged XDP Chipset Support Project Chipset Support DDR3 VREF MARGINING DDR3 SDRAM Bank A (Rank 0) DDR3 SDRAM BANK B (RANK 0) DDR3 Termination Thunderbolt Host (1 of 2) Thunderbolt Host (2 of 2) Thunderbolt Mobile Support Thunderbolt Connector A Thunderbolt Connector B DDC Crossbar WIRELESS SUPPORT SSD Connector Camera 1 of 2 Camera 2 of 2 External A USB3 Connector KEYBOARD/TRACKPAD (1 OF 2) KEYBOARD/TRACKPAD (2 OF 2) SMC SMC Shared Support SMC Project Support SMBus Connections Power Sensors: High Side Power Sensors: Load Side Power Sensors: Extended Thermal Sensors Fan LPC+SPI Debug Connector

w

TABLE_TABLEOFCONTENTS_ITEM

Page 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

fi

(.csa)

TABLE_TABLEOFCONTENTS_HEAD

REV

DATE

J44 MLB-4GB SCHEMATIC 08/20/2013 D

1

ALIASES RESOLVED

A DRAWING TITLE

DRAWING NUMBER

Apple Inc. R

Schematic / PCB #’s

NOTICE OF PROPRIETARY PROPERTY:

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

051-0052

1

SCHEM,MLB-4GB,J44

SCH

CRITICAL

820-3536

1

PCBF,MLB-4GB,J44

PCB

CRITICAL

8

7

BOM OPTION

6

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

1 OF 120 SHEET

1 OF 78

1

8

7

6

5

4

2

3

1

BOM Groups TABLE_BOMGROUP_HEAD

BOM GROUP

BOM OPTIONS TABLE_BOMGROUP_ITEM

ALTERNATE,COMMON,J44_COMMON1,J44_COMMON2,J44_COMMON3,J44_COMMON4,J44_PROGPARTS

J44_COMMON

TABLE_BOMGROUP_ITEM

J44_COMMON1

TBTHV:P15V,SKIP_5V3V3:AUDIBLE,SPI:DUAL_IO

J44_COMMON2

EDP,EDP_LS_CAP,CAMERA_3V3:S0,CAM_WAKE:NO,CAM_XTAL:NO,MEM_ODT:PU,VCORE_FETS

J44_COMMON3

XDP,LPCPLUS,BKLT:PROD,CPUTHRM:ALRT,LOADRC:NO,OTHERRC:NO,DDRRC:NO,TBTRC:NO,BMONRC:NO

TABLE_BOMGROUP_ITEM

D

D

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

SMC_PROG:PVT,BOOTROM:PVT,TBTROM:PVT,TPAD_PSOC:PROG

J44_PROGPARTS

Programmables (All Builds)

TABLE_BOMGROUP_ITEM

LOADISNS,OTHERISNS,DDRISNS,TBTISNS,BMONISNS

ENGISNS

TBT PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

BOM OPTION

1

EPROM,FALCON RIDGE (V13.7) J44

U2890

CRITICAL

TBTROM:PVT

1

IC,SMC-B1,EXT(V2.16F39),PVT,J44

U5000

CRITICAL

SMC_PROG:PVT

1

IC,EFI ROM (V0116),PVT,J44

U6100

CRITICAL

BOOTROM:PVT

U4801

CRITICAL

TPAD_PSOC:PROG

m

341S3918

.c

341S3922

o

SMC

Module Parts CRITICAL

HSWULT,SR18A,PRQ,C0,2.4,28W,2+3,3M,BGA

U0500

CRITICAL

CPU_HSW:2.4G

337S4597

1

HSWULT,SR189,PRQ,C0,2.6,28W,2+3,3M,BGA

U0500

CRITICAL

CPU_HSW:2.6G

337S4598

1

HSWULT,SR188,PRQ,C0,2.8,28W,2+3,4M,BGA

U0500

CRITICAL

CPU_HSW:2.8G

338S1247

1

IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288

U2800

CRITICAL

338S1186

1

IC,BCM15700A2,S2 PCIE CAMERA PROCESSOR

U3900

CRITICAL

376S1194

2

MOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN

Q7310,Q7320

CRITICAL

VCORE_FET:VSHY

376S1193

2

MOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN

Q7311,Q7321

CRITICAL

VCORE_FET:VSHY

376S0964

2

MOSFET,N-CH,25V,30A,9.6M,8P 3.3X3.3 DFN

Q7310,Q7320

CRITICAL

VCORE_FET:REN

376S1104

2

MOSFET,N-CH,25V,30A,6.1M,8P 3.3X3.3 DFN

Q7311,Q7321

CRITICAL

VCORE_FET:REN

EFI ROM

BOM OPTION

341S3924

C

x

REFERENCE DES

1

PSOC 341S3862

fi

QTY

in

C

DESCRIPTION

337S4596

1

IC,TRKPD/KYBD PSOC,CU ONLY(V224) J44

a

PART NUMBER

Alternate Parts TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

376S1053

376S0604

ALL

128S0311

128S0329

ALL

138S0739

138S0706

ALL

COMMENTS: TABLE_ALT_ITEM

Diodes alt to Fairchild

h

TABLE_ALT_ITEM

NEC alt to Sanyo TABLE_ALT_ITEM

Samsung alt to Murata TABLE_ALT_ITEM

197S0481

197S0480

ALL

152S0461

152S1645

ALL

376S1080

376S0820

ALL

Epson alt to NDK TABLE_ALT_ITEM

.c

B

Cyntec alt to Vishay

B

TABLE_ALT_ITEM

Diodes alt to On Semi TABLE_ALT_ITEM

155S0667

155S0583

ALL

138S0725

138S0724

ALL

Panasonic alt to TDK TABLE_ALT_ITEM

Samsung alt to Murata TABLE_ALT_ITEM

376S1032

376S0855

ALL

376S1129

376S0855

ALL

376S1089

376S1128

ALL

353S3452

353S1286

ALL

376S1180

376S0761

ALL

128S0364

128S0264

ALL

107S0254

107S0241

ALL

Toshiba alt for Diodes Dual

w

TABLE_ALT_ITEM

NXP Alt for Diodes Dual TABLE_ALT_ITEM

NXP Alt for Diodes Single TABLE_ALT_ITEM

Maxim alt to Microchip

w

TABLE_ALT_ITEM

Renesas alt to Vishay TABLE_ALT_ITEM

Sanyo 2nd Factory alt TABLE_ALT_ITEM

Cyntec alt to TFT

w

TABLE_ALT_ITEM

138S0843

138S0674

ALL

138S0803

138S0639

ALL

138S0846

138S0811

ALL

197S0542

197S0544

ALL

197S0545

197S0544

ALL

152S1876

152S1804

ALL

107S0255

107S0240

ALL

107S0250

107S0248

ALL

127S0164

127S0162

ALL

353S4070

353S4069

ALL

353S4068

353S4069

ALL

353S3814

353S3812

ALL

Samsung alt to Murata (BKLT) TABLE_ALT_ITEM

Samsung alt to Murata (BKLT) TABLE_ALT_ITEM

Samsung alt to Murata (BKLT) TABLE_ALT_ITEM

NDK alt to TXC TABLE_ALT_ITEM

Epson alt to TXC TABLE_ALT_ITEM

TDK alt to Toko TABLE_ALT_ITEM

A

Cyntec alt to TFT TABLE_ALT_ITEM

Cyntec alt to TFT

SYNC_MASTER=J44

SYNC_DATE=08/20/2013

PAGE TITLE

TABLE_ALT_ITEM

BOM Configuration

Rohm alt to Vishay TABLE_ALT_ITEM

Pericom alt to TI DP Mux U9750

DRAWING NUMBER

TABLE_ALT_ITEM

Apple Inc.

NXP alt to TI DP Mux U9750 TABLE_ALT_ITEM

311S0649

311S0541

ALL

128S0436

128S0392

ALL

ONsemi alt to Toshiba TABLE_ALT_ITEM

8

7

6

5

4

R

TI alt to NXP TABLE_ALT_ITEM

Kemet alt to Sanyo

3

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

2

SIZE

D REVISION

BRANCH

PAGE

2 OF 120 SHEET

2 OF 78

1

A

8

7

6

5

4

2

3

1

BOM Variants DEVELOPMENT/BASE BOM TABLE_BOMGROUP_HEAD

BOM NUMBER

BOM NAME

BOM OPTIONS

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

685-0054

1

J44 MLB COMMON BOM

BASE

CRITICAL

BOM OPTION BASE_BOM

985-0053

1

J44 MLB DEVEL BOM

DEVEL

CRITICAL

DEVEL_BOM

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

BOM OPTION

1

VCORE,FET,VSHY,J44

VCOREFETS

CRITICAL

VCORE_FETS

TABLE_BOMGROUP_ITEM

685-0054

COMMON,MLB-4GB,J44

J44_COMMON TABLE_BOMGROUP_ITEM

985-0053

DEV,MLB-4GB,J44

XDP_CONN TABLE_BOMGROUP_ITEM

639-4878

PCBA,MLB-4GB,2.4G,4GB-HYNIX,J44

639-4879

PCBA,MLB-4GB,2.4G,4GB-ELPIDA,J44

BASE_BOM,CPU_HSW:2.4G,RAM_4G_ELPIDA,CAMDRAM:ELPIDA

639-4880

PCBA,MLB-4GB,2.4G,4GB-MICRON,J44

BASE_BOM,CPU_HSW:2.4G,RAM_4G_MICRON,CAMDRAM:MICRON

639-5272

PCBA,MLB-4GB,2.6G,4GB-HYNIX,J44

639-5273

PCBA,MLB-4GB,2.6G,4GB-ELPIDA,J44

BASE_BOM,CPU_HSW:2.6G,RAM_4G_ELPIDA,CAMDRAM:ELPIDA

639-5274

PCBA,MLB-4GB,2.6G,4GB-MICRON,J44

BASE_BOM,CPU_HSW:2.6G,RAM_4G_MICRON,CAMDRAM:MICRON

639-5275

PCBA,MLB-4GB,2.8G,4GB-HYNIX,J44

639-5276

PCBA,MLB-4GB,2.8G,4GB-ELPIDA,J44

BASE_BOM,CPU_HSW:2.4G,RAM_4G_HYNIX_H,CAMDRAM:HYNIX_H TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

D

SUB-BOMS

D

TABLE_BOMGROUP_ITEM

PART NUMBER

BASE_BOM,CPU_HSW:2.6G,RAM_4G_HYNIX_H,CAMDRAM:HYNIX_H TABLE_BOMGROUP_ITEM

685-0074 TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

Alternate Parts

BASE_BOM,CPU_HSW:2.8G,RAM_4G_HYNIX_H,CAMDRAM:HYNIX_H TABLE_BOMGROUP_ITEM

TABLE_ALT_HEAD

BASE_BOM,CPU_HSW:2.8G,RAM_4G_ELPIDA,CAMDRAM:ELPIDA

PART NUMBER

ALTERNATE FOR PART NUMBER

685-0075

685-0074

BOM OPTION

REF DES

COMMENTS:

ALL

RENESAS ALT TO VISHAY

TABLE_BOMGROUP_ITEM

639-5277

PCBA,MLB-4GB,2.8G,4GB-MICRON,J44

BASE_BOM,CPU_HSW:2.8G,RAM_4G_MICRON,CAMDRAM:MICRON

685-0074

VCORE,FET,VSHY,J44

VCORE_FET:VSHY

685-0075

VCORE,FET,REN,J44

VCORE_FET:REN

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

.c

o

m

TABLE_BOMGROUP_ITEM

fi

x

C

DRAM PARTS 333S0704

8

IC,SDRAM,4GBIT,256MX16,DDR3-1600,F DIE,96FBGA

U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560

CRITICAL

4G_ELPIDA

333S0700

8

IC,SDRAM,4GBIT,256MX16,DDR3-1600,HUMA,96FBGA

U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560

CRITICAL

4G_HYNIX_H

333S0698

8

IC,SDRAM,4GBIT,256MX16,DDR3-1600,REV E,96FBGA

U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560

CRITICAL

4G_MICRON

333S0715

8

IC,SDRAM,4GBIT,256MX16,DDR3-1866,F DIE,96FBGA

U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560

CRITICAL

4G_ELPIDA_1866

333S0717

8

IC,SDRAM,4GBIT,256MX16,DDR3-1866,HUMA,96FBGA

U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560

CRITICAL

4G_HYNIX_H_1866

333S0720

8

IC,SDRAM,4GBIT,256MX16,DDR3-1866,REV E,96FBGA

U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560

CRITICAL

4G_MICRON_1866

C

DRAM SPD Straps TABLE_BOMGROUP_HEAD

BOM GROUP

BOM OPTIONS

RAM_4G_ELPIDA

4G_ELPIDA,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L,PPDDR:1V35

RAM_4G_HYNIX_H

4G_HYNIX_H,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H,PPDDR:1V35

RAM_4G_MICRON

4G_MICRON,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L,PPDDR:1V35

RAM_4G_ELPIDA_1866

4G_ELPIDA_1866,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L,PPDDR:1V5

RAM_4G_HYNIX_H_1866

4G_HYNIX_H_1866,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H,PPDDR:1V5

RAM_4G_MICRON_1866

4G_MICRON_1866,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L,PPDDR:1V5

TABLE_BOMGROUP_ITEM

a

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

h

in

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

NOTE: 1866 PARTS BEING STRAPPED TO RUN AT 1600

13" MBP VARIABLE BOM GROUPS TABLE_BOMGROUP_HEAD

.c

B

BOM GROUP

BOM OPTIONS

J44_COMMON4

SMCBOARDID:8

B

w

w

TABLE_BOMGROUP_ITEM

DRAM SPD Straps

TABLE_BOMGROUP_HEAD

BOM OPTIONS CAMDRAM_TYPE:HYNIX_H

CAMDRAM:ELPIDA

CAMDRAM_TYPE:ELPIDA

CAMDRAM:MICRON

CAMDRAM_TYPE:MICRON

w

BOM GROUP CAMDRAM:HYNIX_H

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

A

SYNC_MASTER=J44

DRAM Parts PART NUMBER 333S0700

QTY 1

SYNC_DATE=01/03/2013

PAGE TITLE

DESCRIPTION IC,SDRAM,4GBIT,DDR3L-1600,HUMA,96B FBGA

REFERENCE DES

CRITICAL

U4000

CRITICAL

BOM Configuration

BOM OPTION

DRAWING NUMBER

CAMDRAM_TYPE:HYNIX_H

333S0704

1

IC,SDRAM,4GBIT,DDR3L-1600,DIE F,96B FBGA

U4000

CRITICAL

CAMDRAM_TYPE:ELPIDA

333S0698

1

IC,SDRAM,4GBIT,DDR3L-1600,REV E,96B FBGA

U4000

CRITICAL

CAMDRAM_TYPE:MICRON

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

3 OF 120 SHEET

3 OF 78

1

A

8

7

6

5

4

2

3

1

Shield Cans 1

1

SH0451

SH0450

SM

SM

SHLD-J44-MLB SHLD-J44-MLB-T29

USB Cage

D

TBT Cage

D

Mounting Holes & Slots OMIT

ZT0411 4P5R2P3-3P5B 1

ABOVE GUMSTICK CARD IN MIDDLE OF BOARD (998-1195)

OMIT 1

SNOWMAN-SHAPED SLOT AT LEFT OF MEMORY BANK (998-5879)

m

ZT0413 6.19X4.60-SNOWMAN

OMIT

ZT0414 6.19X4.60-SNOWMAN

SNOWMAN-SHAPED SLOT AT RIGHT OF MEMORY BANK (998-5879)

.c

o

1

TH0400 TH-NSP 1 SL-1.1X0.5-1.4x0.8

TH0403 TH-NSP 1 SL-1.1X0.5-1.4x0.8

Lower TBT can Ground slot (862-0118)

TH0404 TH-NSP TH0405 TH-NSP

USB can Ground slot (998-3975)

fi

1 SL-1.1X0.45-1.4x0.75

USB can Ground slot (998-3975)

1

C

x

C

Upper TBT can Ground slot (862-0118)

in

a

SL-1.1X0.45-1.4x0.75

SH0460

SH0461

2.9OD1.2ID-1.35H-SM

2.9OD1.2ID-1.35H-SM

1

1

2

2

h

Rubber Mount Standoffs (860-1448)

SH0462

SH0465

2.9OD1.2ID-1.35H-SM

2.9OD1.2ID-1.35H-SM

1

1

2

2

SH0463 2.9OD1.2ID-1.35H-SM

1

1

2

2

SH0420 1

SH0467 2.9OD1.2ID-1.35H-SM

1

1

2

2

FAN STANDOFF (806-5376)

SH0440

SH0441

5.0OD2.0H-SM

THERMAL-4.50-J44-SM

STDOFF-4.5OD1.73H-SM-1.33-3.2

1

1

SH0426

SH0427

THERMAL-4.50-J44-SM

THERMAL-4.50-J44-SM

w

SH0466 2.9OD1.2ID-1.35H-SM

SSD STANDOFF (806-5375)

SH0421

THERMAL-4.50-J44-SM

w

SH0464

w

THERMAL MODULE STANDOFF (860-1645) 2.9OD1.2ID-1.35H-SM

B

.c

B

1

1

POGO PINS (870-2451) SH0435 & SH0436 removed.

1

SH0432

SH0433

POGO-2.3OD-5.5H-SM-LOW-FORCE

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM 1

A

SM 1

RIO FLEX BRACKET BOSSES (860-2354) SH0443

SH0444

3.5OD2.0H-SM

3.5OD2.0H-SM

1

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

PD Parts DRAWING NUMBER

Apple Inc.

1 R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

4 OF 120 SHEET

4 OF 78

1

A

8

7

6

5

4

2

3

1

CRITICAL OMIT_TABLE

U0500 HASWELL-ULT 2C+GT2 BGA-TSP

SYM 1 OF 19

TBT Sink 0

OUT

74 23

OUT

74 23

OUT

74 23

OUT

74 23

OUT

74 23

OUT

74 23

OUT

74 23

OUT

66

TBT Sink 1 (MUXed with HDMI if necessary)

OUT

66

OUT

66

OUT

66

OUT

66

OUT OUT

66

OUT

66

OUT

C54

=DP_TBTSNK1_ML_C_N<0> =DP_TBTSNK1_ML_C_P<0> =DP_TBTSNK1_ML_C_N<1> =DP_TBTSNK1_ML_C_P<1> =DP_TBTSNK1_ML_C_N<2> =DP_TBTSNK1_ML_C_P<2> =DP_TBTSNK1_ML_C_N<3> =DP_TBTSNK1_ML_C_P<3>

C51

C55 B58 C58 B55 A55 A57 B57

C50 C53 B54 C49 B50 A53 B53

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3 DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

eDP Port Assignment: EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

C45

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

C47

DP_INT_ML_C_N<0> DP_INT_ML_C_P<0> DP_INT_ML_C_N<1> DP_INT_ML_C_P<1>

B46 A47 B47

DP_INT_ML_C_N<2> DP_INT_ML_C_P<2> DP_INT_ML_C_N<3> DP_INT_ML_C_P<3>

C46 A49 B49

OUT

62 74

OUT

62 74

OUT

62 74

OUT

62 74

OUT

62 74

OUT

62 74

OUT

62 74

OUT

62 74

D Internal panel

PPVCOMP_S0_CPU 1

EDP_AUXN EDP_AUXP

EDP_RCOMP EDP_DISP_UTIL

A45

DP_INT_AUXCH_C_N DP_INT_AUXCH_C_P

B45

D20

70

A43

MCP_EDP_RCOMP TP_EDP_DISP_UTIL

BI BI

62 74

8

R0530 24.9

62 74

2

1% 1/20W MF 201

.c

o

66

DP_TBTSNK0_ML_C_N<0> DP_TBTSNK0_ML_C_P<0> DP_TBTSNK0_ML_C_N<1> DP_TBTSNK0_ML_C_P<1> DP_TBTSNK0_ML_C_N<2> DP_TBTSNK0_ML_C_P<2> DP_TBTSNK0_ML_C_N<3> DP_TBTSNK0_ML_C_P<3>

m

D

74 23

DDI EDP

DDI Port Assignments:

MCP Daisy-Chain Strategy: CRITICAL OMIT_TABLE

Each corner of CPU has two testpoints. Other corner test signals connected in daisy-chain fashion. Continuity should exist between both TP’s on each corner.

U0500

C

x

HASWELL-ULT 2C+GT2 BGA-TSP

5

TP0531

TP

1

TP-P6

5 5

TP0501

TP

1

TP-P6

5 5

MCP_DC_AW2_AY2 MCP_DC_AW3_AY3 MCP_DC_AY60 MCP_DC_AW61_AY61 MCP_DC_AW62_AY62 MCP_DC_B2 MCP_DC_A3_B3 MCP_DC_A61_B61 MCP_DC_B62_B63

TRUE TRUE

AY2 AY3 AY60

TRUE TRUE

AY61 AY62 B2

TRUE TRUE TRUE

B3 B61 B62 B63

MCP_DC_C1_C2

TRUE

C1

A3

h

TRUE

A4

A61

TRUE

A62 AV1 AW1 AW2 AW3

AW61 AW62 AW63

MCP_DC_A3_B3 MCP_DC_A4

5

1

TP

TP-P6

A60

in

C2

C

NO_TEST

fi

5

SYM 17 OF 19 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

a

NO_TEST

TRUE TRUE TRUE TRUE

MCP_DC_A60 MCP_DC_A61_B61 MCP_DC_A62 MCP_DC_AV1 MCP_DC_AW1 MCP_DC_AW2_AY2 MCP_DC_AW3_AY3 MCP_DC_AW61_AY61 MCP_DC_AW62_AY62 MCP_DC_AW63

1 5

TP

TP-P6 1

TP

TP-P6 1

TP

TP-P6 1 5

TP

TP-P6

TP0500 TP0510 TP0511 TP0520 TP0521

5 5 5

1

TP

TP-P6

TP0530

CRITICAL OMIT_TABLE

U0500

.c

B

w

NC NC NC NC

BGA-TSP AT2 AU44 AV44 D15 F22 H22 J21

SYM 18 OF 19 SPARE RSVD RSVD RSVD RSVD RSVD RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

N23 R23 T23 U10 AL1 AM11 AP7 AU10 AU15 AW14 AY14

NC NC NC NC NC NC NC NC NC NC NC

w

w

NC NC NC

B

HASWELL-ULT 2C+GT2

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

CPU GFX/NCTF/RSVD DRAWING NUMBER

Apple Inc.

REVISION

R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

BRANCH

PAGE

5 OF 120 SHEET

5 OF 78

1

SIZE

D

A

8

7

6

5

4

2

3

1

CRITICAL OMIT_TABLE

U0500

D

D

HASWELL-ULT 2C+GT2 BGA-TSP

BI

OUT

CPU_CATERR_L

70 37

CPU_PECI

N62

BI

R0611 2

1

70

5% 1/20W MF 201

70 70

R0651

R0652

1

R0620

200

121

100

10K

1% 1/20W MF 201

1% 1/20W MF 201

1% 1/20W MF 201

5% 1/20W MF 201

2

2

J62

2

CATERR* PECI

(IPD) (IPU)

PROC_TCK PROC_TMS PROC_TRST*

E60

C61

1

66 22

OUT

AU60

CPU_SM_RCOMP<0> CPU_SM_RCOMP<1> CPU_SM_RCOMP<2>

AV60 AU61

AV15

MEM_RESET_HSW_L

PROCHOT*

PROC_TDI PROC_TDO

F63

BPM0* BPM1* BPM2* BPM3* BPM4* BPM5* BPM6* BPM7*

J60

17

OUT

CPU_MEMVTT_PWR_EN_LSVDDQ

XDP_CPU_TCK XDP_CPU_TMS XDP_CPUPCH_TRST_L

E61 E59

OUT

16 70

IN

16 70

IN

16 70

IN

16 70

IN

12 16 70

IN

16 70

OUT

16 70

THERMAL

PROCPWRGD

(IPU)

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST*

(IPU) (IPU) (IPU) (IPU) (IPU) (IPU)

AV61

XDP_CPU_PRDY_L XDP_CPU_PREQ_L

K62

SM_PG_CNTL1

(IPU) (IPU)

2

XDP_CPU_TDI XDP_CPU_TDO

F62

XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>

H60 H61 H62 K59 H63 K60 J61

BI

16 70

BI

16 70

BI

16 70

BI

16 70

BI

16 70

BI

16 70

BI

16 70

BI

16 70

.c

R0650

1

K63

CPU_PROCHOT_R_L CPU_PWRGD

70

1

PRDY* PREQ*

(IPU)

(IPU)

56

CPU_PROCHOT_L

PROC_DETECT*

PWR JTAG

70 53 37 36

2

70 36

K61

MISC

62 5% 1/20W MF 201

D61

(IPU)

R0610 1

m

NC

SYM 2 OF 19

o

PP1V05_S0

DDR3

61 60 57 53 37 17 16 15 11 8 68 65

PLACE_NEAR=U0500.AU60:12.7mm PLACE_NEAR=U0500.AV60:12.7mm PLACE_NEAR=U0500.AU61:12.7mm PLACE_NEAR=U0500.C61:12.7mm

C

BI

70 16

BI

70 16

BI

70 16 6

BI

70 16

BI

70 16

BI

70 16

BI

70 16 6

BI

70 16 6

BI

70 16 6

BI

70 16

BI

AC60 AC62 AC63 AA63 AA60 Y62

h

70 16 6

CPU_CFG<0> CPU_CFG<1> CPU_CFG<2> CPU_CFG<3> CPU_CFG<4> CPU_CFG<5> CPU_CFG<6> CPU_CFG<7> CPU_CFG<8> CPU_CFG<9> CPU_CFG<10> CPU_CFG<11> CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15>

= = = = = =

NORMAL OPERATION VR SUPPORTS SVID NORMAL OPERATION DISABLED NORMAL OPERATION NORMAL OPERATION

0 0 0 0 0 0

= = = = = =

POWER FEATURES NOT ACTIVE VR DOES NOT SUPPORT SVID NOA ALWAYS UNLOCKED ENABLED PCH-LESS MODE STALL AFTER PCU PLL LOCK

w

1 1 1 1 1 1

Y61 Y60 V62 V61

NOSTUFF

HSW_PRE_ES2

R0640 1

1

1K 5% 1/20W MF 201

NOSTUFF

R0638 1

R0639 1K

2

2

NOSTUFF 1

1K

5% 1/20W MF 201

5% 1/20W MF 201

2

2

R0631

6 16 70 6 16 70 6 16 70

w

6 16 70

1K

5% 1/20W MF 201

5% 1/20W MF 201

2

BI

70 16

BI

70 16

BI

70 16

BI

70 16

BI

70 16

U60 T63 T62 T61 T60 AA62

CPU_CFG<16> CPU_CFG<18> CPU_CFG<17> CPU_CFG<19>

BI

U63 AA61 U62 V63

NC NC NC NC NC PCH_TD_IREF

R0680 1

1

49.9

R0630

1K

BI

70 16

6 16 70

NOSTUFF 1

BI

70 16

V60

CPU_CFG_RCOMP

These can be placed close to J1800 and are only for debug access CPU_CFG<10> CPU_CFG<9> CPU_CFG<8> CPU_CFG<1> CPU_CFG<0>

70 16

w

CFG<10>:SAFE MODE BOOT CFG<9> :NO SVID-CAPABLE VR CFG<8> :ALLOW NOA ON LOCKED UNITS CFG<4> :eDP ENABLE/DISABLE CFG<1> :PCH-LESS MODE CFG<0> :RESET SEQUENCE STALL

A

BI

.c

B

70 16 6

in

a

fi

x

C

1% 1/20W MF 201

A5 E1 D1 J20 H18 B12

CRITICAL OMIT_TABLE

U0500 HASWELL-ULT 2C+GT2 BGA-TSP

CFG0 (IPU) CFG1 (IPU) CFG2 (IPU) CFG3 (IPU) CFG4 (IPU) CFG5 (IPU) CFG6 (IPU) CFG7 (IPU) CFG8 (IPU) CFG9 (IPU) CFG10 (IPU) CFG11 (IPU) CFG12 (IPU) CFG13 (IPU) CFG14 (IPU) CFG15 (IPU) CFG16 CFG18 CFG17 CFG19

SYM 19 OF 19 RESERVED

RSVD_TP RSVD_TP

AV63

RSVD_TP RSVD_TP

C63

EDP_SPARE

B43

RSVD_TP RSVD_TP

A51

RSVD_TP

TP_MCP_RSVD_C63 TP_MCP_RSVD_C62

C62

NC

B51

TP_MCP_RSVD_A51 TP_MCP_RSVD_B51

L60

TP_MCP_RSVD_L60

RSVD

N60

RSVD RSVD

W23 Y22

(IPU) (IPU)

TP_MCP_RSVD_AV63 TP_MCP_RSVD_AU63

AU63

PROC_OPI_COMP

AY15

RSVD RSVD

AV62

B

NC NC NC 70

CPU_OPI_RCOMP

(IPU) (IPU)

CFG_RCOMP RSVD RSVD RSVD RSVD RSVD TD_IREF

D58

VSS VSS

P22

RSVD RSVD

P20

1

NC NC

R0690 49.9

2

1% 1/20W MF 201

N21

R20

NC NC

R0685 8.25K

2

2

1% 1/20W MF 201

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

CPU Misc/JTAG/CFG/RSVD DRAWING NUMBER

CPU_CFG<4>

6 16 70

Apple Inc.

EDP 1

R



R0634 NOTICE OF PROPRIETARY PROPERTY:

1K

2

REVISION

5% 1/20W MF 201

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

BRANCH

PAGE

6 OF 120 SHEET

6 OF 78

1

SIZE

D

A

7

6

5

4

CRITICAL OMIT_TABLE

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI BI

73 68 67

BI

73 68 67 20

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67 73 68 67

BI BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67 73 68 67

BI BI

73 68 67

BI

73 68 67

BI

73 68 67

B

BI

73 68 67

73 68 67

C

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56 AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51

SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3

AW36 AY36

AU43

MEM_A_CKE<0> NC_MEM_A_CKE1 MEM_A_CKE<2> NC_MEM_A_CKE<3>

AW43 AY42 AY43

OUT

20 22 73

73 68 67

BI

OUT

20 22 73

73 68 67

BI

OUT

66

73 68 67

OUT

66

73 68 67

BI

73 68 67

BI

20 22 73

73 68 67

BI

OUT

22

73 68 67

BI

OUT

66

73 68 67

BI

OUT

66

73 68 67

BI

OUT

73 68 67

SA_CS0* SA_CS1*

AP33

MEM_A_CS_L<0> NC_MEM_A_CS_L1

AR32

SA_ODT0

AP32

MEM_A_ODT_CPU0

SA_RAS* SA_WE* SA_CAS*

AY34

MEM_A_RAS_L MEM_A_WE_L MEM_A_CAS_L

CAB2 CAB1

CAB4 CAB6 CAA5

CAB9 CAB8 CAB5 RSVD1 RSVD2 CAA0 CAA2 CAA4 CAA3 CAA1 CAB7 CAA7 CAA6 CAB0 CAA9 CAA8

SA_BA0 SA_BA1 SA_BA2 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AW34 AU34

AU35

=MEM_A_BA<0> MEM_A_BA<1> =MEM_A_BA<2>

AV35 AY41

AU36

=MEM_A_A<0> =MEM_A_A<1> =MEM_A_A<2> =MEM_A_A<3> =MEM_A_A<4> =MEM_A_A<5> MEM_A_A<6> =MEM_A_A<7> =MEM_A_A<8> =MEM_A_A<9> =MEM_A_A<10> =MEM_A_A<11> =MEM_A_A<12> =MEM_A_A<13> =MEM_A_A<14> NC_MEM_A_A15

AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

OUT

73 68 67

BI

OUT

22

73 68 67

BI

73 68 67

BI

OUT

22 66

OUT

20 22 66 73

OUT OUT

73 68 67

BI

73 68 67

BI

73 68 67

BI

20 22 66 73

73 68 67

BI

20 22 66 73

73 68 67

BI

73 68 67

BI

OUT

66

73 68 67

BI

OUT

20 22 66 73

73 68 67

BI

OUT

66

73 68 67

BI

73 68 67

BI

OUT

66

73 68 67

BI

OUT

66

73 68 67

BI

OUT

66

73 68 67

BI

OUT

66

73 68 67

BI

OUT

66

73 68 67

OUT

66

73 68 67

BI

OUT

20 22 66 73

73 68 67

BI

OUT

66

73 68 67

AJ61

MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7>

AN61 AN58 AN55 AW57 AW53 AL42 AL49

SM_VREF_CA

AP49

SM_VREF_DQ0

AR51

SM_VREF_DQ1

AP51

CPU_DIMM_VREFCA CPU_DIMMA_VREFDQ CPU_DIMMB_VREFDQ

BI

66

73 68 67

BI

OUT

66

73 68 67 21

BI

OUT

66

73 68 67

BI

OUT

66

73 68 67

OUT

66

73 68 67

OUT

66

73 68 67

BI BI BI

OUT

66

73 68 67

BI

OUT

22

73 68 67

BI

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

20 67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67 73 68 67

BI BI

73 68 67

BI

73 68 67

BI

73 68 67

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

BI

OUT

73 68 67

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

BI

20 22 73

LPDDR3 CAB3

BI

BI

73 68 67

BI

73 68 67

BI

73 68 67 73 68 67

BI BI

73 68 67

BI

73 68 67

BI

BI

20 67 73

73 68 67

BI

67 73

73 68 67

BI

73 68 67

BI

OUT

19 73

OUT

19 73

OUT

19 73

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

AY31 AW31 AY29 AW29 AV31 AU31 AV29 AU29 AY27 AW27 AY25 AW25 AV27 AU27 AV25 AU25 AM29 AK29 AL28

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25 AL25 AY23 AW23 AY21 AW21 AV23 AU23 AV21 AU21 AY19 AW19 AY17 AW17 AV19 AU19 AV17 AU17 AR21 AR22 AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20 AM20 AR18 AP18

U0500 HASWELL-ULT 2C+GT2 BGA-TSP

SYM 4 OF 19

SB_CK0* SB_CK0 SB_CK1* SB_CK1

AM38

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

AY49

SB_CS0* SB_CS1*

AM32

MEM_B_CLK_N<0> MEM_B_CLK_P<0> NC_MEM_B_CLKN<1> NC_MEM_B_CLKP<1>

OUT

21 22 73

OUT

21 22 73

OUT

66

OUT

66

OUT

21 22 73

OUT

22

OUT

66

OUT

66

MEM_B_CS_L<0> NC_MEM_B_CS_L1

OUT

21 22 73

OUT

22

SB_ODT0

AL32

MEM_B_ODT_CPU0

OUT

22 66

SB_RAS* SB_WE* SB_CAS*

AM35

MEM_B_RAS_L MEM_B_WE_L MEM_B_CAS_L

OUT

21 22 66 73

OUT

21 22 66 73

OUT

21 22 66 73

SB_BA0 SB_BA1 SB_BA2

AL35

OUT

66

OUT

21 22 66 73

OUT

66

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

AP40

OUT

66

OUT

66

OUT

66

OUT

66

OUT

66

OUT

66

OUT

21 22 66 73

OUT

66

OUT

66

OUT

66

OUT

66

OUT

66

OUT

66

OUT

66

OUT

66

OUT

22

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

AW30

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AV30

AN38 AK38 AL38

AU50 AW49 AV50

AK32

MEM_B_CKE<0> NC_MEM_B_CKE1 MEM_B_CKE<2> NC_MEM_B_CKE<3>

D

LPDDR3 CAB3 CAB2 CAB1

CAB4 CAB6 CAA5

CAB9 CAB8 CAB5 RSVD3 RSVD4 CAA0 CAA2 CAA4 CAA3 CAA1 CAB7 CAA7 CAA6 CAB0 CAA9 CAA8

AK35 AM33

AM36 AU49

AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AV26 AN28 AN25 AW22 AV18 AN21 AN18

AW26 AM28 AM25 AV22 AW18 AM21 AM18

=MEM_B_BA<0> MEM_B_BA<1> =MEM_B_BA<2> =MEM_B_A<0> =MEM_B_A<1> =MEM_B_A<2> =MEM_B_A<3> =MEM_B_A<4> =MEM_B_A<5> MEM_B_A<6> =MEM_B_A<7> =MEM_B_A<8> =MEM_B_A<9> =MEM_B_A<10> =MEM_B_A<11> =MEM_B_A<12> =MEM_B_A<13> =MEM_B_A<14> NC_MEM_B_A15 MEM_B_DQS_N<0> MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7> MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7>

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

21 67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

21 67 73

BI

67 73

C

B

w

w

w

73 68 67

BI

AK61

MEM_A_CLK_N<0> MEM_A_CLK_P<0> NC_MEM_A_CLKN<1> NC_MEM_A_CLKP<1>

AV37

m

BI

73 68 67

SYM 3 OF 19

AU37

o

BI

73 68 67

AH60

SA_CLK0* SA_CLK0 SA_CLK1* SA_CLK1

BGA-TSP

.c

73 68 67

AH61

U0500 HASWELL-ULT 2C+GT2

x

BI

AK62

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

fi

BI

73 68 67

AK63

a

D

BI

73 68 67

AH62

in

73 68 67

AH63

MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

h

BI

.c

BI

73 68 67

1

CRITICAL OMIT_TABLE

MEMORY CHANNEL A

73 68 67

2

3

MEMORY CHANNEL B

8

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

CPU DDR3/LPDDR3 Interfaces DRAWING NUMBER

Apple Inc.

REVISION

R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

BRANCH

PAGE

7 OF 120 SHEET

7 OF 78

1

SIZE

D

A

8

7

6

5

4

2

3

HSW-ULT current estimates from Haswell Mobile ULT Processor EDS vol 1, doc #502406, v0.9. LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0. Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.

CRITICAL OMIT_TABLE

NC NC

L59 J58

AJ31 AJ33 AJ37 AN33

D

AP43 AR48 AY35 AY40

PPVCC_S0_CPU

AY44 AY50

R0860 PLACE_NEAR=U0500.C50:50.8mm PP1V05_S0

R0800

1

1

R0802

75

70 53

IN

R0810

2

CPU_VIDALERT_L

1

OUT

CPU_VIDSCLK

1

0

BI

NC NC

2

CPU_VCCSENSE_P TP_PPVCCIO_S0_CPU

5

PPVCOMP_S0_CPU MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

Max load: 300mA

2

70 70

70

CPU_VIDSOUT

R0812

R0802.2:

PLACE_NEAR=U0500.L63:2.54mm

0

R0810.2:

PLACE_NEAR=U0500.L62:38.1mm

R0800.2:

PLACE_NEAR=R0810.1:2.54mm

1

2

70 17 16

5% 1/20W MF 0201

C

IN

53 17

OUT

53 17

IN

x

16

fi B18

PP1V05_S0SW_PCH_VCCUSB3PLL 41mA Max PP1V05_S0SW_PCH_VCCSATA3PLL

VCCIO VCCIO VCCUSB3PLL

VCCASW VCCASW

Y20 AA21 W21

J13

VCCAPLL VCCAPLL VCCAPLL

DCPSUS3

AH14

PP1V5_S0SW_AUDIO_HDA

VCCHDA

11mA Max

AC9

59mA Max[1]

AA9

PP3V3_S5

AH10

114mA Max PP3V3_S0

V8 W9

40mA Max[1]

11

J18

PP1V05_S0_PCH_VCC_ICC VCCCLK: 200mA Max

12 11

57 53 37 17 16 15 11 8 6 68 65 61 60

PP1V05_S0_PCH_VCCACLKPLL 31mA Max PP1V05_S0

A20

VCCACLKPLL

T21

WF: RSVD on Sawtooth Peak rev 1.0

65 61 60 59 45 14 11 8

PP3V3_SUS 3.3mA Max[1]

VCC3 VCC3

VCC1P05 VCC1P05

R21

K18

NC NC NC

VCCDSW3_3

K19

J17

VCCCLK: 200mA Max

VCCSUS3 VCCSUS3

M20 V21

AE20 AE21

VCCCLK VCCCLK VCCCLK VCCCLK VCCCLK VCCCLK VCCSUS3 VCCSUS3

GPIO/LCC

PP3V3_SUS

DCPSUSBYP DCPSUSBYP

VRM/USB2/AZALIA DCPSUS2

VCCASW VCCASW VCCASW DCPSUS1 DCPSUS1 THERMAL SENSOR VCCTS1_5 VCC3 VCC3

8 11 14 45 59 60 61 65

AG14

PP1V05_S0

L63 B59 F60 C59 D63 H59

P60 P61 N59 N61

AG13

185mA Max[1]

J11

PP1V05_S0

H11

1499mA Max[1]

7

AD60 AD59 AA59 AE60 AC59 AG58 U59 V59

AC22 AE22

12 13 17 65

AE23

C0890

0.1UF

1UF

AD57

20% 10V CERM 402

20% 10V CERM 402

10% 6.3V CERM 402

0.1UF

1

2

20% 10V CERM 402

C0891

1

1

2

2

HSW ULT POWER

VCC RSVD RSVD VCC_SENSE

RSVD VCCIO_OUT VCCIOA_OUT RSVD RSVD RSVD VIDALERT* VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY VSS PWR_DEBUG* VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

PP1V05_S0

AG57 C24 C28

BYPASS=U0500.AG10:6.35mm BYPASS=U0500.AG10:6.35mm BYPASS=U0500.AG10:6.35mm

C32

VCCST VCCST VCCST VCC VCC VCC VCC VCC VCC

C36

8 10 42 54 65 68

32A Max

C40 C44 C48 C52 C56 E23 E25

D

E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25

C

G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57

B

6 8 11 15 16 17 37 53 57 60 61 65 68

H15 AE8 AF22

AG19 AG20

PP1V05_S0

AF9

473mA Max[1]

AG8

AD8

R0899 5.11

PPVOUT_S5_PCH_DCPSUSBYP_R MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

AE9

AD10

PLACE_NEAR=U0500.AG19:2.54mm

1

Powered in DeepSx

2 1% 1/20W MF-LF 201

PPVOUT_S5_PCH_DCPSUSBYP MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

1

C0899 1UF

6 8 11 15 16 17 37 53 57 60 61 65 68

2

10% 6.3V CERM 402

BYPASS=R0899:U0500:2.54mm

NC NC

J15

PP1V5_S0

K14

3mA Max PP3V3_S0

K16

1mA Max[1]

U8

PP3V3_S0

T9

17mA Max

47 59 60 61 63 65 68

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

VCCSDIO VCCSDIO SUS OSCILLATOR DCPSUS4

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

CPU/PCH POWER AB8

DRAWING NUMBER

NC

Apple Inc.

AC20

VCCIO VCCIO

AG16

PP1V05_S0

AG17

213mA Max[1]

NC



WF: RSVD on Sawtooth Peak rev 1.0

NOTICE OF PROPRIETARY PROPERTY:

6

REVISION

R

VCCAPLL

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

6 8 11 15 16 17 37 53 57 60 61 65 68

LPT LP POWER

8

T59

0.1UF

C0895

6 8 11 15 16 17 37 53 57 60 61 65 68

AE59

AB57

C0892 1

PP3V3_SUS

AA23

N63

???mA Max PPVRTC_G3H

SYM 12 OF 19

PPVCC_S0_CPU VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

SERIAL IO

ICC

77 68 65 64 62 61 50 47 46 28 24 18 17 15 13 12 11 8 44 43 42 41 40 39 38 37 30

AH13

VCC1P05 VCC1P05 VCC1P05 VCC1P05 VCC1P05

USB2

NC

56 29 27 26 18 17 16 15 13 11 77 68 65 61 60 59

Y8

AD23

L62

NC NC NC NC NC NC NC NC NC 60 57 53 37 17 16 15 11 8 6 68 65 61

.c

VCCSATA3PLL

AZALIA/HDA

65 61 60 59 45 14 11 8

PPVOUT_S0_PCH_DCPRTC

18mA Max

OPI

NC

NC 60 17 11

BYPASS=U0500.AE7:6.35mm

w

B11

57mA Max

A

VCCSPI

USB3

11

DCPRTC

AE7

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

42mA Max WF: RSVD on Sawtooth Peak rev 1.0 PP1V05_S0_PCH_VCCAPLL_OPI

AG10

2

CORE

B

12 11

P9

VCCRTC

w

14 11

PP1V05_S0 29mA Max[1]

BGA-TSP

SYM 13 OF 19

E20

TP_CPU_RSVD_P60 TP_CPU_RSVDP61 TP_CPU_RSVD_N59 TP_CPU_RSVDN61

18

8 11 14 45 59 60 61 65

0.3mA Max[1]

w

57 53 37 17 16 15 11 8 6 68 65 61 60

N8

PP3V3_SUS

A59

CPU_VIDALERT_R_L CPU_VIDSCLK_R CPU_VIDSOUT_R CPU_VCCST_PWRGD CPU_VR_EN CPU_VR_READY

a M9

VCCSUS3

HASWELL-ULT 2C+GT2

in

1838mA Max

VCCHSIO VCCHSIO VCCHSIO

AH11

h

L10

RTC

PP1V05_S0SW_PCH_HSIO

HSIO SPI

65 60 11

U0500

AB23

P62

18

CRITICAL OMIT_TABLE

NC

CPU_PWR_DEBUG

IN

AC58 E63

NC NC NC

NOTE: Aliases not used on CPU supply outputs to avoid any extraneous connections.

2

5% 1/20W MF 0201 70 53

Max load: 300mA

5% 1/20W MF 201

R0811 70 53

43

2

N58

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

130 1% 1/20W MF 201

F59

5% 1/20W MF 201

o

1% 1/20W MF 201

OUT

100

m

70 53

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

1

.c

60 57 53 37 17 16 15 11 8 6 68 65 61

HASWELL-ULT 2C+GT2 BGA-TSP

AH26

1.4A Max (DDR3: 1.5-1.35V) 1.1A Max (LPDDR3: 1.2V)

68 65 54 42 10 8

U0500

RSVD RSVD

PP1V35_S3_CPUDDR

73 65 41 10

K9

1

5

4

3

2

BRANCH

PAGE

8 OF 120 SHEET

8 OF 78

1

SIZE

D

A

7

6

5

4

CRITICAL OMIT_TABLE

CRITICAL OMIT_TABLE

U0500

U0500

U0500

HASWELL-ULT 2C+GT2

HASWELL-ULT 2C+GT2

BGA-TSP

BGA-TSP

A48 A52 A56 AA1 AA58 AB10 AB20 AB22 AB7 AC61 AD21 AD3 AD63 AE10 AE5 AE58 AF11 AF12 AF14 AF15 AF17 AF18

C

AG1 AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55

B

AH57 AJ13 AJ14 AJ23 AJ25 AJ27

AJ45

AP3

AJ47

AP31

AJ50

AP38

AJ52

AP39

AJ54

AP48

AJ56

AP52

AJ58

AP54

AJ60

AP57

AJ63

AR11

AK23

AR15

AK3

AR17

AK52

AR23

AL10

AR31

AL13

AR33

AL17

AR39

AL20

AR43

AL22

AR49

AL23

AR5

AL26

AR52

AL29

AT13

AL31

AT35

AL33

AT37

AL36

AT40

AL39

AT42

AL40

AT43

AL45

AT46

AL46

AT49

AL51

AT61

AL52

AT62

AL54

AT63

AL57

AU1

AL60

AU16

AL61

AU18

AM1

AU20

AM17

AU22

AM23

AU24

AM31

AU26

AM52

AU28

AN17

AU30

AN23

AU33

AN31

AU51

AN32

AU53 AU55

AN35

AU57

AN36

AU59

AN39

AV14

AN40

AV16

AN42

AV20

AN43

AV24

AN45

AV28

AN46

AV33

AN48

AV34

AN49 AN51

AV36

AN52

AV39

AN60 AN63 AN7 AP10 AP17

AV41 AV43 AV46 AV49 AV51 AV55

AP20

D35

AW24

D37

AW33

D38

AW35

D39

AW37

D41

AW4

D42

AW40

D43

AW42

D45

AW44

D46

AW47

D47

AW50

D49

AW51

D5

AW59

D50

AW60

D51

AY11 AY16 AY18 AY22

D53 D54 D55 D57

AY24

D59

AY26

D62

AY30 AY33

D8 E11

AY4

E17

AY51

F20

AY53 AY57 AY59 AY6 B20

F26 F30 F34 F38 F42

B24

F46

B26

F50

B28 B32

F54 F58

B36

F61

B4

G18

B40

G22

B44

G3

B48

G5

B52

G6

B56

G8

B60

H13

C11

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SYM 16 OF 19 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_SENSE VSS

H17 H57 J10 J22

D

J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10

C

V3 V7 W20 W22 Y10 Y59 Y63 V58 AH46 V23 E62

CPU_VCCSENSE_N 1

C14

R0960

C18

100

C20 C25

OUT

53 70

AH16

2

5% 1/20W MF 201

PLACE_NEAR=U0500.E62:50.8mm

C27 C38 C39 C57 D12 D14 D18 D2 D21

B

D23 D25 D26 D27 D29 D30 D31

w

w

w

AJ29

AP29

D34

m

A44

AJ43

AV8 AW16

o

A40

AP26

D33

.c

A36

AP23

AJ41

AV59

x

D

A32

AJ39

BGA-TSP

SYM 15 OF 19 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

fi

A28

AP22

in

A24

AJ35

h

A18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

.c

A14

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

1

CRITICAL OMIT_TABLE

HASWELL-ULT 2C+GT2 SYM 14 OF 19 A11

2

3

a

8

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

CPU/PCH GROUNDS DRAWING NUMBER

Apple Inc.

REVISION

R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

BRANCH

PAGE

9 OF 120 SHEET

9 OF 78

1

SIZE

D

A

8

7

6

5

4

2

3

1

All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 0.9 unless stated otherwise

CPU VCC Decoupling

2

D

CRITICAL

C1001

1

10UF

20% 4V X6S 0402

2

CRITICAL

C1002

1

10UF

20% 4V X6S 0402

2

1

10UF

20% 4V X6S 0402

2

NO STUFF

NO STUFF

CRITICAL

C1003 20% 4V X6S 0402

CRITICAL

CRITICAL 1

C1070

1

10UF 2

20% 4V X6S 0402

2

CRITICAL

C1085

1

10UF 2

2

1

20% 4V X6S 0402

2

1

10UF

2

1

10UF

20% 4V X6S 0402

2

20% 4V X6S 0402

2

1

10UF

20% 4V X6S 0402

2

1

2

C1020

1

C1021

20% 4V X6S 0402

2

20% 4V X6S 0402

1

10UF 2

20% 4V X6S 0402

2

20% 4V X6S 0402

NO STUFF CRITICAL

C1030

C1014

1

CRITICAL 1

10UF

NO STUFF

NO STUFF

CRITICAL 1

CRITICAL

C1012

C105A

CRITICAL 1

10UF 2

20% 4V X6S 0402

C105B

CRITICAL 1

10UF 2

20% 4V X6S 0402

1

2

NO STUFF

C104F

1

10UF

10UF

10UF

20% 4V X6S 0402

20% 4V X6S 0402

20% 4V X6S 0402

20% 4V X6S 0402

1

C1074

1

10UF

20% 4V X6S 0402

NO STUFF

2

1

C1088

1

2

C1089

1

2

CRITICAL 1

1

2

NO STUFF

C1046

1

1

2

20% 4V X6S 0402

20% 4V X6S 0402

2

C1028 20% 4V X6S 0402

C1092 20% 4V X6S 0402

1

20% 4V X6S 0402

1

C1032 20% 4V X6S 0402

2

C1033

2

C1095

1

2

CRITICAL 1

2

2

C1034

2

20% 4V X6S 0402

20% 4V X6S 0402

20% 4V X6S 0402

NO STUFF

1

CRITICAL

C1035 20% 4V X6S 0402

20% 4V X6S 0402

20% 4V X6S 0402

10UF 2

NO STUFF

20% 4V X6S 0402

D

C106E 10UF

2

20% 4V X6S 0402

NO STUFF

CRITICAL 1

10UF

2

2

C105F

C1084 10UF

2

NO STUFF

20% 4V X6S 0402

NO STUFF

C1097 20% 4V X6S 0402

NO STUFF

NO STUFF

1

10UF

2

C1083

CRITICAL 1

10UF

10UF

2

NO STUFF

1

1

NO STUFF

1

20% 4V X6S 0402

C105E

CRITICAL

NO STUFF

10UF

20% 4V X6S 0402

C1096

C1082 10UF

10UF

20% 4V X6S 0402

NO STUFF

10UF

C1049 10UF

2

1

NO STUFF 1

NO STUFF 1

20% 4V X6S 0402

CRITICAL

10UF

20% 4V X6S 0402

NO STUFF

10UF 2

C1094

CRITICAL

10UF 2

NO STUFF 1

10UF 2

20% 4V X6S 0402

NO STUFF

NO STUFF

C1029

C1093

CRITICAL

10UF 2

NO STUFF

1

CRITICAL 1

NO STUFF CRITICAL

10UF 2

10UF 2

C1048

1

NO STUFF 1

10UF

20% 4V X6S 0402

2

20% 4V X6S 0402

20% 4V X6S 0402

NO STUFF

NO STUFF

C1047 10UF

20% 4V X6S 0402

C1027

C1091

C1081 10UF

CRITICAL

10UF 2

10UF

20% 4V X6S 0402

2

1

NO STUFF

C1026 10UF

20% 4V X6S 0402

20% 4V X6S 0402

NO STUFF

NO STUFF

C1025

C1090

CRITICAL

10UF

20% 4V X6S 0402

2

1

NO STUFF

CRITICAL

10UF

20% 4V X6S 0402

CRITICAL

C1077 10UF

20% 4V X6S 0402

2

NO STUFF

CRITICAL

C1075

NO STUFF CRITICAL

2

NO STUFF

10UF

20% 4V X6S 0402

2

2

CRITICAL

CRITICAL

C1073

2

CRITICAL 1

CRITICAL

C106D

10UF

2

2

CRITICAL

20% 4V X6S 0402

C105D 10UF

20% 4V X6S 0402

10UF

2

1

10UF

CRITICAL

C104E

CRITICAL

C105C

20% 4V X6S 0402

10UF

20% 4V X6S 0402

2

CRITICAL 1

10UF

10UF

NO STUFF

C1045

20% 4V X6S 0402

C1011

20% 4V X6S 0402

10UF

NO STUFF

C1044

C1019

CRITICAL

CRITICAL 1

10UF

10UF

NO STUFF 1

10UF

20% 4V X6S 0402

1

NO STUFF

C1024

2

C1010

20% 4V X6S 0402

10UF 2

CRITICAL 1

10UF

C1036

NO STUFF 1

10UF 2

20% 4V X6S 0402

NO STUFF

C1037

1

10UF 2

C

C1038 10UF

20% 4V X6S 0402

2

20% 4V X6S 0402

20% 4V X6S 0402

a

2

1

20% 4V X6S 0402

NO STUFF 1

NO STUFF

C1039

C1087

20% 4V X6S 0402

C1009

10UF

CRITICAL

NO STUFF

C1023

C1018

CRITICAL

NO STUFF

10UF 2

10UF

NO STUFF 1

1

20% 4V X6S 0402

NO STUFF

C1022 10UF

2

C1086

NO STUFF

CRITICAL 1

2

CRITICAL

10UF

20% 4V X6S 0402

NO STUFF

C

20% 4V X6S 0402

CRITICAL 1

NO STUFF

10UF

NO STUFF

CRITICAL 1

1

10UF

2

CRITICAL

CRITICAL

C1072

C1008 10UF

20% 4V X6S 0402

2

CRITICAL

2

1

10UF

NO STUFF

1

CRITICAL

C1004

m

1

10UF

o

CRITICAL

C1000

.c

CRITICAL 1

x

PPVCC_S0_CPU

fi

68 65 54 42 8

Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff Apple implementation : 18x 22uF 0603 stuff, 80x 22uF 0603 nostuff

1

NO STUFF

C1058

1

NO STUFF

C1059

1

NO STUFF

C1062

1

C1063

10UF

10UF

20% 4V X6S 0402

20% 4V X6S 0402

20% 4V X6S 0402

2

2

NO STUFF

C109B

1

NO STUFF

C109C

1

10UF

20% 4V X6S 0402

2

2

NO STUFF

C109D

1

10UF

20% 4V X6S 0402

2

2

NO STUFF

C109E

1

10UF

20% 4V X6S 0402

2

2

1

10UF

20% 4V X6S 0402

2

2

NO STUFF

C109F

C108A

20% 4V X6S 0402

2

20% 4V X6S 0402

2.2UF 2

1

A

2

2

C1050

1

1

C1042

1

2.2UF

20% 6.3V CERM 402-LF

C1051

2

1

NO STUFF 1

C1069

NO STUFF 1

C1098

NO STUFF 1

10UF

10UF

10UF

20% 4V X6S 0402

20% 4V X6S 0402

20% 4V X6S 0402

20% 4V X6S 0402

2

C108D 20% 4V X6S 0402

2

NO STUFF 1

C108E

NO STUFF 1

10UF 2

20% 4V X6S 0402

2

C108F

NO STUFF 1

10UF 2

2

C107A

2

20% 4V X6S 0402

1

C109A 10UF

2

20% 4V X6S 0402

NO STUFF 1

10UF

20% 4V X6S 0402

2

NO STUFF

C1099

10UF

C107B 10UF

2

20% 4V X6S 0402

B

2

1

20% 6.3V CERM 402-LF

C1053

Added 2 extra 2.2uF per Harris Beach v0.9 schematic

1

C1054

10UF

10UF

10UF

10UF

20% 6.3V CERM-X5R 0402-1

20% 6.3V CERM-X5R 0402-1

20% 6.3V CERM-X5R 0402-1

20% 6.3V CERM-X5R 0402-1

20% 6.3V CERM-X5R 0402-1

2

CPU VCC Decoupling

2.2UF

20% 6.3V CERM 402-LF

C1052

C1043

10UF 2

C1068

20% 4V X6S 0402

10UF

2

NO STUFF 1

10UF

.c

C1041 2.2UF

20% 6.3V CERM 402-LF

20% 4V X6S 0402

C1067

20% 4V X6S 0402

NO STUFF 1

10UF 2

NO STUFF 1

10UF

w

1

C108C

C1066

w

20% 2.5V POLY-TANT SM

C1040

20% 4V X6S 0402

2

NO STUFF 1

10UF 2

C1031

Intel recommendation (Table 5-4): 2x 2.2uF 0402, 6x 10uF 0603 Apple implementation : 2x 2.2uF 0402, 6x 10uF 0402

1

C108B

NO STUFF 1

w

PP1V35_S3_CPUDDR

2

NO STUFF 1

10UF

CPU VDDQ DECOUPLING 73 65 41 8

C1065

10UF

20% 4V X6S 0402

470UF-0.0045OHM 2

CRITICAL 1

10UF

20% 4V X6S 0402

CRITICAL

3

C1064

10UF

20% 4V X6S 0402

B 1

NO STUFF 1

10UF

20% 4V X6S 0402

10UF 2

1

10UF

20% 4V X6S 0402

NO STUFF 1

NO STUFF

C1057

10UF

h

2

NO STUFF

C1056

in

NO STUFF 1

2

2

1

C1055 10UF

2

20% 6.3V CERM-X5R 0402-1

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

CPU Decoupling DRAWING NUMBER

Apple Inc.

NO STUFF 1

1

C1060 270UF

2

8

C1061 270UF

20% 2V TANT CASE-B2-SM

2

7

REVISION

R

1x Bulk nostuff, Harris Beach has 2x nostuff

NOTICE OF PROPRIETARY PROPERTY:

20% 2V TANT CASE-B2-SM

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

6

5

4

3

2

BRANCH

PAGE

10 OF 120 SHEET

10 OF 78

1

SIZE

D

A

8

7

56 29 27 26 18 17 16 15 13 8 77 68 65 61 60 59

6

PCH VCCDSW3_3 BYPASS (PCH 3.3V DSW PWR) PP3V3_S5

5

4

PCH VCC3_3 BYPASS (PCH 3.3V GPIO/LPC PWR) 50 PP3V3_S0 8

60 57 53 37 17 16 15 11 8 6 68 65 61

77 68 65 64 62 61 30 28 24 18 17 15 13 12 11 47 46 44 43 42 41 40 39 38 37

PCH VCCASW BYPASS (PCH 1.05V ME CORE PWR) PP1V05_S0 60 57 53 37 17 16 15 11 8 6 68 65 61

NO STUFF

C1200

2

3

1

PCH VCCIO BYPASS (PCH 1.05V USB2 PWR) PP1V05_S0

NO STUFF 1

C1212

1

C1250

1

1

C1251

C1264

1UF

22UF

22UF

1UF

1UF

10% 6.3V CERM 402

20% 6.3V X5R-CERM-1 603

20% 6.3V X5R-CERM-1 603

10% 6.3V CERM 402

10% 6.3V CERM 402

2

BYPASS=U0500.AH10:6.35mm

2

2

2

BYPASS=U0500.V8:12.7mm

1

2

BYPASS=U0500.AG16:6.35mm BYPASS=U0500.AE9:12.7mm BYPASS=U0500.AE9:6.35mm

65 61 60 59 45 14 11 8

PCH VCC3_3 BYPASS (PCH 3.3V THERMAL PWR) 50 PP3V3_S0 8

77 68 65 64 62 61 30 28 24 18 17 15 13 12 11 47 46 44 43 42 41 40 39 38 37

NO STUFF

C1202

60 57 53 37 17 16 15 11 8 6 68 65 61

1

C1214

0.1UF

0.1UF

20% 10V CERM 402

20% 10V CERM 402

2

BYPASS=U0500.Y8:6.35mm

65 61 60 59 45 14 11 8

PCH VCC BYPASS (PCH 1.05V CORE PWR) PP1V05_S0

C1255

2

1

22UF

65 60 11 8

1

C1257

C1266

1UF

10% 6.3V CERM 402

10% 6.3V CERM 402

2

2

2

C1261

1

o

x

R1270 1

0

2

1UF

1UF

10% 6.3V CERM 402

10% 6.3V CERM 402

2

1

1

2

2

20% 6.3V CERM-X5R 0402-1

1

C

CRITICAL

PCH VCCACLKPLL FILTER/BYPASS (PCH 1.05V ACLK PLL PWR) PP1V05_S0_PCH_VCCACLKPLL

L1270

1

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

5% 1/16W MF-LF 402

1UF

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

2 0603

C1270

a

2

BYPASS=U0500.U8:6.35mm

1

C1271

47UF

47UF

20% 4V CERM-X5R 0805-1

20% 4V CERM-X5R 0805-1

2

1

1

2

2

in 0

2

1

1UF

1

PP1V05_S0_PCH_VCC_ICC_R

C1275

h

R1280

1

C1276 47UF

20% 4V CERM-X5R 0805-1

20% 4V CERM-X5R 0805-1

2

1

1

2

2

C1277 1UF 10% 10V X5R 402

CRITICAL NO STUFF

1

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

2 0603

NO STUFF

NO STUFF

C1280

C1281

1

47UF

47UF

20% 4V CERM-X5R 0805-1

20% 4V CERM-X5R 0805-1

2

B

PCH OPI VCCAPLL FILTER/BYPASS (PCH 1.05V OPI PLL PWR) PP1V05_S0_PCH_VCCAPLL_OPI

L1280 2.2UH-240MA-0.221OHM

1

1

2

2

8

57mA Max

C1282 1UF 10% 10V X5R 402

BYPASS=U0500.AA21:12.7mm BYPASS=U0500.AA21:12.7mm BYPASS=U0500.AA21:6.35mm

w 65 60 11 8

1

47UF

8

??mA Max

BYPASS=U0500.J18:12.7mm BYPASS=U0500.J18:12.7mm BYPASS=U0500.J18:6.35mm

2

w

.c

B

0

5% 1/16W MF-LF 402

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

2 0603

2

BYPASS=U0500.AH14:6.35mm

10% 10V X5R 402

PCH VCCCLK FILTER/BYPASS (PCH 1.05V VCCCLK PWR) PP1V05_S0_PCH_VCC_ICC

L1275 2.2UH-240MA-0.221OHM

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

5% 1/16W MF-LF 402

C1272

BYPASS=U0500.A20:12.7mm BYPASS=U0500.A20:12.7mm BYPASS=U0500.A20:6.35mm

R1275

1

8 12

31mA Max

1UF

CRITICAL

PCH VCCSUSHDA BYPASS (PCH 3.3V/1.5V HDA PWR) PP1V5_S0SW_AUDIO_HDA

10% 6.3V CERM 402

C1262 10UF

2.2UH-240MA-0.221OHM

PP1V05_S0_PCH_VCCACLKPLL_R

fi

PP1V05_S0 ??mA Max

C1210

2

BYPASS=U0500.J17:6.35mm BYPASS=U0500.R21:6.35mm

.c

2

60 57 53 37 17 16 15 11 8 6 68 65 61

10% 6.3V CERM 402

2

1

BYPASS=U0500.K9:6.35mm BYPASS=U0500.L10:6.35mm BYPASS=U0500.M9:6.35mm

BYPASS=U0500.AH11:6.35mm

C1208

C1267

1UF

10% 6.3V CERM 402

C1260

1

PCH VCCSDIO BYPASS (PCH 3.3V/1.8V SDIO PWR) PP3V3_S0

1

1UF

10% 6.3V CERM 402

2

1UF 10% 6.3V CERM 402

60 17 8

C1256 1UF

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND RTC PWR) PP3V3_SUS

C1206

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

1

20% 6.3V X5R 603

PCH VCCHSIO BYPASS (PCH 1.05V PCIe/SATA/USB3 PWR) PP1V05_S0SW_PCH_HSIO

BYPASS=U0500.AC9:12.7mm

C

1

10UF

BYPASS=U0500.K14:6.35mm

BYPASS=U0500.J11:12.7mm BYPASS=U0500.J11:6.35mm BYPASS=U0500.AE8:6.35mm

20% 6.3V X5R-CERM-1 603

D

PCH VCCCLK BYPASS (PCH 1.05V CLK PWR) PP1V05_S0

1

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND PWR) PP3V3_SUS

C1204

65 61 60 59 45 14 11 8

60 57 53 37 17 16 15 11 8 6 68 65 61

m

D

PCH VCCSPI BYPASS (PCH 3.3V SPI PWR) PP3V3_SUS

CRITICAL

PCH VCCSATA3PLL FILTER/BYPASS (PCH 1.05V SATA3 PLL PWR) PP1V05_S0SW_PCH_VCCSATA3PLL

L1290 2.2UH-240MA-0.221OHM

PP1V05_S0SW_PCH_HSIO

1

w

83mA Max

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

2 0603

C1290

1

NO STUFF C1291 1

47UF

47UF

20% 4V CERM-X5R 0805-1

20% 4V CERM-X5R 0805-1

2

1

8 12

42mA Max

C1292 1UF

2

2

10% 10V X5R 402

BYPASS=U0500.B11:12.7mm BYPASS=U0500.B11:12.7mm BYPASS=U0500.B11:6.35mm

A

CRITICAL

PCH VCCUSB3PLL FILTER/BYPASS (PCH 1.05V USB3 PLL PWR) PP1V05_S0SW_PCH_VCCUSB3PLL

L1295 2.2UH-240MA-0.221OHM 1

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

2 0603

C1295

1

NO STUFF C1296 1

47UF

47UF

20% 4V CERM-X5R 0805-1

20% 4V CERM-X5R 0805-1

2

1

SYNC_MASTER=J44

PCH Decoupling

41mA Max

DRAWING NUMBER

Apple Inc.

C1297

2

10% 10V X5R 402

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

BYPASS=U0500.B18:12.7mm BYPASS=U0500.B18:12.7mm BYPASS=U0500.B18:6.35mm

LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0 as well as from clarification email, from Srini, dated 9/10/2012 2:11pm.

8

7

6

5

4

REVISION

R

1UF 2

SYNC_DATE=08/12/2013

PAGE TITLE 8 14

3

2

BRANCH

PAGE

12 OF 120 SHEET

11 OF 78

1

SIZE

D

A

8

7

6

5

4

2

3

1

PPVRTC_G3H

20K

20K

5% 1/20W MF 201 2

5% 1/20W MF 2 201

R1302

1

1

330K

1M

5% 1/20W MF 201 2

D 1

2

2

1UF 10% 10V X5R 402

C1303 72 47

1UF 10% 10V X5R 402

OUT

17

AW5

PCH_CLK32K_RTCX1 NC_RTC_CLK32K_RTCX2

IN OUT

AY5

U0500

RTCX1 RTCX2

HASWELL-ULT 2C+GT2 BGA-TSP

PCH_INTRUDER_L

AU6

72

PCH_INTVRMEN

AV7

INTVRMEN

72

PCH_SRTCRST_L

AV6

SRTCRST*

72

1

72 17

5% 1/20W MF 2 201 72

C1300

CRITICAL OMIT_TABLE

R1301

AU7

RTC_RESET_L

HDA_BIT_CLK

R1310

33

1

2

1

2

1

2

72

AW8

HDA_BIT_CLK_R

SYM 5 OF 19 SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3

INTRUDER*

72 47

OUT

HDA_SYNC

R1311

72 47

OUT

HDA_RST_L

R1312

33

72

AV11

HDA_SYNC_R

HDA_BCLK/I2S0_SCLK HDA_SYNC/I2S0_SFRM

5% 1/20W MF 201 PLACE_NEAR=U0500.AV11:1.27mm 72

IN 66

HDA_RST*/I2S_MCLK

AY10

HDA_SDIN0 NC_HDA_SDIN1

AU12

HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD

33

1

2

72 17

HDA_SDOUT_R

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN*/I2S1_TXD HDA_DOCK_RST*/I2S1_SFRM

5% 1/20W MF 201 PLACE_NEAR=U0500.AU11:1.27mm

(IPD-PLTRST#)

TP_PCH_I2S1_TXD TP_PCH_I2S1_SFRM

AV10

TP_PCH_I2S1_SCLK

AY8

I2S1_SCLK

PCH_TRST*

70 16 6

XDP_CPUPCH_TRST_L

AU62

IN

70 16

XDP_PCH_TCK

AE62

IN

PCH_TCK

70 16

IN

XDP_PCH_TDI

70 16

XDP_PCH_TDO

AE61

OUT

XDP_PCH_TMS

AD62

PCH_TMS

AL11

RSVD

AC4

RSVD

C

NC NC 70 16

AE63

PCH_JTAGX

BI

SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2

A17

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1

J6

SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1

B14

SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0

F5

SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0

C17

A15

NC

AV2

IN

30 68 70

IN

30 68 70

OUT

30 68 70

OUT

30 68 70

IN

30 68 70

PCIe Port assignments:

SATA Port assignments:

SSD Lane 3

Primary HDD/SSD

PCIE_SSD_D2R_N<2> PCIE_SSD_D2R_P<2>

H8

PCIE_SSD_R2D_C_N<2> PCIE_SSD_R2D_C_P<2>

B17

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

(IPD)

PCH_TDI

(IPU)

(IPU)

PCIE_SSD_R2D_C_N<1> PCIE_SSD_R2D_C_P<1>

C15

PCIE_SSD_R2D_C_N<0> PCIE_SSD_R2D_C_P<0>

D17

V1

V6 AC1

RSVD RSVD

K10

SATA_RCOMP

JTAGX RSVD

SATALED*

C12

U3

30 68 70

IN

30 68 70

IN

30 68 70

OUT

30 68 70

OUT

30 68 70

IN

30 68 70

IN

30 68 70

OUT

30 68 70

OUT

30 68 70

XDP_SSD_PCIE3_SEL_L XDP_SSD_PCIE2_SEL_L XDP_SSD_PCIE1_SEL_L XDP_SSD_PCIE0_SEL_L

U1

L11

30 68 70

OUT

PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0>

E5

SATA_IREF

PCH_TDO

OUT

PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1>

H6

A12

IN

30 68 70

D

IN

16

IN

16

IN

16

IN

16

72

Reserved: ODD

SSD Lane 1

Unused

SSD Lane 0

Secondary HDD/SSD

PP1V05_S0SW_PCH_VCCSATA3PLL 1

NC NC

SSD Lane 2

8 11

R1370 3.01K

C

1% 1/20W MF 2 201 PLACE_NEAR=U0500.C12:2.54mm

PCH_SATA_RCOMP PCH_SATALED_L

12

fi

IN

J8

(IPU) AD61

70 16

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2

PCIE_SSD_R2D_C_N<3> PCIE_SSD_R2D_C_P<3>

x

R1313

HDA_SDOUT

B15

JTAG

OUT

SATA

(IPD) 72 47

H5

SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3

(IPD-PLTRST#) AU8

HDA_RST_R_L

5% 1/20W MF 201 PLACE_NEAR=U0500.AU8:1.27mm 72 68 47

PCIE_SSD_D2R_N<3> PCIE_SSD_D2R_P<3>

RTCRST*

5% 1/20W MF 201 PLACE_NEAR=U0500.AW8:1.27mm

33

J5

m

R1303

o

1

.c

1

RTC

R1300

AUDIO

65 17 13 8

a

CRITICAL OMIT_TABLE

U0500

in

HASWELL-ULT 2C+GT2 BGA-TSP

66

ENETSD_CLKREQ_L

70 68 32

OUT

70 68 32

OUT

PCIE_CLK100M_CAMERA_N PCIE_CLK100M_CAMERA_P CAMERA_CLKREQ_L

70 68 63

OUT

70 68 63

OUT

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P

IN

AP_CLKREQ_L

66 66

12

70 68 23

OUT

70 68 23

OUT

OUT

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P

IN

SSD_CLKREQ_L

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

PCIECLKRQ0*/GPIO18

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 PCIECLKRQ2*/GPIO20

B38

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

C37

U5

B37 A37

A25

PCH_CLK24M_XTALIN PCH_CLK24M_XTALOUT

B25

IN

17 72

OUT

17 72

PP1V05_S0_PCH_VCCACLKPLL RSVD RSVD

K21 M21

1

NC NC

1% 1/20W MF 201 2 PLACE_NEAR=U0500.C26:2.54mm

C26

PCH_DIFFCLK_BIASREF

TESTLOW TESTLOW TESTLOW TESTLOW

C35

PCH_TESTLOW_C35 PCH_TESTLOW_C34 PCH_TESTLOW_AK8 PCH_TESTLOW_AL8

AK8 AL8

R1380 3.01K

DIFFCLK_BIASREF

C34

8 11

B R1390 R1391 R1392 R1393

10K 10K 10K 10K

1

2

1

2

1

2

1

2

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

PCIECLKRQ3*/GPIO21 CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 PCIECLKRQ4*/GPIO22 CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

CLKOUT_LPC_0

AN15

LPC_CLK24M_SMC_R

OUT

17 72

CLKOUT_LPC_1

AP15

LPC_CLK24M_LPCPLUS_R

OUT

17 72

(IPD-PWROK)

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

B35 A35

TP_ITPXDP_CLK100MN TP_ITPXDP_CLK100MP

PCIECLKRQ5*/GPIO23

w

T2

XTAL24_IN XTAL24_OUT

PCIECLKRQ1*/GPIO19

AD1

B39

w

OUT

70 68 30

B42

A39

PCIE_CLK100M_TBT_N PCIE_CLK100M_TBT_P

70 68 30

C41

N1

FW_CLKREQ_L

TBT_CLKREQ_L

30 12

Y5

NC_PCIE_CLK100M_FWN NC_PCIE_CLK100M_FWP

IN

23 12

A41

w

63 12

B41

.c

IN

C42

U2

68 12

31 12

B

NC_PCIE_CLK100M_ENETSDN NC_PCIE_CLK100M_ENETSDP

h

66

CLOCK SIGNALS

SYM 6 OF 19

C43

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

PP3V3_S0

R1375

100K

1

100K 100K 100K 100K 100K 100K

8

1

2

1

2

1

2

1

2

1

2

1

2

DRAWING NUMBER

PCH_SATALED_L

2 5%

R1340 R1341 R1342 R1343 R1344 R1345

PCH Audio/JTAG/SATA/CLK

62 64 65 68 77 8 11 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50 61

1/20W

MF

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

Apple Inc.

12

201

201

5%

1/20W

MF

201

5%

1/20W

MF

201

ENETSD_CLKREQ_L CAMERA_CLKREQ_L AP_CLKREQ_L FW_CLKREQ_L TBT_CLKREQ_L SSD_CLKREQ_L

7

REVISION

R



12 68

NOTICE OF PROPRIETARY PROPERTY:

12 31

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

12 63 12 12 23 12 30

6

5

4

3

2

BRANCH

PAGE

13 OF 120 SHEET

12 OF 78

1

SIZE

D

A

8

7

6

5

4

2

3

CRITICAL OMIT_TABLE

PPVRTC_G3H

U0500

R1450 330K

5% 1/20W MF 2 201

BGA-TSP

SYM 8 OF 19

IN

NO STUFF

SLP_S0# Isolation 77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

IN

PM_SYSRST_L

AC3

SYS_RESET*

IN

PM_PCH_SYS_PWROK

AG2

SYS_PWROK

72 17 13

IN

PM_PCH_PWROK

AY7

APWROK

0

74LVC1G08 6 SOT891 36 18 13

OUT

PM_SLP_S0_L

4

CLKRUN*/GPIO32 V5

PCH_PWROK

SUS_STAT*/GPIO61 AG4

IN

PM_CLKRUN_L

BI

18 16 15

OUT

PLT_RESET_L

AG7

PLTRST*

SUSCLK/GPIO62 AE6

IN

PM_RSMRST_L

AW6

RSMRST*

SLP_S5*/GPIO63 AP5

PM_SLP_S5_L

PCH_SUSWARN_L

AV4

SUSWARN*/SUSPWRDNACK/GPIO30

SLP_S4* AJ6

PM_SLP_S4_L

SLP_S3* AT4

PM_SLP_S3_L

36 45 68

PM_CLK32K_SUSCLK_R

OUT

37

PM_PWRBTN_L

AL7

PWRBTN* (IPU)

37 36

IN

SMC_ADAPTER_EN

AJ8

36 25 13

IN

PM_BATLOW_L

AN4

ACPRESENT/GPIO31 (IPD-DeepSx) BATLOW*/GPIO72

SLP_SUS* AP4

PM_SLP_SUS_L

PCH_PM_SLP_S0_L

AF3

SLP_S0*

SLP_LAN* AJ7

TP_PCH_SLP_LAN_L

TP_PCH_SLP_WLAN_L

AM5

SLP_WLAN*/GPIO29

2

NC_PM_SLP_A_L

5

NC

SLP_S0# can be driven high outside of S0 U1420 ensures signal will only be high in S0.

CRITICAL OMIT_TABLE HASWELL-ULT 2C+GT2

EDP_BKLEN

OUT

24 13

IN

36 13

IN

68 13

IN

68 13

IN

66

OUT

66 64 13

OUT

68 13

OUT

61 13

OUT

68 13

OUT

EDP_VDDEN

TBT_PWR_REQ_L SMC_RUNTIME_SCI_L AUD_IP_PERIPHERAL_DET AUD_I2C_INT_L

U6 P4 N4 N2

PIRQA*/GPIO77 PIRQB*/GPIO78 PIRQC*/GPIO79 PIRQD*/GPIO80

AD4

NC_PCI_PME_L ODD_PWR_EN_L HDMITBTMUX_LATCH ENET_LOW_PWR AUD_PWR_EN AUD_IPHS_SWITCH_EN

U7 L1 L3 R5 L4

PME* (IPU) GPIO55 GPIO52 GPIO54 GPIO51 GPIO53

OUT

13 36 61

OUT

13 18 29 36 61 63

OUT

13 17 18 36 61 63 68

68

OUT

13 40 61

C

B9 C9

OUT

DP_HDMI_TBT_DDC_CLK DP_HDMI_TBT_DDC_DATA

OUT BI

64 66

DDPB_AUXN C5 DDPC_AUXN B6

DP_TBTSNK0_AUXCH_C_N DP_HDMI_TBT_AUX_N

BI

23 74

BI

64 66 74

DDPB_AUXP B5 DDPC_AUXP A6

DP_TBTSNK0_AUXCH_C_P DP_HDMI_TBT_AUX_P

BI

23 74

BI

64 66 74

D9 D11

BI

28 28

64 66

DDPB_HPD C8

DP_TBTSNK0_HPD

IN

23

DDPC_HPD A8

DPMUX_HPD_OUT

IN

64 66

DP_INT_HPD

IN

62

EDP_HPD D6

h

68 13

EDP_PANEL_PWR

in

62 13

C6

100K

5% 1/20W MF 2 201

DP_TBTSNK0_DDC_CLK DP_TBTSNK0_DDC_DATA

DDPB_CTRLCLK DDPB_CTRLDATA (IPD-PLTRST#) DDPC_CTRLCLK DDPC_CTRLDATA (IPD-PLTRST#)

fi

EDP_BKLCTL

A9

a

B8

EDP_BKLT_EN

DISPLAY

EDP_BKLT_PWM

OUT

PCI

OUT

62 13

eDP SIDEBAND

BGA-TSP SYM 9 OF 19

68 62

R1451

x

U0500

C

36 72

1

.c

NC

3

13 36 45 68

OUT

IN

U1420 08 1

13 29 31 72

LPC_PWRDWN_L

72 36 16 13

SLP_A* AL5

IN

PCIE_WAKE_L

PM_PCH_PWROK

OUT

CRITICAL

PM_DSW_PWRGD

IN

72 61

38

DPWROK AV5 (IPD-DeepSx) WAKE* AJ5

D

PCH_DSWVRMEN

72 17 13

0.1UF 10% 10V 0201

72

AB5

C1420

2 X5R-CERM

SYSTEM POWER MANAGEMENT SUSACK* (IPU) DSWVRMEN AW7

72 36 17 16

5% 1/20W MF 0201 2 1

AK2

72 68 36 17

R14001

PP3V3_S0

PCH_SUSACK_L

o

38

m

R1400 kept for debug purposes.

8 12 17 65

1

HASWELL-ULT 2C+GT2

D

1

w

PP3V3_S5 PP3V3_S0

A

B

.c

B

8

1

2

1

2

10K

1

2

10K

1

2

100K 100K 100K 100K 100K 100K 100K

1

2

1

2

1

2

1

2

1

2

1 1

100K 10K 100K 100K

1 1 1 1

100K 100K 100K 100K 100K

1 1 1 1 1

PM_PWRBTN_L 5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

2 2

2 5% 2 5% 2 5% 2 5% 2 5% 2 2 5% 2 5% 2 5% 5%

1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W

MF MF MF MF MF MF MF MF MF

201 201 201 201 201 201 201 201 201

13 16 36 72

PM_BATLOW_L

13 25 36

PCIE_WAKE_L

13 29 31 72

PM_CLKRUN_L

13 36 45 68

PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L PM_SLP_S0_L PM_SLP_SUS_L EDP_BKLT_EN EDP_PANEL_PWR TBT_PWR_REQ_L SMC_RUNTIME_SCI_L AUD_IP_PERIPHERAL_DET AUD_I2C_INT_L ODD_PWR_EN_L HDMITBTMUX_LATCH ENET_LOW_PWR AUD_PWR_EN AUD_IPHS_SWITCH_EN

7

w

1K 10K

13 36 61 13 18 29 36 61 63

w

R1405 R1410 R1452 R1455 R1460 R1461 R1462 R1463 R1464 R1430 R1431 R1440 R1441 R1442 R1443 R1445 R1446 R1447 R1448 R1449

8 11 15 16 17 18 26 27 29 56 59 60 61 65 68 77 61 62 64 65 68 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50 77

13 17 18 36 61 63 68 13 18 36 13 40 61

13 62 13 62

SYNC_MASTER=J44 13 24

SYNC_DATE=08/12/2013

PAGE TITLE

PCH PM/PCI/GFX

13 36 13 68

DRAWING NUMBER 13 68

Apple Inc. 13 68 R



13 64 66

NOTICE OF PROPRIETARY PROPERTY:

13 68

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

13 61 13 68

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

14 OF 120 SHEET

13 OF 78

1

A

7

6

5

4

70 68 23

IN

70 68 23

IN

70 68 23

OUT

70 68 23

OUT

PCIE_TBT_R2D_C_N<0> PCIE_TBT_R2D_C_P<0>

C23

E10

USB2N0 USB2P0

HASWELL-ULT 2C+GT2

AN8 AM8

USB_EXTA_N USB_EXTA_P

BI

33 71

BI

33 71

USB_EXTB_N USB_EXTB_P

BI

63 71

BI

63 71

USB_BT_N USB_BT_P

BI

29 71

BI

29 71

NC_USB_IRN NC_USB_IRP

BI

66 71

BI

66 71

USB_TPAD_N USB_TPAD_P

BI

34 71

BI

34 71

Ext A (LS/FS/HS)

IN

70 68 23

OUT

70 68 23

OUT

IN IN

70 68 23

OUT

Thunderbolt lane 3 70 68 23

OUT

70 68 63

IN

70 68 63

IN

70 68 63

OUT

70 68 63

OUT

AirPort

66 66

Reserved: FireWire 66 66

71 68 63

SD Card Reader (& Ethernet if combo)

IN IN

71 63

OUT

71 63

OUT

70 68 32

IN

70 68 32

IN

Camera 70 32 70 32

H10

PCIE_TBT_R2D_C_N<2> PCIE_TBT_R2D_C_P<2>

B21

G10

C21

E6

PCIE_TBT_D2R_N<3> PCIE_TBT_D2R_P<3>

70 68 23

71 68 63

PCIE_TBT_D2R_N<2> PCIE_TBT_D2R_P<2>

OUT OUT

F6

PCIE_TBT_R2D_C_N<3> PCIE_TBT_R2D_C_P<3>

B22

PCIE_AP_D2R_N PCIE_AP_D2R_P

G11

PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

C29

A21

F11

B30

NC_PCIE_FW_D2RN NC_PCIE_FW_D2RP

F13

NC_PCIE_FW_R2D_CN NC_PCIE_FW_R2D_CP

B29

USB3RPCIE_SD_D2R_N USB3RPCIE_SD_D2R_P

G17

G13

A29

F17

USB3RPCIE_SD_R2D_C_N USB3RPCIE_SD_R2D_C_P

C30

PCIE_CAMERA_D2R_N PCIE_CAMERA_D2R_P

F15

PCIE_CAMERA_R2D_C_N PCIE_CAMERA_R2D_C_P

B31

C31

G15

A31

E15

NC NC PP1V05_S0SW_PCH_VCCUSB3PLL

E13 A27

PCH_PCIE_RCOMP

72

B27

1% 1/20W MF 201

PERN5_L2 PERP5_L2 PETN5_L2 PETP5_L2 PERN5_L3 PERP5_L3 PETN5_L3 PETP5_L3 PERN3 PERP3 PETN3 PETP3

USB2N3 USB2P3

AR10

USB2N4 USB2P4

AM15

USB2N5 USB2P5

AM13

USB2N6 USB2P6

AP11

USB2N7 USB2P7

AR13

AL15

TP_USB_5N TP_USB_5P

AN13

NC_USB_SDN NC_USB_SDP

AP13

PETN4 PETP4 PERN1/USB3RN2 PERP1/USB3RP2

USB3RN0 USB3RP0

G20

USB3TN0 USB3TP0

C33

USB3RN1 USB3RP1

E18

USB3TN1 USB3TP1

B33

PETN1/USB3TN2 PETP1/USB3TP2 USBRBIAS* USBRBIAS

PERN2/USB3RN3 PERP2/USB3RP3

Unused

66 71

USB3_EXTB_D2R_N USB3_EXTB_D2R_P

F18

USB3_EXTB_R2D_C_N USB3_EXTB_R2D_C_P

A33

PETN2/USB3TN3 PETP2/USB3TP3

RSVD RSVD

OC0*/GPIO40 OC1*/GPIO41 OC2*/GPIO42 OC3*/GPIO43

Reserved: SD (HS)

66 71

USB3_EXTA_R2D_C_N USB3_EXTA_R2D_C_P

B34

Reserved: Camera

66 71

66 71

USB3_EXTA_D2R_N USB3_EXTA_D2R_P

H20

Trackpad

71

NC_USB_CAMERAN NC_USB_CAMERAP

AN11

D

IR

71

(IPD)

PERN4 PERP4

RSVD RSVD PCIE_RCOMP PCIE_IREF

AT10

BT

USB3 Port Assignments:

IN

33 68 71

IN

33 68 71

OUT

33 68 71

OUT

33 68 71

IN

63 68 71

IN

63 68 71

Ext A (SS)

Ext B (SS) OUT

63 68 71

OUT

63 68 71

C

AJ10

71

PCH_USB_RBIAS

AJ11

AN10

PLACE_NEAR=U0500.AJ10:2.54mm

AM10

AL3 AT1 AH2 AV3

1

R1570 22.6

NC NC

1% 1/20W MF 2 201

XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L XDP_USB_EXTD_OC_L

IN

14 16 33

IN

14 16 63

IN

14 16

IN

14 16

1

3.01K

PLACE_NEAR=U0500.A27:2.54mm

PETN5_L1 PETP5_L1

AR8 AP8

Ext B (LS/FS/HS)

in

R1500

USB2N2 USB2P2

AT7

m

IN

70 68 23

A23

PERN5_L1 PERP5_L1

AR7

o

OUT

70 68 23

B23

PCIE_TBT_R2D_C_N<1> PCIE_TBT_R2D_C_P<1>

USB2N1 USB2P1

.c

OUT

E8

SYM 11 OF 19

x

70 68 23

70 68 23

F8

PETN5_L0 PETP5_L0

fi

IN

Thunderbolt lane 2

11 8

USB Port Assignments:

U0500

PERN5_L0 PERP5_L0

PCI-E USB

IN

70 68 23

70 68 23

C22

PCIE_TBT_D2R_N<1> PCIE_TBT_D2R_P<1>

70 68 23

Thunderbolt lane 1

C

F10

1

BGA-TSP

Thunderbolt lane 0

D

PCIE_TBT_D2R_N<0> PCIE_TBT_D2R_P<0>

2

3

CRITICAL OMIT_TABLE

PCIe Port Assignments:

a

8

CRITICAL OMIT_TABLE

2

U0500

1

2

R1544

33

1

2

1

2

1

2

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3>

LPC_FRAME_R_L 5%

1/20W

MF

72 45

OUT

SPI_CLK_R

OUT

SPI_CS0_R_L

w

72 45

201

BI

72 45

72 45 14

AY12 AW11 AV12

AA3

Y7

LFRAME*

SPI_CLK

TP_SPI_CS2_L

AC2

SPI_CS0* SPI_CS1* (IPU)

SPI_CS2* (IPU)

AA2

SMBALERT*/GPIO11

AN2

PCH_SMBALERT_L

SMBCLK SMBDATA

AP2

SMBUS_PCH_CLK SMBUS_PCH_DATA

SML0ALERT*/GPIO60

AL2

SML0CLK SML0DATA

AN1

SML1ALERT*/PCHHOT*/GPIO73

AU4

SML1CLK_GPIO75 SML1DATA/GPIO74

AU3

AH1

AK1

WOL_EN SML_PCH_0_CLK SML_PCH_0_DATA

14

OUT BI

SPI_MOSI

AH3

PCH_SML1ALERT_L SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA

16 19 39 63 68 72

14 68

OUT

39 72

BI

39 72

SML1ALERT# pull-up not provided on this page, may be wire-ORed into other signals. Otherwise, 100k pull-up to 3.3V SUS required.

OUT

38

OUT

32 36 39 43 68 72 76

BI

B

16 19 39 63 68 72

OUT

(IPU) (IPU)

Y4

SPI_MOSI_R

BGA-TSP

SYM 7 OF 19

(IPU)

LAD0 LAD1 LAD2 LAD3

32 36 39 43 68 72 76

(IPU/IPD)

BI

SPI_MISO

BI

SPI_IO<2>

BI

SPI_IO<3>

AA4

SPI_MISO (IPU)

Y6

SPI_IO2 (IPU)

AF1

SPI_IO3

(IPU/IPD) (IPU/IPD)

CL_CLK

AF2

NC_CLINK_CLK

66

CL_DATA

AD2

NC_CLINK_DATA

66

CL_RST*

AF4

NC_CLINK_RESET_L

66

(IPU)

w

72 45 14

AW12

TP_SPI_CS1_L

w

72 45

AU14

LPC

2

SMBUS

72 68 45 36

1

SPI

OUT

LPC_FRAME_L

BI

33 33 33 33

C-LINK

BI

72 68 45 36

R1540 R1541 R1542 R1543

h

BI

72 68 45 36

BI

.c

B

72 68 45 36

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3>

72 68 45 36

HASWELL-ULT 2C+GT2

A

PP3V3_SUS PP3V3_SUS

8 11 14 45 59 60 61 65 8 11 14 45 59 60 61 65

SYNC_MASTER=J44

R1580 R1581 R1582 R1583

100K 100K 100K 100K

1

2

1

2

1

2

1

2

R1548 R1549

1K 1K

1 1

2

R1590 R1591

100K 100K

1

2

1

5%

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

2

2

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

8

1/20W

1/20W

MF

XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L XDP_USB_EXTD_OC_L SPI_IO<2> SPI_IO<3> PCH_SMBALERT_L WOL_EN

PCH PCIe/USB/LPC/SPI/SMBus

14 16 63

DRAWING NUMBER

14 16 14 16

Apple Inc.

14 45 72

REVISION

R

14 45 72

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

14 14 68

201

7

SYNC_DATE=08/12/2013

PAGE TITLE

14 16 33

6

5

4

3

2

BRANCH

PAGE

15 OF 120 SHEET

14 OF 78

1

SIZE

D

A

8

7

6

5

4

2

3

1

TABLE_BOMGROUP_HEAD

BOM GROUP

BOM OPTIONS

RAMCFG_SLOT

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

61 60 57 53 37 17 16 11 8 6 68 65

TABLE_BOMGROUP_ITEM

R1611

U0500

100K

16 15 15 16 18 18 16 15

15 16 18

15 16 18 55

GPIO12:

68 45 16 15

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC 18 16 15 13

IN

BI

XDP_MLB_RAMCFG0

AU2

BI

HDMITBTMUX_SEL_TBT

AM7

LAN_PHY_PWR_CTRL/GPIO12

OUT

MEM_VDD_SEL_1V5_L

AD6

GPIO15 (IPD-RSMRST#)

BI

XDP_LPCPLUS_GPIO

15 16 18 66 64 23

AN5

GPIO27 (IPD-DeepSx)

15

TPAD_SPI_INT_L

AD7

GPIO28

GSPI1_CS*/GPIO87 R7

TPAD_SPI_CS_L

15

TPAD_USB_IF_EN

AN3

GPIO26

GSPI1_CLK/GPIO88 L5

TPAD_SPI_CLK

SSD_PWR_EN

AG6

GPIO56

PCH_TBT_PCIE_RESET_L

AP1

GSPI1_MISO/GPIO89 N7 (IPD) GSPI_MOSI/GPIO90 K2

HDD_PWR_EN

AL4

BI

XDP_SDCONN_STATE_CHANGE_L

AT5

OUT

SD_PWR_EN

AK4 AB6

GPIO47

B

R1614 R1615

100K 100K

1 1

XDP_JTAG_ISP_TCK

U4

GPIO48

16 15

OUT

XDP_JTAG_ISP_TDI

Y3

GPIO49

18 15

OUT

JTAG_TBT_TMS_PCH

P3

GPIO50

OUT

PCH_HSIO_PWR_EN

Y2

HSIOPC/GPIO71

UART1_RST*/GPIO2 J3

GPIO13

UART1_CTS*/GPIO3 J4

GPIO14

I2C0_SDA/GPIO4 F2

GPIO25

TPAD_SPI_IF_EN XDP_MLB_RAMCFG3

AH4

72 68 45 15

BI

SPIROM_USE_MLB

AM4

OUT

CAMERA_PWR_EN_PCH

AG5 AG3

BI

XDP_MLB_RAMCFG1

AM3

GPIO9

AM2

GPIO10

A

8

2 2 2 2 2

100K 100K 100K 100K 100K 100K 100K 100K 100K

1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2

100K 100K

1 1

100K

1

10K

1

100K

1

100K

1

100K 10K 100K

1 1 1

HDMITBTMUX_FLAG_L

IN

15 64

IN

15 18

15

PCH_UART1_TXD

15

PCH_UART1_RTS_L

15

PCH_UART1_CTS_L

15

PCH_I2C0_SDA

15

I2C0_SCL/GPIO5 F3

PCH_I2C0_SCL

15

I2C1_SDA/GPIO6 G4

PCH_I2C1_SDA

15

I2C1_SCL/GPIO7 F1

PCH_I2C1_SCL

15

TBT_POC_RESET_L

OUT

24

SDIO_CMD/GPIO65 F4

BT_PWRRST_L

OUT

15 68

PCH_STRP_TOPBLK_SWP_L

IN

38

ENET_MEDIA_SENSE

IN

15 68

IN

15 62 68

AP_S0IX_WAKE_SEL

C4

SDIO_POWER_EN/GPIO70

SSD_RESET_L

L2

DEVSLP1*/GPIO38

SDIO_D0/GPIO66 D3 (IPD-PLTRST#) SDIO_D1/GPIO67 E4

FW_PME_L

N5

DEVSLP2*/GPIO39

SDIO_D2/GPIO68 C3

LCD_IRQ_L

PCH_TCO_TIMER_DISABLE

V2

SPKR/GPIO81 (IPD-PLTRST#)

SDIO_D3/GPIO69 E2

LCD_PSR_EN

IN

MF

201

63

C

SDIO_CLK/GPIO64 E3

OUT

2

5% 1/20W MF 2 201 OUT

PCH_UART1_RXD

29 15

OUT

13 15 16 18

R1671

AP_RESET_L

SSD_DEVSLP

IN

1

100K

JTAG_ISP_TDO

OUT

OUT

Pull-up on TBT page

Requires connection to SMC via 1K series R

15 62

h

15 18 19 39 42 60 65 68 15 18 19 39 42 60 65 68 15 18 19 39 42 60 65 68 31 42

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

77 42 43 44 46 47 50 61 62 64 65 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 68 61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

XDP_PCH_GPIO76 1/20W 1/20W 1/20W

MF MF MF

201 201 201

1/20W 1/20W 1/20W 1/20W 1/20W

MF MF MF MF MF

201 201 201 201 201

5% 5% 5% 5% 5% 5% 5% 5% 5%

1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W

MF MF MF MF MF MF MF MF MF

201 201 201 201 201 201 201 201 201

5%

1/20W 1/20W 1/20W

MF MF MF

201 201 201

2 2 5% 5% 2 5% 2 5% 2 5% 2 5% 2 2 5% 2 5% 5%

15 29

BI

DEVSLP0*/GPIO33

PLT_RESET_L

15

IN

30 15

P2

15

8 11 13 16 17 18 26 27 29 56 59 60 61 65 68 77

5% 5% 5% 5% 5%

STUFF 100K NO 1 2 100K 1 2 5% 100K 1 2 5%

GPIO46

15

XDP_LPCPLUS_GPIO XDP_PCH_GPIO17

15 16

15 16 45 68

1/20W 1/20W

MF MF

201 201

1/20W

MF

201

1/20W 1/20W 1/20W 1/20W 1/20W 1/20W

MF MF MF MF MF MF

SD_RESET_L SMC_WAKE_SCI_L TPAD_SPI_INT_L TPAD_USB_IF_EN SSD_PWR_EN HDD_PWR_EN XDP_SDCONN_STATE_CHANGE_L SD_PWR_EN TBT_PWR_EN XDP_JTAG_ISP_TCK XDP_JTAG_ISP_TDI JTAG_TBT_TMS_PCH PCH_HSIO_PWR_EN TPAD_SPI_IF_EN SPIROM_USE_MLB CAMERA_PWR_EN_PCH FW_PWR_EN SSD_DEVSLP AP_S0IX_WAKE_SEL

15 15 15 15

15 16

15 15

w

1 1 1 1 1

UART1_TXD/GPIO1 G2

15

R1616 should also be stuffed if platform does not use SD card

15 63 15 36 15

15 15

29 15

15

64 15

15 30 60 61

15 68 15 16 18 15 63

15 15 15 15

15 23

w

100K 100K 100K 100K 100K

UART1_RXD/GPIO0 K4

1% 1/20W MF 2 201

AP_S0IX_WAKE_L

XDP_MLB_RAMCFG2

18 16 15

SD_ON_MLB

R1616 R1617 R1618 R1619 R1620 R1622 R1623 R1624 R1625 R1626 R1627 R1628 R1629 R1630 R1632 R1633 R1634 R1637 R1638 R1640 R1652 R1670 R1691 R1693 R1694 R1695

UART0_CTS*/GPIO94 G1

GPIO45

FW_PWR_EN

OUT

68 15

5% 2 2 5% 5%

UART0_TXD/GPIO92 K3 UART0_RTS*/GPIO93 J2

OUT

100K

PP3V3_S5 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3RS0_CAMERA PP3V3_S0 PP3V3_S0 TBTLC for CR, S0 for RR 2 R1610 100K 1

GPIO44

16 15

BI

1/20W

GPIO59

TBT_PWR_EN

18 16 15

TPAD_SPI_MOSI

UART0_RXD/GPIO91 J1

OUT

AT3

TPAD_SPI_MISO

GPIO58

23 15

18 16 15

5%

15

SMC_WAKE_SCI_L

68 15

1

15

PCH_GSPI0_MOSI

IN

18 15

1K

15

PCH_GSPI0_MISO

36 15

15

R1641

PCH_GSPI0_CLK

GSPI0_CLK/GPIO84 L6

60 15

PP3V3_S0

15

GSPI0_MISO/GPIO85 N6 (IPD) GSPI0_MOSI/GPIO86 L8 (IPD-PLTRST#)

63 15

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

PCH_GSPI0_CS_L

GPIO24

18 16 15

5% 1/20W MF 201 2

49.9

GSPI0_CS*/GPIO83 R6

GPIO17

OUT

D R1655

T3

GPIO57

15 36 45 68

PLACE_NEAR=U0500.AW15:2.54mm 1

AD5

OUT

Pull-up/down on chipset support page (depends on TBT controller) Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down. Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).

NC NC

XDP_PCH_GPIO17

OUT

R1639

BI

SD_RESET_L

61 60 30 15

1

LPC_SERIRQ

37 72

18 23 72

PCH_OPI_COMP

IN

68 15

30

GPIO16

RSVD AF20 RSVD AB21

72

IN

OUT

100K

C

Y1

SERIRQ T4 PCH_OPI_COMP AW15

OUT

TBT_CIO_PLUG_EVENT_L

16 15

R16211

23 18

GPIO8

PM_THRMTRIP_L

RCIN*/GPIO82 V4

63 15

PLT_RESET_L

5% 1/20W MF 201 2

P1

XDP_PCH_GPIO76

BI

BGA-TSP SYM 10 OF 19 BMBUSY*/GPIO76

o

XDP_MLB_RAMCFG0 XDP_MLB_RAMCFG1 XDP_MLB_RAMCFG2 XDP_MLB_RAMCFG3

D

THRMTRIP* D60

HASWELL-ULT 2C+GT2

5% 1/20W MF 2 201

.c

5% 1/20W MF 201 2

x

5% 1/20W MF 2 201

1

fi

100K

m

RAMCFG0:H

R16351

100K

CPU/MISC

RAMCFG1:H

R1636

a

5% 1/20W MF 201 2

RAMCFG2:H 1

GPIO LPIO

100K

.c

R16311

1K

5% 1/20W MF 201 2

CRITICAL OMIT_TABLE

w

RAMCFG3:H

R16501

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

in

PP3V3_S0

PP1V05_S0

15

15 16

15

PCH_GSPI0_CS_L PCH_GSPI0_CLK PCH_GSPI0_MISO PCH_GSPI0_MOSI TPAD_SPI_CS_L TPAD_SPI_CLK TPAD_SPI_MISO TPAD_SPI_MOSI AP_S0IX_WAKE_L HDMITBTMUX_FLAG_L PCH_UART1_RXD PCH_UART1_TXD PCH_UART1_RTS_L PCH_UART1_CTS_L PCH_I2C0_SDA PCH_I2C0_SCL

15 16 15 18

15

15 60

15

PCH_I2C1_SDA PCH_I2C1_SCL

R1660 R1661 R1662 R1663 R1664 R1665 R1666 R1667 R1668 R1669 R1672 R1673 R1674 R1675 R1676 R1677 R1678 R1679

100K 100K 100K 100K

1 1 1 1

47K 47K 47K 47K

1 1 1 1

100K 100K

1 1

100K 100K 100K 100K

1 1 1 1

100K 100K

1 1

100K 100K

1 1

PP3V3_S0 2 2 5% 2 5% 2 5% 5% 2 2 5% 5% 2 2 5% 5% 2 2 5% 5% 2 2 5% 2 5% 2 5% 5% 2 2 5% 5% 2 2 5% 5%

B 1/20W 1/20W 1/20W 1/20W

MF MF MF MF

201 201 201 201

1/20W 1/20W 1/20W 1/20W

MF MF MF MF

201 201 201 201

1/20W 1/20W

MF MF

201 201

1/20W 1/20W 1/20W 1/20W

MF MF MF MF

201 201 201 201

1/20W 1/20W

MF MF

201 201

1/20W 1/20W

MF MF

201 201

15

15 45 68 72 15 18 15 68

SYNC_MASTER=J44

15 30

SYNC_DATE=08/12/2013

PAGE TITLE

15 29

PCH GPIO/MISC/LPIO

FW_PME_L

15 68

LPC_SERIRQ

15 36 45 68

DRAWING NUMBER

Apple Inc.

201

JTAG_ISP_TDO

15 18

BT_PWRRST_L

15 68

R



201

NOTICE OF PROPRIETARY PROPERTY:

201 201 201 201

7

ENET_MEDIA_SENSE LCD_IRQ_L LCD_PSR_EN

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

15 68 15 62 68 15 62

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

16 OF 120 SHEET

15 OF 78

1

A

8

7

6

5

Extra BPM Testpoints

CRITICAL XDP_CONN

1 TP

TP1802 XDP_BPM_L<3> 1 TP TP1803 TP-P6 XDP_BPM_L<4> 1 TP TP1804 TP-P6 XDP_BPM_L<5> 1 TP TP1805 TP-P6 XDP_BPM_L<6> 1 TP TP1806 TP-P6 XDP_BPM_L<7> 1 TP TP1807 TP-P6

70 6

IN

70 6

IN

70 6

IN

70 6

IN

0

R1804

0

1

2 5%

1/20W

MF

8

70 16 6

70 16 12

OBSDATA_B2 OBSDATA_B3

72

CPU_PWR_DEBUG XDP_SYS_PWROK

PWRGD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3

1/16W MF-LF 402 72 68 63 39 19 14

BI

72 68 63 39 19 14

IN

70 16 12

C

CPU_CFG<6> CPU_CFG<7>

72

OUT

2 5%

OBSDATA_B0 OBSDATA_B1

0201

XDP 1

CPU_CFG<4> CPU_CFG<5>

XDP_CPU_VCCST_PWRGD XDP_CPU_PWRBTN_L

70

PLACE_NEAR=U5000.J3:2.54mm

OBSFN_B0 OBSFN_B1

201

MF

XDP

R1802

XDP_BPM_L<0> XDP_BPM_L<1>

SMBUS_PCH_DATA SMBUS_PCH_CLK XDP_PCH_TCK

OUT

SDA SCL TCK1 TCK0

XDP_CPU_TCK

OUT

PCH_JTAGX

OUT

R1835

XDP 0

1

2

XDP

5% 1/20W MF 0201 PLACE_NEAR=J1800.58:28mm

C1804

XDP 1

0.1UF

1K

10% 6.3V CERM-X5R 2 0201

5% 1/16W MF-LF 2 402

1

64

10% 6.3V CERM-X5R 2 0201

OBSDATA_C0 OBSDATA_C1

CPU_CFG<8> CPU_CFG<9>

OBSDATA_C2 OBSDATA_C3

CPU_CFG<10> CPU_CFG<11>

OBSFN_D0 OBSFN_D1

CPU_CFG<19> CPU_CFG<18>

OBSDATA_D0 OBSDATA_D1

CPU_CFG<12> CPU_CFG<13>

IN

6 70

IN

6 70

OBSDATA_D2 OBSDATA_D3

CPU_CFG<14> CPU_CFG<15>

IN

6 70

IN

6 70

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 TDO TRSTn TDI TMS XDP_PRESENT# XDP

XDP

R1831 C1800 0.1UF

1

1

63

IN

6 70

IN

6 70

IN

6 70

IN

6 70

IN

6 70

IN

6 70

IN

6 70

IN

6 70

D

NC NC

XDP 2 R1805 1K 1 XDP_CPURST_L PLT_RESET_L IN 5% 1/20W MF 201 XDP_DBRESET_L PLACE_NEAR=U0500.AG7:2.54mm OUT 17 72 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page XDP_PCH_TDO IN XDP_TRST_L XDP_PCH_TDI OUT XDP_PCH_TMS OUT

C1801

70

C1806

Q1840

0.1UF

10% 2 6.3V CERM-X5R 0201

DMN5L06VK-7

10% 2 6.3V CERM-X5R 0201

SOT-563

PLACE_NEAR=J1800.51:28mm

a

Q1840 DMN5L06VK-7

OUT

14

OUT

XDP_USB_EXTC_OC_L

18 15

18 15

1 TP

IN

XDP_USB_EXTD_OC_L

OUT

XDP_SDCONN_STATE_CHANGE_L

BI

XDP_MLB_RAMCFG1

BI

XDP_MLB_RAMCFG2

BI

IN

XDP_JTAG_ISP_TCK XDP_SSD_PCIE3_SEL_L

TP1876 TP1877 TP-P6 1 TP TP1878 TP-P6 1 TP

12

OUT

XDP_SSD_PCIE2_SEL_L

12

OUT

XDP_SSD_PCIE1_SEL_L

12

OUT

XDP_SSD_PCIE0_SEL_L

JTAG_ISP_TCK MAKE_BASE=TRUE

BI

XDP_LPCPLUS_GPIO

15

OUT

XDP_PCH_GPIO17

15

BI

XDP_PCH_GPIO76

1K 1K

1

2

1

5%

1/20W

MF

201

5%

1/20W

MF

201

2

1K

1

2

1K

1

2

5%

1/20W

MF

201

5%

1/20W

MF

201

1 TP

TP-P6

XDP_JTAG_ISP_TDI

XDP_CPUPCH_TRST_L XDP_CPUPCH_TRST_L

D 3

h

XDP_CPUPCH_TRST_L

XDP_CPU_TDI

C1845 1 0.1UF

SSD_PCIE_SEL_L

330K

U1845 74LVC1G07GF SOT891

ALL_SYS_PWRGD

2 A

15 16 18

NC

5% 1/20W MF 2 201

OUT

6 12 16 70

OUT

6 12 16 70

OUT

6 70

B

NC 5

XDP_CPU_TMS

OUT

NC 70 16 12

GND

6 70

65 59

R1899

PCH_JTAGX

PP1V05_SUS

NO STUFF 1K

2

1

PLACE_NEAR=U0500.AE63:28mm

R1890 51 2 PLACE_NEAR=U0500.AE61:28mm

70 16 12

XDP_PCH_TDO

70 16 12

XDP_PCH_TDI

R1891 51 2 PLACE_NEAR=U0500.AD61:28mm

18 23

R1892

XDP_PCH_TMS

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

XDP 1

XDP 1

XDP 51

2

1

PLACE_NEAR=U0500.AD62:28mm

NO STUFF

R1896 51 2 PLACE_NEAR=U0500.AE62:28mm

XDP_PCH_TCK

30 70 16 12 6

BI

6 12 16 70

XDP_JTAG_CPU_ISOL_L

Y 4

1 NC

PLACE_NEAR=J1800.57:28mm

70 16 12

IN

6 16 70

R1845

VCC

10% 16V X5R-CERM 2 0201

SOT-563

1

70 16 12

XDP_LPCPLUS_GPIO TP-P6

Q1842

IN

IN

CRITICAL XDP DMN5L06VK-7

14 16 63

C

12 16 70

MAKE_BASE=TRUE

NOTE: Must not short XDP pins together!

MAKE_BASE=TRUE 1 TP

OUT

PLACE_NEAR=J1800.55:28mm

PP5V_S0 PP3V3_S5

61 36 17

1 TP

R1881 R1882 R1883 R1884

IN

SOT-563

14 16 33

XDP_SDCONN_STATE_CHANGE_L IN

TP-P6

XDP_MLB_RAMCFG3

OUT

IN

TP1873 TP-P6 1 TP TP1874 TP-P6 MAKE_BASE=TRUE

15

15

XDP_USB_EXTB_OC_L MAKE_BASE=TRUE

12

68 45 16 15

A

MAKE_BASE=TRUE

IN

w

18 15

XDP_USB_EXTA_OC_L

w

14

18 16 15

TP1870

DMN5L06VK-7

D

63 16 14

XDP_USB_EXTB_OC_L

TP-P6

Q1842

6

XDP_USB_EXTA_OC_L

XDP_CPU_TDO

CRITICAL XDP

6

OUT

61 60 58 54 53 45 44 41 32 17 68 65 56 29 27 26 18 17 15 13 11 8 77 68 65 61 60 59

12 16 70

3

BI

33 16 14

w

B

Non-XDP Signals 1 TP

PLACE_NEAR=J1800.53:28mm

6

D

SOT-563

CPU JTAG Isolation

.c

PCH/XDP Signals XDP_MLB_RAMCFG0

18 15

12 16 70

CRITICAL XDP

in

PCH XDP Signals

13 15 18

CRITICAL XDP

XDP 1

0.1UF

518S0847

XDP_CPU_PRESENT_L

These signals do not connect to XDP connector in this architecture, only accessible via Top-Side Probe. Nets are listed here to show XDP associations and to make clear what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.

201

5

IN

MF

G

PM_PCH_SYS_PWROK

IN

70 6

OBSDATA_A2 OBSDATA_A3

CPU_CFG<17> CPU_CFG<16>

S

OUT

70 6

1/20W

4

PM_PWRBTN_L

IN

5%

2

OUT

1/20W

IN

70 6

PLACE_NEAR=U0500.E60:28mm

G

5%

PLACE_NEAR=U0500.C61:2.54mm

70 6

CPU_CFG<2> CPU_CFG<3>

OBSFN_C0 OBSFN_C1

S

2

IN

OBSDATA_A0 OBSDATA_A1

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

1

1

IN

70 6

CPU_CFG<0> CPU_CFG<1>

201

5

XDP 1K

70 6

MF

G

72 36 17 13

R1800

IN

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

OBSFN_A0 OBSFN_A1

S

72 36 13

CPU_VCCST_PWRGD

IN

70 6

1/20W

61

4

70 17 8

XDP_CPU_PREQ_L XDP_CPU_PRDY_L

BI

R1813

XDP_CPU_TCK

5%

1

TDI and TMS are terminated in CPU.

5% 1/16W MF-LF 2 402 70 6

70 16 6

51 2

2

IN

62

150

2

XDP

G

IN

70 6

R1830

S

70 6

M-ST-SM1

1

XDP 51 1

1

IN

D

IN

70 6

R1810

XDP_CPU_TDO

PLACE_NEAR=U0500.F62:28mm

3

70 6

70 16 6

DF40RC-60DP-0.4V

m

D

IN

fi

70 6

NOTE: This is not the standard XDP pinout. Use with 921-0133 Adapter Flex to support chipset debug.

J1800

TP-P6

PP1V05_S0

o

XDP_BPM_L<2>

60 57 53 37 17 16 15 11 8 6 68 65 61

.c

IN

1

Merged (CPU/PCH) Micro2-XDP

PP1V05_S0

60 57 53 37 17 16 15 11 8 6 68 65 61

2

3

x

70 6

4

XDP_CPUPCH_TRST_L R1897 51

NO STUFF 2

PLACE_NEAR=U0500.AU62:28mm

15 16 45 68

1

1

TP1886 TP1887 JTAG_ISP_TDI

MAKE_BASE=TRUE

OUT

18 23

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

CPU/PCH Merged XDP

Unused & MLB_RAMCFGx GPIOs have TPs. USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

DRAWING NUMBER

Apple Inc.

SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug. R

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

NOTICE OF PROPRIETARY PROPERTY:

NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

SSD_PCIEx_SEL_L straps are connected via 1K to common net. LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

18 OF 120 SHEET

16 OF 78

1

A

8

7

6

5

4

2

3

1

System RTC Power Source & 32kHz / 25MHz Clock Generator PCH Reset Button

Chipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal PP3V42_G3H Coin-Cell: VBAT (300-ohm & 10uF RC) No Coin-Cell: 3.42V G3Hot (no RC)

73 65 55 41 22 21 20 19

72 16

R1997

6

2 3

12PF 2

1M

5% 1/20W MF 2 201

1

17 12

PCH 24MHz Crystal C1915

OUT

32 71

OUT

23 71

C1910

2

+/-0.1PF 25V C0G 0201 NC

0

1

5% 1/20W MF

Y1915 NC 24.000MHZ-20PPM-6PF 0201 NC 3.20X2.50MM-SM1

IN

12 72

NC_RTC_CLK32K_RTCX2

NO_TEST=TRUE

IN

OUT

12 72

R1916 1M

5% 1/20W MF 2 201

2

PCH_CLK24M_XTALIN

+/-0.1PF 25V C0G 0201

LPC_CLK24M_SMC

R1927

72 12

IN

IN

LPC_CLK24M_SMC_R

22

1

PLACE_NEAR=U0500.AN15:5.1mm

MAKE_BASE=TRUE

LPC_CLK24M_SMC

2

5% 1/20W MF 201

OUT

17 36 68 72

DMN5L06VK-7 SOT-563

1

PLACE_NEAR=U0500.AP15:5.1mm

22

LPC_CLK24M_LPCPLUS

2

OUT

45 68 72

5% 1/20W MF 201

5% 1/20W MF 2 201

SPI_DESCRIPTOR_OVERRIDE_LS5V

SPI_DESCRIPTOR_OVERRIDE

R1921

D 6

1K

5% 1/20W MF 2 201

DMN5L06VK-7 SOT-563

IN

G

HDA_SDOUT_R IPD = 9-50k

S 1

C 12 72

OUT

SPI_DESCRIPTOR_OVERRIDE_L

VCCST (1.05V S0) PWRGD 29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

PP3V3_S5

PP1V05_S0

C1930 1

IN

5% 1/20W MF 2 201

74AUP1G09 SOT891

VCC

ALL_SYS_PWRGD

2 A

PM_SLP_S3_L

1 B

CPU_VCCST_PWRGD

Y 4

OUT

8 16 70

5 NC

B

GND

w

w

3

.c

10K

U1930

10% 16V X5R-CERM 2 0201

68 63 61 36 18 13

R1931

CRITICAL

0.1UF

61 36 17 16

6 8 11 15 16 37 53 57 60 61 65 68

1

NC

B

100K

1

R1926

LPC_CLK24M_LPCPLUS_R

R1920

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally. If high, ME is disabled. This allows for full re-flashing of SPI ROM. SMC controls strap enable to allow in-field control of strap setting. Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

h

72 12

17 36 68 72

1

Q1920

2

in

PCH 24MHz Outputs

PP5V_S0

12 17

1

6.8PF

61 60 58 54 53 45 44 41 32 16 68 65

Q1920

36

PCH_CLK24M_XTALOUT

2

3

4

NC

C1916

PCH_CLK24M_XTALOUT_R CRITICAL

1

72

17 55

PP1V5_S0SW_AUDIO_HDA

fi

2

OUT

3 60 11 8

R1915

6.8PF

MEMVTT_PWR_EN

NC

PCH ME Disable Strap

1UF

NC_RTC_CLK32K_RTCX2 MAKE_BASE=TRUE

12 72

20% 6.3V 2 X5R 0201

SYSCLK_CLK25M_X1 NOTE: 30 PPM or better required for RTC accuracy

C

1

THRM PAD

GND

71

5% 25V NP0-C0G-CERM 0201

1

SYSCLK_CLK25M_CAMERA SYSCLK_CLK25M_TBT PPVRTC_G3H 8 12 13 65 For SB RTC Power

VOUT 1

R1906

25.000MHZ-12PF-20PPM OMIT

NC

OUT

a

1

X2 X1

1

SM-3.2X2.5MM

4

C1906

71

5% 1/20W MF 0201

Y1905

3 4

SYSCLK_CLK25M_X2_R NO STUFF

2

25M_A 9 25M_B 8 25M_C 15

PCH_CLK32K_RTCX1

6

1

NC NC

0

1

NC 5

D

17 55

GND

o

25V

NP0-C0G-CERM

SYSCLK_CLK25M_X2 CRITICAL

1 NC

NC

.c

0201 5%

71

32.768K 12

7 10 16

1

2

MAKE_BASE=TRUE

5% 1/16W MF-LF 2 402 SILK_PART=SYS RESET

x

R1905

12PF

MEMVTT_PWR_EN

Y 4

G 5

TQFN

17

C1905

2 A

TPS51916 I(leak) = +/- 1uA, Vih(min) = 1.8V 33uW when driven-low

5% 1/20W MF 2 201

74AUP1G07GF SOT891

CPU_MEMVTT_PWR_EN_LSVDDQ

0

CRITICAL CKPLUS_WAIVE=PwrTerm2Gnd

330K

U1970

+V3.3A should be first available ~3.3V power to reduce VBAT draw.

SLG3NB148CV 11 VIOE_25M_A 6 VIOE_25M_B 14 VIOE_25M_C

IN

R1970

VCC

10% 16V X5R-CERM 2 0201

13 36 68 72

BI

1

VBAT and +V3.3A are internally ORed to create VDD_RTC_OUT.

U1900

20% 6.3V 2 X5R 0201

PM_SYSRST_L NO STUFF

2

1/20W 0201 MF 5%

C1902 1UF

10% 16V X5R-CERM 2 0201

1

0.1UF

S

1

1

0.1UF

10% 16V X5R-CERM 2 0201

XDP_DBRESET_L

C1970 1

4

C1922

0.1UF

IN

0

1

6

XDP

D

C1924 1

5% 1/20W MF 2 201

R1996

VG3HOT 13

65 24 23 18

PP1V2_CAM_XTALPCIEVDD PP3V3_TBTLC

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

10K

VDD 5

31

PP3V3_S0

R1995

GreenCLK 25MHz Power 18 Must be powered if any VDDIO is powered. CAM XTAL Power TBT XTAL Power

PP1V35_S3

1

PP3V3_S5 Coin-Cell & G3Hot: 3.42V G3Hot Coin-Cell & No G3Hot: 3.3V S5 No Coin-Cell: 3.3V S5 No bypass necessary PP3V3_S5RS3RS0_SYSCLKGEN 77 68 65 61 15 13 11 8 18 17 16

NC 2

D

PP3V3_S0

m

This looks a little ugly to support new and old parts. With GreenCLK Rev C pin 5 must receive S5 power (Stuff R2042) 60 59 56 29 27 26

Memory VTT Enable Level-Shifter CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

3

51 45 39 38 37 36 34 33 30 17 68 65 61 52

IN

5% 1/20W MF 201 2

5% 1/20W MF 201 2

53 17 8

OUT

53 17 8

IN

CPU_VR_READY MAKE_BASE=TRUE

CPU_VR_READY

NO STUFF

R1951 1

0

61 36 17 16

IN

13 17 72

ALL_SYS_PWRGD CPUVR_PGOOD_R

5% 1/20W MF 0201

NO STUFF WF: Do we need this?

R19632 0

8 74LVC2G08GT/S505 1

SOT833

A

U1950 Y 7

2

13 17 72

OUT

0.1UF

10K 10K

OUT

C1950

10% 16V 2 X5R-CERM 0201

R1950

R1955

A

1 1

1

MAKE_BASE=TRUE

BYPASS=U1950:5MM

PP3V3_S0

CPU_VR_EN

PM_PCH_PWROK PM_PCH_PWROK

w

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

53 8

PCH PWROK Generation

PP3V42_G3H

51 45 39 38 37 36 34 33 30 17 68 65 61 52

2 B

08

72

5% 1/20W MF 0201 1

PM_S0_PGOOD NO STUFF

R19611

4

2

R1960 0

5% 1/20W MF 1 0201 5

CKPLUS_WAIVE=UNCONNECTED_PINS 8 74LVC2G08GT/S505

SOT833 A

U1950 Y 3 6 B

72

SYS_PWROK_R

QTY

197S0480

1

1K

2

REFERENCE DES Y1905

4

CRITICAL

SYNC_MASTER=J44

R1962 1

DESCRIPTION XTAL,25MHZ,20PPM,12PF,3.2X2.5X.6MM,85C

PM_PCH_SYS_PWROK

BOM OPTION

SYNC_DATE=08/12/2013

PAGE TITLE OUT

Chipset Support

13 16 36 72

5% 1/20W MF 201

08

100K

5% 1/20W MF 201 2

PART NUMBER

DRAWING NUMBER

Apple Inc.

CKPLUS_WAIVE=UNCONNECTED_PINS R

NOTICE OF PROPRIETARY PROPERTY:

72 37 36 25 24

8

7

IN

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

SMC_DELAYED_PWRGD

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

19 OF 120 SHEET

17 OF 78

1

A

8

7

6

5

4

2

3

1

GreenCLK 25MHz Power Platform Reset Connections

NO STUFF

R2040

Unbuffered R2081 33

PLT_RESET_L

IN

1

LPCPLUS_RESET_L

2 5% 1/20W MF 201

OUT

0

45 68

PCA9557D_RESET_L

2

OUT

PP3V3_S0

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

0

1

17 18

PP3V3_S5RS3RS0_SYSCLKGEN

17 18

R2041/2 should be stuffed for GreekCLK A or B depending on S2 rail

2

5% 1/20W MF 0201

100K 5% 1/20W MF 201

0

1

REDWOOD RIDGE PLUG_EVENT IS ACTIVE-LOW, ALWAYS DRIVEN (PULL-UP) MAKE_BASE

2 72 23 18 15

5% 1/20W MF 0201

OUT

TBT_CIO_PLUG_EVENT_L

TBT_CIO_PLUG_EVENT_L

TRUE

IN

15 18 23 72

5 1

SC70-HF

U2071

2

4

1

C2071

1

SMC_LRESET_L

2

OUT

36

5% 1/20W MF 0201

R2070

68 65 64 63 60 42 38 37 34 29

PP3V3_S4

R2032

0

CAM_PCIE_RESET_L

2

OUT

R20311

31

DMN5L06VK-7 SOT-563

470K

Q2030

15 18 23

C

DMN5L06VK-7

SMC_PME_S4_DARK_L

37 36 23 18

SMC_PME_SDCONN

SOT-563

6

PCH_TBT_PCIE_RESET_LOUT

5% 1/20W MF 201 2

G 5

PCH_TBT_PCIE_RESET_L MAKE_BASE=TRUE

5% 1/20W MF 2 201

Q2030

5% 1/20W MF 0201

IN

R20611

470K

R2089 1

23 18 15

PP3V3_TBTLC

1

5% 1/20W MF 201 2

68 65 60 42 39 19 18 15

R2062 100K

0.1UF 20%

10V 2 CERM 402

PP3V3_S3

5% 1/20W MF 2 201

VCC

U2060

From PCH

S0 pull-up on PCH page To PCH

SOT891 23

IN

15

IN

JTAG_TBT_TDO JTAG_TBT_TMS_PCH S0 pull-up on PCH page

1 1A

1Y 6

JTAG_ISP_TDO

OUT

15

3 2A

2Y 4

JTAG_TBT_TMS

OUT

23

To RR

C

GND 2

x

4

3

S

D

SMC_PME_S4_DARK_L

1

C2060

74LVC2G07

From RR

To SMC 37 36 23 18

1

100K

G 2

10% 16V X5R-CERM 0201

TBTLC can be on when S0 is off, and vice-versa Isolation ensures no leakage to RR or PCH

o

5% 1/20W MF 2 201

Redwood Ridge JTAG Isolation 65 24 23 17

100K

0.1UF 2

SDCONN_STATE_CHANGE Isolation

0

PLT_RST_BUF_L

3 1

Buffered R2072

CRITICAL MC74VHC1G08

m

Scrub for Layout Optimization

PP3V3_S0

S

65 43 28 8 15 39 50

1

68 44 30 11 17 40 61

D

77 46 37 12 18 41 62

.c

47 38 13 24 42 64

D

2

THUNDERBOLT PULL-UP

R2042 should be stuffed for GreenCLK C

R2042 PP3V3_S5

29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

PP3V3_S0

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

R2015 1

R2041

19

PP3V3_S5RS3RS0_SYSCLKGEN MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE

NO STUFF

5% 1/20W MF 0201

D

I1608

2

5% 1/20W MF 0201

R2071 1

0

1

5

16 15 13

PP3V3_S3

68 65 60 42 39 19 18 15

fi

CRITICAL 6

U2031

VCC

XDP_SDCONN_STATE_CHANGE_L

C2031 1 0.1UF

10% 6.3V CERM-X5R 2 0201

(For development only)

R2094 0

PP3V3_S5_DBGLED

1

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=3.3V

B

DBGLED

1

R2091

K

R2092

DBGLED

1

R2093

20K

20K

20K

20K

5% 1/20W MF 201

5% 1/20W MF 201

5% 1/20W MF 201

5% 1/20W MF 201

2

DBGLED_S5 A

DBGLED

1

2

DBGLED_S4

DBGLED

A

DBGLED

A

D2090

D2091

GREEN-56MCD-2MA-2.65V LTQH9G-SM

GREEN-56MCD-2MA-2.65V LTQH9G-SM

PLACE_SIDE=BOTTOM SILK_PART=S5_ON

K

PLACE_SIDE=BOTTOM SILK_PART=STBY_ON

K

Q2090

IN

68 63 61 36 17 13

IN

36 13

IN

Q2090

Q2091

DMN5L06VK-7

DMN5L06VK-7

SOT-563

SOT-563

S4_PWR_EN PM_SLP_S4_L PM_SLP_S3_L PM_SLP_S0_L

S

1

5

G

S

2

4

MAKE_BASE=TRUE

IN

MAKE_BASE=TRUE

JTAG_ISP_TDI

JTAG_ISP_TCK

OUT

16 18 23

JTAG_ISP_TDI

OUT

16 18 23

18 8

TP_CPU_RSVDN61

18 8

TP_CPU_RSVDP61

TP_CPU_RSVDN61 MAKE_BASE=TRUE TP_CPU_RSVDP61 MAKE_BASE=TRUE

8 18

8 18

B

DBGLED

29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

PP3V3_S5 NOSTUFF

PLACE_SIDE=BOTTOM SILK_PART=S0_ON

BYPASS=U2030:3mm

C2030

DBGLED_S0_D

SOT-563

G

IN

23 18 16

2

GREEN-56MCD-2MA-2.65V LTQH9G-SM

K

DBGLED 3

JTAG_ISP_TCK

23 18 16

Pin N61 needs a TP for Power to perform iFDIM test Renaming the pins N61 and P61 to remove automatic diffpari property

1

D2095

DMN5L06VK-7

2

63 61 36 29 18 13

A

DBGLED_S0I3_D

D

63

DBGLED_S0

PLACE_SIDE=BOTTOM SILK_PART=S0I3_ON

K

DBGLED 6

2

GREEN-56MCD-2MA-2.65V LTQH9G-SM

PLACE_SIDE=BOTTOM SILK_PART=S3_ON

IN

20K

5% 1/20W MF 201

D2093

DBGLED_S3_D

D

R2095

DBGLED

A

GREEN-56MCD-2MA-2.65V LTQH9G-SM

DBGLED

IN

DBGLED

SDCONN_STATE_CHANGE_RIO

DBGLED 1

DBGLED_S0I3

D2092

DBGLED_S4_D

61 60 27 26

2

DBGLED_S3

NC

h

DBGLED

R2090

.c

5% 1/16W MF-LF 402

w

2

PLACE_SIDE=BOTTOM

D

G

6

1

RAM Configuration Straps

0.1UF

10% 10V X5R-CERM 2 0201

DBGLED

Q2091

D

3

Pull-downs for chip-down RAM systems

NOSTUFF CRITICAL

DMN5L06VK-7 SOT-563

w

PP3V3_S5

NC 5

GND

S

63 61 36 29 18 13

1

5

G

S

IN

15

IN

6 74LVC1G08

SOT891

PM_SLP_S4_L

2

CAMERA_PWR_EN_PCH

4 U2030 08 1

4

CAMERA_PWR_EN

NC

5

w

65 61 60 27 26 18 13 11 8 17 16 15 59 56 29 77 68

NOTE: This reference schematic assumes PCH JTAG GPIOs are only used for Thunderbolt. If other ASIC JTAG signals are wired into these GPIOs different isolation techniques will likely be necessary. Multi-router designs also require different circuitry.

B 1

in

Power State Debug LEDs

NOTE: Solution shown is for LPT-LP. Other PCH’s may require isolation on TCK and TDI as well for PCH glitch-prevention.

SOT891

A 2

BYPASS=U2030.5:5MM

To PCH

DBGLED

4 Y

a

OUT

3

16 15

74AUP1G09

OUT

31

16 15

OUT

16 15

OUT

16 15

OUT

16 15

OUT

XDP_MLB_RAMCFG0 XDP_MLB_RAMCFG1 XDP_MLB_RAMCFG2 XDP_MLB_RAMCFG3 RAMCFG3:L

R2050 3

NC

RAMCFG2:L

1

R2051

1

RAMCFG1:L

R2052

RAMCFG0:L 1

R2053

10K

10K

10K

10K

5% 1/20W MF 201

5% 1/20W MF 201

5% 1/20W MF 201

5% 1/20W MF 201

2

2

2

1

2

R2030 1

0

2

5% 1/20W MF 0201

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

Project Chipset Support DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

20 OF 120 SHEET

18 OF 78

1

A

FETs for CPU isolation during DAC margining

DDRVREF_DAC

2

G

Signal aliases required by this page: - =I2C_VREFDACS_SCL - =I2C_VREFDACS_SDA - =I2C_PCA9557D_SCL - =I2C_PCA9557D_SDA

100K

Q2220

1

DMN5L06VK-7

DDRVREF_DAC

SOT-563

VREFMRGN_DQ_A_EN_RC

2

1

D

5% 1/20W MF 201

CRITICAL DDRVREF_DAC

DDRVREF_DAC

5% 1/20W MF 201

C2225 10% 6.3V CERM-X5R 0201

Always used, regardless of margining option.

1

SOT-563 2

2 1

PLACE_NEAR=R2221.2:1mm

R2222

PLACE_NEAR=Q2220.6:2mm

0.022UF

CPU_DIMMB_VREFDQ_B_ISOL 2

DDRVREF_DAC

SOT-563

CRITICAL DDRVREF_DAC

G

73

CPU_DIMM_VREFCA_A_ISOL

2

DAC-Based Margining

10% 6.3V X5R-CERM 0201

MEM_VREFDQ_B_RC

Q2265

1

24.9

PLACE_NEAR=R2261.2:1mm

R2262

D

PLACE_NEAR=Q2260.6:2mm

1% 1/20W MF 201

C2260

1

R2207 DDRVREF_DAC

C2200

1

5% 1/20W MF 201

C2201

2.2UF 20% 6.3V CERM 402-LF

100K

DDRVREF_DAC 1

0.1UF 2

10% 6.3V CERM-X5R 0201

2

8

IN

SMBUS_PCH_CLK

6 SCL

BI

SMBUS_PCH_DATA

7 SDA

1

VREFMRGN_DQ_A

VOUTB

2

VREFMRGN_DQ_B

VOUTC

4

VREFMRGN_CA_AB

U2200 VOUTA

Addr=0x98(WR)/0x99(RD)

10 A1

VOUTD

1

1

2

332

1

2

R2266

332

1

2

R2286

VREFMRGN_MEMVREG

5

CRITICAL DDRVREF_DAC

5% 1/20W MF 201

PCA9557

4 5

72 68 63 39 19 16 14

IN BI

SMBUS_PCH_CLK SMBUS_PCH_DATA

1 2

A0 A1 A2

SCL SDA THRM 17

PAD

NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles. 18

IN

RESET* GND

7 9 10 11 12 13 14

5

G

1% 1/20W MF 201

PLACE_NEAR=Q2220.3:4mm 21 65 73

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

1

1/20W 1/20W

MF MF

201

PLACE_NEAR=Q2265.4:2.54mm

1%

1/20W

MF

2

R2280

MEM_VREFCA_B_RC

1

24.9

2

PLACE_NEAR=Q2265.1:2.54mm 1% 1/20W MF 201

201 PLACE_NEAR=Q2225.4:2.54mm

201

PP3V3_S3

15 18 19 39 42 60 65 68

CRITICAL DDRVREF_DAC

1

B

0.1UF 10% 6.3V CERM-X5R 0201

2

B1 C2

V+

R2214

MAX4253 UCSP C1

C3

DDRVREF_DAC

U2204

2

VREFMRGN_CPU_EN VREFMRGN_DQ_A_EN VREFMRGN_DQ_B_EN VREFMRGN_CA_A_EN VREFMRGN_CA_B_EN VREFMRGN_MEMVREG_EN VREFMRGN_SPARE_EN

6

1% 1/20W MF 201

10% 6.3V X5R-CERM 0201

2

PLACE_NEAR=Q2225.1:2.54mm

VREFMRGN_CA_B_RDIV

2

VREFMRGN_MEMVREG_BUF

33.2K 1

V-

R2213

NC

OUT

55

1

100K 5% 1/20W MF 201

DDRREG_FB PLACE_NEAR=R7415.2:1mm

CRITICAL DDRVREF_DAC

DDRVREF_DAC

15

2 1% 1/20W MF 201

C4 B4

B1 A2

V+

U2204 MAX4253 UCSP

2

w

RST* on ’platform reset’ so that system watchdog will disable margining.

1

C2205

8

3

P0 P1 P2 P3 P4 P5 P6 P7

R2282

C2280

R22x6 pin 2:

201

DDRVREF_DAC

w

(OD)

Addr=0x30(WR)/0x31(RD)

332

MF

VREFMRGN_CA_A_RDIV 1%

100K

QFN

PLACE_NEAR=R2281.2:1mm

0.022UF 1/20W

VREFMRGN_DQ_B_RDIV 1%

R2200 1

U2201

2

R2281

PP0V675_S3_MEM_VREFCA_B

2 5% 1/20W MF 201

VREFMRGN_DQ_A_RDIV

h

NOTE: MEMVREG and SPARE share a DAC output, cannot enable both at the same time!

VCC

0.1UF 10% 6.3V CERM-X5R 0201

72 68 63 39 19 16 14

332

R2246

.c

C2202

16

DDRVREF_DAC

2

2 1

2

PLACE_NEAR=Q2220.3:2mm

w

B

2

1K

R2283

1

1%

GND 3

24.9

1

1% 1/20W MF 201

SOT-563

(All 4 R’s) DDRVREF_DAC

R2226

in

9 A0

1

DMN5L06VK-7

2

MSOP

DAC5574

63 39 19 16 14 72 68

10% 6.3V CERM-X5R 0201

C

2

R2260

MEM_VREFCA_A_RC

Q2225

1

0.1UF

20 65 73

1K

CRITICAL DDRVREF_DAC

VDD 63 39 19 16 14 72 68

C2285

10% 6.3V X5R-CERM 0201

2

D

NONE NONE NONE 402

1

DDRVREF_DAC

5% 1/20W MF 201

PLACE_NEAR=Q2260.6:4mm

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

1

3

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

DDRVREF_DAC

VREFMRGN_CA_B_EN_RC

1% 1/20W MF 201

1K

PLACE_NEAR=Q2260.6:2.54mm

CRITICAL DDRVREF_DAC

R2261

PP0V675_S3_MEM_VREFCA_A

2 5% 1/20W MF 201

S

PP3V3_S3_VREFMRGN_DAC

2

2

2

2 1

2

4

100K 1

1 2

1K

SOT-563

CPU_DIMM_VREFCA_B_ISOL

fi

1

SHORT

2

1% 1/20W MF 201

DMN5L06VK-7

R2263

x

R2285

R2218

PP3V3_S3

a

42 39 19 18 15 68 65 60

73

DDRVREF_DAC

21 65 73

R2240

0.022UF

DAC sets voltage level, PCA9557 & FETs enable outputs and disables margining after platform reset. OMIT

PLACE_NEAR=Q2260.3:4mm

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

1

6

10% 6.3V CERM-X5R 0201

1% 1/20W MF 201

C2240

1

0.1UF

3

D

5% 1/20W MF 201

R2242

0.022UF

S

C2265

100K

SOT-563

4

1

.c

R2215

DMN5L06VK-7

DDRVREF_DAC

5% 1/20W MF 201

1% 1/20W MF 201

1K

1

DDRVREF_DAC

Q2220

S

G

5

CRITICAL

VREFMRGN_CA_A_EN_RC

2

2

100K

R2241

PP0V675_S3_MEM_VREFDQ_B PLACE_NEAR=R2241.2:1mm

PLACE_NEAR=Q2260.3:2mm 1

CRITICAL DDRVREF_DAC

G

o

R2265 1

2

2 5% 1/20W MF 201

2

DDRVREF_DAC

NOTE: CPU has single output for VREFCA. Split into two signals for independent DAC margining support. When DAC margining VREFCA ensure VREFMRGN_CPU_EN is low to remove short due to CPU.

1 2

3

S

2

SOT-563

24.9

2 1

2

DMN5L06VK-7

D 2

1K

R2243

6

CPU_DIMM_VREFCA

10% 6.3V CERM-X5R 0201

20 65 73

1

1% 1/20W MF 201

SOT-563

1

0.1UF

D

2

G

Q2260

1

IN

5% 1/20W MF 201

CRITICAL

S

73 7

C2245

100K

1

DMN5L06VK-7

4

R2202

step sizes: 7.70mV per step 6.99mV per step ?.??mV per step

DDRVREF_DAC

5% 1/20W MF 201

1

PLACE_NEAR=Q2220.6:4mm

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

R2220

MEM_VREFDQ_A_RC

Q2265

m

DDRVREF_DAC NOTE: CPU DAC output DDR3 (1.5V) DDR3L (1.35V) LPDDR3 (1.2V)

VREFMRGN_DQ_B_EN_RC

2

5

D

100K 1

3

4

IN

S

R2245 CPU_DIMMB_VREFDQ

10% 6.3V X5R-CERM 0201

D

G

5

CRITICAL

73 7

1% 1/20W MF 201

C2220

1

DMN5L06VK-7

1% 1/20W MF 201

1K

PLACE_NEAR=Q2220.6:2.54mm

73

R2221

PP0V675_S3_MEM_VREFDQ_A

2 5% 1/20W MF 201

2

2

Q2260

17 20 21 22 41 55 65 73

1K

DMN5L06VK-7

R2223

BOM options provided by this page: - DDRVREF_DAC - Stuffs DAC margining circuit.

C

PP1V35_S3

Q2225

1

0.1UF

100K

6

CPU_DIMMA_VREFDQ 1

IN

S

R2201 73 7

EN RC’s to avoid drain glitches May not be necessary due to C22x0

R2225

CRITICAL

1

VRef Dividers

CPU_DIMMA_VREFDQ_A_ISOL

D

73

2

3

6

CPU-Based Margining

Power aliases required by this page: - =PP3V3_S3_VREFMRGN - =PPDDR_S3_MEMVREF

D

4

2

Page Notes

5

G

6

S

7

1

8

A1

A3

VREFMRGN_SPARE_BUF DDRVREF_DAC

A4

V-

1

B4

R2217 1M

Pins B1 & B4: CKPLUS_WAIVE=unconnected_pins

PCA9557D_RESET_L

2

DDRVREF_DAC

5% 1/20W MF 201

R2212 1 100K

A

MEM A VREF DQ DAC Channel:

MEM B VREF DQ B

A

PCA9557D Pin:

1

MEM B VREF CA

C

2

4

5

LPDDR3 (1.2V)

0.675V (DAC: 0x34)

DDR3L (1.35V)

1.200V (DAC: 0x5D)

1.343V (DAC: 0x68)

0.300V - 0.900V (+/- 300mV)

0.337V - 1.013V (+/- 337.5mV)

0.800V - 1.600V (+/- 400mV)

0.972V - 1.714V (+/- 371mV)

0.000V - 1.199V (0x00 - 0x5D)

0.000V - 1.354V (0x00 - 0x69)

0.000V - 2.397V (0x00 - 0xBA)

0.000V - 2.694V (0x00 - 0xD1)

DAC step size:

(- = sourced)

+82uA - -82uA

6.36mV / step @ output

8

(- = sourced)

+21uA -

6.36mV / step @ output

7

-21uA (- = sourced)

+25uA -

4.28mV / step @ output

6

DRAWING NUMBER

NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

Apple Inc.

REVISION

R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

-25uA (- = sourced)

3.53mV / step @ output

5

SYNC_DATE=08/12/2013

DDR3 VREF MARGINING

DAC range:

+73uA - -73uA

SYNC_MASTER=J44 PAGE TITLE

Margined target:

VRef current:

2

D

DDR3L (1.35V)

0.600V (DAC: 0x2E.5)

5% 1/20W MF 201

MEM VREG

C

3

LPDDR3 (1.2V) Nominal value

MEM A VREF CA

4

3

2

BRANCH

PAGE

22 OF 120 SHEET

19 OF 78

1

SIZE

D

A

8 PP1V35_S3

5

PP0V675_S3_MEM_VREFCA_A PP0V675_S3_MEM_VREFDQ_A

73 65 20 19 73 65 20 19

73 65 55 41 22 21 20 19 17

73 66 22 20 73 66 22 20 7 73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20

73 66 22 20 73 66 22 20 7 73 66 22 20

73 66 22 20 7 73 66 22 20 7 73 66 22 20 7

73 22 20 7 73 22 20 7

73 22 20 7 73 22 20 7

FBGA

NC

MT41K256M16HA-125:E OMIT_TABLE

BA0 BA1 BA2 RAS* CAS* WE*

J7 CK MEM_A_CLK_P<0> K7 CK* MEM_A_CLK_N<0> CKE CS*

K1 MEM_A_ODT<0>

ODT

MEM_A_ZQ<0>L8

ZQ

73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20

E3 =MEM_A_DQ<0> 67 F7 =MEM_A_DQ<1> 67 F2 =MEM_A_DQ<2> 67 F8 =MEM_A_DQ<3> 67 H3 =MEM_A_DQ<4> 67 H8 =MEM_A_DQ<5> 67 G2 =MEM_A_DQ<6> 67 H7 =MEM_A_DQ<7> 67 D7 =MEM_A_DQ<8> 67 C3 =MEM_A_DQ<9> 67 C8 =MEM_A_DQ<10> 67 C2 =MEM_A_DQ<11> 67 A7 =MEM_A_DQ<12> 67 A2 =MEM_A_DQ<13> 67 B8 =MEM_A_DQ<14> 67 A3 =MEM_A_DQ<15> 67

73 66 22 20 7 73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20

73 66 22 20 73 66 22 20 7 73 66 22 20

73 66 22 20 7

F3 =MEM_A_DQS_P<0> G3 =MEM_A_DQS_N<0>

73 66 22 20 7

C7 =MEM_A_DQS_P<1> B7 =MEM_A_DQS_N<1>

67

73 22 20 7

67

73 22 20 7

E7 D3

73 22 20

H1 VREFDQ

M8 VREFCA

RAS* CAS* WE*

K9 MEM_A_CKE<0> L2 MEM_A_CS_L<0>

CKE CS*

K1 MEM_A_ODT<0>

ODT

MEM_A_ZQ<1>L8

ZQ

LDQS LDQS* UDQS UDQS*

LDM UDM

VSSQ

VSS

0.047UF

SDRAM BYPASSING (NOTE: 4X 2.2UF AND 6X 0.1UF PER CHIP) PP1V35_S3

73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20

73 66 22 20 73 66 22 20 7 73 66 22 20

73 66 22 20 7 73 66 22 20 7 73 66 22 20 7

73 22 20 7 73 22 20 7

73 22 20 7 73 22 20 7

73 22 20

MEM_A_BA<0>M2 MEM_A_BA<1>N8 MEM_A_BA<2>M3 MEM_A_RAS_LJ3 MEM_A_CAS_LK3 MEM_A_WE_L L3

NC

MT41K256M16HA-125:E OMIT_TABLE

RAS* CAS* WE*

CKE CS*

K1 MEM_A_ODT<0>

ODT

E3 =MEM_A_DQ<32> F7 =MEM_A_DQ<33> F2 =MEM_A_DQ<34> F8 =MEM_A_DQ<35> H3 =MEM_A_DQ<36> H8 =MEM_A_DQ<37> G2 =MEM_A_DQ<38> H7 =MEM_A_DQ<39> D7 =MEM_A_DQ<40> C3 =MEM_A_DQ<41> C8 =MEM_A_DQ<42> C2 =MEM_A_DQ<43> A7 =MEM_A_DQ<44> A2 =MEM_A_DQ<45> B8 =MEM_A_DQ<46> A3 =MEM_A_DQ<47>

73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20 73 66 22 20

67

73 66 22 20 7

67

73 66 22 20

67

73 66 22 20

67

73 66 22 20

67

73 66 22 20

67

73 66 22 20

67

73 66 22 20

67

73 66 22 20

67

73 66 22 20

67

73 66 22 20

67

73 66 22 20 7

67

73 66 22 20

67 67

73 66 22 20 7

67

73 66 22 20 7

F3 =MEM_A_DQS_P<4> G3 =MEM_A_DQS_N<4>

67 67

73 22 20 7

73 22 20 7

UDQS UDQS*

C7 =MEM_A_DQS_P<5> B7 =MEM_A_DQS_N<5>

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

D C2300 1 C2301 1 C2310 1

C2311 1 C2320 1 C2321 1

C2330 1 C2331 1

20% 10V X5R-CERM 2 402

20% 10V X5R-CERM 2 402

20% 10V X5R-CERM 2 402

2.2UF

E3 =MEM_A_DQ<16> F7 =MEM_A_DQ<17> F2 =MEM_A_DQ<18> F8 =MEM_A_DQ<19> H3 =MEM_A_DQ<20> H8 =MEM_A_DQ<21> G2 =MEM_A_DQ<22> H7 =MEM_A_DQ<23> D7 =MEM_A_DQ<24> C3 =MEM_A_DQ<25> C8 =MEM_A_DQ<26> C2 =MEM_A_DQ<27> A7 MEM_A_DQ<32> 7 A2 =MEM_A_DQ<29> B8 =MEM_A_DQ<30> A3 =MEM_A_DQ<31>

67 67

BA0 BA1 BA2

MEM_A_RAS_LJ3 MEM_A_CAS_LK3 MEM_A_WE_L L3

RAS* CAS* WE*

67

73 22 20 7

H1

FBGA

NC

MT41K256M16HA-125:E OMIT_TABLE

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

J7 CK MEM_A_CLK_P<0> K7 CK* MEM_A_CLK_N<0>

E7 D3

73 22 20

CKE CS*

K1 MEM_A_ODT<0>

ODT

MEM_A_ZQ<3>L8

ZQ

2.2UF

2.2UF

67

67

R2360

C2351 1 C2360 1 C2361 1

C2370 1 C2371 1

20% 10V X5R-CERM 2 402

20% 10V X5R-CERM 2 402

2.2UF

2.2UF

20% 10V X5R-CERM 2 402

67 67 67 67 67

1

67 68 73 67 67 67

C2303 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2343 0.1UF

C7 =MEM_A_DQS_P<3> 67 B7 =MEM_A_DQS_N<3> 67

10% 2 6.3V CERM-X5R 0201

E7 D3

1

2.2UF

20% 10V X5R-CERM 2 402

1

C2304 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2344 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2305 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2345 0.1UF

10% 2 6.3V CERM-X5R 0201

2.2UF

1

C2313 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2353 0.1UF

10% 2 6.3V CERM-X5R 0201

2.2UF

20% 10V X5R-CERM 2 402

1

C2314 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2354 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2315 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2355 0.1UF

10% 2 6.3V CERM-X5R 0201

2.2UF

20% 10V X5R-CERM 2 402

1

C2323 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2363 0.1UF

10% 2 6.3V CERM-X5R 0201

C2325 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2365 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2333 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2373 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2334 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2374 0.1UF

10% 2 6.3V CERM-X5R 0201

1

7

6

C2324 0.1UF

10% 6.3V 2 CERM-X5R 0201

1

C2364 0.1UF

10% 6.3V 2 CERM-X5R 0201

C2335 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2375 0.1UF

10% 2 6.3V CERM-X5R 0201

C2368 1 10% 6.3V 2 X5R 201

J1 NC J9 NC L1 NC L9 NC M7 NC

1

C2369

0.047UF

10% 2 6.3V X5R 201

E3 =MEM_A_DQ<48> F7 =MEM_A_DQ<49> F2 =MEM_A_DQ<50> F8 =MEM_A_DQ<51> H3 =MEM_A_DQ<52> H8 =MEM_A_DQ<53> G2 =MEM_A_DQ<54> H7 =MEM_A_DQ<55> D7 =MEM_A_DQ<56> C3 =MEM_A_DQ<57> C8 =MEM_A_DQ<58> C2 =MEM_A_DQ<59> A7 =MEM_A_DQ<60> A2 =MEM_A_DQ<61> B8 =MEM_A_DQ<62> A3 =MEM_A_DQ<63>

B 67 67 67 67 67 67 67 67 67 67 67 67 67 67 67 67

LDQS LDQS* UDQS UDQS*

C7 =MEM_A_DQS_P<7> 67 B7 =MEM_A_DQS_N<7> 67

67 73 67 73

E7 D3

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

PAGE TITLE

DDR3 SDRAM Bank A (Rank 0) DRAWING NUMBER

Apple Inc.

VSS

5

4

3

2

SIZE

D REVISION

R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

1

C

2

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

2.2UF

20% 10V X5R-CERM 2 402

T2 RESET* MEM_RESET_L VSSQ

1% 1/20W MF 201

2

B1 B9 D1 D8 E2 E8 F9 G1 G9

1% 1/20W MF 201

240

VSS

VSSQ

22 21 20 70

2.2UF

20% 10V X5R-CERM 2 402

20% 10V X5R-CERM 2 402

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

T2 RESET* MEM_RESET_L

2.2UF

20% 10V X5R-CERM 2 402

C2340 1 C2341 1 C2350 1 2.2UF

67

F3 MEM_A_DQS_P<6> 7 G3 MEM_A_DQS_N<6> 7

LDM UDM

B1 B9 D1 D8 E2 E8 F9 G1 G9

22 21 20 70

2.2UF

20% 10V X5R-CERM 2 402

1

1

ZQ

K9 MEM_A_CKE<0> L2 MEM_A_CS_L<0>

2.2UF

20% 10V X5R-CERM 2 402

67

F3 =MEM_A_DQS_P<2> 67 G3 =MEM_A_DQS_N<2> 67

0.047UF

4GB-DDR3L-1600-256MX16

MEM_A_BA<0>M2 MEM_A_BA<1>N8 MEM_A_BA<2>M3

2.2UF

20% 10V X5R-CERM 2 402

67

a

U2360

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

67

73 22 20 7

LDM UDM

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14>

67

73 66 22 20 7

LDQS LDQS*

VDD

VDDQ

VREFDQ

10% 6.3V 2 X5R 201

73 66 22 20

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

BA0 BA1 BA2

K9 MEM_A_CKE<0> L2 MEM_A_CS_L<0>

J1 NC J9 NC L1 NC L9 NC M7 NC

0.047UF

h

H1

M8

FBGA

J7 CK MEM_A_CLK_P<0> K7 CK* MEM_A_CLK_N<0>

MEM_A_ZQ<2>L8

VREFDQ

4GB-DDR3L-1600-256MX16

20% 4V CERM-X5R-1 2 201

C2349

.c

73 66 22 20 73 66 22 20 7

U2340

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

10% 6.3V 2 X5R 201

1

w

73 66 22 20

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

0.47UF

C2348 1

0.047UF

17 19 20 21 22 41 55 65 73

PP0V675_S3_MEM_VREFCA_A PP0V675_S3_MEM_VREFDQ_A

in

73 65 20 19

w

73 66 22 20

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14>

VREFCA

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

VDD

VDDQ

73 66 22 20

73 65 20 19

C2367 1

20% 4V CERM-X5R-1 2 201

73 66 22 20

PP1V35_S3

M8

73 65 55 41 22 21 20 19 17

VREFCA

PP0V675_S3_MEM_VREFCA_A PP0V675_S3_MEM_VREFDQ_A

73 65 20 19

B2 D9 G7 K2 K8 N1 N9 R1 R9

PP1V35_S3

0.47UF

73 66 22 20

1

C2329

10% 2 6.3V X5R 201

2

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

2

B1 B9 D1 D8 E2 E8 F9 G1 G9

T2 RESET* MEM_RESET_L

1% 1/20W MF 201

C2347 1

240

BA0 BA1 BA2

J7 CK MEM_A_CLK_P<0> K7 CK* MEM_A_CLK_N<0>

22 21 20 70

240

VSS

73 65 20 19

R2340

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

1

fi

R2320 VSSQ

73 65 55 41 22 21 20 19 17

A

J1 NC J9 NC L1 NC L9 NC M7 NC

NC

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

T2 RESET* MEM_RESET_L

1% 1/20W MF 201

B

FBGA

MT41K256M16HA-125:E OMIT_TABLE

B1 B9 D1 D8 E2 E8 F9 G1 G9

22 21 20 70

240

MEM_A_RAS_LJ3 MEM_A_CAS_LK3 MEM_A_WE_L L3

10% 6.3V 2 X5R 201

4GB-DDR3L-1600-256MX16

A1 A8 C1 C9 D2 E9 F1 H2 H9

R2300

MEM_A_BA<0>M2 MEM_A_BA<1>N8 MEM_A_BA<2>M3

U2320

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

67

73 22 20 7

LDM UDM

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

67

73 22 20 7

UDQS UDQS*

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14>

C2328 1

0.047UF

1

K9 MEM_A_CKE<0> L2 MEM_A_CS_L<0>

73 66 22 20

73 66 22 20 7

LDQS LDQS*

VDD

VDDQ

73 66 22 20

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

B2 D9 G7 K2 K8 N1 N9 R1 R9

H1

M8

4GB-DDR3L-1600-256MX16

10% 6.3V 2 X5R 201

1

73 22 20

MEM_A_RAS_LJ3 MEM_A_CAS_LK3 MEM_A_WE_L L3

J1 NC J9 NC L1 NC L9 NC M7 NC

0.047UF

w

C

MEM_A_BA<0>M2 MEM_A_BA<1>N8 MEM_A_BA<2>M3

10% 6.3V 2 X5R 201

20% 4V CERM-X5R-1 2 201

C2309

m

73 66 22 20

0.047UF

1

o

73 66 22 20

U2300

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

0.47UF

C2308

1

.c

73 66 22 20

2

PP0V675_S3_MEM_VREFCA_A PP0V675_S3_MEM_VREFDQ_A

x

73 66 22 20

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

VREFDQ

VDD

VDDQ

VREFCA

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

20% 4V CERM-X5R-1 2 201

D

73 65 20 19

3

C2327 1

0.47UF

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14>

PP1V35_S3

73 65 20 19

C2307 1

73 66 22 20

4

A1 A8 C1 C9 D2 E9 F1 H2 H9

73 65 55 41 22 21 20 19 17

6

7

BRANCH

PAGE

23 OF 120 SHEET

20 OF 78

1

A

8 PP1V35_S3

73 65 21 19 73 65 21 19

6

5

PP0V675_S3_MEM_VREFCA_B PP0V675_S3_MEM_VREFDQ_B

73 65 55 41 22 21 20 19 17

73 66 22 21 73 66 22 21 7 73 66 22 21 73 66 22 21 73 66 22 21 73 66 22 21 73 66 22 21 73 66 22 21 73 66 22 21 73 66 22 21

73 66 22 21 73 66 22 21 7 73 66 22 21

73 66 22 21 7 73 66 22 21 7 73 66 22 21 7

73 22 21 7 73 22 21 7

73 22 21 7 73 22 21 7

FBGA

NC

MT41K256M16HA-125:E OMIT_TABLE

BA0 BA1 BA2 RAS* CAS* WE*

J7 CK MEM_B_CLK_P<0> K7 CK* MEM_B_CLK_N<0> CKE CS*

K1 MEM_B_ODT<0>

ODT

MEM_B_ZQ<0>L8

ZQ

73 66 22 21 73 66 22 21 73 66 22 21 73 66 22 21

E3 =MEM_B_DQ<0> 67 F7 =MEM_B_DQ<1> 67 F2 =MEM_B_DQ<2> 67 F8 =MEM_B_DQ<3> 67 H3 =MEM_B_DQ<4> 67 H8 =MEM_B_DQ<5> 67 G2 =MEM_B_DQ<6> 67 H7 =MEM_B_DQ<7> 67 D7 =MEM_B_DQ<8> 67 C3 =MEM_B_DQ<9> 67 C8 =MEM_B_DQ<10> 67 C2 =MEM_B_DQ<11> 67 A7 =MEM_B_DQ<12> 67 A2 =MEM_B_DQ<13> 67 B8 =MEM_B_DQ<14> 67 A3 =MEM_B_DQ<15> 67

73 66 22 21 7 73 66 22 21 73 66 22 21 73 66 22 21 73 66 22 21 73 66 22 21 73 66 22 21 73 66 22 21 73 66 22 21

73 66 22 21 73 66 22 21 7 73 66 22 21

73 66 22 21 7 73 66 22 21 7

F3 =MEM_B_DQS_P<0> G3 =MEM_B_DQS_N<0> C7 =MEM_B_DQS_P<1> B7 =MEM_B_DQS_N<1>

67

73 22 21 7

67

73 22 21 7

E7 D3

73 22 21

H1 VREFDQ

M8 VREFCA

J1 NC J9 NC L1 NC L9 NC M7 NC

MEM_B_BA<0>M2 MEM_B_BA<1>N8 MEM_B_BA<2>M3

FBGA

NC

MT41K256M16HA-125:E OMIT_TABLE

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

BA0 BA1 BA2

MEM_B_RAS_LJ3 MEM_B_CAS_LK3 MEM_B_WE_L L3

RAS* CAS* WE*

LDQS LDQS*

J7 CK MEM_B_CLK_P<0> K7 CK* MEM_B_CLK_N<0>

UDQS UDQS*

K9 MEM_B_CKE<0> L2 MEM_B_CS_L<0>

CKE CS*

K1 MEM_B_ODT<0>

ODT

MEM_B_ZQ<1>L8

ZQ

LDM UDM

1

T2 RESET* MEM_RESET_L

R2520

T2 RESET* MEM_RESET_L VSSQ

1% 1/20W MF 201

0.047UF

SDRAM BYPASSING (NOTE: 4X 2.2UF AND 6X 0.1UF PER CHIP) PP1V35_S3

2.2UF

E3 =MEM_B_DQ<16> F7 =MEM_B_DQ<17> F2 =MEM_B_DQ<18> F8 =MEM_B_DQ<19> H3 =MEM_B_DQ<20> H8 =MEM_B_DQ<21> G2 =MEM_B_DQ<22> H7 =MEM_B_DQ<23> D7 =MEM_B_DQ<24> C3 =MEM_B_DQ<25> C8 =MEM_B_DQ<26> C2 =MEM_B_DQ<27> A7 =MEM_B_DQ<28> A2 =MEM_B_DQ<29> B8 =MEM_B_DQ<30> A3 =MEM_B_DQ<31>

VSS

67

73 66 22 21 73 66 22 21 73 66 22 21 73 66 22 21 73 66 22 21 73 66 22 21 73 66 22 21 73 66 22 21

73 66 22 21 73 66 22 21 7 73 66 22 21

73 66 22 21 7 73 66 22 21 7 73 66 22 21 7

73 22 21 7 73 22 21 7

73 22 21 7 73 22 21 7

MEM_B_RAS_LJ3 MEM_B_CAS_LK3 MEM_B_WE_L L3

RAS* CAS* WE*

K1 MEM_B_ODT<0>

ODT

MEM_B_ZQ<2>L8

ZQ

73 66 22 21

E3 =MEM_B_DQ<32> F7 =MEM_B_DQ<33> F2 =MEM_B_DQ<34> F8 =MEM_B_DQ<35> H3 =MEM_B_DQ<36> H8 =MEM_B_DQ<37> G2 =MEM_B_DQ<38> H7 =MEM_B_DQ<39> D7 =MEM_B_DQ<40> C3 =MEM_B_DQ<41> C8 =MEM_B_DQ<42> C2 =MEM_B_DQ<43> A7 MEM_B_DQ<32> 7 A2 =MEM_B_DQ<45> B8 =MEM_B_DQ<46> A3 =MEM_B_DQ<47>

67

73 66 22 21 7

67

73 66 22 21

67

73 66 22 21

67

73 66 22 21

67

73 66 22 21

67

73 66 22 21

67

73 66 22 21

67

73 66 22 21

67

73 66 22 21

67

C2540 1 C2541 1 C2550 1 C2551 1 2.2UF

67

67

73 66 22 21

67

73 66 22 21 7

67 68 73

73 66 22 21

67 67

73 66 22 21 7

67

73 66 22 21 7

h

H1

A1 A8 C1 C9 D2 E9 F1 H2 H9

H1

M8

F3 MEM_B_DQS_P<6> G3 MEM_B_DQS_N<6>

UDQS UDQS*

C7 =MEM_B_DQS_P<5> B7 =MEM_B_DQS_N<5>

BA0 BA1 BA2

MEM_B_RAS_LJ3 MEM_B_CAS_LK3 MEM_B_WE_L L3

RAS* CAS* WE*

FBGA

NC

MT41K256M16HA-125:E OMIT_TABLE

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

7 67 73 7 67 73

73 22 21 7 73 22 21 7

J7 CK MEM_B_CLK_P<0> K7 CK* MEM_B_CLK_N<0>

67 67

73 22 21 7 73 22 21 7

E7 D3

73 22 21

K9 MEM_B_CKE<0> L2 MEM_B_CS_L<0>

CKE CS*

K1 MEM_B_ODT<0>

ODT

MEM_B_ZQ<3>L8

ZQ

2.2UF

20% 10V X5R-CERM 2 402

67 67 67 67 67 67 67 67 67

2.2UF

2.2UF

20% 10V X5R-CERM 2 402

20% 10V X5R-CERM 2 402

2.2UF

1

C2503 0.1UF

10% 6.3V 2 CERM-X5R 0201

1

C2504 0.1UF

10% 2 6.3V CERM-X5R 0201

C2560 1 C2561 1 C2570 1 C2571 1

2.2UF

20% 10V X5R-CERM 2 402

20% 10V X5R-CERM 2 402

2.2UF

20% 10V X5R-CERM 2 402

1

C2505 0.1UF

10% 2 6.3V CERM-X5R 0201

2.2UF

20% 10V X5R-CERM 2 402

1

C2513 0.1UF

10% 2 6.3V CERM-X5R 0201

2.2UF

20% 10V X5R-CERM 2 402

1

C2514 0.1UF

10% 2 6.3V CERM-X5R 0201

2.2UF

20% 10V X5R-CERM 2 402

1

C2515 0.1UF

10% 2 6.3V CERM-X5R 0201

20% 10V X5R-CERM 2 402

1

C2523 0.1UF

10% 2 6.3V CERM-X5R 0201

T2 RESET* MEM_RESET_L

R2560

1

67

C2543 0.1UF

10% 6.3V 2 CERM-X5R 0201

67 67

1

C2544 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2545 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2553 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2554 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2555 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2563 0.1UF

10% 2 6.3V CERM-X5R 0201

8

7

6

1

C2564 0.1UF

10% 2 6.3V CERM-X5R 0201

C 1

C2525 0.1UF

10% 6.3V 2 CERM-X5R 0201

1

C2565

10% 6.3V 2 CERM-X5R 0201

C2568 1 10% 6.3V 2 X5R 201

J1 NC J9 NC L1 NC L9 NC M7 NC

1

1

C2533 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2573 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2534 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2574 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2535 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C2575 0.1UF

10% 2 6.3V CERM-X5R 0201

C2569

0.047UF

10% 6.3V 2 X5R 201

E3 =MEM_B_DQ<48> F7 =MEM_B_DQ<49> F2 =MEM_B_DQ<50> F8 =MEM_B_DQ<51> H3 =MEM_B_DQ<52> H8 =MEM_B_DQ<53> G2 =MEM_B_DQ<54> H7 =MEM_B_DQ<55> D7 =MEM_B_DQ<56> C3 =MEM_B_DQ<57> C8 =MEM_B_DQ<58> C2 =MEM_B_DQ<59> A7 =MEM_B_DQ<60> A2 =MEM_B_DQ<61> B8 =MEM_B_DQ<62> A3 =MEM_B_DQ<63>

B 67 67 67 67 67 67 67 67 67 67 67 67 67 67 67 67

LDQS LDQS*

F3 =MEM_B_DQS_P<6> G3 =MEM_B_DQS_N<6>

UDQS UDQS*

C7 =MEM_B_DQS_P<7> B7 =MEM_B_DQS_N<7>

LDM UDM

67 67

67 67

E7 D3

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

PAGE TITLE

DDR3 SDRAM BANK B (RANK 0)

T2 RESET* MEM_RESET_L

Apple Inc. VSSQ

1% 1/20W MF 201

0.1UF

67

VSS

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

5

4

3

2

SIZE

D REVISION

R

NOTICE OF PROPRIETARY PROPERTY:

2

B1 B9 D1 D8 E2 E8 F9 G1 G9

VSS

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

VSSQ

1% 1/20W MF 201

C2524

10% 2 6.3V CERM-X5R 0201

DRAWING NUMBER 22 21 20 70

240

1

67

C7 =MEM_B_DQS_P<3> B7 =MEM_B_DQS_N<3>

0.047UF

4GB-DDR3L-1600-256MX16

MEM_B_BA<0>M2 MEM_B_BA<1>N8 MEM_B_BA<2>M3

2.2UF

20% 10V X5R-CERM 2 402

20% 10V X5R-CERM 2 402

67

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

22 21 20 70

240

U2560

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

B1 B9 D1 D8 E2 E8 F9 G1 G9

R2540

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

67

LDQS LDQS*

LDM UDM

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14>

2.2UF

20% 10V X5R-CERM 2 402

1

CKE CS*

73 66 22 21

73 66 22 21 7

J7 CK MEM_B_CLK_P<0> K7 CK* MEM_B_CLK_N<0> K9 MEM_B_CKE<0> L2 MEM_B_CS_L<0>

73 66 22 21

1

73 22 21

BA0 BA1 BA2

73 66 22 21 73 66 22 21

73 66 22 21

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

VDD

VDDQ

2

A

MEM_B_BA<0>M2 MEM_B_BA<1>N8 MEM_B_BA<2>M3

NC

10% 6.3V 2 X5R 201

2.2UF

20% 10V X5R-CERM 2 402

67

a 73 66 22 21 7

FBGA

MT41K256M16HA-125:E OMIT_TABLE

J1 NC J9 NC L1 NC L9 NC M7 NC

0.047UF

.c

73 66 22 21

4GB-DDR3L-1600-256MX16

20% 4V CERM-X5R-1 2 201

C2549

C2520 1 C2521 1 C2530 1 C2531 1

PP0V675_S3_MEM_VREFCA_B PP0V675_S3_MEM_VREFDQ_B

w

73 66 22 21

U2540

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

10% 6.3V 2 X5R 201

1

w

73 66 22 21

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

0.47UF

C2548 1

0.047UF

w

73 66 22 21

B

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14>

VREFDQ

VDD

VDDQ

VREFCA

A1 A8 C1 C9 D2 E9 F1 H2 H9

20% 4V CERM-X5R-1 2 201

B2 D9 G7 K2 K8 N1 N9 R1 R9

C2567 1

0.47UF

73 66 22 21

73 65 21 19 73 65 21 19

C2547 1

73 66 22 21

PP1V35_S3

2.2UF

20% 10V X5R-CERM 2 402

0.1UF

VREFDQ

73 65 55 41 22 21 20 19 17

M8

PP0V675_S3_MEM_VREFCA_B PP0V675_S3_MEM_VREFDQ_B

VREFCA

73 65 21 19

in

73 65 21 19

B2 D9 G7 K2 K8 N1 N9 R1 R9

PP1V35_S3

2.2UF

20% 10V X5R-CERM 2 402

67

F3 =MEM_B_DQS_P<2> G3 =MEM_B_DQS_N<2>

E7 D3

D

17 19 20 21 22 41 55 65 73

C2500 1 C2501 1 C2510 1 C2511 1

2

2

B1 B9 D1 D8 E2 E8 F9 G1 G9

22 21 20 70

240

VSS

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

VSSQ

1% 1/20W MF 201

73 65 55 41 22 21 20 19 17

1

C2529

10% 6.3V 2 X5R 201

fi

22 21 20 70

240

10% 6.3V 2 X5R 201

4GB-DDR3L-1600-256MX16

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

R2500

U2520

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

67

73 22 21 7

LDM UDM

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

67

73 22 21 7

UDQS UDQS*

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14>

C2528 1

0.047UF

1

K9 MEM_B_CKE<0> L2 MEM_B_CS_L<0>

73 66 22 21

73 66 22 21 7

LDQS LDQS*

VDD

VDDQ

73 66 22 21

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

B2 D9 G7 K2 K8 N1 N9 R1 R9

H1

M8

4GB-DDR3L-1600-256MX16

10% 6.3V 2 X5R 201

1

73 22 21

MEM_B_RAS_LJ3 MEM_B_CAS_LK3 MEM_B_WE_L L3

J1 NC J9 NC L1 NC L9 NC M7 NC

0.047UF

B1 B9 D1 D8 E2 E8 F9 G1 G9

C

MEM_B_BA<0>M2 MEM_B_BA<1>N8 MEM_B_BA<2>M3

10% 6.3V 2 X5R 201

20% 4V CERM-X5R-1 2 201

C2509

m

73 66 22 21

0.047UF

1

o

73 66 22 21

U2500

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

0.47UF

C2508

1

.c

73 66 22 21

2

PP0V675_S3_MEM_VREFCA_B PP0V675_S3_MEM_VREFDQ_B

x

73 66 22 21

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

VREFDQ

VDD

VDDQ

VREFCA

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

20% 4V CERM-X5R-1 2 201

D

73 65 21 19

3

C2527 1

0.47UF

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14>

PP1V35_S3

73 65 21 19

C2507 1

73 66 22 21

4

A1 A8 C1 C9 D2 E9 F1 H2 H9

73 65 55 41 22 21 20 19 17

7

BRANCH

PAGE

25 OF 120 SHEET

21 OF 78

1

A

8

7

6

5

4

2

3

Memory CMD/CTL Termination - Channel A 73 68 65 55 22

73 66 20 7

IN

73 66 20 7

IN

73 66 20 7

IN

73 66 20 73 66 20

MEM_ODT:PU

R2782 73 20

IN

MEM_A_ODT<0> (Connects to DRAM)

MEM_ODT:CPU

MAKE_BASE=TRUE

66 7

IN

36

1

R2781

1

1

MEM_A_ODT_CPU0 (Connects to CPU)

0.00 2

1% 1/20W MF PLACE_NEAR=U0500.AP32:8MM 0201

36

73 66 20

IN IN

73 66 20 7

2

5% 1/20W MF 201

73 21

IN

MEM_B_ODT<0> (Connects to DRAM)

1

MEM_ODT:CPU

MAKE_BASE=TRUE

IN IN

73 66 20

IN

66 7

IN

R2791

0.00 2 1

MEM_B_ODT_CPU0 (Connects to CPU)

1

1% 1/20W MF 0201

PLACE_NEAR=U0500.AL32:8MM

36

IN

73 66 20

IN

73 66 20

IN

73 66 20 73 66 20

IN IN

MEM_A_A<0> MEM_A_A<2> MEM_A_A<9> MEM_A_A<13>

RP2705 RP2706 RP2706 RP2706

MEM_A_BA<1> MEM_A_A<4> MEM_A_A<6> MEM_A_A<8>

RP2705

MEM_A_A<10>

36 36 36 36 36 36 36 36

36 36 36 36 36

1

8

2

7

5%

1/32W

4X0201

3

6

5%

1/32W

4X0201

4

5

5%

1/32W

4X0201

1

2

5% 1/20W MF 201

C

73 20 7

IN

73 66 20

IN

73 66 20

IN

73 66 20

IN

73 66 20

IN

7

3

6

4

5

1

8

2

7

3

6

4

5

2

IN

5%

1/32W

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

RP2705 RP2707 RP2707 RP2707

MEM_A_A<12> MEM_A_A<1> MEM_A_A<11> MEM_A_A<14>

36 36 36 36

4

5

2

7

3

6

4

MEM_A_CS_L<0> MEM_A_BA<0> MEM_A_A<3> MEM_A_A<5> MEM_A_A<7>

MEM_A_CKE<0>

5% 5%

1/32W

5

1

C2702

1/32W

4X0201

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

36 36 36 36

3

6

4

5

1

8

5%

1/32W

4X0201

1

8

5%

1/32W

4X0201

5%

1/32W

4X0201

RP2704

36

4

5

1/32W

4X0201

5%

1/32W

4X0201

1/32W

2

2

20% 4V CERM-X5R-1 201

1

C2704

1

C2705

1

NC

8

NC

5% 1/32W 4X0201

RP2701

2

0.47UF

0.47UF

20% 4V CERM-X5R-1 201

20% 4V CERM-X5R-1 201

2

36

1

NC

8

NC

5% 1/32W 4X0201

RP2704 36 3

NC 1

1

C2706

1

0.47UF

0.47UF

20% 4V CERM-X5R-1 201

20% 4V CERM-X5R-1 201

2

6

C2707

NC

5% 1/32W 4X0201

22 7

IN

22 7

IN

NC_MEM_A_CS_L1 NC_MEM_A_CKE1

22 7

IN

NC_MEM_A_A15

C2708 0.47UF

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_A_CS_L1

7 22

NC_MEM_A_CKE1

7 22

NC_MEM_A_A15

7 22

20% 4V CERM-X5R-1 201

C

RP2705 4X0201

36 3

NC 1

C2710

fi

6

NC

5% 1/32W 4X0201

0.47UF 2

Memory Reset Pull Up

C2703

20% 4V CERM-X5R-1 201

2

5%

NC

36 1

0.47UF

7 5%

7 5% 1/32W 4X0201

0.47UF

2

36

RP2701 RP2701 RP2707 RP2706

2

NC

RP2704

4X0201

RP2701

2

2

20% 4V CERM-X5R-1 201

D

36

C2700 0.47UF

4X0201

5%

7

RP2704 1

x

73 20 7

8

2

2

5% 1/20W MF 201

MEM_ODT:CPU

R2790

IN

73 66 20

MEM_ODT:PU

36

IN

73 66 20 7

73 66 20

R2792

IN

73 66 20 73 66 20

5% 1/20W MF 201

MEM_ODT:CPU

R2780

2

IN

RP2702 RP2702 RP2702 RP2702 RP2703 RP2703 RP2703 RP2703

MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_BA<2>

o

D

73 65 55 41 22 21 20 19 17

PP0V675_S0_DDRVTT PP1V35_S3

.c

73 68 65 55 22

MEMORY RPACK SPARES

PP0V675_S0_DDRVTT

m

Memory ODT Option MEM_ODT:CPU drives ODT from CPU, terminated to 0.675V VTT. MEM_ODT:PU disconnect ODT from CPU, ODT pins on DRAM pulled up to 1.35V VDDQ.

1

20% 4V CERM-X5R-1 201

PP1V35_S3

a

Reset is an open drain in Haswell ULT and needs pull up

Memory CMD/CTL Termination - Channel B

17 19 20 21 22 41 55 65 73

1

in

R2710 470

1% 1/20W MF 2 201

R2711 1

MEM_RESET_L

2

5% 1/20W MF 0201

1

20 21 70

NO STUFF C2711

h

MEM_RESET_HSW_L

66 6

0

0.47UF 2

20% 4V CERM-X5R-1 201

Memory Clock Far-End Termination

Place Source C termination before first DRAM

Place RC end termination after last DRAM

w

Memory Clock Near-End Termination

.c

B

R2750 MEM_A_CLK_N<0>

73 22 20 7

C2750

IN

MEM_A_CLK_N<0>

30 1 5% 1/20W MF 201

1

3.3PF 5% 25V CERM 201 73 22 20 7

IN

2

2

R2751

MEM_A_CLK_P<0>

73 22 20 7

IN

MEM_A_CLK_P<0>

MEM_A_CLK0_TERM_R

w

IN

C2751 0.1UF 1

2

2

73 22 21 7

IN

73 22 21 7

C2760

A

IN

30 1

1

5% 1/20W MF 201

2

R2761

3.3PF 5% 25V CERM 201 73 22 21 7

IN

2

MEM_B_CLK_P<0>

73 22 21 7

IN

MEM_B_CLK_P<0>

1

30

IN

73 66 21

IN

73 66 21 73 66 21

IN IN

73 66 21

IN

73 66 21

IN

73 66 21

IN

73 66 21

IN

73 66 21 7

IN

73 66 21

IN

IN

73 66 21 7

IN

73 66 21

IN

73 66 21

IN IN

RP2722 RP2722 RP2722 RP2722 RP2730 RP2730 RP2730 RP2730

MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_BA<2> MEM_B_A<0> MEM_B_A<2> MEM_B_A<9> MEM_B_A<13>

RP2725 RP2724 RP2724 RP2724

MEM_B_A<10> MEM_B_A<4> MEM_B_A<6> MEM_B_A<8>

RP2725 RP2725 RP2726 RP2726 RP2726

MEM_B_A<12> MEM_B_BA<1> MEM_B_A<1> MEM_B_A<11> MEM_B_A<14>

73 21 7

IN

73 66 21

IN

73 66 21 73 66 21 73 66 21

36 36 36 36

36 36 36 36 36

4

5

3

6

5%

1/32W

4X0201

2

7

5%

1/32W

4X0201

1

8

5%

1/32W

4X0201

5%

1/32W

4X0201

4

5

3

6

2

7

1

8

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5

3

6

5%

1/32W

4X0201

2

7

5%

1/32W

4X0201

1

8

5%

1/32W

4X0201

5%

1/32W

4X0201

7

1

8

3

6

2

7

1

8

1

2

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

1/32W

IN IN IN

RP2720

MEM_B_CS_L<0> MEM_B_BA<0> MEM_B_A<3> MEM_B_A<5> MEM_B_A<7>

RP2720 RP2720 RP2726 RP2724

36 36 36 36 36

6

2

7

5%

1/32W

4X0201

1

8

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

4

5

4

5

5%

1/32W

1

73 21 7

IN

RP2728

MEM_B_CKE<0>

36

1

36

C2722

NC

1/32W

3

6

NC

5% 1/32W 4X0201

1

RP2728

C2723

0.47UF

0.47UF

20% 4V CERM-X5R-1 201

2

20% 4V CERM-X5R-1 201

C2724

1

B

36

NC

3

6

NC

5% 1/32W 4X0201

36

C2725

0.47UF

0.47UF

2

20% 4V CERM-X5R-1 201

2

20% 4V CERM-X5R-1 201

1

C2726

1

C2727

NC

4

5

NC

5% 1/32W 4X0201

RP2720 36 0.47UF

0.47UF

20% 4V CERM-X5R-1 201

20% 4V CERM-X5R-1 201

2

NC

4

5

RP2728 36

NC 1

C2728 20% 4V CERM-X5R-1 201

4X0201 1

2

7

NC

5% 1/32W 4X0201

0.47UF

4X0201

NC

5% 1/32W 4X0201

8 5%

2

RP2725

20% 4V CERM-X5R-1 201

RP2728 1

4X0201

3

C2720 0.47UF

2

4

2

1

2

0.1UF MEM_B_CLK0_TERM_R

36 36 36 36 36 36 36 36

5%

C2761

R2760 MEM_B_CLK_N<0>

73 66 21 7

PP0V675_S0_DDRVTT

2

5% 1/20W MF 201

MEM_B_CLK_N<0>

IN

73 66 21

10% 6.3V CERM-X5R 0201

30 1

IN

73 66 21 7

73 66 21

w

73 22 20 7

73 66 21 7

73 68 65 55 22

C2730

22 7

IN

22 7

IN

22 7

IN

NC_MEM_B_A15 NC_MEM_B_CS_L1 NC_MEM_B_CKE1

MAKE_BASE=TRUE

NC_MEM_B_A15

NO_TEST=TRUE

2

20% 4V CERM-X5R-1 201

SYNC_MASTER=J44_YONAS-4GB

7 22

SYNC_DATE=04/02/2013

DDR3 Termination

2

DRAWING NUMBER

Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

5

4

3

2

SIZE

D REVISION

R

6

7 22

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

7

7 22

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_B_CKE1

0.47UF

10% 6.3V CERM-X5R 0201

5% 1/20W MF 201

8

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_B_CS_L1

BRANCH

PAGE

27 OF 120 SHEET

22 OF 78

1

A

8

7

6

5

4

2

3

1

CRITICAL OMIT_TABLE

1

2

10%

0.1UF 70 68 14

IN

C2803

PCIE_TBT_R2D_C_N<1>

1

70 68 14

D

IN

C2804

PCIE_TBT_R2D_C_P<2>

10%

1

2

10%

0.1UF 70 68 14

IN

C2805

PCIE_TBT_R2D_C_N<2>

1

70 68 14

10%

IN

PCIE_TBT_R2D_C_P<3>

C2806

IN

PCIE_TBT_R2D_C_N<3>

C2807

1

2

10%

0.1UF 70 68 14

1

65 24 23 18 17

16V X5R-CERM

0201

16V X5R-CERM

0201

16V X5R-CERM

0201

16V X5R-CERM

0201

16V X5R-CERM

10%

3.3K

5% 1/20W MF 201 2

1

R2891 3.3K

5% 1/20W MF 2 201

1UF

3.3K

10% 6.3V 2 CERM 402

5% 1/20W MF 201 2

CRITICAL OMIT_TABLE

8

R28901

5% 1/20W MF 2 201

P5 PERST_OD_N R4 PWR_ON_POC_RSTN

TBTROM_WP_L TBTROM_HOLD_L

C

(TBT_SPI_MISO)

74 74

6 CLK 4MBIT 1 CS*W25X40CLXIG USON 3 WP*

74

R28291

18 16

IN

18

IN

5% 1/20W MF 201 2

18 16

10K

7 HOLD*

18

IN OUT

9

4

GND THRM_PAD

1

R2825

74 23

100

5% 1/20W MF 2 201

74 23

74 23 74 23

74 23 74 23

74 23 74 23

74 23

74 5

IN

SNK0 AC Coupling DP_TBTSNK0_ML_C_P<0> C2820 10% 16V 1

0.1UF

74 5

IN

DP_TBTSNK0_ML_C_N<0>

C2821

74 5

IN

DP_TBTSNK0_ML_C_P<1>

C2822

74 5

IN

DP_TBTSNK0_ML_C_N<1>

C2823

1

0.1UF 1

0.1UF 1

0.1UF

B 74 5

IN

DP_TBTSNK0_ML_C_P<2>

C2824

1

0.1UF 74 5

IN

DP_TBTSNK0_ML_C_N<2>

C2825

1

0.1UF

2

74 23

DP_TBTSNK0_ML_P<0>

13 23 74

DP_TBTSNK0_ML_N<0>

2

10% 16V X5R-CERM

0201

2

DP_TBTSNK0_ML_P<1>

10% 16V X5R-CERM

0201

2

DP_TBTSNK0_ML_N<1>

10% 16V X5R-CERM

0201

2

DP_TBTSNK0_ML_P<2>

10% 16V X5R-CERM

0201

2

DP_TBTSNK0_ML_N<2>

10% 16V X5R-CERM

0201

23 74

R28301

74 23

100K

74 23

5% 1/20W MF 201 2

23 74

74 23 74 23

23 74

74 23 74 23

23 74

74 23 74 23

23 74 74 23

C2826

1

0.1UF 74 5

IN

DP_TBTSNK0_ML_C_N<3>

C2827

1

0.1UF 74 13

BI

DP_TBTSNK0_AUXCH_C_P

C2828

1

0.1UF 74 13

BI

DP_TBTSNK0_AUXCH_C_N

C2829

1

0.1UF

74 64

IN

IN

1

DP_TBTSNK1_ML_C_N<0>

C2831

1

0.1UF 74 64

IN

DP_TBTSNK1_ML_C_P<1>

IN

DP_TBTSNK1_ML_C_N<1>

C2832

1

0.1UF 74 64

C2833

1

0.1UF

A

74 64

IN

DP_TBTSNK1_ML_C_P<2>

C2834

1

0.1UF 74 64

IN

DP_TBTSNK1_ML_C_N<2>

IN

DP_TBTSNK1_ML_C_P<3>

C2835

1

0.1UF 74 64

C2836

1

0.1UF 74 64

IN

10% 16V X5R-CERM

0201

2

DP_TBTSNK0_ML_N<3>

10% 16V X5R-CERM

0201

2

DP_TBTSNK0_AUXCH_P

10% 16V X5R-CERM

0201

2

DP_TBTSNK0_AUXCH_N

10% 16V X5R-CERM

0201

SNK1 AC Coupling C2830 10% 16V

DP_TBTSNK1_ML_C_P<0>

0.1UF

74 64

DP_TBTSNK0_ML_P<3>

2

DP_TBTSNK1_ML_C_N<3>

C2837

1

0.1UF

2

23 74 64

23 74

OUT

R28311 100K

DP_TBTSNK1_ML_P<0>

23 74

DP_TBTSNK1_ML_N<0> 0201

2

DP_TBTSNK1_ML_P<1>

10% 16V X5R-CERM

0201

2

DP_TBTSNK1_ML_N<1>

10% 16V X5R-CERM

0201

2

DP_TBTSNK1_ML_P<2>

10% 16V X5R-CERM

0201

2

DP_TBTSNK1_ML_N<2>

10% 16V X5R-CERM

0201

2

DP_TBTSNK1_ML_P<3>

10% 16V X5R-CERM

0201

2

DP_TBTSNK1_ML_N<3>

10% 16V X5R-CERM

0201

OUT

74 68 26

OUT

74 68 26

IN

23 74

23 74

IN

26

IN

BI

DP_TBTSNK1_AUXCH_C_P

C2838

1

0.1UF 74 64

BI

DP_TBTSNK1_AUXCH_C_N

C2839

1

0.1UF

8

2

DP_TBTSNK1_AUXCH_P

10% 16V X5R-CERM

0201

2

DP_TBTSNK1_AUXCH_N

10% 16V X5R-CERM

0201

7

OUT

74 68 26

OUT

74 68 26

IN

74 68 26

IN

26

OUT

26

IN

C2842

PCIE_TBT_D2R_C_P<1> PCIE_TBT_D2R_C_N<1>

74 26

OUT

74 26

OUT

74 26

OUT

74 26

OUT

74 26

BI

74 26

BI

23 74

23 74

23 74

26

23 74

23 74

IN OUT

26

OUT

26 23

OUT

23 74

W2 AB1 AA6 U6 R6 W8

DP_TBTSNK0_ML_P<3> DP_TBTSNK0_ML_N<3>

E14 DPSNK0_3_P D13 DPSNK0_3_N

DP_TBTSNK0_ML_P<2> DP_TBTSNK0_ML_N<2>

E16 DPSNK0_2_P D15 DPSNK0_2_N

DP_TBTSNK0_ML_P<1> DP_TBTSNK0_ML_N<1>

E18 DPSNK0_1_P D17 DPSNK0_1_N

DP_TBTSNK0_ML_P<0> DP_TBTSNK0_ML_N<0>

E20 DPSNK0_0_P D19 DPSNK0_0_N

DP_TBTSNK0_AUXCH_P DP_TBTSNK0_AUXCH_N

70 68 70 68

C2843 C2844

PCIE_TBT_D2R_C_P<2> PCIE_TBT_D2R_C_N<2>

1

1

0.1UF

C2845 C2846

PCIE_TBT_D2R_C_P<3> PCIE_TBT_D2R_C_N<3>

1

1

0.1UF

C2847

1

DP_TBTSNK1_ML_P<1> DP_TBTSNK1_ML_N<1>

TDI TMS TCK TDO TEST_EN TEST_PWR_GOOD

TMU_CLK_OUT AA4

E8 DPSNK1_2_P D7 DPSNK1_2_N

E10 DPSNK1_1_P D9 DPSNK1_1_N E12 DPSNK1_0_P D11 DPSNK1_0_N H3 DPSNK1_AUX_P H1 DPSNK1_AUX_N

DP_TBTSNK1_HPD

U4 DPSNK1_HPD

10%

16V

2

PCIE_TBT_D2R_N<0>

X5R-CERM

0201

10%

16V

2

PCIE_TBT_D2R_P<1>

X5R-CERM

0201

10%

16V

2

PCIE_TBT_D2R_N<1>

X5R-CERM

0201

10%

16V

2

PCIE_TBT_D2R_P<2>

X5R-CERM

0201

10%

16V

2

PCIE_TBT_D2R_N<2>

10%

16V

2

PCIE_TBT_D2R_P<3>

X5R-CERM

0201

X5R-CERM

0201

10%

16V

2

PCIE_TBT_D2R_N<3>

X5R-CERM

0201

10%

16V

X5R-CERM

0201

OUT

14 68 70

OUT

14 68 70

OUT

14 68 70

OUT

14 68 70

OUT

14 68 70

OUT

14 68 70

OUT

14 68 70

OUT

14 68 70

R2855

TBT_CLKREQ_L

1K 1% 1/20W MF 2 201

OUT

PCIE_CLK100M_TBT_P PCIE_CLK100M_TBT_N

71

65 24 23 18 17

12 68 70

IN

12 68 70

DPSRC_1_P A10 DPSRC_1_N B11

TP_DP_TBTSRC_ML_CP<1> TP_DP_TBTSRC_ML_CN<1>

DPSRC_0_P A8 DPSRC_0_N B9

TP_DP_TBTSRC_ML_CP<0> TP_DP_TBTSRC_ML_CN<0>

DPSRC_AUX_P J4 DPSRC_AUX_N J2

TP_DP_TBTSRC_AUXCH_CP TP_DP_TBTSRC_AUXCH_CN

U2 L6 H5 Y7 Y1 T7 V7 M7 T1 T3

DP_TBTSRC_HPD

1

806

65 24 23 18 17 65 42 25 24 23

10K

G24 PA_CIO0_TX_P/DPSRC_0_P E24 PA_CIO0_TX_N/DPSRC_0_N

TBT_A_D2R_P<0> TBT_A_D2R_N<0>

G22 PA_CIO0_RX_P E22 PA_CIO0_RX_N

TBT_A_CONFIG1_BUF TBT_A_CONFIG2_RC

PB_CIO2_TX_P/DPSRC_0_P R24 PB_CIO2_TX_N/DPSRC_0_N N24 PB_CIO2_RX_P R22 PB_CIO2_RX_N N22

P1 PA_CONFIG1/CIO_0_LSEO K5 PA_CONFIG2/CIO_0_LSOE

PB_CONFIG1/CIO_2_LSEO D3 PB_CONFIG2/CIO_2_LSOE M1

TBT_A_R2D_C_P<1> TBT_A_R2D_C_N<1>

L24 PA_CIO1_TX_P/DPSRC_2_P J24 PA_CIO1_TX_N/DPSRC_2_N

PB_CIO3_TX_P/DPSRC_2_P W24 PB_CIO3_TX_N/DPSRC_2_N U24

TBT_A_D2R_P<1> TBT_A_D2R_N<1>

L22 PA_CIO1_RX_P J22 PA_CIO1_RX_N

TBT_A_LSTX TBT_A_LSRX

PB_CIO3_RX_P W22 PB_CIO3_RX_N U22

5% 1/20W MF 201 2

TBT_B_D2R_P<0> TBT_B_D2R_N<0> TBT_B_CONFIG1_BUF TBT_B_CONFIG2_RC TBT_B_R2D_C_P<1> TBT_B_R2D_C_N<1> TBT_B_D2R_P<1> TBT_B_D2R_N<1>

DP_TBTPA_ML_C_P<1> DP_TBTPA_ML_C_N<1>

A16 PA_DPSRC_1_P B17 PA_DPSRC_1_N

DP_TBTPA_ML_C_P<3> DP_TBTPA_ML_C_N<3>

A18 PA_DPSRC_3_P B19 PA_DPSRC_3_N

DP_TBTPA_AUXCH_C_P DP_TBTPA_AUXCH_C_N DP_TBTPA_HPD

M3 PA_DPSRC_HPD

TBT_A_HV_EN TBT_A_CIO_SEL TBT_A_DP_PWRDN

R8 GPIO_0/PA_HV_EN/BYP0 N2 GPIO_10/PA_CIO_SEL/BYP1 P3 GPIO_12/PA_DP_PWRDN/BYP2

5% 1/20W MF 2 201

5

R28801

1

R2878 100K

5% 1/20W MF 201 2

5% 1/20W MF 201 2

5% 1/20W MF 201 2

1

R2879 100K

5% 1/20W MF 2 201

5% 1/20W MF 2 201

1

R2883

OUT IN

100K 5% 1/20W MF 2 201

PP3V3_S4_TBT

18 36 37

NO STUFF

15 18 72

R28841

15 23 64 66

OUT

23 24

IN

23 25

OUT

23 26 27

OUT

23 28

5% 1/20W MF 201 2

26 23

27 68 74

26 25 23

27 68 74

28 27 23

IN

27 68 74

IN

27 68 74

IN

27

IN

27

27 68 74

OUT

27 68 74

IN

27 68 74

IN

27 68 74

27 74 27 74

PB_DPSRC_3_P A22 PB_DPSRC_3_N B23

DP_TBTPB_ML_C_P<3> DP_TBTPB_ML_C_N<3>

OUT

27 74

OUT

27 74

DP_TBTPB_AUXCH_C_P DP_TBTPB_AUXCH_C_N

BI

27 74

BI

27 74

NO STUFF 1

R2886

10K

10K

5% 1/20W MF 201 2

5% 1/20W MF 2 201

R28881

NOTE: The following pins 0 - GPIO_13 8 9 1 - GPIO_1 2 - GPIO_2 10 3 - GPIO_3 11 4 - GPIO_5 12 5 - PCIE_RST_1_N 13 14 6 - PCIE_RST_2_N 15 7 - PCIE_RST_3_N

1

R2887

10K

10K

5% 1/20W MF 201 2

5% 1/20W MF 2 201

require testpoints: - GPIO_15 - GPIO_11 - GPIO_14 - GPIO_0 - GPIO_12 - GPIO_10 - PB_LSTX - PB_LSRX

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

Thunderbolt Host (1 of 2) DRAWING NUMBER

Apple Inc.



27

NOTICE OF PROPRIETARY PROPERTY: OUT

23 27 28

OUT

27

OUT

23 27

All other port signals can be NC.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

2

SIZE

D REVISION

R

IN

B

TBT_BATLOW_L TBT_A_DP_PWRDN TBT_B_DP_PWRDN TBT_A_HV_EN TBT_B_HV_EN

25 23

OUT

OUT

R28851

100K

OUT

OUT

3

100K

15

OUT

TBT_B_HV_EN TBT_B_CIO_SEL TBT_B_DP_PWRDN

R2882

17 18 23 24 65

65 42 25 24 23

IN OUT

DP_TBTPB_ML_C_P<1> DP_TBTPB_ML_C_N<1>

DP_TBTPB_HPD

1

100K

100K

PB_DPSRC_1_P A20 PB_DPSRC_1_N B21

4

17 71

R28321

27

GPIO_1/PB_HV_EN/BYP0 F1 GPIO_11/PB_CIO_SEL/BYP1 R2 GPIO_13/PB_DP_PWRDN/BYP2 F3

IN

TBT_EN_CIO_PWR_L TBT_DDC_XBAR_EN_L HDMITBTMUX_SEL_TBT TBTDP_AUXIO_EN DP_TBTSRC_HPD

27 26 23

PP3V3_TBTLC

27

PB_DPSRC_HPD N6

5% 1/20W MF 2 201

5% 1/20W MF 201 2

66 64 23 15

IN

PB_AUX_P K3 PB_AUX_N K1

10K

100K

1K

28 23

OUT

L4 PA_AUX_P L2 PA_AUX_N

R2863

5% 1/20W MF 2 201

R28811

R2896

24 23

TBT_B_LSTX TBT_B_LSRX

PB_LSTX/CIO_3_LSEO M5 PB_LSRX/CIO_3_LSOE P7

N8 PA_LSTX/CIO_1_LSEO J6 PA_LSRX/CIO_1_LSOE

TBT_B_R2D_C_P<0> TBT_B_R2D_C_N<0>

1

10K

PP3V3_TBTLC PP3V3_S4_TBT

1

27 23

TBT_A_R2D_C_P<0> TBT_A_R2D_C_N<0>

R2862

5% 1/20W MF 2 201

C

SYSCLK_CLK25M_TBT

2

1% 1/20W MF 201

23

TBT_GPIO2 TBT_PWR_EN SMC_PME_S4_DARK_L TBT_CIO_PLUG_EVENT_L HDMITBTMUX_SEL_TBT TBT_GPIO7 TBT_EN_CIO_PWR_L TBT_BATLOW_L TBTDP_AUXIO_EN TBT_DDC_XBAR_EN_L

1

10K

R2895

23

DPSRC_HPD_OD AC2

5% 1/20W MF 2 201

Divides 3.3V to 1.8V

R28991 TP_DP_TBTSRC_ML_CP<2> TP_DP_TBTSRC_ML_CN<2>

10K

R2861

NO STUFF

DPSRC_2_P A12 DPSRC_2_N B13

R2867

1

12

IN

NO STUFF 1

If strap != bit then security is enabled?

TBT_TMU_CLK_OUT

TP_DP_TBTSRC_ML_CP<3> TP_DP_TBTSRC_ML_CN<3>

PP3V3_TBTLC

Security strap setting is XORed with bit in the flash, so the active-level depends on the code in the flash.

SYSCLK_CLK25M_TBT_R TP_TBT_XTAL25OUT

DPSRC_3_P A14 DPSRC_3_N B15

GPIO_2/TMU_CLK_IN/AC_PRESENT GPIO_3/FORCE_PWR GPIO_4/WAKE_OD_N GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD GPIO_6_OD/CIO_SDA_OD GPIO_7_OD/CIO_SCL_OD GPIO_8/EN_CIO_PWR_OD* GPIO_9/SX_CTRL_OD* GPIO_14 GPIO_15

D

1

Used for straps in host mode TP_TBT_PCIE_RESET0_L TBT_DFT_STRAP_1 TBT_ROM_SECURITY_XOR TBT_DFT_STRAP_3

W6 AB3 AD3 V1

XTAL_25_IN AA24 XTAL_25_OUT AB23

E6 DPSNK1_3_P D5 DPSNK1_3_N

DP_TBTSNK1_AUXCH_P DP_TBTSNK1_AUXCH_N

AD1 L8

REFCLK_100_IN_P AB21 REFCLK_100_IN_N AD21

AB5 DPSNK0_HPD

DP_TBTSNK1_ML_P<0> DP_TBTSNK1_ML_N<0>

PCIE_RST_0_N PCIE_RST_1_N PCIE_RST_2_N PCIE_RST_3_N

PCIE_TBT_D2R_P<0>

2

TBT_RSENSE TBT_RBIAS

PCIE_CLKREQ_OD_N V3

G4 DPSNK0_AUX_P G2 DPSNK0_AUX_N

DP_TBTSNK1_ML_P<3> DP_TBTSNK1_ML_N<3> DP_TBTSNK1_ML_P<2> DP_TBTSNK1_ML_N<2>

RSVD

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k).

6

1

0.1UF

23 74

26 25 23

74 64

IN

26

74 68 26 23 74

0201

2

74 68 26

74 68 26

23 74

X5R-CERM 10% 16V X5R-CERM

5% 1/20W MF 201 2

70 68

RBIAS W20

EE_DI EE_DO EE_CS_N EE_CLK

JTAG_ISP_TDI JTAG_TBT_TMS JTAG_ISP_TCK JTAG_TBT_TDO TBT_TEST_EN TBT_TEST_PWR_GOOD

w

DP_TBTSNK0_ML_C_P<3>

w

IN

AA2 Y3 T5 U8

DP_TBTSNK0_HPD

OUT

74 23 74 5

TBT_SPI_MOSI TBT_SPI_MISO TBT_SPI_CS_L TBT_SPI_CLK

0201

X5R-CERM

70 68

RSENSE U20

.c

(TBT_SPI_CS_L)

U2890

70 68

0.1UF PETP_3 AD17 PETN_3 AD19

AD23 MONDC0 AC24 MONDC1 DEBUG: For monitoring current/voltage W18 MONOBSP TBT_MONOBSP W16 MONOBSN TBT_MONOBSN DEBUG: For monitoring clock AB7 THERMDA TBTTHMSNS_D1_P 77 43 Use AA8 GND ball for THERM_DN

w

(TBT_SPI_CLK)

2

DO/IO1

PETP_2 AD13 PETN_2 AD15

TP_TBT_MONDC0 TP_TBT_MONDC1

74

5 DI/IO0

1

0.1UF

VCC

(TBT_SPI_MOSI)

68

0201

TBT_PWR_ON_POC_RST_L

NONE NONE NONE 0201 2

3.3K

C2841

0.1UF

AA18 PERP_3 AB19 PERN_3

PCH_TBT_PCIE_RESET_L

NOSTUFF

R2893

PCIE_TBT_R2D_P<3> PCIE_TBT_R2D_N<3>

IN

R2815

1

PETP_1 AD9 70 PETN_1 AD11

AB15 PERP_2 AA16 PERN_2

IN

1

R28921

PCIE_TBT_R2D_P<2> PCIE_TBT_R2D_N<2>

1

0.1UF 0.1UF

AA12 PERP_1 AB13 PERN_1

24

OMIT

C2890 1

70 68

PCIE_TBT_R2D_P<1> PCIE_TBT_R2D_N<1>

18 15

PP3V3_TBTLC

BYPASS=U2890:2mm

70 68

70 68

2

0.1UF

70 68

70 68

2

0.1UF

0201

C2840

PCIE_TBT_D2R_C_P<0> PCIE_TBT_D2R_C_N<0>

FCBGA (1 OF 2)

70 68

2

0.1UF

16V X5R-CERM

70

m

C2802

PCIE_TBT_R2D_C_P<1>

70

o

IN

PETP_0 AD5 PETN_0 AD7

.c

70 68 14

0201

U2800 REDWOOD-RIDGE

x

10%

0.1UF

16V X5R-CERM

AB9 PERP_0 AA10 PERN_0

fi

2

PCIE_TBT_R2D_P<0> PCIE_TBT_R2D_N<0>

PCIE GEN2

1

70 68

70 68

MISC

IN

C2801

PCIE_TBT_R2D_C_N<0>

0201

PORTS

70 68 14

16V X5R-CERM

10%

PORT

2

a

1

0.1UF

DISPLAY

C2800

PCIE_TBT_R2D_C_P<0>

in

IN

h

70 68 14

BRANCH

PAGE

28 OF 120 SHEET

23 OF 78

1

A

8

7

6

5

4

2

3

1

U2950

CRITICAL OMIT_TABLE

C2900

1

C2901

1

C2902

1

C2903

1

C2904

C2905

1

1

C2906

1.0UF

1.0UF

1.0UF

1.0UF

1.0UF

1.0UF

1.0UF

20% 6.3V X5R 0201-1

20% 6.3V X5R 0201-1

20% 6.3V X5R 0201-1

20% 6.3V X5R 0201-1

20% 6.3V X5R 0201-1

20% 6.3V X5R 0201-1

20% 6.3V X5R 0201-1

2

2

2

2

2

2

G10

1

2

J12 1

C2930

L10

1.0UF

1.0UF

1.0UF

G18

M11

H19

N10

20% 6.3V X5R 0201-1

20% 6.3V X5R 0201-1

20% 6.3V X5R 0201-1

H9

N14

J18

P11

VCC1P0_CIO

24

PP3V3_TBTLC

2

C2932

2

1

1

CSP

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

A1

A2

B1

B2

VOUT

VIN

C1

17 18 23 24 65

D

K19

2

GND 1

U10

P19

U14

T19

V11

D

6

Q2945 DMN5L06VK-7

20% 6.3V X5R 0201-1

SOT-563

S

1

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

G

2

PP3V3_S0

W12

VCC3P3

PP1V05_TBT

N4

POC input to RR -

PP3V3_TBTLC

K9

SVR_VCC1P0

M17

H13

C2970

P17

H15

1.0UF

V19

H17

20% 6.3V X5R 0201-1

H7

CRITICAL

1

10UF 20% 6.3V CERM-X5R 0402-1

C2922

1

C2921

10UF 2

20% 6.3V CERM-X5R 0402-1

1

10UF 2

20% 6.3V CERM-X5R 0402-1

C2920

1

10UF 2

20% 6.3V CERM-X5R 0402-1

CRITICAL 2

N18

SVR_IND0

R18

B3

W10

NC

B5

A2

SOD-323

G20

A24

NSR1020MW2T1G

H21

AA22

H23

GND

AC20 AC22

20% 6.3V X5R 0201-1

2

C2981

C2960

1.0UF

1.0UF

20% 6.3V X5R 0201-1

20% 6.3V X5R 0201-1

C2961

1

D

S

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

1.0UF 20% 6.3V X5R 0201-1

2

2

L20 M13 M21 M23

.c

AC4

VSS

65 42 25 24 23

N16

VSS

N20

72 37 36 25 17

IN

PP3V3_S4_TBT

TBT "POC" Power-up Reset

SMC_DELAYED_PWRGD

P13 P21

C14

P23

C16

P9

C18

R12

C2

R16

C20

R20

C22

T13

C24

T17

C4

T21

C6

T23

C8

B

M9 N12

C12

w w

C2980 1.0UF

2

1

L12

h

AC18

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

PP3V3_S0

Q2995

R2995 1 100K 5% 1/20W MF 201

15

IN

1

DMN32D2LFB4 DFN1006H4-3

SYM_VER_3

2

2

TBT_POC_RESET_L

1

T9

D21

w

25 mA EDP

1

K23

AC16

A

PP3V3_S4_TBT_F 1

K21

AC14

B7

SM

K13

AC12

C10

2

J20

AC10

B1

2

J16

AB17

AC8

2

J14

AB11

AC6

2

C

PLACE_NEAR=C2953.1:1mm

in

AA20

AA8

B

2

1

1

G8

AA14

20% 6.3V CERM-X5R 0402-1

PP3V3_TBTRDV

G6

A

10UF

20% 6.3V CERM-X5R 0402-1

XW2960

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

SVR_AMON

K

D2920

C2953

1

10UF

20% 6.3V CERM-X5R 0402-1

C2995

U12

D23

U16

E4

V13

F11

V21

F13

V23

R2990

CRITICAL

R2992 1

100K

100K

5% 1/20W MF 201

5% 1/20W MF 201

1

6

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM DIDT=TRUE SWITCH_NODE=TRUE

SM

C2923

A6

P1V05TBT_SW

2

C2952

1

10UF

20% 6.3V CERM-X5R 0402-1

L18

a

1

2

C2951

1

10UF

23 24 25 42 65

3.1 W (Dual-Port) 2.4 W (Single-Port) EDP: 1.25 A

2

U2990 TPS3895ADRY USON

2

TBTPOCRST_MR_L

1

ENABLE

TBTPOCRST_SENSE

3

SENSE

C2990 0.1UF

VCC

10% 25V X5R 402

SENSE_OUT

4

Push-pull output TBT_PWR_ON_POC_RST_L

CT

5

TBTPOCRST_CT

1

OUT

10% 16V X7R-CERM 0201

C2991

24.9K

330PF 2 2

10% 50V X7R-CERM 0402

Vth = 2.508V nominal

V9

F17

Y11

F19

Y13

F21

Y15

F23

Y17

F5

Y19

SYNC_MASTER=J44

F7

Y21

PAGE TITLE

F9

Y23

SYNC_DATE=08/12/2013

Thunderbolt Host (2 of 2) DRAWING NUMBER

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).

5

4

3

2

SIZE

D REVISION

R

NOTICE OF PROPRIETARY PROPERTY:

6

2

Delay = 4.04ms nominal

F15

Apple Inc.

7

1

0.001UF

1% 1/20W MF 201

Y9

8

23

GND

R2991

2

680NH-30%-3.6A-35MOHM

1900 mA EDP

VCC3P3_RDV_DECAP

A4

C2950

D

L2920

PP3V3_S4_TBT

17 18 23 24 65

100 mA EDP

1

23

DMN5L06VK-7

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

Y5

IN

3

2

VCC3P3_LC

1

20% 6.3V X5R 0201-1

2

M15

G

20% 6.3V X5R 0201-1

L14

S

C

1

1.0UF

2

C2911

x

1

1.0UF

fi

C2910

TBT_EN_CIO_PWR_L

Q2945

Pull-up (S0) on PCH page

Isolated to reduce noise from SVR

W4

J8

TBT_PWR_REQ_L

OUT

150 mA EDP

V5

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=1.05V

13

SOT-563

3

E2 H11

W14 24

SVR input to RR - 1100 mA EDP

4

V17

D1

.c

V15

o

VCC

U18

G

5

M19

C2940 1.0UF

2

T11 T15

5% 1/20W MF 201

TBT_EN_CIO_PWR

D2

ON

2

R14

VCC1P0_RDV_DECAP

100K

CRITICAL

P15

L16

R2945

C2

1200 mA EDP

R10

K17

K7

C2931

1

K11

(2 OF 2)

K15

PP1V05_TBT

U2940

PP1V05_TBTCIO

J10

FCBGA G16

1.05V TBT "CIO" Switch Internal switch not functional on RR.

TPS22920

REDWOOD-RIDGE

G14

700 mA EDP

8 mOhm Typ 11.5 mOhm Max

Max Current = 4A (85C)

U2800

G12

Load Switch

R(on) @ 1.05V

D1

PP1V05_TBTRDV MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=1.05V

TPS22920

Type

m

D

Part

BRANCH

PAGE

29 OF 120 SHEET

24 OF 78

1

A

8 Page Notes

7

6

5

4

2

3

1

Power aliases required by this page: - =PPVIN_SW_TBTBST (8-13V Boost Input) - =PP15V_TBT_REG (15V Boost Output) Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE)

D

20% 25V X5R-CERM 0603

2

27

200K 1% 1/16W MF-LF 402

VIN

25

EN/UVLO

TBTBST_INTVCC

28

INTVCC

TBTBST_PWREN_L

SNS2

3

20% 10V X5R-CERM 402

SYM_VER_2

1

1

2.2UF 2

2

R3093

C3087

20% 10V X5R-CERM 402

2

1

1% 1/16W MF-LF 402

5% 50V COG-CERM 0402

33

TBTBST_RT

49.9K

68PF

TBTBST_SS

2

SM 2

34

SYNC

TBTBST_VC_RC

0.0033UF 2

2

10% 50V X7R-CERM 0402

R3094 1

1

26.7K 1% 1/16W MF-LF 402

1

0.33UF

2 2



SGND

10% 6.3V CERM-X5R 402

137K

10PF

1% 1/16W MF-LF 402 2

5% 50V C0G-CERM 0402

R3096 1

C3089

2

1% 1/16W MF-LF 402

5% 50V CERM 402

GND_TBTBST_SGND

h .c

B

6

S

w

1

D

2

Max Current = 2A?

C3095

FREQ = 480KHZ

20% 25V POLY-TANT CASE-D3L

NO STUFF

C3096 2



SGND shorted to GND inside package, no XW necessary.

1

15.8K

100PF

GND

26 27 65

Vout = 15.47V 33UF-0.06OHM

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

UVLO(falling) = 1.22 * (R1 + R2) / R2 UVLO(rising) = UVLO(falling) + (2uA * R1) UVLO = 4.55V (falling), 4.95 (rising)

PP15V_TBT

TBTBST_FBX

C3094

16

C3093

15

1

14

20% 10V X5R-CERM 402

13

2

1

2.2UF

1% 1/16W MF-LF 402

12

C3092

73.2K

1

C3088

NO STUFF

37

R3092

1

31

FBX

24

1

R3095

NC

2

2

Second FET needed for dual-port designs.

10

NC

36

SS

PLACE_NEAR=C3095.1:2 mm

2

35

32

1

TBTBST_VSNS

1

RT

4

S

C3086

23

TBT_A_HV_EN

G

1

2.2UF

C

D3095 PDS540XF PWRDI5

XW3095

17

C3085

a

3

CRITICAL

TBTBST_SNS2

VC

in

D

DFN1006H4-3

1

30

TBTBST_VC

Q3005

IN

6

QFN

fi

2

DMN32D2LFB4

26 23

o

LT3957

28

SNS1

1

0 5% 1/20W MF 0201 2

U3090

330K 5% 1/16W MF-LF 402

R3089

3

TBTBST_EN_UVLO

TBTBST_SNS1

SW

CRITICAL

2

1

x

TBTBST_PWREN_DIV_L

R3081

1

10UF 2

38

3

D G

1

R3091

1

20% 25V X5R-CERM 0603

2

2

C3091

1

10UF

21

C3090

0.1UF 10% 25V X5R 402

TBTBST_BOOST MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE

1

C

C3080

2 PIMB063T-SM

Voltage not specified here, add property on another page. 1

470K 5% 1/16W MF-LF 402 2

L3095 3.3UH-6.5A 1

PPVIN_SW_TBTBST

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

2

4

R3080 1

65

.c

BGA

9

PPBUS_G3H 8-13V Input Changes required for 2S.

S

68 65 58 52 51 40

CRITICAL

8

Q3080 SI8409DB

Thunderbolt 15V Boost Regulator

-30V +/-12V -1.4V 46mOhm @ 4.5V Vgs 3.7A @ 70C

20

SI8409DB: Vds(max): Vgs(max): Vgs(th): Rds(on): Id(max):

CRITICAL

m

D

1

1

C3097

10UF

10UF

10% 25V X5R 1206-2

10% 25V X5R 805

2

2

1

C3099 0.001UF

2

10% 50V X7R-CERM 0402

Vout = 1.6V * (1 + Ra / Rb)

B Q3088 DMN5L06VK-7

1

SOT-563

R3088 330K

G

2

Max Vgs: 10V

2

5% 1/16W MF-LF 402

TBTBST_SHDN_DIV 1

R3087

3

D

Q3088

w

330K

2

DMN5L06VK-7

5% 1/16W MF-LF 402

SOT-563

4

S

G

5

SMC_DELAYED_PWRGD

17 24 36 37 72

w

IN

BATLOW# Isolation

IN

PM_BATLOW_L

3

36 13

D

SYM_VER_3

23 24 42 65

1

PP3V3_S4_TBT

SYNC_MASTER=J44

TBT_BATLOW_L TBT_BATLOW_L

SYNC_DATE=08/12/2013

PAGE TITLE

Pull-up on RR page 2

DFN1006H4-3

G

DMN32D2LFB4

S

Q3000

A

Thunderbolt Mobile Support OUT

23 25

DRAWING NUMBER

23 25

MAKE_BASE=TRUE

Apple Inc.

REVISION

R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

BRANCH

PAGE

30 OF 120 SHEET

25 OF 78

1

SIZE

D

A

8

7

6

5

4

2

3

1

3.3V/HV Power MUX V3P3 must be S4 to support wake from Thunderbolt devices.

2

19 20

OUT

6 7

C3215

1

1

4.7UF 10% 25V X5R-CERM 0603

C3210

2

C3285

CRITICAL

10% 16V X5R-CERM 0201

CD3211A0RGPR QFN 16 ENHVU

S4_PWR_EN

25 23

IN

TBT_A_HV_EN

11 HV_EN

61 46 27

IN

PM_SLP_S3_BUF_L

17 S0

1

2

OUT

C3276

10% 25V X5R 402

2

TBTAPWRSW_ISET_V3P3

ISET_S0 10

68

TBTAPWRSW_ISET_S0

ISET_S3 9

68

TBTAPWRSW_ISET_S3

21

1 2 3 13 15 1

1

74 23

BI

74 23

BI

DP_TBTPA_AUXCH_C_N DP_TBTPA_AUXCH_C_P

R3214

1% 1/20W MF 2 201





1

R3211

22.6K

22.6K

1% 1/20W MF 201 2

74 23

IN

74 23

IN

R3212

1% 1/20W MF 2 201

REFERENCE DES

CRITICAL

R3210,R3213

TBTHV:P12V

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

R3211,R3214

TBTHV:P12V

CRITICAL FERR-120-OHM-3A 1

2

PP3V3RHV_S4_TBTAPWR_F MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

0603

C3200

1

10% 50V X7R-CERM 0402

TBTACONN_20_RC 2 1

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V

C3201

2

(Both C’s) 0.47UF

C3275

1

0.47UF

2 20% 4V 201 CERM-X5R-1

74 68

GND_VOID=TRUE

R3294 1

GND_VOID=TRUE 1

1K

2 NO_XNET_CONNECTION=TRUE

74 23 74 23

IN IN

DP_TBTPA_ML_C_P<3> DP_TBTPA_ML_C_N<3>

C3278

1

0.22UF

C3279

1

0.22UF

2 20% X5R 2 20% X5R

74

6.3V 0201

74

74

2 20% X5R

6.3V 0201

28

BI

28

IN

2 20% X5R

6.3V 0201

74 74

5% 1/20W MF 201

2 NO_XNET_CONNECTION=TRUE

DP_TBTPA_ML_P<3> DP_TBTPA_ML_N<3>

6.3V 0201

R3279 1

1

1

DP_TBTPA_DDC_DATA DP_TBTPA_DDC_CLK

4

OUT

TBT_A_CONFIG1_BUF

TBT: Unused

R3278 470K

23

IN

23

OUT

23

OUT

DP_TBTPA_HPD

74 26

2

TBT_A_CONFIG1_RC TBT_A_CONFIG2_RC 1

1

1M 5% 1/20W MF 201

A

R3251 1M

2

2

5% 1/20W MF 201

1

1

2

2

330PF 10% 16V X7R-CERM 0201

18

TBT_A_CONFIG1_RC

DPMLO+ DPMLO-

19

DP_A_LSX_ML_P<1> DP_A_LSX_ML_N<1>

20

(IPU)

23

26 74 26 74

26

26 74 26 74

TBT: LSX_A_R2P/P2R (P/N)

(IPD)

HPDOUT

HPD

17

TBT_A_HPD

26

10% 16V X7R-CERM 0201

C3270 DP Dir

TBT Dir 74 68 74 68

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V

J3200 B2 B4 B6 B8 B10 B12 B14 B16 B18 B20

F-RT-TH GND0 HPD ML_LANE0P CONFIG1 ML_LANE0N CONFIG2 GND1 GND2 ML_LANE3P ML_LANE1P ML_LANE3N ML_LANE1N GND3 GND4 ML_LANE2P AUX_CHP ML_LANE2N AUX_CHN RETURN DP_PWR

C3271 0.22UF

C3206 10% 25V X5R-CERM 0201

2

C3202 10% 16V X5R-CERM 0201

6.3V 0201

TBT_A_R2D_C_P<0> TBT_A_R2D_C_N<0>

IN

23 68 74

IN

23 68 74

470K

5% 1/20W MF 201

2

5% 1/20W MF 201

B DP_A_LSX_ML_P<1> DP_A_LSX_ML_N<1>

26 74 26 74

TBT: LSX_R2P/P2R (P/N)

GND_VOID=TRUE

(Both C’s)

C3272 74 68

1

2 20% X5R

1

2

0.22UF

TBT_A_R2D_P<1> TBT_A_R2D_N<1>

C3273

20% X5R

0.22UF

6.3V 0201

TBT_A_R2D_C_P<1> TBT_A_R2D_C_N<1>

IN

23 68 74

IN

23 68 74

6.3V 0201

TBT: TX_1 GND_VOID=TRUE 1

DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a).

GND_VOID=TRUE 1

R3273

470K

470K

5% 1/20W MF 2 201

5% 1/20W MF 2 201

470k R’s for ESD protection on AC-coupled signals.

Sink HPD range: High: 2.0 - 5.0V Low: 0 - 0.8V

5% 1/20W MF 201

6.3V 0201

20% X5R

R3271

470K 2

2 20% X5R 2

GND_VOID=TRUE 1

R3270

1

0.01UF

B1 B3 B5 B7 B9 B11 B13 B15 B17 B19

1

GND_VOID=TRUE 1

GND_VOID=TRUE

(0-18.9V)

1

0.22UF

TBT: TX_0 TBTACONN_7_C

SHIELD PINS

MDP-J44

TBT_A_R2D_P<0> TBT_A_R2D_N<0>

R3272

100K

2

GND_VOID=TRUE

(Both C’s)

514-0876

0.01UF

330PF

2

PORT B

1

C3295

1

CRITICAL

74 68

R3241

C3205 10% 25V X5R-CERM 0201

TBT_A_D2R1_AUXDDC_P TBT_A_D2R1_AUXDDC_N

1

C3294

12

LSTX LSRX

CA_DET

SHIELD PINS

2

R3252

DP+ DP-

14

TBT_A_D2R1_AUXDDC_N TBT_A_D2R1_AUXDDC_P

23 27

IN

0.01UF

5% 1/20W MF 201

w

26

22

IN

GND_VOID=TRUE

5% 1/20W MF 201

TBT: RX_1

OUT

CA_DETOUT

11

13

(0-18.9V)

S24 S22 S21 S20 S19 S18 S17

2

74 26

23

23

(IPD) AUXIO+

IN

TBT: RX_1

16

10

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V

2

w

5% 1/20W MF 201

TBT_A_HPD

(IPU) AUXIO-

DDC_DAT DDC_CLK

5

DP_TBTPA_ML_P<1> DP_TBTPA_ML_N<1> TBT_A_LSTX TBT_A_LSRX

AUXAUX+

2

6

C

DP Dir

w

470K

26

3

DP_TBTPA_AUXCH_N DP_TBTPA_AUXCH_P

24

23

GND THMPAD

12

1

TBT: RX_0

R3295 1K

5% 1/20W MF 201

B

TBT Dir

TBT_A_D2R_C_P<0> TBT_A_D2R_C_N<0>

h

OUT

10% 50V X7R-CERM 0402

.c

OUT

74 68 23

8

TBT_A_CIO_SEL TBTDP_AUXIO_EN TBT_A_DP_PWRDN

TBTACONN_1_C

in

0.01UF GND_VOID=TRUE

74 68

74

R3201

0.01UF

2 20% 4V 201 CERM-X5R-1

15

Thunderbolt Connector A

L3200

Max 1170mA (12W minimum)

1

1

0.22UF

BOM OPTION

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

C3274

10% 16V X5R-CERM 0201 2 10% 16V X5R-CERM 0201

0.22UF

ILIM = 40000 / RISET

2

TBT_A_D2R_P<0> TBT_A_D2R_N<0>

1



2

74 68 23

2

1% 1/20W MF 2 201

118S0145

Min 1090mA

1

1

C3233

36.5K

118S0145

Nominal IHVS0/S3 1120mA

C3232

TB_ENA AUXIO_EN DP_PD

TBTB+

x

DESCRIPTION

74 68

7

TBT_A_D2R_C_N<1> TBT_A_D2R_C_P<1>

fi

QTY

HVQFN24-COMBO 74 68

20% 4V 201 CERM-X5R-1

0.1UF

C3231

DP_TBTPA_ML_C_P<1> DP_TBTPA_ML_C_N<1>

For 12V systems: PART NUMBER

C3230

Single-fault protection requires two R’s per HV ISET_Sx with CD3210. Single R on ISET_V3P3 OK.

22.6K

1% 1/20W MF 201 2

1

TBTAPWRSW_ISET_S3_R TBTAPWRSW_ISET_S0_R

TBTHV:P15V

22.6K

TBTHV:P15V

R3210 1

12V: See below

68

R3213

1

20% 4V 201 CERM-X5R-1 2

23

TBTHV:P15V

THRM PAD

TBTHV:P15V

2

0.47UF

0.1UF

20% 6.3V CERM-X5R 0402

2

74 68 23

D

U3220 CBTL05024

1

0.47UF

C3211

10UF

68

GND

C

C3286

C3277

TBT_A_D2R_N<1> TBT_A_D2R_P<1>

0.1UF

ISET_V3P3 8

IN

1

OUT

FAULTZ 4

5 EN

61 60 27 18

1

0.1UF

U3210

10% 25V X5R 402

74 68 23

SIGNAL_MODEL=TBT_MUX

VDD CRITICAL

2

(Both C’s)

PP3V3RHV_S4_TBTAPWR MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

VHV

0.1UF 2

12 14

10% 16V X5R-CERM 0201

GND_VOID=TRUE

26

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

V3P3OUT 18 V3P3

1

0.1UF

PP3V3_S4_TBTAPWR

PP15V_TBT 15.75V Max

C3220

25

2

10% 16V X5R-CERM 0201

9

0.1UF

21

C3281

m

65 27 25

1

o

20% 6.3V X5R-CERM-1 603

Max 1200mA 930mA (assumes 15V, 12W minimum) 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

a

D

1

22UF

20% 6.3V 2 POLY-TANT CASE-B2-SM

Min 1030mA 830mA 830mA

.c

C3280

1

100UF

Nominal 1100mA 890mA 890mA

IV3P3 IHVS0 IHVS3

CRITICAL

C3287

PP3V3_S4_TBTAPWR

26

PP3V3_S5

S16 S15 S14 S13 S12

29 27 18 17 16 15 13 11 8 77 68 65 61 60 59 56

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

Thunderbolt Connector A DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

32 OF 120 SHEET

26 OF 78

1

A

8

7

6

5

4

2

3

1

3.3V/HV Power MUX V3P3 must be S4 to support wake from Thunderbolt devices.

2

19 20

OUT

6 7

C3315

1

1

4.7UF 10% 25V X5R-CERM 0603

C3310

2

C3385

CRITICAL

10% 16V X5R-CERM 0201

CD3211A0RGPR QFN 16 ENHVU

1

C3386

1

C3376

10% 25V X5R 402

2

61 60 26 18

IN

S4_PWR_EN

28 23

IN

TBT_B_HV_EN

11 HV_EN

ISET_S0 10

61 46 26

IN

PM_SLP_S3_BUF_L

17 S0

ISET_S3 9

68

74 23

BI

74 23

BI

DP_TBTPB_AUXCH_C_N DP_TBTPB_AUXCH_C_P

1

1

1

1

R3311

22.6K

22.6K

1% 1/20W MF 201 2

74 23

IN

74 23

IN

R3312

1% 1/20W MF 2 201

R3314

1% 1/20W MF 2 201



BOM OPTION

2

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

R3310,R3313

TBTHV:P12V

2

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

R3311,R3314

TBTHV:P12V

CRITICAL FERR-120-OHM-3A 2

PP3V3RHV_S4_TBTBPWR_F MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

0603

C3300

1

10% 50V X7R-CERM 0402

TBTBCONN_20_RC 2 1

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V

C3301

2

(Both C’s) 0.47UF

C3375

1

0.47UF

2 20% 4V 201 CERM-X5R-1

74 68 74 68

GND_VOID=TRUE

R3394 1

GND_VOID=TRUE 1

1K

2 NO_XNET_CONNECTION=TRUE

74 23 74 23

IN IN

DP_TBTPB_ML_C_P<3> DP_TBTPB_ML_C_N<3>

C3378

1

0.22UF

C3379

1

0.22UF

2 20% X5R 2 20% X5R

74

6.3V 0201

74

2 20% X5R

6.3V 0201

74 74

5% 1/20W MF 201

2 NO_XNET_CONNECTION=TRUE

DP_TBTPB_ML_P<3> DP_TBTPB_ML_N<3>

6.3V 0201

R3379 1

1

BI IN

DP_TBTPB_DDC_DATA DP_TBTPB_DDC_CLK

4

OUT

TBT: Unused

R3378 470K

TBT_B_CONFIG1_BUF

23

IN

23

OUT

23

OUT

DP_TBTPB_HPD

74 27

2

TBT_B_CONFIG1_RC TBT_B_CONFIG2_RC 1

1

1M 5% 1/20W MF 201

A

R3351 1M

2

2

5% 1/20W MF 201

1

1

2

2

330PF 10% 16V X7R-CERM 0201

DP+ DP-

14

12

LSTX LSRX

CA_DET

18

TBT_B_CONFIG1_RC

DPMLO+ DPMLO-

19

DP_B_LSX_ML_P<1> DP_B_LSX_ML_N<1>

20

(IPU)

23

27 74 27 74

27

27 74 27 74

TBT: LSX_A_R2P/P2R (P/N)

(IPD)

HPDOUT

HPD

17

TBT_B_HPD

27

2

GND_VOID=TRUE

C3370 DP Dir

TBT Dir 74 68 74 68

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V

J3200 A2 A4 A6 A8 A10 A12 A14 A16 A18 A20

F-RT-TH GND0 HPD ML_LANE0P CONFIG1 ML_LANE0N CONFIG2 GND1 GND2 ML_LANE3P ML_LANE1P ML_LANE3N ML_LANE1N GND3 GND4 ML_LANE2P AUX_CHP ML_LANE2N AUX_CHN RETURN DP_PWR

C3371 0.22UF

C3306 10% 25V X5R-CERM 0201

2

C3302 10% 16V X5R-CERM 0201

6.3V 0201

TBT_B_R2D_C_P<0> TBT_B_R2D_C_N<0>

IN

23 68 74

IN

23 68 74

470K

5% 1/20W MF 201

2

5% 1/20W MF 201

B DP_B_LSX_ML_P<1> DP_B_LSX_ML_N<1>

27 74 27 74

TBT: LSX_R2P/P2R (P/N)

GND_VOID=TRUE

(Both C’s)

C3372 74 68

1

2 20% X5R

1

2

0.22UF

TBT_B_R2D_P<1> TBT_B_R2D_N<1>

C3373

20% X5R

0.22UF

6.3V 0201

TBT_B_R2D_C_P<1> TBT_B_R2D_C_N<1>

IN

23 68 74

IN

23 68 74

6.3V 0201

TBT: TX_1 GND_VOID=TRUE 1

DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a).

GND_VOID=TRUE 1

R3373

470K

470K

5% 1/20W MF 2 201

5% 1/20W MF 2 201

470k R’s for ESD protection on AC-coupled signals.

Sink HPD range: High: 2.0 - 5.0V Low: 0 - 0.8V

5% 1/20W MF 201

6.3V 0201

20% X5R

R3371

470K 2

2 20% X5R 2

GND_VOID=TRUE 1

R3370

1

0.01UF

A1 A3 A5 A7 A9 A11 A13 A15 A17 A19

1

GND_VOID=TRUE 1

GND_VOID=TRUE

(0-18.9V)

1

0.22UF

TBT: TX_0 TBTBCONN_7_C

SHIELD PINS

MDP-J44

TBT_B_R2D_P<0> TBT_B_R2D_N<0>

R3372

100K

330PF

2

(Both C’s)

514-0876

0.01UF

C3395

1

CRITICAL

74 68

R3341

C3305

PORT A

1

10% 16V X7R-CERM 0201

GND_VOID=TRUE

10% 25V X5R-CERM 0201

TBT_B_D2R1_AUXDDC_P TBT_B_D2R1_AUXDDC_N

1

C3394

TBT_B_D2R1_AUXDDC_N TBT_B_D2R1_AUXDDC_P

SHIELD PINS

2

R3352

22

23 26

IN

0.01UF

5% 1/20W MF 201

w

27

CA_DETOUT

11

13

5% 1/20W MF 201

TBT: RX_1

OUT

23

(IPD) AUXIO+

IN

TBT: RX_1

16

10

(0-18.9V)

S23 S11 S10 S9 S8 S7 S6

2

74 27

23

(IPU) AUXIO-

DDC_DAT DDC_CLK

5

DP_TBTPB_ML_P<1> DP_TBTPB_ML_N<1> TBT_B_LSTX TBT_B_LSRX

AUXAUX+

2

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V

2

w

5% 1/20W MF 201

TBT_B_HPD

3 1

IN

C

DP Dir

w

470K

27

TBT_B_DP_PWRDN

GND THMPAD

12

1

TBT: RX_0

R3395 1K

5% 1/20W MF 201

B

TBT Dir

TBT_B_D2R_C_P<0> TBT_B_D2R_C_N<0>

h

OUT

2 20% 4V 201 CERM-X5R-1

10% 50V X7R-CERM 0402

.c

OUT

74 68 23

1

6

TBTBCONN_1_C

in

0.01UF GND_VOID=TRUE

C3374

6.3V 0201

R3301

0.01UF

TBT_B_D2R_P<0> TBT_B_D2R_N<0>

24

23

Thunderbolt Connector B

L3300

Max 1170mA (12W minimum)

1

74 68 23

28

DP_TBTPB_AUXCH_N DP_TBTPB_AUXCH_P

15

x

CRITICAL

1

0.22UF

20% X5R



118S0145

Min 1090mA

74

2

1% 1/20W MF 2 201

118S0145

Nominal IHVS0/S3 1120mA

0.22UF

ILIM = 40000 / RISET

REFERENCE DES

8

TB_ENA AUXIO_EN DP_PD

TBT_B_CIO_SEL TBTDP_AUXIO_EN

TBTB+

fi

DESCRIPTION

10% 16V X5R-CERM 0201 2 10% 16V X5R-CERM 0201

1

C3333

36.5K

For 12V systems: QTY

C3332

DP_TBTPB_ML_C_P<1> DP_TBTPB_ML_C_N<1>

Single-fault protection requires two R’s per HV ISET_Sx with CD3210. Single R on ISET_V3P3 OK.

22.6K



TBTHV:P15V

R3310 1

TBTBPWRSW_ISET_S3_R TBTBPWRSW_ISET_S0_R

TBTHV:P15V

1% 1/20W MF 201 2

1

74

23

TBTHV:P15V 12V: See below

22.6K

2

28

TBTBPWRSW_ISET_S3

21

1 2 3 13 15

R3313

1

0.1UF

C3331

74 68

7

TBT_B_D2R_C_N<1> TBT_B_D2R_C_P<1>

20% 4V 201 CERM-X5R-1

TBTBPWRSW_ISET_S0 68

68

PART NUMBER

C3330

HVQFN24-COMBO 74 68

TBTBPWRSW_ISET_V3P3

THRM PAD

TBTHV:P15V

1

20% 4V 201 CERM-X5R-1 2

0.1UF

ISET_V3P3 8

5 EN

2

0.47UF

D

U3320 CBTL05024

1

0.47UF

0.1UF

20% 6.3V CERM-X5R 0402

2

OUT

C3377

TBT_B_D2R_N<1> TBT_B_D2R_P<1>

C3311

10UF 2

74 68 23

OUT

FAULTZ 4

GND

C

1

0.1UF

U3310

10% 25V X5R 402

74 68 23

SIGNAL_MODEL=TBT_MUX

VDD CRITICAL

2

(Both C’s)

PP3V3RHV_S4_TBTBPWR MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

VHV

0.1UF 2

12 14

10% 16V X5R-CERM 0201

GND_VOID=TRUE

27

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

V3P3OUT 18 V3P3

1

0.1UF

PP3V3_S4_TBTBPWR

PP15V_TBT 15.75V Max

C3320

25

2

10% 16V X5R-CERM 0201

9

0.1UF

21

C3381

m

65 26 25

1

o

20% 6.3V X5R-CERM-1 603

Max 1200mA 930mA (assumes 15V, 12W minimum) 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

a

D

1

22UF

20% 6.3V 2 POLY-TANT CASE-B2-SM

Min 1030mA 830mA 830mA

.c

C3380

1

100UF

Nominal 1100mA 890mA 890mA

IV3P3 IHVS0 IHVS3

CRITICAL

C3387

PP3V3_S4_TBTBPWR

27

PP3V3_S5

S5 S4 S3 S2 S1

29 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

Thunderbolt Connector B DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

33 OF 120 SHEET

27 OF 78

1

A

8

7

6

5

4

2

3

1

DDC Pull-Ups 2.2k pull-ups are required by PCH to indicate active display interface. DP++ spec violation, should remove! NOTE: Only DDC_DATA is sensed, so DDC_CLK pull-ups are unstuffed.

D PP3V3_S0

R3451

R3452

m

77 68 65 64 62 61 37 30 24 18 17 15 13 12 11 8 50 47 46 44 43 42 41 40 39 38

D

DDC Crossbar

1

R3453 1

R3454 1

2.2K

2.2K

2.2K

2.2K

1% 1/20W MF 2 201

1% 1/20W MF 2 201

1% 1/20W MF 2 201

1% 1/20W MF 2 201

5% 1/20W MF 201 2

TS3DS10224

2

14 10

27

OUT

27

BI

3

DP_TBTPB_DDC_CLK DP_TBTPB_DDC_DATA

4

ENA

QFN

CRITICAL

INA+ INA-

GND

5

SAI/SBI = 1: INA == OUTA0, INB == OUTB0 SAI/SBI = 0: INA == OUTB0, INB == OUTA0

SOT-563

5

G

15

OUTB1+ OUTB1-

6

OUTB0+ OUTB0-

8

7

C DP_TBTSNK1_DDC_CLK DP_TBTSNK1_DDC_DATA

SBO

IN BI

64 64

DP_TBTSNK0_DDC_CLK DP_TBTSNK0_DDC_DATA

9

IN BI

13 13

11

S 4

TBT_DDC_XBAR_EN_L

h

IN

SAO

17

ENB INB+ INB-

D 3

DMN5L06VK-7

23

OUTA0+ OUTA0-

18

19

in

Q3485

20

SAI

12 SBI

TBT_DDC_XBAR_EN

OUTA1+ OUTA1-

x

1

DP_TBTPA_DDC_CLK DP_TBTPA_DDC_DATA

fi

BI

20% 10V CERM 402

a

26

0.1UF

THRM PAD

OUT

C3480

21

26

2

U3400 16

C

1

.c

100K

13

R34851

VCC

o

Only necessary on dual-port hosts. On single-port hosts alias TBTPA_DDC to TBTSNK0_DDC. NEVER SEND AUXCH THROUGH CROSSBAR!

1

B

w

.c

B

w

Second FET needed for dual-port designs. CONNECTS TO TBTBTS_PWREN_L ON PAGE 30.

TBTBST_PWREN_L

w

Q3485

OUT

25

D 6

DMN5L06VK-7 SOT-563

2 27 23

IN

G

S 1

TBT_B_HV_EN

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

DDC Crossbar DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

34 OF 120 SHEET

28 OF 78

1

A

8

7

6

5

4

2

3

1

D

.c

o

m

D

C

h

in

a

fi

x

C

PCIe Wake Muxing PP3V3_S5

R3561 100K

5% 1/20W MF 2 201

SEL

C3560

1

5

0.1UF

OUTPUT

L H

PCIE_WAKE_L (B0) AP_S0IX_WAKE_L (B1)

VCC

10% 6.3V CERM-X5R 2 0201

CRITICAL

U3560

S 6

AP_S0IX_WAKE_SEL

IN

15

NC7SB3157P6XG SC70

AP_PCIE_WAKE_L

4 A

B0 3 B1 1

PCIE_WAKE_L AP_S0IX_WAKE_L

GND 2

NOSTUFF 1

0

5% 1/20W MF 0201

2

13 31 72

OUT

15

w

R3560

OUT

w

VER-3 72 63

BLUETOOTH 68 65 64 63 60 42 38 37 34 18

PP3V3_S4

C3510

1

5

1

B

w

56 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59

.c

B

U3510

10% 6.3V CERM-X5R 0201

2

USB3740 DFN

SMC_PME_S4_WAKE_L

0.1UF

VDD

DP_2

6

71 63

71 63

USB_BT_CONN_P USB_BT_CONN_N

10 9

DP

DM_2

7

DP_1

2

DM

DM_1

1

Q3510 BI

14 71

USB_BT_N

BI

14 71

S

1

NC

G

5

2

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

WIRELESS SUPPORT DRAWING NUMBER 1

PM_SLP_S4_L SEL

IN

4

R3512

Apple Inc.

15K

13 18 36 61 63

GND 8

6

S

3 4

L H

7

3

BT_WAKE

OUTPUT 2

8

D

DFN1006H4-3

SYM_VER_2

OE* SIGNAL_MODEL=BT_MUX

34 36 38

DMN32D2LFB4

USB_BT_P

CRITICAL

A

OUT

NO_XNET_CONNECTION=TRUE

1% 1/20W MF 201

BT_WAKE (1) USB_BT (2)

R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

3

2

SIZE

D REVISION

BRANCH

PAGE

35 OF 120 SHEET

29 OF 78

1

A

8

7

6

5

4

2

3

1

OOB Isolation

D 65 41 30

D

PP3V3_S0SW_SSD BYPASS=U3710:5 mm

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

PP3V3_S0

1

PLACE_NEAR=J3700.1:3mm

CRITICAL

74LVC1G08 SOT891

2

PP3V3_S0SW_SSD_FLT MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.15mm VOLTAGE=3.3V

0603

C3701

1

0.1UF

0.1UF

10% 10V X5R-CERM 0201

2

C3702

2

PLACE_NEAR=L3700.1:1mm

1

10% 10V X5R-CERM 0201

514S0449 CRITICAL

R3700

100K

100K

1% 1/20W MF 201 2

1% 1/20W MF 201 2

J3700 SSD-GS3 F-RT-SM 1

GND_VOID 53

2

52

3

51

C3710

IN

PCIE_SSD_R2D_C_P<3>

C3711

70 68 12

IN

PCIE_SSD_R2D_C_N<2>

C3712

70 68 12

IN

PCIE_SSD_R2D_C_P<2>

C3713

IN

PCIE_SSD_R2D_C_N<1>

C3714

1

2

GND_VOID=TRUE 10% 16V X5R-CERM

1

2

GND_VOID=TRUE 10% 16V X5R-CERM

1

2

GND_VOID=TRUE 10% 16V X5R-CERM

1

2

GND_VOID=TRUE 10% 16V X5R-CERM

1

2 GND_VOID=TRUE 10% 16V X5R-CERM

0.1UF

70 68

0.1UF 0.1UF

0.1UF 70 68 12

IN

C3715

PCIE_SSD_R2D_C_P<1>

IN

C3716

PCIE_SSD_R2D_C_N<0>

1

GND_VOID=TRUE 10% 16V X5R-CERM

1

2

70 68 12

IN

C3717

PCIE_SSD_R2D_C_P<0>

0201

10%

GND_VOID=TRUE 16V X5R-CERM

PCIE_SSD_R2D_N<3> PCIE_SSD_R2D_P<3>

TRUE

11

45 TRUE

TRUE

12

44 TRUE

PCIE_SSD_R2D_N<2> PCIE_SSD_R2D_P<2>

TRUE

14

TRUE

15

0201 70 68

PCIE_SSD_R2D_N<1> PCIE_SSD_R2D_P<1>

70 68

0201

0201

PCIE_SSD_R2D_N<0> PCIE_SSD_R2D_P<0>

SSD_CLKREQ_CONN_L

h Delay = 55ms

1

R3741 232K

5% 1/20W MF 201

1% 1/20W MF 201

2

2

CRITICAL

1

C3740 0.1UF

VDD

U3740

2

SLG4AP016V

10% 6.3V CERM-X5R 0201

TDFN P3V3SSD_VMON

2 SENSE + 0.7V DLY

7 IN THRM PAD

GND 5

R3742

SSD_RESET_L

EN 6 OUT 8

SSD_PWR_EN SSD_CLKREQ_L

(OD)

9

1

MR* 3

w

4 RESET*

36

SMC_OOB1_D2R_L

OUT

36

NC

3

5

NC PP3V3_S0

C3719

PCIE_SSD_D2R_N<3> PCIE_SSD_D2R_P<3>

1

0.1UF 10% 10V X5R-CERM 0201

OUT

16

IN

15

IN

36

IN

15 30 60 61

2

CRITICAL 6 2

74LVC1G08 SOT891

U3711

4

C

08

1 NC

5

OUT

12 68 70

OUT

12 68 70

PCIE_SSD_D2R_N<2> PCIE_SSD_D2R_P<2>

OUT

12 68 70

OUT

12 68 70

PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1>

OUT

12 68 70

OUT

12 68 70

PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0>

OUT

12 68 70

OUT

12 68 70

3

NC

42 TRUE 41 TRUE

SMC_PWRFAIL_WARN_L: There is 10k pullup on the SSD, its OPEN drain on SMC.

40

17

39

18

38 TRUE

TRUE

19

37 TRUE

20

36

TRUE

21

35 TRUE

TRUE

22

34 TRUE

23

33

24 25

32

26

31

27

30

28

29

54

59

55

60

56

61

57

62

58

63

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P

IN

12 68 70

IN

12 68 70

B

17 33 34 36 37 38 39 45 51 52 61 65 68

w

1

100K

IN

Gumstick3 Connector

w

R3740

PP3V42_G3H 30 41 65

1

PP3V3_S0SW_SSD

SMC_OOB1_R2D_L

1

43

TRUE

0201

.c

Supervisor & CLKREQ# Isolation

2

0201

Per Intel PDG, use PCIe style decoupling, when muxing PCIe & SATA

B

46

16

70 68

0.1UF

10

13 70 68

2

0.1UF

47

9

0201

70 68

0.1UF 70 68 12

70 68

70 68

0.1UF 70 68 12

0201

8

SSD_PCIE_SEL_L SSD_DEVSLP SMC_PWRFAIL_WARN_L SSD_PWR_EN

x

PCIE_SSD_R2D_C_N<3>

2 GND_VOID=TRUE 10% 16V X5R-CERM

48

a

IN

70 68 12

70 68 12

1

PP3V3_S0 SSD_RESET_CONN_L NC_SSD_MFG_RSVD

7

in

C

6

49

fi

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

50

6

U3710 08

50 47 46 44 43 42 41 18 17 15 13 12 11 8 40 39 38 37 30 28 24 77 68 65 64 62 61

SMC_OOB1_R2D_CONN_L SMC_OOB1_D2R_CONN_L

4 5

4

BYPASS=U3711:5 mm

.c

GND_VOID

1

R3701

PLACE_NEAR=L3700.1:1mm

o

1

m

1

PP3V3_S0SW_SSD

10% 10V X5R-CERM 0201

CRITICAL

L3700 FERR-26-OHM-6A 65 41 30

C3718 0.1UF

2

IN

15

IN

15 30 60 61

OUT

12

100K

2

1% 1/20W MF 201

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

SSD Connector DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

37 OF 120 SHEET

30 OF 78

1

A

8

7

6

5

4

2

3 PP1V8_CAM

L3902

1.0UH-1.6A-55MOHM 1 2 P1V35_CAM_SRVLXD_PHASE

BYPASS=U3900.K13:2.54MM 75 32 31

PP1V35_CAM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.35V

1

L3906 1

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.35V

U3900

1

FBGA SYM 3 OF 3

PCIE_GND

A4 D4 G4 K4 N4

B

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0.675V

1

1

C3930 1.0UF

C3927

20% 6.3V 0201-1

1

PP1V2_CAM_XTALPCIEVDD

2

32 75

C3931 10UF

31

PP1V2_CAM_PCIE_VDD_FLT

1

C3932 1.0UF

1

1

0.1UF

C3971 1000PF

10%

10% 2 16V X7R-CERM 0201

0201

1

C3972 0.1UF

VSSC SR_VLXC_O

SR_VLXD_O

0603

C3933

C3918

1

1000PF

10% 6.3V 0201

2 CERM-X5R

C3938

1

C3916 0.1UF

10% 16V 2 X7R-CERM 0201

10% 16V 2 X7R-CERM 0201

C3928

20% 6.3V 2 X5R 402

10% 2 6.3V CERM-X5R 0201

1

C3917 1000PF

10% 2 16V X7R-CERM 0201

1

C3910 0.1UF

10% 2 6.3V CERM-X5R 0201

1

2

PLACE_NEAR=U3900.M14:2.54MM

P1V2_CAM_SRVLXC_PHASE 31

M13 N14

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM DIDT=TRUE

1

4.7UF

P1V35_CAM_SRVLXD_PHASE

K13 K14

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM DIDT=TRUE

PP1V35_CAM

C3926

31

XW3901 SM GND_CAM_PVSSD

1

2

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.175MM VOLTAGE=0V

31 32 75

PP1V2_CAM_XTALPCIEVDD

1

PP1V8_CAM

VDD1P8_O G15

1

F6 F7 F8 F9 L6 L5 L8 L9

C3941 2.2UF

1

C3939

20% 6.3V 2 CERM 402-LF

PP3V3_S3RS0_CAMERA

C3942

1

10% 6.3V 2 CERM-X5R 0201

C3934 1000PF

10% 2 16V X7R-CERM 0201

1

C3935 0.1UF

10% 2 6.3V CERM-X5R 0201

1

C3936 1000PF

10% 2 16V X7R-CERM 0201

15 42

1K

1

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V MAKE_BASE=TRUE

OUT

75 32

OUT

75 32

OUT

75 32

OUT

75 32

OUT

75 32 17 31 75 32

OUT

75 32

OUT

0.1UF

0.1UF

75 32

OUT

10% 2 6.3V CERM-X5R 0201

75 32

OUT

75 32

OUT

75 32

OUT

75 32

OUT

75 32

OUT

75 32

OUT

75 32

OUT

75 32

OUT

75 32

1

R3976 51K

5% 1/20W MF

2 201

R3912 1

240

1% 1/20W MF 201

7

OUT

75 32

OUT

75 32

OUT

75 32

OUT

2 75 32

OUT

75 32

OUT

6

FBGA SYM 2 OF 3

72 29 13

OUT

32 31

IN

75 68 32

IN

75 68 32

IN

MEM_CAM_BA<0> MEM_CAM_BA<1> MEM_CAM_BA<2>

K3 DDR_BA0 L2 DDR_BA1 K2 DDR_BA2

DDR_DQS_P0 E2 DDR_DQS_N0 D2

MEM_CAM_DQS_P<0> MEM_CAM_DQS_N<0>

MEM_CAM_CLK_P MEM_CAM_CLK_N

H2 DDR_CK_P0 G2 DDR_CK_N0

DDR_DQS_P1 A2 DDR_DQS_N1 A3

MEM_CAM_DQS_P<1> MEM_CAM_DQS_N<1>

MEM_CAM_DM<0> MEM_CAM_DM<1>

C1 DDR_DM0 C4 DDR_DM1

MEM_CAM_ZQ_S2 MEM_CAM_CKE MEM_CAM_CS_L

G3 DDR_ZQ J3 DDR_CKE L4 DDR_CS*

DDR_RAS* DDR_WE* DDR_CAS* DDR_RESET*

CRITICAL OMIT_TABLE

H3 J2 H4 R3

2

D

330K

L3901

1

C3975 0.1UF

70 32

IN

70 32

IN

70 32

IN

70 32

IN

70 32

OUT

70 32

OUT

P8 MIPI_DP0 R8 MIPI_DM0

PCIE_CAMERA_R2D_P PCIE_CAMERA_R2D_N

MEM_CAM_DQ<0> MEM_CAM_DQ<1> MEM_CAM_DQ<2> MEM_CAM_DQ<3> MEM_CAM_DQ<4> MEM_CAM_DQ<5> MEM_CAM_DQ<6> MEM_CAM_DQ<7> MEM_CAM_DQ<8> MEM_CAM_DQ<9> MEM_CAM_DQ<10> MEM_CAM_DQ<11> MEM_CAM_DQ<12> MEM_CAM_DQ<13> MEM_CAM_DQ<14> MEM_CAM_DQ<15>

PCIE_CAMERA_D2R_C_P PCIE_CAMERA_D2R_C_N

71 32

OUT

71 32

IN

2

5% 1/20W MF 0201

31

R3990

12

OUT

100K

18

IN

MEM_CAM_RAS_L MEM_CAM_WE_L MEM_CAM_CAS_L MEM_CAM_RESET_L

72

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

32

IN

BI

32 75

18

IN

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

NOSTUFF

A13 XTAL_P A12 XTAL_N

I2C_CAM_SMBDBG_CLK I2C_CAM_SCK I2C_CAM_SMBDBG_DAT I2C_CAM_SDA

D15 R10 C15 R9

I2C_CLK_DBG I2C_CLK_SENSOR I2C_DATA_DBG I2C_DATA_SENSOR

TP_CAM_JTAG_TCK TP_CAM_JTAG_TDI TP_CAM_JTAG_TDO TP_CAM_JTAG_TMS TP_CAM_JTAG_TRST_L CAM_JTAG_SRST_L

F13 E12 F12 D12 D11 C11

JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST* JTAG_SRST*

CAMERA_CLKREQ_L CAM_PCIE_RESET_L CAM_PCIE_WAKE_L

P13 PCIE_CLKREQ* R14 PCIE_RST* N12 PCIE_WAKE*

1

R3901

C3990

100K

0.1UF

5% 1/20W MF

10% 6.3V 2 CERM-X5R 0201

OUT OUT

32 75

OUT

32

G12 E15 R13 H12

100K R12 CAM_RAMCFG0 P12 CAM_RAMCFG1 P11 CAM_RAMCFG2 P10 CAM_GPIO3 P9 NC N11 NC N10 NC N9

GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07

4

5% 1/20W MF 201 2

31 31 31

NOSTUFF

R39371 100K

5% 1/20W MF 201 2

NC

UARTCTS D13 UARTRTS D14

CAM_UARTCTS TP_CAM_UARTRTS

UARTRXD E13 UARTTXD E14

CAM_UARTRXD TP_CAM_UARTTXD

TEST_OUT J12 TEST_MODE M10

CAM_TEST_OUT CAM_TEST_MODE

STRAP_XTAL_FREQ C13

CAM_XTAL_FREQ CAM_XTAL_SEL

31

31

B 31 31

31

31

DDR_PWR_SEL RESET* SENSOR_WAKE* SHUTDOWN*

PD = 1.35V

2 201

32 31

PP1V8_CAM CAM_A1

31

R3915

31

100K 5% 1/20W MF

CAM_SENSOR_WAKE_L CAMERA_PWR_EN

NO STUFF 1

PU on PCH page

R3911 100K

100K

31

A1 SILICON BUG

31 32

1

R3910

2 201

CAM_JTAG_SRST_L PP1V8_CAM

CAM_TEST_MODE

CAM_TEST_OUT

5% 1/20W MF 2 201

5% 1/20W MF

2 201

CAM_XTAL:YES

R3904

1

R3906

100K

CAM_XTAL_FREQ PU = 25MHz

5% 1/20W MF 2 201

100K 5% 1/20W MF

SYNC_MASTER=J44

2 201

CAM_XTAL_SEL CAM_XTAL:NO

PAGE TITLE 31

DRAWING NUMBER

1

R3907

Apple Inc.

100K 5% 1/20W MF

2 201

SYNC_DATE=08/12/2013

Camera 1 of 2

3

2

SIZE

D REVISION

R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

5

C

R3936

1

31

32 75

B10 PCIE_REFCLKP A10 PCIE_REFCLKN

CLK25M_CAM_CLKP CLK25M_CAM_CLKN

1

32 75

B11 TP_CAM_TEST_MODE0 C14 TP_CAM_TEST_MODE1 B14 TP_CAM_TEST_MODE2 A15 TP_CAM_LV_JTAG_TCK E11 TP_CAM_LV_JTAG_TDI E10 TP_CAM_LV_JTAG_TDO F11 TP_CAM_LV_JTAG_TMS F10 TP_CAM_LV_JTAG_TRSTN G11 NC G10 NC H11 NC H10 NC J10 NC K11 NC K10 NC L11 PP1V8_CAM 32 31 NC L10 NOSTUFF NC 1

DEBUG_00 DEBUG_01 DEBUG_02 DEBUG_03 DEBUG_04 DEBUG_05 DEBUG_06 DEBUG_07 DEBUG_08 DEBUG_09 DEBUG_10 DEBUG_11 DEBUG_12 DEBUG_13 DEBUG_14 DEBUG_15 DEBUG_16

CRITICAL OMIT_TABLE

A8 PCIE_TDP0 B8 PCIE_TDN0

CAM_PWR_SEL CAM_DEBUG_RESET_L

32 75

OUT

FBGA SYM 1 OF 3

STRAP_XTAL_SEL C12

BI

1

PLACE_NEAR=U3900.M13:2.54MM

B7 PCIE_RDP0 A7 PCIE_RDN0

PCIE_CLK100M_CAMERA_C_P PCIE_CLK100M_CAMERA_C_N

NOSTUFF

PP1V8_CAM

PLACE_NEAR=U3900.M13:4MM

GND_CAM_PVSSC

MIPI_DATA_P MIPI_DATA_N

BI

0

20% 2 6.3V X5R 402

31

1008

C3915 4.7UF

20% 2 6.3V X5R 402

P7 MIPI_CP_CLK R7 MIPI_CM_CLK

OUT

1

1

B9 PCIE_TESTP NC C9 PCIE_TESTN NC

5% 1/20W MF 201 2

PCIE_WAKE_L

31

C3914 4.7UF

10% 2 6.3V CERM-X5R 0201

MIPI_CLK_P MIPI_CLK_N

31 68 32

1

P6

5% 1/20W MF 2 201 C2 E3 E4 D3 F3 F1 F4 F2 B5 C3 B1 B4 A5 C5 B2 B3

5% 1/20W MF 2 201

R3935

MIPI_DP1 NC R6 MIPI_DM1 NC

1

DDR_DQ00 DDR_DQ01 DDR_DQ02 DDR_DQ03 DDR_DQ04 DDR_DQ05 DDR_DQ06 DDR_DQ07 DDR_DQ08 DDR_DQ09 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15

5% 1/20W MF 201

330K

5% 1/20W MF 201

31

U3900

R3991

L3 M4 N3 M3 M1 M2 P4 N2 P3 P2 J4 R2 L1 P1 R4

DDR_AD00 DDR_AD01 DDR_AD02 DDR_AD03 DDR_AD04 DDR_AD05 DDR_AD06 DDR_AD07 DDR_AD08 DDR_AD09 DDR_AD10 DDR_AD11 DDR_AD12 DDR_AD13 DDR_AD14

0.1UF

31 68 32

10% 2 6.3V CERM-X5R 0201

MEM_CAM_A<0> MEM_CAM_A<1> MEM_CAM_A<2> MEM_CAM_A<3> MEM_CAM_A<4> MEM_CAM_A<5> MEM_CAM_A<6> MEM_CAM_A<7> MEM_CAM_A<8> MEM_CAM_A<9> MEM_CAM_A<10> MEM_CAM_A<11> MEM_CAM_A<12> MEM_CAM_A<13> MEM_CAM_A<14>

w

C3960

OUT

w

75 32

17 31

PP1V2_CAM_XTALPCIEVDD

1

OUT

31 32 75

PP1V2_CAM_XTALPCIEVDD

XTAL_AVDD1P2 B13

75 32 31

w

PP1V2_CAM PP1V35_CAM

R3933

1

31

BCM15700

C3937

BCM15700

VSENSE_C M11 VSENSE_D K12

IN

75 68 32

1K

5% 1/20W MF 201 2

U3900

R11

5% 1/20W MF 2 201

1

BYPASS=U3900.F15:2.54MM 10% 2 10V X5R 402 BYPASS=U3900.G15:2.54MM

31

C3974

10% 2 6.3V CERM-X5R 0201

R39131 R39141

BYPASS=U3900:7mm BYPASS=U3900:3mm BYPASS=U3900:3mm BYPASS=U3900:5mm BYPASS=U3900:5mm BYPASS=U3900:5mm

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V

B15

51K

C3940 0.1UF

20% 6.3V 2 X5R 402

1UF

PP1V2_CAM

75 68 32

PP1V8_CAM

32 31

20% 6.3V 2 X5R 402

4.7UF

R3975

0.1UF

10% 2 6.3V CERM-X5R 0201

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.175MM VOLTAGE=0V

VDD1P2_O F15

1

C3951

BYPASS=U3900.J1:2.54MM BYPASS=U3900.L7:2.54MM BYPASS=U3900.J1:2.54MM BYPASS=U3900.D6:2.54MM BYPASS=U3900.L7:2.54MM BYPASS=U3900.D6:2.54MM

VDD_3P3A J11

L3901:1 L3902:1

1

XW3900 SM GND_CAM_PVSSC

1

BYPASS=U3900.F6:2.54MM BYPASS=U3900.F9:2.54MM BYPASS=U3900.F6:2.54MM BYPASS=U3900.L9:2.54MM BYPASS=U3900.F9:2.54MM BYPASS=U3900.L9:2.54MM

o C3919 0.1UF

BYPASS=U3900.D7:2.54MM

4.7UF

H14 H15 J13 J14 J15

C3973

10% 2 16V X7R-CERM 0201

20% 6.3V 2 CERM-X5R 0402-1

1000PF

1

VDD_1P35A F14

VDDC

2

R3931 330K

1000PF

10% 2 6.3V CERM-X5R 0201

.c

1

(=PP3V3_S3RS0_CAMERA)

M14 M15 N15

1

2

(=PP3V3_S3RS0_CAMERA)

CAM_UARTRXD

1

PP1V8_CAM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.8V

1

31

C3970

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V

PLL_VDD1P8 D6

SR_VDD_3P3D

I2C_CAM_SMBDBG_CLK 31 I2C_CAM_SMBDBG_DAT 31

1

31

1.0UH-1.6A-55MOHM 1 2 P1V2_CAM_SRVLXC_PHASE

MIPI_AVDD1P8 L7

SR_VDD_3P3C

1

17 31

2 6.3V CERM-X5R

10UF

20% 6.3V 2 X5R 0201-1

PP1V2_CAM_PCIE_PVDD_FLT

DDR_AVDD1P8 J1

OTP_VDD3P3 D7

5% 1/20W MF 2 201

PP1V2_CAM

L3904

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V

PCIE_PVDD1P2 D9

SR_PVSSD

CAM_RAMCFG2 CAM_RAMCFG1 CAM_RAMCFG0

100K

0603

20% 6.3V 2 CERM-X5R 0402-1

2 X5R

VDDO18

8

100K

220-OHM-1.4A

PCIE_VDD1P2 C8

5% 1/20W MF 2 201

R3920 1R3921

L3903

10% 2 6.3V CERM-X5R 0201

SR_PVSSC

100K

PP1V8_CAM

32 31

5% 1/20W MF 2 201

1

CAM_UARTCTS

20% 6.3V 2 X5R 402

GND_CAM_PVSSD

31

1

PP0V675_CAM_VREF

DDR_VDDIO_CK G5

B12 XTAL_AVSS

A

20% 2 6.3V X5R 402

220-OHM-1.4A

PMU_AVSS

31

4.7UF

x

C

PLACE_NEAR=U3900.K13:4MM

fi

A1 A6 B6 D1 D5 E5 G1 G6 G7 G8 G9 H5 H6 H7 H8 H9 J5 J6 J7 J8 J9 K1 K5 K6 K7 K8 K9 A14 M9 N1 P5 R1 R5 E9

C3913

a

K15 L12 L13 L14 L15

10% 2 6.3V CERM-X5R 0201

h

GND_CAM_PVSSD

4.7UF

.c

31

N13 P14 P15 R15

1

5% 1/20W MF 2 201

1

DDR_VREF_O N5

GND_CAM_PVSSC

0.1UF

20% 6.3V 2 X5R 0201-1

C3912

1

C3900

0.1UF

31

C3924

R3934

100K

5% 1/20W MF 2 201

1008

NOSTUFF

1

R3932

100K

m

MIPI_AGND DDR_VDDIO

G14 M12

10% 2 6.3V CERM-X5R 0201

10% 2 6.3V CERM-X5R 0201

CRITICAL

1

1.0UF

0.1UF

OMIT_TABLE C10 C7

C3923

in

N7 N8 N6

1

0.1UF

20% 2 6.3V X5R 0201-1

2

C3922

NOSTUFF

1

R3930

0402

BCM15700

D

1

1.0UF

22NH

PP1V35_DDR_CLK

C3921

NOSTUFF

1 31

1

31 32

BRANCH

PAGE

39 OF 120 SHEET

31 OF 78

1

A

8

6

5

1

BYPASS=U4000.B2:4mm

C4002

1

10UF

C4003

PP0V675_CAM_VREF

1 0201

0.47UF

2

75

75

2.2UF

20% 10V 2 X5R-CERM 402

C4007

1

0.1UF

C4008 2.2UF

10% 2 6.3V CERM-X5R 0201

70 14

BYPASS=U4000.K2:4mm 1

20% 10V 2 X5R-CERM 402

0.1UF

10% 2 6.3V CERM-X5R 0201

70 14

IN

PCIE_CAMERA_R2D_C_N

C4032

70 31

IN

PCIE_CAMERA_D2R_C_P

C4031

70 68 12

C4011

IN

75 31

IN

75 31

IN

75 31

IN

75 31

IN

75 31

IN

75 31

IN

75 31

IN

75 31

IN

75 31

IN

75 31

IN

MEM_CAM_BA<0> MEM_CAM_BA<1> MEM_CAM_BA<2>

K4B4G1646B-HYK0

84.5 1% 1/20W MF 2 201

75 31

IN

75 31

IN

75 31

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

OMIT_TABLE

M2 BA0 N8 BA1 M3 BA2

MEM_CAM_RAS_L MEM_CAM_CAS_L MEM_CAM_WE_L

IN

IN

NO STUFF

75 31

IN

K9 CKE L2 CS*

82

75

1% 1/20W MF 2 201

MEM_CAM_CKE_R 31

NO STUFF

IN

DQSU C7 DQSU* B7

MEM_CAM_DQS_P<1> MEM_CAM_DQS_N<1>

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

MEM_CAM_ODT

K1 ODT

MEM_CAM_ZQ_DDR

L8 ZQ

MEM_CAM_RESET_L

T2 RESET*

1

R4021

R4006

IN

C4062

1

2 PCIE_CAMERA_D2R_P OUT 10% 16V X5R-CERM 0201

14 68 70

2 PCIE_CAMERA_D2R_N OUT 10% 16V X5R-CERM 0201

14 68 70

PCIE_CLK100M_CAMERA_C_P

2

10% 16V X5R-CERM

1

D

0201

PCIE_CLK100M_CAMERA_C_N

2

10% 16V X5R-CERM

0201

OUT

31 70

OUT

31 70

C4014 BI

31 75

BI

31 75

BI

31 75

BI

31 75

BI

31 75

BI

31 75

BI

31 75

BI

31 75

12PF 1

MEM_CAM_DQ<8> MEM_CAM_DQ<9> MEM_CAM_DQ<10> MEM_CAM_DQ<11> MEM_CAM_DQ<12> MEM_CAM_DQ<13> MEM_CAM_DQ<14> MEM_CAM_DQ<15> MEM_CAM_DM<0> MEM_CAM_DM<1>

CAM_XTAL:NO

m

CAM_XTAL:YES

R4007 0

1 0201

Y4000

2

CLK25M_CAM_CLKP

IN

31 71

R4009

2

CLK25M_CAM_XTALP_R NOSTUFF

71

5% 1/20W MF

5% 1/20W MF 0201

R4012 1M

1% 1/20W MF 2 201

25.000MHZ-12PF-20PPM CAM_XTAL:YES

2

71

0

1

1

SM-3.2X2.5MM

5% CAM_XTAL:YES 25V NP0-C0G-CERM 0201

0

1

0201 5% MF 1/20W

2

CAM_XTAL:YES

R4010

CLK25M_CAM_XTALN

1

0

5% 1/20W MF 0201

NOTE: TBD PPM crystal required

2 CLK25M_CAM_CLKN OUT 31 71 CAM_XTAL:YES CAM_XTAL:NO 1

C4016 100PF

5% 2 25V NP0-CERM 0201

BI

31 75

BI

31 75

C

BI

31 75

PP1V8_CAM

31

31 75

BI

1

R4005 100K

BI

31 75

BI

31 75

BI

31 75

BI

31 75

BI

31 75

BI

31 75

BI

31 75

CAM_WAKE:NO

BI

31 75

R40311

5% 1/20W MF

CAM_WAKE:YES

2 201

R4030 68 32

CAM_SENSOR_WAKE_L_CONN

1 0201

0

2

31

CAM_SENSOR_WAKE_L

5% 1/20W MF

0

IN

31 75

IN

31 75

5% 1/20W MF 0201 2

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

h

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

5% 2 25V NP0-CERM 0201

D7 C3 C8 C2 A7 A2 B8 A3

DML E7 DMU D3

VSSQ

100PF

MEM_CAM_DQ<0> MEM_CAM_DQ<1> MEM_CAM_DQ<2> MEM_CAM_DQ<3> MEM_CAM_DQ<4> MEM_CAM_DQ<5> MEM_CAM_DQ<6> MEM_CAM_DQ<7> MEM_CAM_DQS_P<0> MEM_CAM_DQS_N<0>

J7 CK K7 CK*

MEM_CAM_CKE MEM_CAM_CS_L

E3 F7 F2 F8 H3 H8 G2 H7

DQSL F3 DQSL* G3

J3 RAS* K3 CAS* L3 WE*

MEM_CAM_CLK_P MEM_CAM_CLK_N

IN

NC NC

in

R4020

25V 5% 0201 NP0-C0G-CERM

CRITICAL

IN 1

C4061

PCIE_CLK100M_CAMERA_N

CLK25M_CAM_XTALP CRITICAL

o

IN

75 31

NC

71

.c

75 31

PCIE_CLK100M_CAMERA_P

31 70

x

C

IN

IN

SYSCLK_CLK25M_CAMERA

IN

fi

2

75 31

FBGA

12PF CAM_XTAL:YES 1 2

NC NC NC NC NC

a

5% 1/20W MF 201

IN

4GB-DDR3-256MX16

C4015

J1 J9 L1 L9 M7

3

1K

IN

75 31

U4000

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

2 4

R4003

75 31

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

71 17

1

1

MEM_CAM_A<0> MEM_CAM_A<1> MEM_CAM_A<2> MEM_CAM_A<3> MEM_CAM_A<4> MEM_CAM_A<5> MEM_CAM_A<6> MEM_CAM_A<7> MEM_CAM_A<8> MEM_CAM_A<9> MEM_CAM_A<10> MEM_CAM_A<11> MEM_CAM_A<12> MEM_CAM_A<13> MEM_CAM_A<14>

VREFDQ H1

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

VDD

1K

NOSTUFF

C4030

31 70

2 PCIE_CAMERA_R2D_N OUT 10% 16V X5R-CERM 0201

R4008 VDDQ

IN

PCIE_CAMERA_D2R_C_N

0.1UF

10% 2 6.3V CERM-X5R 0201

R40021

75 31

IN

1

2 PCIE_CAMERA_R2D_P OUT 10% 16V X5R-CERM 0201

0.1UF

1K

IN

1

0.1UF

70 68 12

75 31

1

0.1UF

BYPASS=U4000.R9:4mm

70 31

1

10% 6.3V CERM-X5R 2 0201

IN

1

0.1UF

0.1UF

75 31

C4033

0.1UF

C4010 1

5% 1/20W MF 201 2

PCIE_CAMERA_R2D_C_P

1

0.1UF

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.675V

1% 1/20W MF 201 2

IN

C4009

PP0V675_MEM_CAM_VREFCA

R40231

1

0.1UF

C4006

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.675V

1% 1/20W MF 201 2

75 31

BYPASS=U4000.D2:4mm 1

1

PP0V675_MEM_CAM_VREFDQ

5% MF 1/20W

1K

75 31

C4005

BYPASS=U4000.H9:4mm

R40221

75 31

1

20% 10% 4V 6.3V 2 CERM-X5R-1 2 CERM-X5R 201 0201

20% 6.3V 2 CERM-X5R 0402-1

R4000 0

C4004

1

10UF

20% 6.3V 2 CERM-X5R 0402-1

75 31

2

3

PP1V35_CAM BYPASS=U4000.A1:4mm

D

4

VREFCA M8

75 31

7

1

B

.c

R4004

B

240

CAMERA SENSOR

w

1% 1/20W MF 2 201

L4009

w

90-OHM-50MA TCM0605-1 SYM_VER-1

CRITICAL

1

4

MIPI_CLK_N

IN

31 68 75

2

3

MIPI_CLK_P

IN

31 68 75

J4002

CCR20-AK7100-1 F-RT-SM 14

w

PLACE_NEAR=J4002.2:2.54MM

CRITICAL

1 2

75 68

3

75 68

4 5

75 68

6

75 68

MIPI_CLK_CONN_N MIPI_CLK_CONN_P CAM_SENSOR_WAKE_L_CONN MIPI_DATA_CONN_N MIPI_DATA_CONN_P

L4007

90-OHM-50MA TCM0605-1 SYM_VER-1

32 68

1

4

MIPI_DATA_N

BI

31 68 75

2

3

MIPI_DATA_P

BI

31 68 75

7

A

ALS

8 9 10 11 12

13

68

SMBUS_SMC_1_S0_SDA 14 36 BI SMBUS_SMC_1_S0_SCL 14 36 IN I2C_CAM_SCK IN 31 68 I2C_CAM_SDA 31 68 BI PP5V_S3RS0_ALSCAM_F

39 43 68 72 76

PLACE_NEAR=J4002.5:2.54MM 39 43 68 72 76

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

CRITICAL L4010 FERR-120-OHM-1.5A 2 1 PP5V_S0 0402-LF

C4013 1 0.1uF

20% 10V CERM 2 402

518S0892

SYNC_MASTER=J44 PAGE TITLE 16 17 41 44 45 53 54 58 60 61 65 68

DRAWING NUMBER

Apple Inc.

NOSTUFF

L4011

NOTICE OF PROPRIETARY PROPERTY: 33 46 55 56 57 60 62 63 65 66 68

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

77.2 mA nominal max 96.2 mA peak

7

6

5

4

3

2

SIZE

D REVISION

R

FERR-120-OHM-1.5A 2 1 PP5V_S4 0402-LF

8

SYNC_DATE=08/12/2013

Camera 2 of 2 BRANCH

PAGE

40 OF 120 SHEET

32 OF 78

1

A

8

7

6

5

4

2

3

1

RIGHT USB PORT A

D

USB Port Power Switch

D

CRITICAL

CRITICAL

L4605

U4600

FERR-120-OHM-3A

TPS2557DRB

PP5V_S3_LTUSB_A_ILIM

SON 66 65 63 62 60 57 56 55 46 32 68

2

PP5V_S4

3

IN_0 IN_1

OUT1 OUT2

6

FAULT*

ILIM

5

1

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=5V

7

2

68 PP5V_S3_LTUSB_A_F MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V

0603

C4605

1

0.01UF 8

USB_PWR_EN

4

CRITICAL 1

1

10UF 20% 6.3V CERM-X5R 0402-2

1

C4691

R4600 GND

C4696

0.1UF 2

2

EN

1% 1/20W MF 201

220UF-35MOHM

10% 16V X5R-CERM 0201

2

10% 16V X5R-CERM 0201

1

1

C4695

J4600 F-RT-TH

90-OHM

10UF

2

20% 6.3V CERM-X5R 0402-2

R4601

1 2 3 4 5 6 7 8 9 10

L4600

1

DLP0NS

SYM_VER-1

2

4

22.1K

71

1% 1/20W MF 201

71

USB2_EXTA_MUXED_N USB2_EXTA_MUXED_P

1

.c

2

CRITICAL USB3.0-J44-ALT

CRITICAL

USB_ILIM_L

20% 6.3V POLY-TANT CASE-B2-SM1

2

22.1K

THRM PAD

1

C4690

USB_ILIM

m

61

XDP_USB_EXTA_OC_L

o

OUT

9

16 14

Current limit per port (R4600+R4601): 2.19A min / 2.76A max

USB2_EXTA_MUXED_F_N 71 USB2_EXTA_MUXED_F_P 71

2

CRITICAL

2

CRITICAL

2

D4601

D4600

ESD0P2RF-02LS

ESD0P2RF-02LS

TSSLP-2-1

Mojo SMC Debug Mux

1

fi

PP3V42_G3H

1

1

0.1UF

IN

71 37 36

OUT

2

VCC

SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L

5 M+ 4 M-

USB_EXTA_P USB_EXTA_N

7 D+ 6 D-

U4650

2

71 68 14

5% 1/20W MF 201 71 68 14

Y+ 1 Y- 2

PI3USB102EZLE BI

71 14

BI

8

TQFN CRITICAL

SEL 10

OE*

SMC_DEBUGPRT_EN_L SEL

IN

OUT

USB3_EXTA_D2R_P

L H

GND SXRX+ SSRXGND

GND_VOID=TRUE

C

GND_VOID=TRUE

CRITICAL

2

2

D4621

CRITICAL

D4620

ESD0P2RF-02LS

ESD0P2RF-02LS

TSSLP-2-1

TSSLP-2-1

36

1

OUTPUT

3

GND SIGNAL_MODEL=MOJO_MUX_SMSC

USB3_EXTA_D2R_N

GND

DD+

1

h

71 14

OUT

in

71 37 36

R4650 100K

9

10% 10V X5R-CERM 0201

a

BYPASS=U4650.9:3:5mm

C4650

SSTX-

11 12 13 14 15 16 17 18 19 20 21 22 23

1

THE PI3USB102E CAN CLAMP VOLTAGE IN THE INTERNAL USB PINS

52 51 45 39 38 37 36 34 30 17 68 65 61

SSTX+

TSSLP-2-1

x

C

3

VBUS

SMC (M) USB (D)

.c

B

71 68 14

IN

USB3_EXTA_R2D_C_N

B GND_VOID=TRUE

C4620 0.1UF 1

2

IN

w

71 68 14

USB3_EXTA_R2D_C_P

71 68

USB3_EXTA_R2D_N

71

USB3_EXTA_R2D_P

C4621 10%

6.3V

CERM-X5R 0201

0.1UF 1

10%

2

6.3V

CERM-X5R 0201

GND_VOID=TRUE GND_VOID=TRUE

GND_VOID=TRUE

CRITICAL

2

2

w

D4611

CRITICAL

D4610

ESD0P2RF-02LS

ESD0P2RF-02LS

TSSLP-2-1

TSSLP-2-1 1

w

1

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

External A USB3 Connector DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

46 OF 120 SHEET

33 OF 78

1

A

8

7

6

5

4

2

3

IPD Flex Connector

1

CRITICAL

J4800

FF14-18C-R11DL

SMC Manual Reset & Isolation

F-RT-SM 20

R4808

Left shift, option & control keys combined with power button cause SMC RESET# assertion. Keys ANDed with PSoC power to isolate when PSoC is not powered. No IPD on OE input pin PP3V3_S4 (symbol error). 51 45 39 38 37 36 34 33 30 17 68 65 61 52

65 64 63 60 42 38 37 34 29 18 68

PP3V3_S4

0

1

518S0848

2

68

5% 1/20W MF 0201

PP3V42_G3H

1

0.1UF

10

36 68

68 34

68 34

PLACE_NEAR=J4800.4:3MM

4 OE

PP5V_S5

68 65 56

1

68 34

(IPD) 68 34

WS_LEFT_OPTION_KBD

2 IN_2

68 34

WS_CONTROL_KBD

3 IN_3

(IPD)

0402-LF

WS_LEFT_SHIFT_KEY

OUT_1 9

1 IN_1

OUT_2 8

WS_LEFT_OPTION_KEY

34

OUT_3 7

WS_CONTROL_KEY

34

68 34

C4807 0.1UF

68 34

10% 10V 2 X5R-CERM 0201

(IPD)

68 34

68 34

PLACE_NEAR=J4800.4:4MM

Pull-up in U5110.

SMC_TPAD_RST_L

OUT_ALL# 6

68 34

34

1

OUT

37

7 8 9 10 11

Z2_MOSI PSOC_F_CS_L Z2_CS_L Z2_KEY_ACT_L PICKB_L Z2_HOST_INTN

13 14 15 16 17 18

19

R48001 5% 1/20W MF 201 2

o

11

.c

5

D

6

PSOC_SCLK PSOC_MOSI Z2_SCLK PSOC_MISO Z2_MISO

51K

THRM PAD

GND

5

12

2

(IPD)

WS_LEFT_SHIFT_KBD

3

SMBUS_SMC_2_S3_SDA

m

68 34

68 34

FERR-120-OHM-1.5A

TQFN

PP3V3_S4

68 34

L4807

SLG4AP4103 65 64 63 60 42 38 37 34 29 18 68

2

4

VOLTAGE=5V MIN_NECK_WIDTH=0.20MM39 MIN_LINE_WIDTH=0.50MM76

68 34

U4850

Z2_CLKIN SMBUS_SMC_2_S3_SCL

PP5V_S4_CUMULUS

10% 16V X7R-CERM 2 0402

VDD

1 34

76 68 39 36 68

10% 6.3V 2 CERM-X5R 0201

C4850 1

D

C4808 0.1UF

BYPASS=U4850.10:5:5 mm

PP3V3_TPAD_CONN VOLTAGE=3.3V MIN_NECK_WIDTH=0.20MM 68 MIN_LINE_WIDTH=0.50MM

NOSTUFF

C

USB INTERFACES TO MLB SPI HOST TO Z2 TRACKPAD PICK BUTTONS KEYBOARD SCANNER

PLACE_SIDE=BOTTOM PP3V3_S3_PSOC MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V

5% 1/16W MF-LF 402

1

220K

5% 1/20W MF 201 2

68 34 34 68 34 34

1

68 34 68 34 68 34 68 34 68 34 68 34 68 34 68 34

NC NC

PSOC_MISO PSOC_F_CS_L PSOC_MOSI PSOC_SCLK Z2_MISO Z2_CS_L Z2_MOSI Z2_SCLK

U4801 CY8C24794 MLF-1 (SYM-VER2)

337S4426

TP_PSOC_SCL TP_PSOC_SDA TP_PSOC_P1_3 TP_ISSP_SCLK_P1_1

71 14

USB_TPAD_P

1

24

57

WS_KBD4 WS_KBD5 WS_KBD6 TP_ISSP_SDATA_P1_0

ISSP SCLK/I2C SCL R4801

A

P2_2 P2_0 P4_6 P4_4 P4_2 P4_0 P3_6 P3_4 P3_2 P3_0 P5_6 P5_4 P5_2 P5_0 THRML PAD

2

71

Z2_CLKIN TP_P7_7

USB_TPAD_R_P

USB_TPAD_N

1

38 37 36

34 68 34 68

IN

2

G

68 34 68 34

THE TPAD BUTTONS WILL BE DISABLE WHEN THE LID IS CLOSED LID OPEN => SMC_LID_LC ~ 3.42V LID CLOSE => SMC_LID_LC < 0.50V

S 1

SMC_LID

R4814 34

WS_KBD15_C

34 68 34 68 34 68

34 68 34 34

34 68 34 68 34 68

2

71

113

68 34 68 34

2

68 34 68 68

R4815 34

WS_KBD16N

1

Q4801

68 37 36

OUT

SMC_ONOFF_L

1

2

68 34 68 34 68 34

S 4

C4810 1

NC

20% 10V CERM 2 402

1K

68 34 68 34

2

68

5% 1/16W MF-LF 402

PLACE_NEAR=J4813.5:5MM

NC

68 34

R4810

SOT-563

G

68 34

Spare MOSFET symbol

D 3

DMN5L06VK-7

5

0

5% 1/16W MF-LF 402

NC

34 68 34 68

1

1% 1/16W MF-LF 402

34 68

0.1UF

68 34 68 34 68 34

WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD

B

31 F-RT-SM

34 68

FF14A-30C-R11DL-B-3H

34 68 34 68 34 68 34 68 34 68

34 68 34 68 34 68

34 68

SYNC_MASTER=J44

USB_TPAD_R_N

C4802 100PF

5% 25V 2 NP0-CERM 0201

1

C4803 0.1UF

10% 6.3V 2 CERM-X5R 0201

1

C4801 4.7UF

20% 2 6.3V X5R 402

BYPASS=U4801.22:19:5 mm BYPASS=U4801.22:19:8 mm BYPASS=U4801.22:19:11 mm

KEYBOARD/TRACKPAD (1 OF 2) TMP102

6

PIN NAME CURRENT R_SNS V+

3V3 LDO

VDD VOUT VDD

PSOC 18V BOOSTER

7

SYNC_DATE=08/12/2013

PAGE TITLE

IC 1

5% 1/20W MF 201

8

68 34

(PP3V3_S3_PSOC)

R4802 71 14

68 34

WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD_ONOFF_L

ISSP SDATA/I2C SDA

5% 1/20W MF 201

24

68 34

SOT-563

.c

TPAD_VBUS_EN

CRITICAL OMIT

WS_KBD17 WS_KBD16N WS_KBD15_C WS_KBD14 WS_KBD13 WS_KBD12 WS_KBD11 WS_KBD10 WS_KBD9 WS_KBD8 WS_KBD7 WS_KBD1 WS_KBD2 WS_KBD3

D

6

w

IN

P2_3 P2_1 P4_7 P4_5 P4_3 P4_1 P3_7 P3_5 P3_3 P3_1 P5_7 P5_5 P5_3 P5_1

42 41 40 39 38 37 36 35 34 33 32 31 30 29

68 34

PLACE THESE COMPONENTS CLOSE TO J4800 THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

w

61

NC

P2_5 P2_7 P0_1 P0_3 P0_5 P0_7 VSS VDD P0_6 P0_4 P0_2 P0_0 P2_6 P2_4

34 68 34

1 2 3 4 5 6 7 8 9 10 11 12 13 14

WS_CONTROL_KEY Z2_KEY_ACT_L

15 P1_7 16 P1_5 17 P1_3 18 P1_1 19 VSS 20 D+ 21 D22 VDD 23 P7_7 24 P7_0 25 P1_0 26 P1_2 27 P1_4 28 P1_6

B

68 34

DMN5L06VK-7

20% 2 6.3V X5R 402

WS_KBD23 WS_KBD22 WS_KBD21 WS_KBD20 WS_KBD19 WS_KBD18

SMC_PME_S4_WAKE_L PICKB_L BUTTON_DISABLE Z2_HOST_INTN WS_LEFT_SHIFT_KEY WS_LEFT_OPTION_KEY

68 34

68 34

Q4801

4.7UF

10% 2 6.3V CERM-X5R 0201

68 34

BUTTON_DISABLE

C4806

56 55 54 53 52 51 50 49 48 47 46 45 44 43

34

C4805 0.1UF

5% 2 25V NP0-CERM 0201

R4803

OUT

1

100PF

1

38 36 29

C4804

34

a

1.5 1

in

2

h

PP3V3_S4

68 34

C

32

w

60 42 38 37 34 29 18 68 65 64 63

51 45 39 38 37 36 34 33 30 17 68 65 61 52

TPAD Buttons Disable

BYPASS=U4801.49:50:11 mm BYPASS=U4801.49:50:8 mm BYPASS=U4801.49:50:5 mm

R4804

J4813 PP3V3_S4 PP3V42_G3H

65 64 63 60 42 38 37 34 29 18 68

fi

-

518S0752 CRITICAL

x

PSOC USB CONTROLLER

Keyboard Connector

5

VIN

10UA 80UA 60MA (MAX) 60MA (MAX) 8MA (TYP) 14MA (MAX) 4MA (MAX)

2.55 KOHM

V_SNS 0.0255 0.204 0.6 0.012 0.012 0.021 0.0188

10 OHM 0.2 OHM 1.5 OHM 4.7 OHM

4

V V V V V V V

POWER 0.255E-6 16.32E-6 36E-3 0.72E-3 96E-6 294E-6 75.2E-6

DRAWING NUMBER

Apple Inc.

W W W W W W W

REVISION

R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

3

2

BRANCH

PAGE

48 OF 120 SHEET

34 OF 78

1

SIZE

D

A

8

7

6

5

4

3

2

1

D

D Keyboard Backlight Connector 516S0899 CRITICAL

J4915 AA07A-S010-VA1

KBDLED_CATHODE2 PPVOUT_S0_KBDBKLT

NC PIN 6 WAS USED KEYBOARD BKLT DETECTION NOT USED ANYMORE

2 4 6 8 10

1 3 5 7 9

KBDLED_CATHODE1 PPVOUT_S0_KBDBKLT

58 68 35 58 68

J4915 PIN 5 IS GROUNDED ON KEYBOARD BACKLIGHT FLEX

.c

13 14

o

68 58 68 58 35

m

F-ST-SM 12 11

C

h

in

a

fi

x

C

B

w

.c

B

w

w

OUT

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

KEYBOARD/TRACKPAD (2 OF 2) DRAWING NUMBER

Apple Inc. R



NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

.

BRANCH

PAGE

49 OF 120 SHEET

35 OF 78

1

A

8

7

6

5

4

2

3

1

D

D U5000

BI

68 45 13

OUT

68 45 13

IN

13

OUT

15

OUT

76 68 62 39

C

BI

76 72 68 43 39 32 14

BI

76 72 68 43 39 32 14

BI

76 68 39 34

BI

76 68 39 34

BI

76 63 43 39

BI

76 63 43 39

BI

38

BI

38

BI

76 68 52 51 39

BI

76 68 52 51 39

BI

44

SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA NC_SMBUS_SMC_4_ASF_SCL NC_SMBUS_SMC_4_ASF_SDA SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

BI

76 68 62 39

OUT

44

IN

38

OUT

38

IN

38

OUT

60 40 38

OUT

58

OUT 38

38

IN OUT

38

OUT

70 37

BI

70 37

OUT

38

IN

37

IN

38 34 29

B

OUT

51 38

37 23 18

IN IN

61 37

OUT

38 37

IN 38

38 37 34

38

IN

OUT

37

IN

52 51 37

IN

18 13

IN

68 63 61 18 17 13

IN

63 61 29 18 13

IN

61 13

IN

68 37 34

IN

68 45 37

IN

68 45 37

OUT

30

OUT

63 38

OUT

(OD) (OD)

E10 D13 M4 N2 N8 M8 L8 K8 N7 M7 N4 N3

(OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD)

SMC_FAN_0_CTL SMC_FAN_0_TACH NC_SMC_FAN_1_CTL NC_SMC_FAN_1_TACH SMC_TOPBLK_SWP_L SMC_SENSOR_PWR_EN

I2C0SCL I2C0SDA I2C1SCL I2C1SDA I2C2SCL I2C2SDA I2C3SCL I2C3SDA I2C4SCL I2C4SDA I2C5SCL I2C5SDA

H11 L13 C11 A12 G3

PM6/FAN0PWM0 PM7/FAN0TACH0 PK6/FAN0PWM1 PK7/FAN0TACH1 PN2/FAN0PWM2 D10 PN3/FAN0TACH2

SMC_SYS_KBDLED NC_SMC_ACTUATOR_DISABLE_L NC_SMC_5VSW_PWR_EN SYS_ONEWIRE NC_SMC_FAN_5_CTL SMC_PCH_SUSACK_L (OD)

L11 N12 N11 M11

PN4/FAN0PWM3 PN5/FAN0TACH3 PN6/FAN0PWM4 PN7/FAN0TACH4 J4 PH2/FAN0PWM5 J2 PH3/FAN0TACH5

CPU_PECI_R SMC_PECI_L

C4 PECI0RX C6 PECI0TX

NC_SMC_BIL_BUTTON_L SMC_DP_HPD_L SMC_PME_S4_WAKE_L SMC_PME_S4_DARK_L SMC_S4_WAKESRC_EN SMC_SENSOR_ALERT_L NC_SMC_T101_COM_1 SMC_LID SMC_PCH_SUSWARN_L SMS_INT_L SMC_BC_ACOK PM_SLP_S0_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L SMC_ONOFF_L

M13 L12 M5 J12 J13 L5 D8 K6

(OD)

D4 E4 F5 N5 N6 K5 M6 L6

(OD)

PP0/IRQ116 PP1/IRQ117 PP2/IRQ118 PP3/IRQ119 PP4/IRQ120 PP5/IRQ121 PP6/IRQ122 PP7/IRQ123 PQ0/IRQ124 PQ1/IRQ125 PQ2/IRQ126 PQ3/IRQ127 PQ4/IRQ128 PQ5/IRQ129 PQ6/IRQ130 PQ7/IRQ131

L3 U0RX M1 U0TX

SMC_RX_L SMC_TX_L SMC_PWRFAIL_WARN_L SMC_WIFI_PWR_EN

E13 USB0DM (PL7) E12 USB0DP (PL6)

(OD)

C0C0+ C1PC5/C1+ T3CCP1/PJ5/C2T3CCP0/PJ4/C2+

K2 K1 L2 L1 C5 D5

CPU_PROCHOT_L IN SMC_VCCIO_CPU_DIV2 IN SMC_S5_PWRGD_VIN IN SPI_DESCRIPTOR_OVERRIDE_LOUT CPU_CATERR_L IN CPU_THRMTRIP_3V3 IN

SSI0CLK/PA2 SSI0FSS/PA3 SSI0RX/PA4 SSI0TX/PA5

M2 M3 L4 N1

SMC_PM_G2_EN PM_DSW_PWRGD SMC_DELAYED_PWRGD SMC_PROCHOT

U1RX/B0 U1TX/PB1 T0CCP0/PB6 T0CCP1/PB7

F11 E11 F4 F3

SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L NC_SMC_SYS_LED NC_SMC_GFX_THROTTLE_L

SSI1RX/PF0 SSI1TX/PF1 SSI1CLK/PF2 SSI1FSS/PF3 PF4 PF5

M9 N9 L10 K10 L9 K9

SPI_SMC_MISO SPI_SMC_MOSI SPI_SMC_CLK SPI_SMC_CS_L S5_PWRGD PM_PCH_SYS_PWROK

ALL_SYS_PWRGD SMC_THRMTRIP

WT2CCP0/PH0 K3 WT2CCP1/PH1 K4 WT3CCP0/PH4 WT3CCP1/PH5 WT4CCP0/PH6 WT4CCP1/PH7

J3 H4 H3 G4

PM_PWRBTN_L PM_SYSRST_L NC_MEM_EVENT_L SMC_ADAPTER_EN

T1CCP0/PJ0 T1CCP1/PJ1 T2CCP0/PJ2 T2CCP1/PJ3

C9 B9 A9 C8

SMC_OOB1_D2R_L SMC_OOB1_R2D_L SMC_BOARDID NC_BDV_BKL_PWM

WT5CCP1/PM3 H10

PM_BATLOW_L

38 40

IN

38 40

IN

38 40

IN

38 42

IN

38 41

IN

38 40

IN

38 40

IN

38 41

IN

38 40

IN

38

IN

38

IN

38 41

IN

38 41

IN

38 42

IN

38

IN

38 41

IN

38 41

IN

38 41

IN

38 42

IN

38 42

IN

38 42

IN

17 30 33 34 37 38 39 45 51 52 61 65 68

1

C5002 1UF

1

C5003 0.1UF

20% 2 6.3V X5R 0201

10% 10V 2 X5R-CERM 0201

1

C5007 0.1UF

10% 10V 2 X5R-CERM 0201

38 42

37 37 17 6 70

1

C5004 0.1UF

10% 10V 2 X5R-CERM 0201

(OD)

13 72

OUT

17 24 25 37 72

OUT

37

IN

33 37 71

OUT

33 37 71

OUT

38 38

IN

45 72

OUT

45 72

OUT

45 72

56 61

IN

13 16 17 72

OUT

33

IN

38

1

C5008 0.1UF

10% 10V 2 X5R-CERM 0201

OUT

OUT

13 16 72

OUT

13 17 68 72

IN

0.1UF

10% 10V 2 X5R-CERM 0201

1

R5002

C5006

1M

0.1UF

45 38 37 68 52

IN

63

BI

0.1UF

37

IN

37 37

1

10% 10V 2 X5R-CERM 0201

LM4FSXAH5BB

WIFI_EVENT_L SMC_WAKE_L NC_SMC_HIB_L

BGA (2 OF 2) SWCLK/TCK SWDIO/TMS PK4/RTCCLK SWO/TDO WAKE* TDI HIB* NC XOSC0 XOSC1 VDDA OSC0 OSC1 VREFA+ VREFAVBAT

G10 RST*

SMC_RESET_L (OD)

B11 N13 M12

SMC_CLK32K NC_SMC_XOSC1

M10

SMC_EXTAL SMC_XTAL

G12 G13

N10

K12

GNDA

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.1MM VOLTAGE=1.2V

K13 D6

C10 A10 A11 B10 A2

SMC_TCK SMC_TMS SMC_TDO SMC_TDI

37 45 68 37 45 68 37 45 68

C

37 45 68

NC

D3

PP3V3_S5_AVREF_SMC

D2 D1

37 68

XW5000 SM

42 41 40 38 37

GND_SMC_AVSS

C3 E3

1

2

PLACE_NEAR=U5000.A1:4MM

OMIT_TABLE VDD

GND

J1 J6

PP1V2_S5_SMC_VDDC

C5001 0.1UF

U5000

5% 1/20W MF 2 201

10% 10V 2 X5R-CERM 0201

C5009

10% 10V 2 X5R-CERM 0201

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V

1

D7 E6 E8 E9 F10 J7 J9 J10

VDDC

A1 C7 D9 E5 F9 H5 H9 J5 J8 J11

1

C5020 0.01UF

1

C5021 1UF

10% 10V 2 X5R-CERM 0201

20% 2 6.3V X5R 0201

BYPASS=U5000.D2:D1:1MM BYPASS=U5000.D2:D1:1MM

K11

B

PLACE_NEAR=U5000.D6:5MM PLACE_NEAR=U5000.K13:5MM PLACE_NEAR=U5000.J6:5MM PLACE_NEAR=U5000.J1:5MM PLACE_NEAR=U5000.D6:5MM PLACE_NEAR=U5000.K13:5MM PLACE_NEAR=U5000.J6:5MM PLACE_NEAR=U5000.J1:5MM

1

C5010 1.0UF

20% 2 6.3V X5R 0201-1

16 17 61 37

BI

C5005

1

PP3V3_S5_SMC_VDDA

45 72

IN

OUT

1

2 0402

37

OUT

IN

L5001

30-OHM-1.7A

6 37 53 70

OUT

BI

PP3V42_G3H

1

37 56 61

OUT

SMC_DEBUGPRT_EN_L NC_SMC_GFX_OVERTEMP

WT0CCP0/PG4 K7 WT0CCP1/PG5 L7

38 40

IN

o

IN

38 40

IN

.c

18 68 45 15

IN

x

IN

SMC_CPU_HI_ISENSE SMC_PBUS_VSENSE SMC_BMON_ISENSE SMC_DCIN_ISENSE SMC_DCIN_VSENSE SMC_BMON_DISCRETE_ISENSE SMC_CPU_ISENSE SMC_OTHER5V_HI_ISENSE SMC_OTHER3V3_HI_ISENSE SMC_DDR_ISENSE SMC_LCDBKLT_ISENSE SMC_ADC11_PD SMC_ADC12_PD SMC_SSD_ISENSE SMC_PP3V3S0_ISENSE SMC_CAMERA_ISENSE SMC_ADC16_PD SMC_PP5VS0_ISENSE SMC_CPUDDR_ISENSE SMC_PCH_ISENSE SMC_CPU_VSENSE SMC_LCDPANEL_ISENSE SMC_CPU_IMON_ISENSE SMC_TBT_ISENSE

fi

72 68 45 14

E2 E1 F2 F1 B3 A3 B4 A4 B5 A5 B6 A6 C1 C2 B1 B2 G2 G1 H1 H2 B7 A7 B8 A8

a

IN

AIN00 AIN01 AIN02 AIN03 AIN04 AIN05 AIN06 AIN07 AIN08 AIN09 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 AIN16 AIN17 AIN18 AIN19 AIN20 AIN21 AIN22 AIN23

in

BI

72 68 17

BGA LPC0AD0 (1 OF 2) LPC0AD1 LPC0AD2 OMIT_TABLE LPC0AD3 LPC0CLK LPC0FRAME* LPC0RESET* LPC0SERIRQ LPC0CLKRUN* LPC0PD* LPC0SCI* PK5

h

BI

72 68 45 14

B13 A13 C12 D11 H12 D12 C13 H13 G11 F13 F12 B12

.c

72 68 45 14

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_CLK24M_SMC LPC_FRAME_L SMC_LRESET_L LPC_SERIRQ PM_CLKRUN_L LPC_PWRDWN_L SMC_RUNTIME_SCI_L SMC_WAKE_SCI_L

w

BI

w

BI

72 68 45 14

w

72 68 45 14

m

LM4FSXAH5BB

1

C5017 1.0UF

20% 2 6.3V X5R 0201-1

1

C5015 0.1UF

10% 2 10V X5R-CERM 0201

1

C5016 0.1UF

1

C5014 1.0UF

10% 2 10V X5R-CERM 0201

1

C5012 0.1UF

20% 2 6.3V X5R 0201-1

10% 10V 2 X5R-CERM 0201

1

C5013 0.1UF

10% 2 10V X5R-CERM 0201

1

C5011 0.1UF

10% 10V 2 X5R-CERM 0201

38 13 37

30

OUT

30

OUT

38

OUT

38

OUT

13 25

NOTE: SMS INTERRUPT IS NOT USED, PULL UP TO SMC RAIL.

A

NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

SMC DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

50 OF 120 SHEET

36 OF 78

1

A

8

7

6

5

4

2

3

1

SMC Reset "Button", Supervisor & AVREF Supply R5127 68 65 45 39 38 33 30 17 37 36 34 61 52 51

PP3V42_G3H

0

1

70 53 36 6

CPU_PROCHOT_L

BI

PP3V42_G3H_SMC_SPVSR MIN_LINE_WIDTH=0.4 mm NOSTUFF MIN_NECK_WIDTH=0.1 mm

2

5% 1/16W MF-LF 402

1

C5127

6 D

VOLTAGE=3.42V

DMN5L06VK-7

5% 25V NP0-C0G-CERM 2 0201

GND_SMC_AVSS PP3V42_G3H 17

PP1V05_S0 SMC_PROCHOT

V+

SMC_TPAD_RST_L SMC_ONOFF_L

IN IN

SMC_MANUAL_RST_L OMIT

R5101 0

4 DELAY

REFOUT 8

GND

C5101 1

SMC_RESET_L

OUT

20% 10V X5R-CERM 2 0402-1

SILK_PART=SMC_RST

1

0.01UF

10% 2 10V X5R-CERM 0201

36 37 38 40 41 42 37 36

52 51 37 36

MAKE_BASE=TRUE

0

R5110 SMC_XTAL_R CRITICAL

Y5110 3.2X2.5MM-SM

SMC_EXTAL

1

3 2 4

C5110

NCNC

1

12PF

C5111

SMC_PME_S4_DARK_L

37 36 23 18

MAKE_BASE=TRUE

12PF

5% 25V 2 NP0-C0G-CERM 0201

5% 25V 2 NP0-C0G-CERM 0201

SMC_PME_S4_DARK_L

h

1

330

5% 1/20W MF 2 201

R5158

72

43 2 1 CPU_PECI_R 5% NOSTUFF 1/20W

OUT

To SMC

3.3K 2 PM_THRMTRIP_L 1 PM_THRMTRIP_R_L 15 IN

1

C5134

CPU_PECI

6 70

BI

From/To CPU/PCH

MF 201

47PF

37 72

5% 2 25V NP0-C0G-CERM 0201

5% 1/20W MF 201

PLACE_NEAR=Q5150.2:5MM

C 51 45 39 38 37 36 34 33 30 17 68 65 61 52

77 68 65 64 62 61 30 28 24 18 17 15 13 12 11 8 50 47 46 44 43 42 41 40 39 38

37 36 23 18

SMC_DP_HD_L IS NOT USED ANY MORE

36

B 13

IN

.c

R5112 22

PM_CLK32K_SUSCLK_R 1 PLACE_NEAR=U0500.AE6:5.1mm

2

38 36 38 36 34 68 45 36 68 45 36 71 36 33 71 36 33

IN

18 23 36 37

68 45 36 68 45 36

60 57 53 37 17 16 15 11 8 6 68 65 61

68 45 36

PP1V05_S0

68 45 36

1

R5197

SMC_CLK32K 5% 1/20W MF 201

100K

OUT

36

36

SMC_VCCIO_CPU_DIV2

w

100K

100K 100K

1

2

1

2

SMC_ONOFF_L SMC_SENSOR_ALERT_L SMC_LID SMC_TX_L SMC_RX_L SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L SMC_TMS SMC_TDO SMC_TDI SMC_TCK

R5170 R5172 R5171 R5173 R5174 R5175 R5176 R5177 R5178 R5179 R5180

10K 10K 100K 10K 100K 20K 20K 10K 10K 10K 10K

1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2

R5187 100K R5192 100K R5193 10K

1 1 1

2 2 2

R5117

1

2

36

37 36

CPU_THRMTRIP_3V3

68 45

SMC_ROMBOOT

1

R5196

R5167 R5168

SMC_BC_ACOK SMC_S5_PWRGD_VIN SMS_INT_L 36

1% 1/20W MF 2 201

w

1% 1/20W MF 2 201

1/20W 1/20W

MF MF

201 201

5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%

1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W

MF MF MF MF MF MF MF MF MF MF MF

201 201 201 201 201 201 201 201 201 201 201

5% 5% 5%

1/20W 1/20W 1/20W

MF MF MF

201 201 201

5%

1/20W

MF

201

5% 5% 5%

1/20W 1/20W 1/20W

MF MF MF

201 201 201

5%

1/20W

MF

201

5%

1/20W

MF

201

B

R5188 1K

5% 1/20W MF 2 201

36 13 37 36

w

100K

5% 5%

1

61 56 36

A

PP3V3_S0

SMC_PME_S4_DARK_L SMC_DP_HPD_L

52 51 37 36

PP3V42_G3H

PP3V3_S4

68 65 64 63 60 42 38 34 29 18

68 37 36 34

12.000MHZ-30PPM-10PF-85C 36

70 36

in

1% 1/20W MF 201

36 37

R5151

R5134

2

a

SMC USB Clock require these crystal values:5,6,8,10,12,16,18,20,24,25 MHz

2.49K2

IN

1

x

SILK_PART=PWR_BTN

1

R5153

5% 1/20W MF 2 201

1

DFN1006-3

PLACE_SIDE=TOP

5% 1/10W MF-LF 2 603

SMC Crystal Circuit

SMC_XTAL

36 37 51 52

R5115

SILK_PART=PWR_BTN

36

MMBT3904LP-7

34 36 37 68

1NOSTUFF

1.6K

fi

C

SMC_BC_ACOK

5% 1/20W MF 0201

3

Q5158

SMC_BC_ACOK

S 2

SMC_PECI_L_R

2

CPU_THRMTRIP_3V3

OUT

CRITICAL

1

0

5% 1/10W MF-LF 603 2

IN

0

1

G 5

SMC_THRMTRIP

.c

R51161

SMC_PECI_L

From SMC

Debug Power "Buttons"

PLACE_SIDE=BOTTOM

70 36

SOT-563

C5126

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=0V

MR1* and MR2* must both be low to cause manual reset. Used on mobiles to support SMC reset via keyboard. NOTE: Internal pull-ups are to VIN, not V+.

OUT

DMN5L06VK-7

36 68

1 G

R5152

Q5159

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=3.3V

GND_SMC_AVSS

PLACE_SIDE=BOTTOM

SMC_ONOFF_L OMIT

3 D

36 38 45 52 68

4 S

10UF

10% 10V X5R-CERM 2 0201

OMIT

OUT

PM_THRMTRIP_L

PAD

0.01UF

5% 1/10W MF-LF 2 603

72 37 15

PP3V3_S5_AVREF_SMC

C5125 1

D

SYM_VER_2

5% 1/20W MF 2 201

CRITICAL THRM

2

1

RESET* 5

9

34 68 37 36 34

VREF-3.3V-VDET-3.0V DFN 6 MR1* (IPU) SN0903049 7 MR2* (IPU)

D 3

DFN1006H4-3

100K

VIN

U5110

10% 6.3V CERM-X5R 2 402

Q5150 DMN32D2LFB4

m

0.47UF

36

R5100

o

C5120 1

CRITICAL IN

1

3

1

Desktops: 5V Mobiles: 3.42V

61 65 68 6 8 11 15 16 17 37 53 57 60

G 2

1 S

PLACE_NEAR=Q5159.6:5MM

51 45 39 38 37 36 34 33 30 68 65 61 52

D

SMC12 PECI Support

SOT-563

47PF

20% 2 6.3V X5R 402 42 41 40 38 37 36

Q5159

C5131 1

4.7UF

SMC_PM_G2_EN SMC_ADAPTER_EN SMC_THRMTRIP

72 36 25 24 17

SMC_DELAYED_PWRGD

61 36

SMC_S4_WAKESRC_EN

R5198 100K R5185 10K R5186 10K R5191 100K R5190 100K

1 1 1

2 2 2

1

2

1

2

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

SMC Shared Support DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

51 OF 120 SHEET

37 OF 78

1

A

7

6

5

C

40 38 36

OUT

SMC_BMON_ISENSE

SMC_CPU_HI_ISENSE MAKE_BASE=TRUE

SMC_PBUS_VSENSE MAKE_BASE=TRUE

SMC_BMON_ISENSE MAKE_BASE=TRUE

OUT

SMC_DCIN_ISENSE

40 38 36

OUT

SMC_DCIN_VSENSE

42 38 36

OUT

SMC_BMON_DISCRETE_ISENSE SMC_BMON_DISCRETE_ISENSE

41 38 36

OUT

SMC_CPU_ISENSE

SMC_DCIN_ISENSE MAKE_BASE=TRUE

SMC_DCIN_VSENSE MAKE_BASE=TRUE MAKE_BASE=TRUE

SMC_CPU_ISENSE MAKE_BASE=TRUE

40 38 36

OUT

SMC_OTHER5V_HI_ISENSE

40 38 36

OUT

SMC_OTHER3V3_HI_ISENSE SMC_OTHER3V3_HI_ISENSE MAKE_BASE=TRUE

OUT

SMC_DDR_ISENSE

OUT

SMC_LCDBKLT_ISENSE

38 36

OUT

SMC_ADC11_PD

38 36

OUT

SMC_ADC12_PD

41 38 36

OUT

SMC_SSD_ISENSE

41 38 36

OUT

SMC_PP3V3S0_ISENSE

42 38 36

OUT

SMC_CAMERA_ISENSE

38 36

OUT

SMC_ADC16_PD

41 38 36

OUT

SMC_PP5VS0_ISENSE

SMC_DDR_ISENSE MAKE_BASE=TRUE

SMC_LCDBKLT_ISENSE MAKE_BASE=TRUE

SMC_ADC11_PD

SMC_SSD_ISENSE MAKE_BASE=TRUE

SMC_PP3V3S0_ISENSE MAKE_BASE=TRUE

SMC_CAMERA_ISENSE MAKE_BASE=TRUE

SMC_ADC16_PD SMC_PP5VS0_ISENSE

SMC_PCH_ISENSE

42 38 36

SMC_CPUDDR_ISENSE SMC_PCH_ISENSE MAKE_BASE=TRUE

OUT

SMC_CPU_VSENSE

OUT

SMC_LCDPANEL_ISENSE

42 38 36

OUT

SMC_CPU_IMON_ISENSE

OUT

SMC_TBT_ISENSE

36 38 40

IN

36 38 42

IN

36 38 41

IN

36 38 40

IN

36 38 40

IN

36 38 41

IN

36 38 40

PCH_SML1ALERT_L

100

1

2

SMC_CPU_VSENSE MAKE_BASE=TRUE

SMC_LCDPANEL_ISENSE MAKE_BASE=TRUE

SMC_CPU_IMON_ISENSE MAKE_BASE=TRUE

SMC_TBT_ISENSE

OMIT_TABLE CPUHYS

IN

17 30 33 34 36 37 38 39 45 51 52 61 65 68

SMC_CPUHI_COMP_ALERT_L

1

100

D

HALL-EFFECT-SENSOR-MLB-D1 SM

R5217 41

PP3V42_G3H

J5250 1 2 3 4

NC

2

5% 1/20W MF 201

NC

8 7 6 5

NC

R5250 SMC_LID_R

1

0

2

5% 1/16W MF-LF 402

NC

36 38 41

IN

36 38 41

IN

36 38 42

IN

SMC_BMON_COMP_ALERT_L

CPUTHMSNS_THM_L

1

36 38 41

36 38 41

IN

36 38 42

IN

36 38 42

IN

36 38 42

100

5% 1/20W MF 201 IN

CPUTHRM_THRM:SMC

IN

TBTTHMSNS_THM_L

1

1

100

5% 1/20W MF 201 43

IN

TBTTHMSNS_ALERT_L

677-0912

100

2

CPUTHRM_ALRT:SMC

5% 1/20W MF 201

2

TBTTHRM_THRM:SMC

1

2

TBTTHRM_ALRT:SMC

5% 1/20W MF 201

36 38 42

0.001UF

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

1

SUBASSY,PCBA HALL EFFECT,J44

J5250

CRITICAL

BOM OPTION

Specify one of these BOM GROUPs.

R5210 100

C5250

639-4502 (J44 HALL EFFECT BOARD) REPORTS TO 677-0912

R5214

R5220 43

PART NUMBER

2

CPUTHMSNS_ALERT_L

34 36 37

2

R5216 IN

36 38 41

IN

100

5% 1/20W MF 201

43

IN

1

SMC_LID 1

10% 50V 2 X7R-CERM 0402

BMONHYS

R5213

IN

IN

MAKE_BASE=TRUE

APN: 998-4692

5% 1/20W MF 201

43

MAKE_BASE=TRUE

42 38 36

36 38 40

IN

IN

MAKE_BASE=TRUE

SMC_CPUDDR_ISENSE

R5215

IN

36 38

MAKE_BASE=TRUE

OUT

IN

Hall Effect Pads

NOSTUFF

36 38

MAKE_BASE=TRUE

OUT

36 38 40

42

SMC_ADC12_PD

41 38 36

36 38 40

IN

36 38

MAKE_BASE=TRUE

41 38 36

42 38 36

SMC_OTHER5V_HI_ISENSE MAKE_BASE=TRUE

40 38 36

36 38 40

IN

14

40 38 36

41 38 36

IN

m

SMC_PBUS_VSENSE

1

o

SMC_CPU_HI_ISENSE

OUT

.c

D

OUT

40 38 36

2

3

Thermal Alerts

SMC12 ADC Assignments 40 38 36

4

TABLE_BOMGROUP_HEAD

BOM GROUP

BOM OPTIONS

CPUTHRM:BOTH

CPUTHRM_THRM:SMC,CPUTHRM_ALRT:SMC TABLE_BOMGROUP_ITEM

CPUTHRM:THRM

SMC12 Pin Assignments

C

TABLE_BOMGROUP_ITEM

x

8

CPUTHRM_THRM:SMC,CPUTHRM_ALRT:PU TABLE_BOMGROUP_ITEM

CPUTHRM:ALRT

CPUTHRM_THRM:PU,CPUTHRM_ALRT:SMC

CPUTHRM:NONE

CPUTHRM_THRM:PU,CPUTHRM_ALRT:PU

TABLE_BOMGROUP_ITEM

NC_SMBUS_SMC_4_ASF_SCL NC_SMBUS_SMC_4_ASF_SCL NC_SMBUS_SMC_4_ASF_SDA NC_SMBUS_SMC_4_ASF_SDA

38 36

NC_BDV_BKL_PWM

NC_SMC_SYS_LED

NC_SMC_GFX_THROTTLE_L

38 36

NC_SMC_GFX_OVERTEMP

38 36

NC_SMC_FAN_1_CTL

38 36

NC_SMC_FAN_1_TACH

38 36

NC_SMC_5VSW_PWR_EN

38 36

NC_SMC_FAN_5_CTL

MAKE_BASE=TRUE MAKE_BASE=TRUE

38 36

38 36

NC_MEM_EVENT_L

36 38

NO_TEST=TRUE 38 36

B

38 36

MAKE_BASE=TRUE 1

NO_TEST=TRUE

10K

5% 1/20W MF 2 201

36 38

NO_TEST=TRUE

SMC_PCH_SUSWARN_L

0

1

MAKE_BASE=TRUE

2

36 38

60 40 38 36

0

1

MAKE_BASE=TRUE

2

PCH_SUSACK_L

13

IN

38 36 34 29

IN

SMC_PME_S4_WAKE_L

38 36 34 29

IN

SMC_PME_S4_WAKE_L

5% 1/20W MF 0201

SMC_SENSOR_PWR_EN SMC_SENSOR_PWR_EN

SMC_SENSOR_PWR_EN

36 38 40 60 36 38 40 60

SMC_WIFI_PWR_EN

SMC_WIFI_PWR_EN

36 38 63

MAKE_BASE=TRUE

38 36 38 36 38 36

36

IN

1

R5282 100K

5% 1/20W MF 2 201

62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 39 40 41 42 43 44 46 47 50 61

1

R5285 100K

5% 1/20W MF 2 201

SMC_WIFI_PWR_EN SMC_SENSOR_PWR_EN

NOSTUFF

R5286

SMC_RESET_L

100K

5% 1/20W MF 2 201

R5294

10K

1

2 5%

1/20W

MF

201

5%

1/20W

MF

201

NOSTUFF 10K

1

2

A

36 37 45 52 68

PAGE TITLE

SMC Project Support

NOSTUFF

C5270 1

NOSTUFF

DRAWING NUMBER

1000PF

10% 16V X7R-CERM 2 0201

GND_SMC_AVSS

Apple Inc. GND_SMC_AVSS

PCH_STRP_TOPBLK_SWP_L

R

OUT

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

15

7

6

5

4

3

2

SIZE

D REVISION



36 37 38 40 41 42

NOTICE OF PROPRIETARY PROPERTY:

5% 1/20W MF 201

8

R5295

1

R5283 2

PP3V3_S4

29 34 36 38

SMC_ADC16_PD SMC_ADC12_PD SMC_ADC11_PD

NOSTUFF

1K

65 64 63 60 42 38 37 34 29 18 68

OUT

NOSTUFF

5% 1/20W MF 2 201 42 41 40 38 37 36

1

B 18 29 34 37 38 42 60 63 64 65 68

60 40 38 36

R5284

1K

SMC_TOPBLK_SWP_L

PP3V3_S4

MAKE_BASE=TRUE

1

R52961 5% 1/20W MF 201 2

Requires EMC1412-1 or EMC1412-2 instead of EMC1412-A, new APN needs to be created.

SMC_PME_S4_WAKE_L

100K

PP3V3_S0

TABLE_BOMGROUP_ITEM

63 38 36

Top Block Swap

A

TBTTHRM_THRM:PU,TBTTHRM_ALRT:PU

w

MAKE_BASE=TRUE

63 38 36

TBTTHRM:NONE TBTTHRM:GONE

w

5% 1/20W MF 0201

SMC_PCH_SUSACK_L

TBTTHRM_THRM:PU,TBTTHRM_ALRT:SMC TABLE_BOMGROUP_ITEM

w

OUT

TBTTHRM:ALRT

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

S4 SMC Wake Sources

13

OUT

R5231 36

TBTTHRM_THRM:SMC,TBTTHRM_ALRT:PU

36 38

NO_TEST=TRUE

PCH_SUSWARN_L

TBTTHRM:THRM

SMCBOARDID:8

36 38

NO_TEST=TRUE

NC_SMC_T101_COM_1 NC_SMC_T101_COM_1 MAKE_BASE=TRUE NO_TEST=TRUE NC_SMC_ACTUATOR_DISABLE_LNC_SMC_ACTUATOR_DISABLE_L

IN

BOM OPTIONS TBTTHRM_THRM:SMC,TBTTHRM_ALRT:SMC

R5233

36 38

R5230 36

BOM GROUP TBTTHRM:BOTH

TABLE_BOMGROUP_ITEM

SMCBOARDID:16

SMC_BOARDID

NO_TEST=TRUE

38 36

MAKE_BASE=TRUE

SMC_BOARDID

36 38

NC_MEM_EVENT_L MAKE_BASE=TRUE

5% 1/20W MF 2 201

NO_TEST=TRUE

NC_SMC_BIL_BUTTON_L MAKE_BASE=TRUE

10K

36 38

NC_SMC_FAN_5_CTL MAKE_BASE=TRUE

R5232

NO_TEST=TRUE

NC_SMC_5VSW_PWR_EN

NC_SMC_BIL_BUTTON_L

38 36

1 36 38

NC_SMC_FAN_1_TACH

36 37

TABLE_BOMGROUP_HEAD

NO_TEST=TRUE

NC_SMC_FAN_1_CTL MAKE_BASE=TRUE

PP3V42_G3H

36 38

NC_SMC_GFX_OVERTEMP MAKE_BASE=TRUE

51 45 39 38 37 36 34 33 30 17 68 65 61 52

NO_TEST=TRUE

NC_SMC_GFX_THROTTLE_L MAKE_BASE=TRUE

OUT

Specify one of these BOM GROUPs.

36 38

a

NC_SMC_SYS_LED

MAKE_BASE=TRUE 38 36

SMC_SENSOR_ALERT_L 36 38

NO_TEST=TRUE

in

MAKE_BASE=TRUE 38 36

36 38

NO_TEST=TRUE

NC_BDV_BKL_PWM

fi

38 36

MAKE_BASE=TRUE

36 38

NO_TEST=TRUE

h

MAKE_BASE=TRUE

.c

38 36

BRANCH

PAGE

52 OF 120 SHEET

38 OF 78

1

8

7

6

5

LYNX POINT LP S0 "SMBus 0" Connections 77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

R53001 1K

5% 1/20W MF 201 2

U0500 (MASTER)

D

39 19 16 14 72 68 63 39 19 16 14 72 68 63

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

1

R5301 HDMI Redriver (on RIO) 1K

5% 1/20W MF 2 201

SMBUS_PCH_CLK MAKE_BASE=TRUE

SMBUS_PCH_DATA

SMBUS_PCH_DATA

MAKE_BASE=TRUE

2.0K

5% 1/20W MF 201 2

U5000

(WRITE: 0xCC READ: 0xCD) SMBUS_PCH_CLK

52 51 45 38 37 36 34 33 30 17 68 65 61

R53501

(MASTER)

14 16 19 39 63 68 72

68 62 39 36 76

14 16 19 39 63 68 72

68 62 39 36 76

1

Internal DP

R5351 2.0K

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

R53801

52 51 39 36 76 68

36 39 62 68 76

52 51 39 36 76 68

R5381 2.0K

5% 1/20W MF 201 2

(MASTER) 36 39 62 68 76

1

2.0K

U5000

(See Table)

SMBUS_SMC_0_S0_SCL

PP3V42_G3H

SMC

J8300

5% 1/20W MF 2 201

1

SMC SMBus "5" G3H Connections

PP3V3_S0

SMC

J9510

2

3

SMC SMBus "0" S0 Connections

PP3V3_S0

LYNX POINT LP

4

5% 1/20W MF 2 201

SMBUS_SMC_5_G3_SCL

Battery Charger

ISL6259 - U7100 (Write: 0x12 Read: 0x13) SMBUS_SMC_5_G3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SDA MAKE_BASE=TRUE

U2200 SMBUS_PCH_DATA

Margin Control

o

U2201 SMBUS_PCH_CLK

72 19 16 14 68 63 39

SMBUS_PCH_DATA

J44 Samsung

Internal DP Parade T-con

- (0x10-0x2F or 0x30-0x4F)

Y

LGD Y

XDP Connectors

J1800 (MASTER)

39 19 16 14 72 68 63

SMBUS_SMC_5_G3_SCL

SMBUS_PCH_CLK SMBUS_PCH_DATA

68 65 60 42 19 18 15

PP3V3_S3

R53701 1K

5% 1/20W MF 201 2

U5000

1

R5371 1K

5% 1/20W MF 2 201

R5391 2.0K

5% 1/20W MF 201 2

U5000

5% 1/20W MF 2 201

SMBUS_SMC_3_SCL

C

MAKE_BASE=TRUE

SMBUS_SMC_3_SDA MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SDA

Trackpad

(Write: 0x92 Read: 0x93) SMBUS_SMC_3_SCL

(Write: 0x90 Read: 0x91)

SMBUS_SMC_3_SDA

SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA

36 39 43 63 76 36 39 43 63 76

34 36 39 68 76 34 36 39 68 76

TBT & MLB Prox

EMC1412: U5850

in

MAKE_BASE=TRUE

TMP105: J9510 J4800

a

(MASTER) 68 39 36 34 76

1

2.0K

X29 Temp (on RIO)

SMC

68 39 36 34 76

36 39 51 52 68 76

Connections

R53901

(MASTER) 63 43 39 36 76

36 39 51 52 68 76

PP3V3_S0

SMC

x

39 19 16 14 72 68 63

SMC SMBus "3" S0 77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

SMC SMBus "2" S3 Connections

fi

C

.c

(Write: 0x30 Read: 0x31) 72 19 16 14 68 63 39

(See Table) SMBUS_SMC_5_G3_SDA

m

SMBUS_PCH_CLK

J7050

Battery Battery Manager - (Write: 0x16 Read: 0x17)

(Write: 0x98 Read: 0x99) 72 19 16 14 68 63 39

D

36 39 51 52 68 76

Battery

VRef DACs

72 19 16 14 68 63 39

36 39 51 52 68 76

(Write: 0xD8 Read: 0xD9) SMBUS_SMC_3_SCL

36 39 43 63 76 36 39 43 63 76

h

SMBUS_SMC_3_SDA

PP3V3_S0

LYNX POINT LP

U0500 (MASTER) 72 14

SML_PCH_0_CLK

72 14

SML_PCH_0_DATA

SMC SMBus "1" S0 Connections

R53101 8.2K

5% 1/20W MF 201 2

1

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

R5311 8.2K

PP3V3_S0

w

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

B

.c

LYNX POINT LP S0 "SMLink 0" Connections

5% 1/20W MF 2 201

R53601

SMC

2.0K

5% 1/20W MF 201 2

U5000

MAKE_BASE=TRUE

w

B

MAKE_BASE=TRUE

39 36 32 14 76 72 68 43

R5361 2.0K

5% 1/20W MF 2 201

EMC1704-02: U5870 (Write: 0x98 Read: 0x99)

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SCL

72 76 14 32 36 39 43 68

SMBUS_SMC_1_S0_SDA

72 76 14 32 36 39 43 68

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA MAKE_BASE=TRUE

w

39 36 32 14 76 72 68 43

(MASTER)

CPU, Mem, Airflow, Fixstack Prox

1

LYNX POINT LP S0 "SMLink 1" Connections

ALS

J4002 (Write: 0x72 Read 0x73)

LYNX POINT LP

A

U0500

SMBUS_SMC_1_S0_SCL

72 76 14 32 36 39 43 68

SMBUS_SMC_1_S0_SDA

72 76 14 32 36 39 43 68

(Write: 0x88 Read: 0x89) 39 36 32 14 76 72 68 43 39 36 32 14 76 72 68 43

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA

SMBus Connections DRAWING NUMBER

Apple Inc. R

SMLink 1 is slave port to access PCH.

8

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

53 OF 120 SHEET

39 OF 78

1

A

8

7

6

5

4

2

3

CPU High Side Current Sense (IC0R)

PBUS Voltage Sense & Enable (VP0R)

Gain: 100x, EDP: 9.5 A Rsense: 0.003 (R5400) Vsense: 28.5 mV, Range: 11 A SMC ADC: 00

Gain: 0.167x Vnominal: 12.6 V, Range: 19.7 V SMC ADC: 01

65 64 62 61 50 47 46 44 24 18 17 15 13 12 11 8 43 42 41 39 38 37 30 28 77 68

PP3V3_S0

OUT

1 3

20% 10V 2 CERM 402

PPBUS_S5_HS_COMPUTING

R5400 1

D

PLACE_NEAR=U5400.5:10MM

U5400

3

INA214

77 42

ISNS_HS_COMPUTING_N

5 IN-

SC70

0.003

1% 77 1W 42 ISNS_HS_COMPUTING_P TFT 0612 2 4

CRITICAL 58 52 51 40 25 68 65

OUT

4.53K2 1 1% 1/20W MF 201

1

REF 1

R5405 15K

PLACE_NEAR=U5400.4:10MM CRITICAL

60 38 36

SMC_CPU_HI_ISENSE 1

OUT

IN

36 38

6

SMC_SENSOR_PWR_EN

R54821 100K

G

2

1% 1/16W MF-LF 402 2

S

C5409

3

0.22UF

68 65 58 52 51 40 25

PPBUS_G3H

1

PLACE_NEAR=U5400.6:5MM

2

PBUS_S0_VSENSE_IN

R54881 27.4K

G

5

1% 1/16W MF-LF 402 2

S

PLACE_NEAR=R5400.1:10 MM

GND_SMC_AVSS

D PLACE_NEAR=U5000.E1:5MM

PBUS_S0_VSENSE

D

XW5480 SM

PLACE_NEAR=U5000.E2:5MM

NOSTUFF

PBUSVSENS_EN_L

D

1

20% 6.3V 2 X5R 0201

5% 1/20W MF 2 201

GND

PPBUS_G3H

R5409

100x 4 IN+

SOT-963 N-CHANNEL

PLACE_NEAR=U5000.E2:5MM

CPUHI_IOUT

6

Q5480 NTUD3169CZ

Enables PBUS VSense divider when in S0.

BYPASS=U5400.3:5MM

2

65 57 55 54 53

CRITICAL

(to CPU High Side Threshold Alert circuit)

C5401 0.1UF

V+

41

1

4

36 37 38 40 41 42

Rthevenin = 4573 Ohms

P-CHANNEL

1

PLACE_NEAR=U5410.5:10MM

R5410 1 OMIT Short Rsense

0.003

1% 1w CYN 0612-SHORT

U5410 5 IN-

PLACE_NEAR=U5000.A4:5MM

OUT

4.53K2

HS_OTHER5V_IOUT

6

1

100x 77

ISNS_HS_OTHER5V_P

4 IN+

1

REF 1

R5415

2 4

15K

OTHERISNS

C

1

Gain: 0.148x Vnominal: 16.5 V, Range: 22.29 V SMC ADC: 04

36 38

0.22UF OTHERRC:YES

PLACE_NEAR=U5410.6:5MM

GND_SMC_AVSS

36 37 38 40 41 42

OTHER 3.3V High Side Current Sense (IO3R) BYPASS=U5440.3:5MM

OMIT Short Rsense

0.1UF

OUT

4.53K2

HS_OTHER3V3_IOUT

6

1

200x ISNS_HS_OTHER3V3_P

4 IN+

1% 1/20W MF 201

1

REF 1

R5445

2 4

15K

OTHERISNS

SMC_OTHER3V3_HI_ISENSE

1

OUT

C5449 0.22UF

OTHERRC:YES PLACE_NEAR=U5000.B5:5MM

OTHERISNS

CRITICAL

PLACE_NEAR=U5440.6:5MM

GND_SMC_AVSS

1

U5450 5 IN-

OUT

6

ISNS_LCDBKLT_IOUT

4 IN+

PLACE_NEAR=U7700.1:10MM

LOADISNS CRITICAL

REF 1

1

R5455 6.04K

GND

DCIN_S5_VSENSE

PPDCIN_G3H_ISOL

5

R54981 31.6K

G

1% 1/16W MF-LF 402 2

S

4

Rthevenin = 4573 Ohms

SMC_DCIN_VSENSE

OUT

36 38

PLACE_NEAR=U5000.B3:5MM

1

100K

R5499

1% 1/16W MF-LF 402 2

1

5.49K

C5499 0.22UF

1% 1/16W MF-LF 402 2

20% 2 6.3V X5R 0201

PDCINVSENS_EN_L_DIV

GND_SMC_AVSS

36 37 38 40 41 42

PLACE_NEAR=U5000.B3:5MM

Charger (BMON) Current Sense (IPBR)

DC-IN (AMON) Current Sense (ID0R)

Charger Gain: 36x, EDP: 8 A Rsense: 0.005 (R7150) SMC ADC: 02

Charger Gain: 20x, EDP: 4.6 A Rsense: 0.020 (R7120) SMC ADC: 03

B PLACE_NEAR=U5000.F2:5MM

SMC_LCDBKLT_ISENSE

1

OUT

LOADISNS

IN

CHGR_BMON

1

300K 2 1% 1/20W MF 201

36 38

R5439 SMC_BMON_ISENSE 1

OUT

36 38

52

IN

45.3K2

CHGR_AMON

SMC_DCIN_ISENSE

1

1% 1/20W MF 201

C5429

1

3300PF

C5459 0.22UF

36 38

C5439

10% 2 10V X7R-CERM 0201

PLACE_NEAR=U5000.F2:5MM

GND_SMC_AVSS

LOADRC:YES

OUT

2200PF

10% 10V 2 X7R-CERM 0201

PLACE_NEAR=U5000.F1:5MM

GND_SMC_AVSS

36 37 38 40 41 42

36 37 38 40 41 42

PLACE_NEAR=U5000.B6:5MM

GND_SMC_AVSS

36 37 38 40 41 42

w

PLACE_NEAR=U5450.6:5MM

PLACE_NEAR=U5000.F1:5MM

R5429 52

20% 2 6.3V X5R 0201

1% 1/20W MF 2 201

w

ISNS_LCDBKLT_P

2

IN

4.53K2 1 1% 1/20W MF 201

100x 77 58

3

PLACE_NEAR=U5000.B3:5MM

R54911

PLACE_NEAR=U5000.B6:5MM

R5459

INA214 SC70

LOADRC:YES

20% 10V 2 CERM 402

w

ISNS_LCDBKLT_N

C5450 0.1UF

V+

IN

36 37 38 40 41 42

.c

BYPASS=U5450.3:5MM

PP3V3_S4SW_SNS

PLACE_NEAR=U7700.2:10MM 77 58

C

1% 1/16W MF-LF 402 2

1

LOADISNS 65 60 42 41 40

3

B

36 38

h

LCD Backlight Current Sense (IBLC) Gain: 100x. EDP: 0.9 A Rsense: 0.025 (R7700) Vsense: 22.5 mV, Range: 1.32 A SMC AD: 10

100K

P-CHANNEL

20% 2 6.3V X5R 0201

1% 1/20W MF 2 201

GND

PLACE_NEAR=U5440.4:10MM

PPBUS_G3H

R54921

G

PLACE_NEAR=U5000.B5:5MM

R5449

INA210 SC70

OTHERRC:YES

20% 10V 2 CERM 402

U5440 5 IN-

65 52 51

C5441

2

58 52 51 40 25 68 65

3 77 ISNS_HS_OTHER3V3_N

77

DCINVSENS_EN_L

S

a

1

0.003

1% 1w CYN 0612-SHORT

2

fi

OTHERISNS

PP3V3_S4SW_SNS

PLACE_NEAR=U5440.5:10MM

R5440 1

6

D

in

42 41 40

3

PPBUS_S5_HS_OTHER3V3

Q5490

D

V+ 65 56

PM_SLP_SUS_L

IN

36 37 38 40 41 42

NTUD3169CZ SOT-963 N-CHANNEL

x

61 13

Gain: 200x, EDP: 5 A Rsense: 0.003 (R5440) or Rsense SHORT 65 60 Vsense: 12 mV, Range: 5.5 A SMC ADC: 08

GND_SMC_AVSS PLACE_NEAR=U5000.E1:5MM

CRITICAL

Enables DC-In VSense divider when AC present.

PLACE_NEAR=U5000.A4:5MM

OTHERISNS

CRITICAL

OUT

C5419

20% 2 6.3V X5R 0201

1% 1/20W MF 2 201

GND

PLACE_NEAR=U5410.4:10MM

PPBUS_G3H

1% 1/20W MF 201

SMC_OTHER5V_HI_ISENSE

C5489

20% 2 6.3V X5R 0201

PBUSVSENS_EN_L_DIV

DC In Voltage Sense & Enable (VD0R)

R5419

INA214 SC70

OTHERRC:YES

36 38

0.22UF

1% 1/16W MF-LF 402 2

0.1UF

2

58 52 51 40 25 68 65

3 77 ISNS_HS_OTHER5V_N

C5411

20% 10V 2 CERM 402

1

5.49K

o

PPBUS_S5_HS_OTHER5V

m

BYPASS=U5410.3:5MM

V+ 65 56

1% 1/16W MF-LF 402 2

OTHERISNS

PP3V3_S4SW_SNS

OUT

PLACE_NEAR=U5000.E1:5MM

R54891

100K

.c

42 41 40

3

Gain: 100x, EDP: 7 A Rsense: 0.003 (R5410) or Rsense SHORT 65 60 Vsense: 21 mV, Range: 11 A SMC ADC: 07

SMC_PBUS_VSENSE

R54811

OTHER 5V High Side Current Sense (IO5R)

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

117S0008

1

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

C5419,C5449

OTHERRC:NO

117S0008

1

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

C5459

LOADRC:NO

A

CRITICAL

SYNC_MASTER=J44

BOM OPTION

SYNC_DATE=08/12/2013

PAGE TITLE

Power Sensors: High Side DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

54 OF 120 SHEET

40 OF 78

1

A

7

6

5

4

PCH 1.05V Current Sense (IC1C)

IN

PLACE_NEAR=R7640.4:5MM

4 IN+

500x

6

4.53K2

P1V05S0_IOUT

1

1% 1/20W MF 201

1

REF 1

R5565 20K

2

CRITICAL

LOADISNS

SMC_PCH_ISENSE 1

OUT

C5569

77 54

0.22UF

IN

LOADRC:YES

PLACE_NEAR=U5560.6:5MM

77 54

GND_SMC_AVSS

IN

4.42K2

0.1UF

IN

NC_ISNS_DDR_S3P

4 IN+

SC70

OUT

6

PLACE_NEAR=U5000.A5:5MM

4.53K2

ISNS_DDR_IOUT

1

100x

1% 1/20W MF 201

1

REF 1

R5575 20K

PLACE_NEAR=XW7450.1:10MM

Gain: 100x, EDP: 5 A (16.5 W) Rsense: 0.005 (R5580) Vsense: 25 mV, Range: 6.6 A SMC ADC: 13

2

DDRISNS

1

OUT

36 38

C5579 0.22UF

65 30

107S0241 CRITICAL

GND_SMC_AVSS

36 37 38 40 41 42 65 60

1

U5510

3 77

INA210

0

0 1 W MF 0612-SHORT

5 IN-

20% 2 10V CERM 402

77

ISNS_CPUDDR_P

SC70

PLACE_NEAR=U5000.H1:5MM

OUT

6

4.53K2 1

ISNS_CPUDDR_IOUT

4 IN+

1% 1/20W MF 201

1

REF 1

R5515

2 4

20K

LOADISNS

SMC_CPUDDR_ISENSE 1

C5519

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

PLACE_NEAR=U5000.H1:5MM

LOADRC:YES

PLACE_NEAR=U5510.6:5MM

GND_SMC_AVSS

h

Gain: 500x, EDP: 1.0 A Rsense: 0.005 (R5520) or Rsense SHORT PP3V3_S4SW_SNS 42 41 40 Vsense: 21.5 mV, Range: 1.32 A 65 60 SMC ADC: 14

LOADISNS

BYPASS=U5520.3:5MM

1

PLACE_NEAR=U5520.5:10MM

R5520

1 3 77

ISNS_PP3V3S0_N

0

0 1 W MF 77 0612-SHORT 2 4

U5520 5 IN-

OUT

4 IN+

6

4.53K2 1

ISNS_PP3V3S0_IOUT

1% 1/20W MF 201

1

REF 1

R5525 20K

PLACE_NEAR=U5520.4:10MM CRITICAL

3 77

U5580

ISNS_SSD_N

1% 1W MF 77 0612-2 2 4

SC70

PLACE_NEAR=U5000.C2:5MM

R5589

INA214

5 IN-

OUT

4.53K2

ISNS_S0_SSD_IOUT

6

ISNS_SSD_P

4 IN+

1% 1/20W MF 201

1

REF 1

R5585 20K

PLACE_NEAR=U5580.4:10MM

1

OUT

36 38

C5589

C

0.22UF

20% 6.3V 2 X5R 0201

5% 1/20W MF 2 201

GND

CRITICAL

SMC_SSD_ISENSE

1

100x

PLACE_NEAR=U5000.C2:5MM

GND_SMC_AVSS

LOADISNS

36 37 38 40 41 42

NOSTUFF

C5553 0.22UF

PP3V3_S0

1

SMC_PP3V3S0_ISENSE

1

OUT

NOSTUFF

20% 6.3V X5R 0201

0.1UF

10% 2 6.3V CERM-X5R 0201 BYPASS=U5551:3MM

CPUHYS

R5553 CPUHI_COMP_FB CPUHYS

CPUHYS

1

R5554

Trip Target on CPU High current: 2.5 A Hysteresis Circuit: Vref = 0.737 V Vth = 0.616 V -> 2.054 A on CPU High current Vtl = 0.771 V -> 2.571 A on CPU High current Hysteresis Margin = 0.518 A

R5556

294K

1% 1/20W MF 2 201

1

12K

5

3

2

MCP6541T

1

255K 2 1% 1/16W MF-LF 402

CPUHYS

CPUHI_COMP_OUT

B

4 2

1

R5555 84.5K

1% 1/20W MF 2 201

CPUHI_IOUT_R 1

C5552 0.1UF

NOSTUFF 1

R5557 0

5% 1/20W MF 2 0201

PLACE_NEAR=U5000.B1:5MM

OMIT 42

CPUHYS

NOSTUFF

36 38

C5529

GND_SMC_AVSS

U5551 SC70-5 1

1% 1/20W MF 201

CPUHI_COMP_VREF CPUHYS

0.22UF

PLACE_NEAR=U5520.6:5MM

2

CPUHYS

C5551

1

20% 6.3V 2 X5R 0201

5% 1/20W MF 2 201

GND

PP3V3_S0_FET

0.1uF

20% 2 10V CERM 402

V+

PLACE_NEAR=U5000.B1:5MM

500x ISNS_PP3V3S0_P

BYPASS=U5580.3:5MM

C5580

1

R5529

INA211 SC70

LOADRC:YES

w

PP3V3_S0 OMIT Short Rsense

65 60

20% 2 10V CERM 402

V+

w

65 46 39 18 8 13 30 42 61

C5520 0.1UF

3 68 47 40 24 11 15 37 43 62

2

77 50 41 28 12 17 38 44 64

NO_XNET_CONNECTION=TRUE

36 37 38 40 41 42

.c

3.3V S0 Rail Current Sense (IR3C)

B

NO_XNET_CONNECTION=TRUE

Gain: 100x Rsense: 0.003 (R5400)

36 38

0.22UF

NOSTUFF

CRITICAL

OUT

20% 6.3V 2 X5R 0201

5% 1/20W MF 2 201

GND

PP1V35_S3

36 37 38 40 41 42

LOADISNS

CPU High Side Current (IC0R) Threshold Alert

R5519

2

73 65 20 19 17 55 22 21

PLACE_NEAR=U5000.B4:5MM

GND_SMC_AVSS

LOADRC:YES

200x PLACE_NEAR=U5510.4:10MM

LOADRC:YES

a

OMIT Short Rsense

C5510 0.1UF

PLACE_NEAR=U5510.5:10MM

ISNS_CPUDDR_N

0.22UF

PLACE_NEAR=U5540.4:5MM

fi

LOADISNS

in

R5510 1

C5549

NOSTUFF

BYPASS=U5510.3:5MM

3

PP1V35_S3_CPUDDR

36 38

PLACE_NEAR=U5580.6:5MM

V+ 65 10 8 73

LOADISNS

OUT

20% 6.3V 2 X5R 0201

NOSTUFF

715K 2 0.1% 1/16W MF 402

NO_XNET_CONNECTION=TRUE

PP3V3_S0SW_SSD_FET

CPU DDR 1.35V S3 (CPU Only) Current Sense (IM1C) Gain: 200x, EDP: 2.5 A Rsense: 0.005 (R5510) or Rsense SHORT 65 PP3V3_S4SW_SNS 41 40 Vsense: 12.5 mV, Range: 6.6 A 60 42 SMC ADC: 18

1

PP3V3_S4SW_SNS

0.005

DDRRC:YES

PLACE_NEAR=U5570.6:5MM

0.1% 1/16W MF 402 2

SMC_CPU_ISENSE 1

5% 1/20W MF 2 201

R5541

715K

PLACE_NEAR=U5580.5:10MM

R5580 1

PLACE_NEAR=U5000.A5:5MM

NOSTUFF

65 60 42 41 40

PP3V3_S0SW_SSD

20% 6.3V 2 X5R 0201

5% 1/20W MF 2 201

GND

CRITICAL

SMC_DDR_ISENSE

R5544

PLACE_NEAR=U5000.B4:5MM

SSD Current Sense (ISDC)

DDRRC:YES

R5579

INA214

20K

1

.c

IN

77 55

5 IN-

R5540

1

LOADISNS

x

3 77 55

NC_ISNS_DDR_S3N

LOADISNS

1

1% 1/20W MF 201

0.1% 1/16W MF 0402

1% 1/20W MF 201

V-

D

LOADRC:YES

R5549

SC70-5 4.53K2 4 CPUVR_ISUM_IOUT 1

1.05K2 77 CPUVR_ISNS_R_N

CPUVR_ISNS_N

4.42K2 1

ISL28133

V+ 3

20% 10V 2 CERM 402

U5540

1

R5543 77

R5548

CPUVR_ISNS2_N

CPUVR_ISNS_R_P

77

1% 1/20W MF 201

C5570

20% 2 10V CERM 402

U5570

PLACE_NEAR=XW7450.2:10MM

IN

1.05K2

0.1% 1/16W MF 0402

PLACE_NEAR=R7320.4:5MM NO_XNET_CONNECTION=TRUE

BYPASS=U5570.3:5MM

1

V+

C

77 54

DDRISNS PP3V3_S4SW_SNS

1

1

PLACE_NEAR=R7310.3:5MM NO_XNET_CONNECTION=TRUE

36 37 38 40 41 42

DDR 1.35V S3 (CPU & Memory) Current Sense (IM0C) 40 60

1

R5547

CPUVR_ISNS1_N LOADISNS

Gain: 100x, EDP: 9 A Rsense: 0.002 (R7450) or XW7450 Vsense: 21 mV, Range: 16.5 A 42 41 65 SMC ADC: 09

R5542

0.1% 1/16W MF 0402

LOADISNS

PLACE_NEAR=U5000.H2:5MM

NOSTUFF

LOADISNS

C5540 0.1UF

CRITICAL

R5546

PLACE_NEAR=R7320.3:5MM NO_XNET_CONNECTION=TRUE

BYPASS=U5540.5:3MM

LOADISNS

4.42K2 77 CPUVR_ISNS_P

CPUVR_ISNS2_P

LOADISNS 1

0.1% 1/16W MF 0402

LOADISNS

36 38

20% 2 6.3V X5R 0201

5% 1/20W MF 2 201

GND

1

PLACE_NEAR=R7310.4:5MM NO_XNET_CONNECTION=TRUE

PP3V3_S0

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

4.42K2

CPUVR_ISNS1_P

5

OUT

IN

3

ISNS_1V05_S0_P

77 54

R5569

INA211 SC70

R5545

PLACE_NEAR=U5000.H2:5MM

2

5 IN-

PLACE_NEAR=R7640.3:5MM

LOADRC:YES

m

0.1uF

3 77 57

ISNS_1V05_S0_N

C5560

20% 2 10V CERM 402

2

BYPASS=U5560.3:5MM

1

U5560 IN

Gain: 219.33x, EDP: 40 A Rsense: 2x of 0.00075 (R7310, R7320), Rsum: 0.000375 Vsense: 15 mV, Range: 40.12 A SMC ADC: 06

LOADISNS

V+

77 57

1

CPU Fixed Current Sense (IC0C)

Gain: 500x, EDP: 5 A Rsense: 0.001 (R7640) or Rsense SHORT Vsense: 5 mV, Range: 6.6 A 65 60 42 41 40 PP3V3_S4SW_SNS SMC ADC: 19

D

2

3

o

8

CPUHYS 1

R5552

SMC_CPUHI_COMP_ALERT_L

U5552

OUT

38

D 3

DMN32D2LFB4 DFN1006H4-3

10% 2 25V X5R 402

SYM_VER_2

0

5% 1/20W MF 2 0201

1 G

S 2

BMON_IOUT_D

36 37 38 40 41 42

5V S0 Rail Current Sense (IR5C) Gain: 500x, EDP: 1.0 A Rsense: 0.005 (R5530) or Rsense SHORT PP3V3_S4SW_SNS Vsense: 23.5 mV, Range: 1.32 A 60 42 41 40 65 SMC ADC: 17

LOADISNS

1

R5530 1 OMIT Short Rsense

3 77

ISNS_PP5VS0_N

0

0 1 W MF 77 0612-SHORT 2 4

5 IN-

ISNS_PP5VS0_P

65 60

SC70

OUT

6

CRITICAL

LOADISNS

REF 1

ISNS_PP5VS0_IOUT

4.53K2

1

1% 1/20W MF 201

1

R5535 51K

GND

40

SMC_PP5VS0_ISENSE 1

SYNC_MASTER=J44 OUT

C5539

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

BOM OPTION

117S0008

2

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

C5569,C5519

LOADRC:NO

117S0008

3

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

C5529,C5539,C5549

LOADRC:NO

SYNC_DATE=08/12/2013

PAGE TITLE

Power Sensors: Load Side DRAWING NUMBER

0.22UF

117S0008

1

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

Apple Inc.

DDRRC:NO

C5579

LOADRC:YES

R

NOTICE OF PROPRIETARY PROPERTY:

6

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

36 37 38 40 41 42

5

4

3

2

SIZE

D REVISION



PLACE_NEAR=U5000.G1:5MM

LOADISNS

GND_SMC_AVSS

7

36 38

20% 6.3V 2 X5R 0201

5% 1/20W MF 2 201 PLACE_NEAR=U5530.6:5MM

8

CPUHI_IOUT

IN

R5539

INA211

4 IN+

PP5V_S0_FET

K

PLACE_NEAR=U5000.G1:5MM

500x

PLACE_NEAR=U5530.4:10MM

RB521ZS-30

LOADRC:YES

20% 2 10V CERM 402

U5530

A

C5530 0.1UF

3 PLACE_NEAR=U5530.5:10MM

2

A

PP5V_S0

D5557 SM-201

BYPASS=U5530.3:5MM

V+ 60 58 54 32 17 16 53 45 44 68 65 61

w

NOSTUFF

BRANCH

PAGE

55 OF 120 SHEET

41 OF 78

1

A

8

7

6

5

4

2

3

1

CPU High Side (IC0R) Peak Detection Support R5660 77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

PP3V3_S0

47

1

R5666

2

77

1

R5662 1K

C5660

1

1% 1/20W MF 2 201

0.1UF

10% 2 6.3V CERM-X5R 0201 BYPASS=U5660.3:5MM

77

R5661

3

16K

V+ CKPLUS_WAIVE=NdifPr_badTerm 77 42 40

Thunderbolt TBT Current/Voltage Sense (IHSC/VHSC) 0

1

PP3V3_S4SW_SNS

5 IN-

0

INA210 SC70

OUT

TBTISNS

77

ISNS_TBT_P

4 IN+

R5649

1

1

20K

2

PP3V3_S4

4.53K2 SMC_TBT_ISENSE

2

1% 1/20W MF 201

TBTISNS

1

OUT

36 38

C5649

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

0.22UF

NOSTUFF

PLACE_NEAR=U5000.A8:5MM

GND_SMC_AVSS

36 37 38 40 41 42

LCD Panel Current Sense (ILDC) BYPASS=U5620.3:5MM

R5629

INA211 SC70

PLACE_NEAR=U5000.A7:5MM

OUT

6

ISNS_LCDPANEL_IOUT 14.53K2 1% 1/20W MF 201

ISNS_LCDPANEL_P

IN

4 IN+

1

REF 1

R5625 51K

2

LOADISNS

1

OUT

36 38

C5629 0.22UF

20% 2 6.3V X5R 0201

5% 1/20W MF 2 201

GND

SMC_LCDPANEL_ISENSE

LOADISNS

LOADRC:YES

PLACE_NEAR=U5620.6:5MM

PLACE_NEAR=U5000.A7:5MM

1

PP3V3_S3RS0_CAMERA V+

U5610

PP3V3_S3RS0_CAMERA 1

77

XW5610

NC_ISNS_CAMERAN 5 IN-

SC70

OUT

6

77

SM

NC_ISNS_CAMERAP 4 IN+

REF 1

PP3V3_S3RS0_CAMERA_R 65 50 43 39 28 15 8 12 18 37 41 46 62 77

65 60 18 15 39 19 68

R5611 1

PP3V3_S0

GND

0

2

LOADISNS

2

68 61 44 40 30 17 11 13 24 38 42 47 64

R5615 20K

2

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V

1

5% 1/20W MF 2 201

4.53K2 1% 1/20W MF 201

NOSTUFF

PLACE_NEAR=U5610.6:5MM

CAMERA_3V3:S0

SMC_CAMERA_ISENSE

BMON_IOUT_R

BMONHYS 1

R5677

R5672

41

0

1 G

BMON_IOUT_D

D5677 SM-201

A

B

RB521ZS-30 V+

IN

IN

BMONRC:YES

U5670

CKPLUS_WAIVE=NdifPr_badTerm

CHGR_CSO_R_P

5 IN-

CHGR_CSO_R_N

4

R5679

INA213 SC70

OUT

CRITICAL IN+ REF 50x

4.53K2 SMC_BMON_DISCRETE_ISENSE

BMON_IOUT

6

1

1% 1/20W MF 201

1

1

R5671 15K

BMONISNS

PLACE_NEAR=U5000.A3:5MM

5% 1/20W MF 2 201

OUT

36 38

BMONRC:YES 1

C5679 0.22UF

20% 6.3V 2 X5R 0201

PLACE_NEAR=U5000.A3:5MM

NOSTUFF

PLACE_NEAR=U5670.6:5MM

GND_SMC_AVSS OUT

36 38

0.22UF

68 65 54 10 8

20% 2 6.3V X5R 0201

36 37 38 40 41 42

CPU Core Voltage Sense (VC0C) XW5680 SM

C5619 PPVCC_S0_CPU

1

2

R5689 CPUVSENSE_IN

4.53K2

LOADRC:YES

SMC_CPU_VSENSE

1

1% 1/20W MF 201

PLACE_NEAR=R7310.2:5 MM

1

OUT

36 38

C5689 0.22UF

PLACE_NEAR=U5000.B7:5MM

PLACE_NEAR=U5000.B2:5MM

20% 2 6.3V X5R 0201

36 37 38 40 41 42

PLACE_NEAR=U5000.B7:5MM 36 37 38 40 41 42

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

CAMERA_3V3:S3

CPU Core IMON Current Sense (IC2C) Gain: 1 A / 28.273 mV, Range: 40 A. SMC ADC: 22

DESCRIPTION

REFERENCE DES

117S0008

4

RES,MTL FILM,100K,1/16W,0201,SMD,LF

C5619,C5629,C5649

117S0008

1

RES,MTL FILM,100K,1/16W,0201,SMD,LF

C5679

8

S 2

K

53

QTY

SYM_VER_2

NOSTUFF

GND

5% 1/16W MF-LF 402

PART NUMBER

38

DFN1006H4-3

5% 1/20W MF 2 0201

GND_SMC_AVSS 2

OUT

D 3

DMN32D2LFB4

10% 2 25V X5R 402

0

5% 1/20W MF 2 0201

SMC_BMON_COMP_ALERT_L

U5672

C5672 0.1UF

NOSTUFF 1

R5612 1

BMONHYS

NOSTUFF 1

BYPASS=U5670:3MM

SMC ADC: 20 1

GND_SMC_AVSS

5% 1/16W MF-LF 402

PP3V3_S3

4

PLACE_NEAR=U5000.B2:5MM

1

BMONHYS

BMON_COMP_OUT

2

1% 1/20W MF 2 201

LOADRC:YES

ISNS_CAMERA_IOUT

500x

SC70-5 1

69.8K

CKPLUS_WAIVE=NdifPr_badTerm

R5619

INA211

MCP6541T

R5675

10% 6.3V CERM-X5R 2 0201

77 52

w

31 15 42

20% 10V 2 CERM 402

5

BMONHYS

0.1UF

C5610 0.1UF

3

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.175MM VOLTAGE=3.3V MAKE_BASE=TRUE

w

42 31 15

BYPASS=U5630.3:5MM

PP3V3_S4SW_SNS

3

2

1% 1/20W MF 201

BMON_COMP_VREF

1% 1/16W MF-LF 402

U5671

1

C5670 1

w

LOADISNS 65 60 42 41 40

1

10K

255K 2 1

BMONHYS

R5676

0

77 52

PP3V3_S3RS0_CAMERA

BMON_COMP_FB

BMONHYS

R5674

C

R5673

3

Gain: 500x. EDP: 0.82 A Rsense: 0.005 (R5610) or XW5610 Vsense: 4.1 mV, Range: 1.32 A SMC AD: 15

31 15 42

BMONHYS 1

BMONISNS

.c

Camera (S2 Controller) Current Sense (ICMC)

B

0.1UF

Trip Target on Battery current: 3.5 A Hysteresis Circuit: Vref = 0.854 V Vth = 0.758 V -> 3.031 A on Battery current Vtl = 0.887 V -> 3.549 A on Battery current Hysteresis Margin = 0.518 A

36 37 38 40 41 42

2

20% 6.3V X5R 0201

10% 2 6.3V CERM-X5R 0201 BYPASS=U5671:3MM

1% 1/20W MF 2 201

h

GND_SMC_AVSS

C5671

1

CHGR_CSO_R_P/N are swapped on purpose to measure Battery discharge power into system.

LOADRC:YES

20% 10V 2 CERM 402

500x 77 62

1

BMONHYS

in

5 IN-

5% 1/20W MF 0201

0.22UF

PP3V3_S0

a

3

ISNS_LCDPANEL_N

IN

C5620 0.1UF

U5620 77 62

2

NOSTUFF

fi

LOADISNS

V+

0

C5673

200K

1

D

R5669

SENSE+ pins of EMC1704 sink 10-20uA current. This deviation has been designed in our Peak Detection circuit. With 10uA sink: 0.125A - 2.1A -> 13mV - 83 mV With 20uA sink: 0.125A - 2.1A -> 23mV - 92 mV

NOSTUFF

TBTRC:YES

PLACE_NEAR=U5640.6:5MM

Gain: 500x. EDP: 1 A RSENSE: 0.005 (R8320) or Rsense SHORT PP3V3_S4SW_SNS 65 60 42 41 40 Vsense: 5 mV, Range: 1.32 A SMC AD: 21

43 77

NOSTUFF

PLACE_NEAR=U5660.6:10MM

Gain: 50x. EDP: 8 A Rsense: 0.005 (R7150) Vsense: 50 mV, Range: 13.2 A SMC AD: 05

20% 2 6.3V X5R 0201

5% 1/20W MF 2 201

GND

PLACE_NEAR=U5640.4:10MM

0

5% 1/20W MF 0201

R5645

2 4

ISNS_CPUHIGAIN_N

5% 1/20W MF 0201

o

R5647 1

REF 1

TBTRC:YES

PLACE_NEAR=U5000.A8:5MM

TBTISNS

200x

0 1 W MF 0612-SHORT

2

2

Battery BMON Discrete Current Sense (IP0R) & Threshold Alert PLACE_NEAR=XW5640.2:10MM

ISNS_TBT_IOUT

6

20% 6.3V 2 X5R 0201

2

68 65 60 38 29 18 37 34 64 63

ISNS_TBT_N

0.22UF

NOSTUFF

C5640

0

5% 1/20W MF 0201

In battery discharge scenario negative voltage will be present on IN+/- pins with INA output voltage decreasing from 3.3V with increasing discharge current.

C5665

.c

OMIT Short Rsense

3 77

1

PLACE_NEAR=U5660.6:5MM

20% 10V 2 CERM 402

U5640

PLACE_NEAR=U5640.5:10MM

R5640 1

R5664

x

3

PP3V3_S4_TBT

24 23 65 25

1

OUT

R5667

ISNS_HS_COMPUTING_N 1

IN

43 77

2 ISNS_CPUHIGAIN_OUT_R

5% 1/20W MF 0201

1

5% 1/20W MF 2 201

ISNS_TBT_IVOUT

0.1UF

V+

0

ISNS_CPUHIGAIN_OUT 1

GND

PLACE_NEAR=XW5640.2:10MM

BYPASS=U5640.3:5MM

1

6

OUT

15K

CKPLUS_WAIVE=NdifPr_badTerm

NOSTUFF

2

5% 1/20W MF 0201

4

SC70

CRITICAL IN+ 200x REF

m

65 60 42 41 40

R5648

5 IN-

ISNS_HS_COMPUTING_N

IN

R5665

INA210

2

Gain: 200x. EDP: 2.8 A XW5640 Rsense: 0.005 (R5640) or Rsense SHORT SM 1 2 ISNS_TBT_IVIN Vsense: 14 mV, Range: 3.3 A PLACE_NEAR=R5640.1:10 MM SMC AD: 23

ISNS_HS_COMPUTING_P

IN

77 42 40

U5660

77 42 40

0

1

OUT

NOSTUFF

R5668

ISNS_CPUHIGAIN_R_N

1% 1/20W MF 2 201

ISNS_CPUHIGAIN_P

PLACE_NEAR=U5660.6:10MM

1 PLACE_NEAR=R5400:10MM

2

5% 1/20W MF 0201

ISNS_HS_COMPUTING_P 1

IN

PLACE_NEAR=U5660.6:10MM

D

A

77 42 40

0

1

PLACE_NEAR=U5660.6:10MM

5% 1/20W MF 201

C

ISNS_CPUHIGAIN_R_P

7

CRITICAL

1

0

SMC_CPU_IMON_ISENSE OUT

2

MF With R7210 (Ri) set to 316 Ohm, 0201 PLACE_NEAR=U5000.B8:5MM R7310 (Rsen) set to 0.75 mOhm, R7230 set to 95.3 kOhm, Num Phases (N) is 2, and Io (ICCmax) is 40A, then 1A of Io gives 28.273mV at the Vimon.

5

4

DRAWING NUMBER

R5699 5% 1/20W

BOM OPTION

6

CPUVR_IMON

Power Sensors: Extended

1

C5699

2

0.22UF 20% 6.3V NOSTUFF X5R 0201

36 37 38 40 41 42

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

2

SIZE

D REVISION

R

NOTICE OF PROPRIETARY PROPERTY:

PLACE_NEAR=U5000.B8:5MM

GND_SMC_AVSS

3

Apple Inc. 36 38

BRANCH

PAGE

56 OF 120 SHEET

42 OF 78

1

A

8

7

6

5

4

2

3

1

Thermal Sensor A: Thunderbolt Die, MLB Proximity I2C Write: 0xD8, I2C Read: 0xD9

R5850 PP3V3_S0

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

1

47

PP3V3_S0_TBTTHMSNS_R

2

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

5% 1/16W MF-LF 402 BI

TBTTHMSNS_D1_P

1

0.1uF

PLACE_NEAR=U5850.2:5MM NO_XNET_CONNECTION=TRUE

Thermal Diode: TBT Die (THSP)

U5850 EMC1412-A

2

77

TBTTHMSNS_D1_N

XW5851 SM PLACE_NEAR=U2800.AA8:2MM

76 63 39 36

BI

76 63 39 36

BI

R5851 1R5852 15K

1% 1/20W MF 2 201

100K

1% 1/20W MF 2 201

D

TBTTHRM_ALRT:PU

THERM*/ADDR

4

TBTTHMSNS_THM_L

OUT

38

ALERT*

6

TBTTHMSNS_ALERT_L

OUT

38

7 SMDATA 8 SMCLK

SMBUS_SMC_3_SDA SMBUS_SMC_3_SCL

THRM

m

2

PLACE_NEAR=U5850.3:5MM

U5850 I2C Address: By setting R5851 to 15k, I2C address for U5850 is 0xD8/0xD9.

1

TBTTHRM_THRM:PU

TQFN 2 DP 3 DN

402

1

TBTTHRM_SNS

VDD

C5851 1

0.0022uF 10% 50V TBTTHRM_SNS CERM

Placement Note: The P leg connects to THERMDA pin of the TBT chip, the N leg connect to pin AA8.

20% 2 10V CERM 402

TBTTHMSNS_D1_P MAKE_BASE=TRUE

C5850

GND PAD

5

Note: Use GND pin AA8 on U2800 for N leg.

9

77 43 23

77 43 23

1

D

TBTTHRM_SNS

Thermal Diode: MLB Proximity (TMLB)

.c

o

Placement Note: Place U5850 on the TOP side, on the left portion of the board, 1" to the right of USB connector.

C

x

C

fi

Thermal Sensor B & CPU High Peak Detection: CPU Proximity, Memory Proximity, Airflow, Fin Stack Proximity I2C Write: 0x98, I2C Read: 0x99

R5870 1

3

Placement Note: Place Q5871, Airflow thermal indicator, above the SSD, on the BOTTOM side.

Q5871

CRITICAL

Q5873

C5872

1

.c

2

77

CPUTHMSNS_D2_N

1

0.0022uF

BC846BLP 3

1

PLACE_NEAR=U5870.4:5MM NO_XNET_CONNECTION=TRUE

3

DFN1006H4-3

10% 50V CERM 2 402

CRITICAL

PLACE_NEAR=U5870.5:5MM

Thermal Diode: CPU Proximity (TC0P)

Placement Note: Place Q5872 between two rows of Memory devices, between channel A and B, on the BOTTOM side.

Placement Note: Place Q5873 under the CPU, on the BOTTOM side.

w

w

w

Thermal Diode: Memory Proximity (TM0P)

R5871 1R5872 100K

1% 1/20W MF 2 201

CPUTHRM_THRM:PU

EMC1704-2 QFN

1

100K

1% 1/20W MF 2 201

CPUTHRM_ALRT:PU

2

DP1

THERM* 9

CPUTHMSNS_THM_L

OUT

38

3

DN1

ALERT* 10

CPUTHMSNS_ALERT_L

OUT

38

4

DP2/DN3

SMDATA 11

SMBUS_SMC_1_S0_SDA

BI

14 32 36 39 68 72 76

5

DN2/DP3

SMCLK 12

SMBUS_SMC_1_S0_SCL

BI

14 32 36 39 68 72 76

16 15

SENSE+ SENSE-

13 14

DUR_SEL TH_SEL GND 8

B

PLACE_NEAR=U5870.3:5MM

CPUTHMSNS_D2_P

2

DFN1006H4-3 1

10% 50V CERM 2 402

CRITICAL

U5870

0.0022uF

CPUTHMSNS_D1_N

C5870

20% 2 10V CERM 402

VDD

C5871 1

h

Q5872

1

0.1uF

CRITICAL 77

BC846BLP

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PLACE_NEAR=U5870.2:5MM NO_XNET_CONNECTION=TRUE

1

BC846BLP DFN1006H4-3 2

77

a

Thermal Diode: Airflow (TA0P)

PP3V3_S0_CPUTHMSNS_R

2

CPUTHMSNS_D1_P

in

77

47

5% 1/16W MF-LF 402

ADDR_SEL 6 GPIO 7

CPUTHMSNS_ADDR_SEL 1

NC

R5875

B

0

5% 1/20W MF 2 0201 THRM_PAD 17

PP3V3_S0

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

Thermal Sensor: Fin Stack Proximity (Th1H) Placement Note: Place U5870 at corner near Fan, on the TOP side.

77 42

IN

77 42

IN

ISNS_CPUHIGAIN_P ISNS_CPUHIGAIN_N

CPUTHMSNS_DUR_SEL CPUTHMSNS_TH_SEL 1

R5874 10K

5% 1/20W MF 2 201

A

NOSTUFF

1

R5873 10K

5% 1/20W MF 2 201

SYNC_MASTER=J44

NOSTUFF

SYNC_DATE=08/12/2013

PAGE TITLE

Thermal Sensors DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

58 OF 120 SHEET

43 OF 78

1

A

8

7

6

5

4

3

2

1

FAN CONNECTOR

D

m

D

.c

o

KEEP THE 5 PIN CONNECTOR FROM D1

62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 46 47 50 61

PP3V3_S0

PP5V_S0

16 17 32 41 45 53 54 58 60 61 65 68

C

fi

x

C

CRITICAL

R6060

1

a

5% 1/20W MF 201

R6065 47K

SMC_FAN_0_TACH

1

R6061

1

h DFN1006H4-3

SYM_VER_3

FAN_RT_PWM

3

2

SMC_FAN_0_CTL

7

518S0769

B

w

w

w

B

IN

NC

5V DC MOTOR CONTROL GND TACH

.c

36

NC

1 2 3 4 5

DMN32D2LFB4

S

2

F-RT-SM 6

Q6060

G

1

100K 5% 1/20W MF 201

FAN_RT_TACH

2 5% 1/20W MF 201

NC

2

in

OUT

D

36

J6050

FF14A-5C-R11DL-B-3H

47K

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

Fan DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

60 OF 120 SHEET

44 OF 78

1

A

8

7

6

5

4

2

3

1

LPC+SPI Connector (Matt Card Connector) LPCPLUS CRITICAL

SPI ROM Dual-IO Mode (Mode 0 & 3) supported. SPI Frequency: 50MHz for CPU, 20MHz for SMC.

R6101

C6100

3.3K

1

R6103

U6100

10% 16V X5R-CERM 2 0201

5% 1/20W MF 2 201

72 45

SPI_MLB_CLK

6

SCK

72 45 72 45

SPI_MLB_CS_L SPIROM_WP_L SPIROM_HOLD_L

1 3 7

BI

72 68 36 14

BI

72 68 36 14

BI

45 72

R6102 1

0

72 45

IN

68 16 15

BI

68 18

IN

OMIT_TABLE

CE* WP* RST*/HOLD*

SPI:DUAL_IO SPIROM_USE_MLB

SPI_MLB_MOSI

5

SI/SIO0

72 68 36 14

SST25VF064C 72 45

IN

IN BI

64MBIT WSON

100K

72 68 17 72 68 36 14

VDD

0.1UF

5% 1/20W MF 201 2

CRITICAL

8

BYPASS=U6100:3mm 1

1

SPI_MLB_MISO

2

SO/SOI1

45 72

68 37 36

OUT

VSS THRM_PAD

66 66

2

68 37 36

IN

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

34

LPC_CLK24M_LPCPLUS LPC_AD<0> LPC_AD<2> LPC_AD<1> LPC_AD<3> SPI_ALT_MOSI XDP_LPCPLUS_GPIO LPCPLUS_RESET_L SMC_TDO NC_SMC_TRST_L NC_SMC_MD1 SMC_TX_L

5% 1/20W MF 0201 PLACE_NEAR=U6100.7:12MM

NOTE: If HOLD* is asserted ROM will ignore SPI cycles in normal and Dual-IO modes.

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

33

.c

NOTE: Not all ROM APNs currently used support Quad-IO. Also not compatible with Matt card ROM override. Quad-IO support is for experimentation only.

a in

R6110 SPI_CS0_R_L

1 PLACE_NEAR=U0500.Y7:50MM

B

IN

SPI_CLK_R

1

PLACE_NEAR=U0500.AA3:50MM

BI

SPI_MOSI_R (SPI_IO<0>)

72

PLACE_NEAR=U0500.AA2:50MM

SPI_MISO

1

PLACE_NEAR=U0500.AA2:50MM

BI

2

72

SPI_MOSI

SPI_MISO_R

1

0

5% 1/20W MF 0201 72 36

IN

SPI_SMC_MOSI

2

SMC12 Master IN

SPI_SMC_CLK

IN

45 72

IN

45 72

BI

15 36 68

IN

13 36 68

OUT

36 37 68

OUT

36 37 68

OUT

36 37 38 52 68

OUT

37 68

OUT

36 37 68

OUT

36 37 68

SPI_ALT_MISO

R6128 0

5% 1/20W MF 2 0201

LPCPLUS 1

R6127 0

5% 1/20W MF 2 0201

LPCPLUS 1

R6126 0

5% 1/20W MF 2 0201

45 72 45 72

Matt Card ROM Slave

45 72 45 72

LPCPLUS 1

R6125 0

5% 1/20W MF 2 0201

2 PLACE_NEAR=U6100.1:12MM

SPI_MLB_CS_L

OUT

45 72

SPI_MLB_CLK

OUT

45 72

PLACE_NEAR=U6100.6:12MM

SPI ROM Slave

R6122 33

1% 1/20W MF 201

2 PLACE_NEAR=U6100.5:12MM

2

SPI_MLB_MOSI

BI

45 72

SPI_MLB_MISO

BI

45 72

PLACE_NEAR=U6100.2:12MM

B

SPI:QUAD_IO

R6130 1

SPI:QUAD_IO

R6131 33

1% 1/20W MF 201

33

1% 1/20W MF 201

2 PLACE_NEAR=U6100.3:12MM

SPIROM_WP_L

45 72

SPIROM_HOLD_L

2

45 72

PLACE_NEAR=U6100.7:12MM

R6115 1

0

2 PLACE_NEAR=U5000.N9:12MM

R6116 1

0

5% 1/20W MF 0201 72 36

IN

PLACE_NEAR=U5000.M9:12MM

5% 1/20W MF 0201 72 36

33

1% 1/20W MF 201

w

R6114 1

LPCPLUS 1

2

1

1

SPI_SMC_MISO

1% 1/20W MF 201

R6123

72

SPI_IO<3>

OUT

33

1% 1/20W MF 201

SPI_IO<2>

72 36

A

1

w

72 14

BI

SPI_CLK

5% 1/20W MF 0201

(SPI_IO<1>) 72 14

0

2

15 45 68 72

13 36 68

w

BI

0

33

1

5% 1/20W MF 0201

R6113 72 14

SPI_CS0_L

R6112 1

OUT

14 36 68 72

R6120

72

R6121

2

5% 1/20W MF 0201

CPU Master 72 14

0

2

5% 1/20W MF 0201

R6111 72 14

0

BI

C

PLACE_NEAR=J6100.2:5MM SPI_ALT_MOSI PLACE_NEAR=J6100.15:5MM SPI_ALT_CLK PLACE_NEAR=J6100.12:5MM SPI_ALT_CS_L PLACE_NEAR=J6100.14:5MM

h

IN

.c

72 14

IN

45 72

516S1039

fi

SPI Bus Series Termination

PM_CLKRUN_L SPI_ALT_CLK SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_ROMBOOT SMC_RX_L SMC_TMS

OUT

x

C

D SPI_ALT_MISO LPC_FRAME_L SPIROM_USE_MLB

m

SPI:DUAL_IO

M-ST-SM 31 32

PP3V42_G3H PP5V_S0

o

52 51 39 38 37 36 34 33 30 17 68 65 61 61 60 58 54 53 44 41 32 17 16 68 65

9

D

68 45 15 72

J6100

DF40C-30DP-0.4V

PP3V3_SUS

4

65 61 60 59 14 11 8

SPI_SMC_CS_L

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

2

LPC+SPI Debug Connector

PLACE_NEAR=U5000.L10:12MM

R6117 1

0

5% 1/20W MF 0201

DRAWING NUMBER

Apple Inc.

2 PLACE_NEAR=U5000.K10:12MM R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

61 OF 120 SHEET

45 OF 78

1

A

8

7

6

5

4

2

3

1

AUDIO CODEC, ANALOG BLOCKS CRITICAL

APPLE P/N 353S4080

L6201

120-OHM-25%-1.3A PP3V3_S0_AUDIO_ANALOG

1

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.1 mm VOLTAGE=3.3V

PP4V5_AUDIO_ANALOG

46

BYPASS=U6201.H12:L10:5 mm

D

C6218 1

C6216 1

0.1UF

0.1UF

10% 16V X7R-CERM 2 0402

CRITICAL C6215 1 10UF

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.07MM

TP_AUD_CODEC_MICBIAS1_L

ANALOG HS3 HS4 HS3_REF HS4_REF HSIN+ HSIN-

SYM 1 OF 2

L8 MICBIAS1_L L7 MICBIAS1_R

TP_AUD_CODEC_MICBIAS2_L

SENSE_B1 SENSE_B2 SENSE_C SENSE_D

L5 MICBIAS2_L L4 MICBIAS2_R

TP_AUD_CODEC_MICBIAS2_R

N8 MICIN1_L+ M8 MICIN1_L-

GND_AUDIO_CODEC

N5 MICIN2_L+ M5 MICIN2_L-

0.1UF

CODEC_MICIN2

AUD_HSBIAS_IN AUD_HSBIAS AUD_HSBIAS_REF

R6206

N4 MICIN2_R+ M4 MICIN2_RHSBIAS_IN HSBIAS HSBIAS_REF HSBIAS_FILT

in

2.21K2

L12 L13 M13 N11

1

1% 1/20W MF 201

C6220 1UF

.c

20% 10V 2 X5R-CERM 0402

B

M11 L6 L9 L10

AUD_HSBIAS_FILT

HSGND

4.7UF

PLLGND

C6221

D13

1

A10 C8 C10

10% 25V X5R 402

HPGND HPGND HPGND

2

h

1

AGND AGND AGND AGND

50 46

AUD_HP_PORT_L AUD_HP_PORT_R

MIN_NECK_WIDTH=0.07MM MIN_NECK_WIDTH=0.07MM

50

50

IN

50

IN

50 77

IN

50 77

IN

50 77

IN

50 77

HS_MIC_P

IN

49 77

MIN_LINE_WIDTH=0.3MM 2 MIN_NECK_WIDTH=0.07MM HS_MIC_N

IN

49 77

C6224

10% 25V 402 X5R

GND_AUDIO_CODEC

46 50

C6225 1UF 1

C

10% 25V X5R 402

LINEOUT1_L+ E12 LINEOUT1_L- E13

AUD_TYPEDET NC_AUD_LO1_LP NC_AUD_LO1_LN

LINEOUT1_R+ F11 LINEOUT1_R- F12

NC_AUD_LO1_RP NC_AUD_LO1_RN

LINEOUT2_L+ F13 LINEOUT2_L- G11

OUT

50

AUD_LO2_L_P AUD_LO2_L_N

OUT

48 77

OUT

48 77

LINEOUT2_R+ G12 LINEOUT2_R- G13

AUD_LO2_R_P AUD_LO2_R_N

OUT

48 77

OUT

48 77

LINEOUT3_L+ H11 LINEOUT3_L- J11

AUD_LO3_L_P AUD_LO3_L_N

OUT

48 77

OUT

48 77

LINEOUT3_R+ J12 LINEOUT3_R- J13

AUD_LO3_R_P AUD_LO3_R_N

OUT

48 77

OUT

48 77

LINEOUT4_L+ K11 LINEOUT4_L- K12

NC_AUD_LO4_LP NC_AUD_LO4_LN

LINEOUT4_R+ K13 LINEOUT4_R- L11

NC_AUD_LO4_RP NC_AUD_LO4_RN

VCOM M12 VREF_ADC N12

46 50

50

IN

C13 AUD_US_HS_GND MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.07MM C12 AUD_CH_HS_GND MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.07MM B13 AUD_HP_PORT_REFUS MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.07MM B12 AUD_HP_PORT_REFCH MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.07MM N6 77 CODEC_HS_MIC_P MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.06MM M6 77 CODEC_HS_MIC_N MIN_LINE_WIDTH=0.3MM 1UF MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.06MM MIN_NECK_WIDTH=0.07MM 1 2 E11 D11 M3 L3

OUT OUT

AUD_TIPDET_1 AUD_TIPDET_2

a

10% 16V X5R-CERM 0201 2 GND_AUDIO_CODEC 1

BYPASS=U6201.A1:A2:5 MM

fi

N7 MICIN1_R+ M7 MICIN1_R-

C6226

MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM

SENSE_A1 C11 SENSE_A2 D12

VFBGA

N9 LINEIN_R+ M9 LINEIN_R-

TP_AUD_CODEC_MICBIAS1_R

50 46

U6201

FLYP FLYN FLYN

N10 LINEIN_L+ M10 LINEIN_L-

GND_AUDIO_CODEC

C

46 50

GND_AUDIO_CODEC HPOUT_L A12 HPOUT_R A13

CS4208-CRZR

A8 B10 B11

CODEC_FLYN 50 46

GND_AUDIO_CODEC

m

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.07MM VREF_DAC H13 VREF_DAC MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.07MM VHP_FILTN A11 VHP_FILT-

15UF

20% 4V X5R 2 0402

D

10UF

o

C6222 1

C6213

46 50

0.1UF

LFT. SPKR AMP. SIG. SOURCE RT. SPKR AMP. SIG. SOURCE LFT SUBWOOFER AMP. SIG. SOURCE RT. SUBWOOFER AMP. SIG. SOURCE

CODEC_VCOM CODEC_VREF_ADC CRITICAL 1 C6210 1UF-10OHM

A2

CRITICAL

20% 10V 2 X5R-CERM 0402-1

10% 16V X7R-CERM 2 0402

x

CODEC_FLYP MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.07MM

1

10% 16V X7R-CERM 2 0402

C6212 1

.c

BYPASS=U6201.H12:H13:5 mm

VA N13

20% 4V X5R 0402 BYPASS=U6201.A8:B10:5 mm

20% 16V 2 TANT-POLY 0805-LLP-1

VA_PLL A1

20% 16V 2 TANT-POLY 0805-LLP-1

2

VA_HP A9

15UF

1

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

BYPASS=U6201.N13:M11:5 mm

VA_REF H12

C6219 GND_AUDIO_CODEC

10UF

10% 16V X7R-CERM 2 0402

C6214 1 0.1UF

C6217 GND_AUDIO_CODEC

CRITICAL

50 46

1

PP3V3_S0

2 0402

CRITICAL

20% 25V TANT 2 0603-LLP

CRITICAL 1 C6211 10UF

B

20% 2 16V TANT-POLY 0805-LLP-1 46 50

w

GND_AUDIO_CODEC

w

4.5V POWER SUPPLY FOR CODEC APPLE P/N 353S2456

L6200

XW6201 SM 62 60 57 56 55 33 32 68 66 65 63

PP5V_S4

1

2

R6200 77 68 65 64 62 61 50 47 30 28 24 18 17 15 13 12 11 8 46 44 43 42 41 40 39 38 37

PP3V3_S0

A

1

PM_SLP_S3_BUF_L 61 27 26

2.2K 2

5% NO STUFF 1/20W MF 201

w

PLACE XW6201 NEAR 5V SOURCE MIN_LINE_WIDTH=0.20MM

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM VOLTAGE=4.5V

MIN_NECK_WIDTH=0.15MM U6200 FERR-22-OHM-1A-0.065-OHM VOLTAGE=5V TPS71745 2 1 6 IN SON PP5V_S4_AUDIO_XW 1 4V5_REG_IN OUT MIN_LINE_WIDTH=0.60MM 0201 CRITICAL MIN_NECK_WIDTH=0.20MM VOLTAGE=5V 4 4V5_REG_EN EN NR/FB 3 4V5_NR

R6207 2

22K

5% 1/16W MF-LF 402

1

1

NC 5

GND 2

C6200

1

0.1UF

C6201 1UF

20% 2 10V X7R-CERM 0402

10% 10V 2 X5R 402

CRITICAL

XW6200 SM 1

PP4V5_AUDIO_ANALOG

2

46

CRITICAL

C6202 1

1

10% 25V X5R-CERM 2 0201

20% 2 10V X5R-CERM 0201-1

0.01UF

C6203

SYNC_MASTER=J44

1.0UF

SYNC_DATE=08/12/2013

PAGE TITLE

AUDIO:CODEC, ANALOG DRAWING NUMBER

GND_AUDIO_CODEC

PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5

46 50

Apple Inc.

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.15MM VOLTAGE=0V

R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

62 OF 120 SHEET

46 OF 78

1

A

8

7

6

5

PP1V5_S0

PP1V5_S0_AUDIO_DIG

PP3V3_S0

C6300

1

4.7UF 20% 4V X5R-1 402

1

MIN_NECK_WIDTH=0.07MM VOLTAGE=1.5V

BYPASS=U6201.E1:F1:5 mm

C6301

1

0.1UF

2

BYPASS=U6201.G1:F1:5 mm

C6302 0.1UF

10% 2 16V X7R-CERM 0402

1

10% 2 16V X7R-CERM 0402

BYPASS=U6201.J2:J1:5 mm

0.1UF

C63051 20% 10V 2 X5R-CERM 0402-1

10% 10% 6.3V 2 6.3V CERM-X5R 2 CERM-X5R 0201 0201

49

IN OUT

5% 1/20W MF 201

49

C

OUT

IN

72 12

IN

72 68 12

OUT

HDA_BIT_CLK HDA_SYNC HDA_SDIN0

72 47 12

IN

HDA_SDOUT

72 12

IN

HDA_RST_L

R6331 1

22

2

72

CS4208_HDA_SDOUT0_R TP_CS4208_HDA_SDOUT1

5% 1/20W MF 201

NC_CS4208_MCLKA NC_CS4208_SCLKA NC_CS4208_LRCLKA NC_CS4208_SDOUTA NC_CS4208_MCLKB NC_CS4208_SCLKB NC_CS4208_LRCLKB NC_CS4208_SDOUTB

F2 E2 D1 C1 D2 C2 C3 B1 D3

BCLK SYNC SDI0 SDI1 SDO0 SDO1 SDO2 SDO3 RST*

A5 B2 B4 A3 B3

MCLK_A SCLK_A LRCK_A SDOUT_A SDIN_A

A6 B6 B5 B8 A4

MCLK_B SCLK_B LRCK_B SDOUT_B SDIN_B

VL_DM K1

VL_IF G1

U6201 CS4208-CRZR VFBGA

DIGITAL SYM 2 OF 2

C9 GPO0 B9 GPO1

NC_CS4208_GPO0 NC_CS4208_GPO1 72 12

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5

VL_SP A7

VD J2 H3 H2 H1 C4 C5 C7

GPIO0_SPKR_SHUTDOWN PD_CS4208_GPIO1 SPKRCONN_L_ID SPKRCONN_R_ID DFET_OPENUS DFET_OPENCH

402

SPDIF_IN G3 SPDIF_OUT G2

R6330

CS4208_SPDIF_IN CS4208_SPDIF_OUT

DMIC_SDA0 N3 DMIC_SCL0 N2 DMIC_SDA1 N1 DMIC_SCL1 M1

NC NC NC NC NC NC NC NC NC

F6 F7 F8 G6 G7 G8 H6 H7 H8

33

2

SPDIF_OUT_JACK

50

OUT

5% 1/16W MF-LF 402

NC_DMIC_CLK0

DMIC_SDA2 M2 DMIC_SCL2 L1 DMIC_SDA3 K2 DMIC_SCL3 L2

1

o

68 50

5% 1/20W MF 2 201

SHORT2 1

DMIC_CLK3_R

NC_DMIC_CLK1

.c

100K 2

100K

R6302

NC_DMIC_CLK2

x

1

IN

R6325

R6332 1

75

2

C

DMIC_SDA3

IN

DMIC_CLK3

OUT

47 50 68

50 68

1% 1/16W MF-LF 402

fi

R6322

68 50

0.1UF

a

NOSTUFF

5% 1/20W MF 201

OUT

D

C6307

10% 2 6.3V CERM-X5R 0201

OMIT 1

VL_HD E1

5% 1/20W MF 2 201

48

1

20% 10V 2 X5R-CERM 0402-1

PP3V3_S0

R6324

100K 2

BYPASS=U6201.A7:E3:5 mm

C63061 10UF

100K

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

10UF

1

1

PP3V3_S0

BYPASS=U6201.K1:K3:5 mm

C6303 1 C6304 0.1UF

D

R6323

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

MIN_LINE_WIDTH=0.6 MM

0201

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

1

APPLE P/N 353S4080

2

m

65 63 61 60 59 8 68

2

3

AUDIO CODEC, DIGITAL BLOCKS

L6300

FERR-22-OHM-1A-0.065-OHM 1

4

in

LGND LGND LGND LGND LGND

PP6301 P3MM 68 50 47

DMIC_SDA3

1

SM PP

PLACE_NEAR=U6201.N3:5 mm

h

F1 E3 F3 J3 K3

J1 DGND

C6 SDA B7 SCL

B

.c

B

PP6304 P3MM

w

72 47 12

HDA_SDOUT

1

SM PP

w

w

PLACE_NEAR=U6201.D2:5 mm

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

AUDIO:CODEC, DIGITAL DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

63 OF 120 SHEET

47 OF 78

1

A

8

7

6

5

4

2

3 66 48

1

PP5V_S0_AUDIO_AMP_L CRITICAL

L6410

C6413

IN

L6411

APN: 353S2888 & 353S2958 GAIN = +3 DB 1ST ORDER FC (L&R) = NOM 569 HZ 1ST ORDER FC (SUB) = NOM 9 HZ

77 46

C6412 1

C6414 FERR-1000-OHM 0.01UF 2 AUD_SPKRAMP_LIN_N 1 2 77 AUD_LO2_L_N1

IN

0402

48

1

0.1UF

U6410 MAX98300

NO_TEST=TRUE 77

10% 50V X7R-CERM 0402

77

WLP

SPKRAMP_LIN_PA3 IN+ SPKRAMP_LIN_NB3 INNO_TEST=TRUE

SPKR_SHUTDOWN

GAIN C3

SPKR_L_GAIN

1

SPKRCONN_L_OUT_N OUT 50

68 77

R6410

100K

100K

PGND

5% 1/16W MF-LF 402 2

5% 1/16W MF-LF 402 2

o

m

CRITICAL

D

1

R6400

0402

50 68 77

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

B2 NC

FERR-1000-OHM GPIO0_SPKR_SHUTDOWN 1 2

OUT

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

A2

IN

SPKRCONN_L_OUT_P

OUT+ B1 OUT- C1

C2 SHDN*

L6401

47

C6411

10% 2 16V X5R-CERM 0201

CRITICAL

PVDD

50V X7R-CERM 0402

NO_TEST=TRUE

CRITICAL

BYPASS=U6410.A1:A2:5 mm

47UF

20% 6.3V TANT-POLY 2 CASE-A4

FERR-1000-OHM 0.01UF 2 AUD_SPKRAMP_LIN_P 1 2 AUD_LO2_L_P 1 77 NO_TEST=TRUE 0402 CRITICAL 10%

4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375)

D

CRITICAL

A1

77 46

CRITICAL

PP5V_S0_AUDIO_AMP_R CRITICAL CRITICAL C6422 1 L6420 C6423 47UF FERR-1000-OHM 20% 0.01UF 6.3V 2 1 2 1 2 TANT-POLY 77 AUD_LO2_R_P AUD_SPKRAMP_RIN_P CASE-A4

.c

66 48

77 46

IN

0402

IN

x

77 46

NO_TEST=TRUE

0402

10% 50V X7R-CERM48 0402

CRITICAL C2

SSM2375 WLCSP

NO_TEST=TRUE

CRITICAL

L6431

C6434 FERR-1000-OHM 0.22UF AUD_LO3_R_N 1 2 AUD_SPKRAMP_RSUBIN_N 1 2 RSUBIN_N 77

48

SPKR_SHUTDOWN

OUT+ C3 OUT- B3

A2 SD*

GAIN A3

GND

10% 16V CERM 402

B 66 48

OUT+ B1

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

OUT- C1

NO_TEST=TRUE

C2 SHDN*

SPKR_SHUTDOWN

GAIN C3

50 68 77

C

68 77

SPKR_R_GAIN

B2 NC

R64201 A2

PGND

100K

5% 1/16W MF-LF 402 2

C6431

10% 16V 2 X5R-CERM 0201

SPKRCONN_SR_OUT_P MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

RSUB_GAIN

EDGE B2

NO_TEST=TRUE

0402

B1 IN+ A1 IN-

C1

IN

U6430

NO_TEST=TRUE

10% 16V CERM 402

CRITICAL

77 46

VDD

CRITICAL

in

NO_TEST=TRUE

0402

A3 IN+ SPKRAMP_RIN_P 77 SPKRAMP_RIN_N B3 IN-

OUT

SPKRCONN_R_OUT_N 50 OUT

0.1UF

20% 6.3V 2 TANT CASE-AL1

h

IN

SPKRCONN_R_OUT_P MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

1

SPKRCONN_SR_OUT_N MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

C6436

OUT

50 68 77

OUT

50 68 77

4700PF

10% 50V 2 X7R-CERM 0402

B

.c

77 46

1

100UF

CRITICAL L6430 C6433 FERR-1000-OHM 0.22UF AUD_LO3_R_P 1 2 AUD_SPKRAMP_RSUBIN_P 1 2 RSUBIN_P 77

WLP

BYPASS=U6430.C2:C1:5 mm

C6432 1

CRITICAL

U6420

a

PP5V_S0_AUDIO_AMP_R

10% 16V 2 X5R-CERM 0201

MAX98300 NO_TEST=TRUE

fi

CRITICAL

66 48

77

C6421 0.1UF

CRITICAL

PVDD

NO_TEST=TRUE

CRITICAL 10% 50V L6421 C6424X7R-CERM FERR-1000-OHM 0.01UF 0402 1 2 1 2 77 AUD_SPKRAMP_RIN_N AUD_LO2_R_N

C

BYPASS=U6420.A1:A2:5 mm

1 A1

CRITICAL

PP5V_S0_AUDIO_AMP_L

NO_TEST=TRUE

0402

FERR-1000-OHM AUD_LO3_L_N 1 2 77

0402

AUD_SPKRAMP_LSUBIN_N

NO_TEST=TRUE

C6444 0.22UF 1

2 LSUBIN_N NO_TEST=TRUE

10% 16V CERM 402

C6441

20% 6.3V 2 TANT CASE-AL1

10% 2 16V X5R-CERM 0201

0.1UF

100UF

CRITICAL

VDD

U6440

w

CRITICAL

L6441

IN

NO_TEST=TRUE 10% 16V CERM 402

CRITICAL

77 46

LSUBIN_P

1

SPKRCONN_SL_OUT_P

50 68 77

OUT

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

SSM2375 WLCSP

48

SPKR_SHUTDOWN

B1 IN+ A1 IN-

OUT+ C3 OUT- B3

A2 SD*

GAIN A3 EDGE B2

GND C1

FERR-1000-OHM 0.22UF 2 AUD_SPKRAMP_LSUBIN_P 1 2 AUD_LO3_L_P 1 77

C6442 1 C2

C6443

w

IN

CRITICAL

CRITICAL

L6440

77 46

w

BYPASS=U6440.C2:C1:5 mm CRITICAL

OUT

LSUB_GAIN 1

SPKRCONN_SL_OUT_N

50 68 77

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

C6446 4700PF

10% 2 50V X7R-CERM 0402

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

AUDIO: SPEAKER AMP DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

64 OF 120 SHEET

48 OF 78

1

A

8

7

6

5

4

3

2

1

D

D R6550 HS_MIC_P

1

OUT

R6556

1

100K 5% 1/20W MF 201

HS_MIC_N 77 46

AUD_HS_MIC_P

IN

5% 1/16W MF-LF 402

CRITICAL

1

MIN_NECK_WIDTH=0.06MM MIN_LINE_WIDTH=0.2MM

2.2K 2

C6550

1

C6558 27PF

3300PF

10% 10V 2 X7R-CERM 0201

2

50 77

CRITICAL 5% 25V 2 NP0-C0G 0201

R6559 1

OUT

2.2K 2 5% 1/16W MF-LF 402

IN

AUD_HS_MIC_N

50 77

m

77 46

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.06MM

IN

.c

47

C

o

R/C6550 FILTER TO ADDRESS OUT-OF-BAND NOISE ISSUE SEEN ON EARLY HEADSETS (SEE RADAR # 6210118)

BYPASS=U6500.B2:3MM

DFET_OPENCH

C

R6520 10K

10% 35V 2 CERM-X5R 0402

0.1UF

10% 2 16V X5R-CERM 0201

1

C6563 0.01UF

10% 10V 2 X5R-CERM 0201

5% 1/16W MF-LF 2 402

VDD

U6500

TAIC3027A0YFFR WCSP C2 PSEL OUT1 A1 OUT2 A2 C1 CP

DFET_CPO1

GND

C6501

B1

1

1000PF

BYPASS=U6501.B2:3MM

DFET_OPENUS

BYPASS=U6501.B2:3MM

B

1

R6521 10K

5% 1/16W MF-LF 2 402

C6530 1.0UF

10% 35V 2 CERM-X5R 0402

1

C6542 0.1UF

10% 2 16V X5R-CERM 0201

1

C6543 0.01UF

10% 10V 2 X5R-CERM 0201

.c

1

49 50 77

C6502

AUD_CONN_RING2_XW AUD_CONN_RING2_XW

OUT

49 50 77

OUT

49 50 77

GND

1000PF

5% 2 25V NP0-C0G 0402

w

w

1

VDD

U6501

TAIC3027A0YFFR WCSP C2 PSEL OUT1 A1 OUT2 A2 C1 CP

B1

w

DFET_CPO2

B B2

IN

49 50 77

OUT

h

47

OUT

in

5% 25V 2 NP0-C0G 0402

AUD_CONN_SLEEVE_XW AUD_CONN_SLEEVE_XW

a

1

C6562

fi

1

1.0UF

B2

C6560

x

BYPASS=U6500.B2:3MM

1

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

AUDIO: JACK DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

65 OF 120 SHEET

49 OF 78

1

A

8

7

6

5

4

2

3

CODEC OUTPUT SIGNAL PATHS FUNCTION HP/HS OUT TWEETERS SUB SPDIF OUT

VOLUME 0X02 (2) 0X03 (3) 0X04 (4) N/A

SPEAKER CONNECTOR

CONVERTER 0X02 (2) 0X03 (3) 0X04 (4) 0X0E (14)

PIN COMPLEX 0X10 (16) 0X12 (18) 0X13 (19) 0X21 (33)

MUTE CONTROL N/A CODEC GPIO0 CODEC GPIO0 N/A

FUNCTION DMIC 1 DMIC 2

CONVERTER 0X09 (9) 0X09 (9)

PIN COMPLEX 0X1C (28) 0X1C (28)

HEADSET MIC

0X07 (7)

0X18 (24)

CRITICAL

J6602

HP=80HZ

2-MIC CONNECTOR

78171-6006 M-RT-SM 7

APN: 518S0672

APN: 518S0818

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

CODEC INPUT SIGNAL PATHS

D

1

PP3V3_S0

77 68 48

IN

77 68 48

IN

68 47

IN

J6601

77 68 48

IN

FF14A-6C-R11DL-B-3H

77 68 48

IN

SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_L_ID

1 2 3 4 5 6

CRITICAL

VREF 3.3V 3.3V

DMIC_SDA3 68 47

F-RT-SM 7

OUT

SPKRCONN_SL_OUT_P SPKRCONN_SL_OUT_N

D

8

OMIT

1 2 3 4 5 6

R6680 SHORT2

1

OTHER CODEC GPIO LINES LEFT SPEAKER ID RIGHT SPEAKER ID DFET CONTROL

GPIO2 INPUT GPIO3 INPUT GPIO4 OUTPUT

68

DMIC_SDA2

402

HIGH = FG, LOW = MERRY HIGH = FG, LOW = MERRY HIGH = DFETs OPEN

68 47

OUT

DMIC_CLK3

CRITICAL

J6603 78171-6006 M-RT-SM 7

m

2.7V

8

CRITICAL

L6611

XW6600 SM

77

2

AUD_CONN_SLEEVE

1

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.06MM

0402

o

1

OUT

IN

77 68 48

IN

68 47

IN

77 68 48

IN

77 68 48

IN

SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N SPKRCONN_R_ID

1 2 3 4 5 6

PLACE_NEAR=J6600.5:5mm

120-OHM-25%-1.3A AUD_HP_PORT_REFCH 77 46

77 68 48

2

CRITICAL

SPKRCONN_SR_OUT_P SPKRCONN_SR_OUT_N

8

L6612

AUD_CH_HS_GND

1

2

77 49

C

77 49

AUD_CONN_SLEEVE_XW MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.1MM

0402

XW6601 SM

AUD_HS_MIC_P

1

OUT

2

CRITICAL

L6613

PLACE_NEAR=J6600.6:5mm

XW6602 SM

1

OUT

77

2

0402

AUD_HP_PORT_REFUS

AUD_CONN_RING2

1

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.06MM

2

fi

120-OHM-25%-1.3A 77 46

CRITICAL

L6614

120-OHM-25%-1.3A AUD_US_HS_GND 77 46

1

OUT

2

77 49

AUD_CONN_RING2_XW MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.1MM

a

0402

XW6603 SM OUT

AUD_HS_MIC_N

1

2

CRITICAL

L6604

120-OHM-25%-1.3A 1 2 AUD_CONN_HP_LEFT

AUD_HP_PORT_L IN

0402

CRITICAL

R66021 46

OUT

AUD_TIPDET_21

2 0201

GND_AUDIO_CODEC

AUD_CONN_TIPDET_2

L6607

FERR-470-OHM

1

R6603 2.2K

46

5% 1/16W MF-LF 402 2 46

CRITICAL

OUT

AUD_TIPDET_1

1

CRITICAL

L6605

2 0201

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.06MM

0402

AUD_HP_PORT_R

CRITICAL

9 10 11

C6600 1

L6606

OUT

AUD_TYPEDET

1

2

AUD_CONN_TYPEDET

0201

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

IN

SPDIF_OUT_JACK

w

47

1UF

10% 10V 2 X5R 402-1

w

FERR-470-OHM 46

F-RT-TH MIC AUDIO GND 2RTN DET2 DET1 1RTN

5 6 2 1 8 7 3 4

R.AUDIO

AUDIO GND AUDIO

AUD_CONN_TIPDET_1

120-OHM-25%-1.3A 1 2 AUD_CONN_HP_RIGHT

IN

NC

h

FERR-470-OHM

5% 1/16W MF-LF 402 2

B

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.06MM

L6608

2.2K

J6600 AUDIO-SPDIF-J44

.c

46

APN: 514-0875

in

77 49

C

x

OUT

.c

120-OHM-25%-1.3A 77 46

PP3V3_S0

1

w

2

5% 1/16W MF-LF 2 402

C6602 1 100PF

5% 25V NP0-CERM 2 0201

C6603

C6605 1

100PF

ESDALC5-1BM2

5% 25V NP0-CERM 2 0201

SOD882

1

CRITICAL

2

C6604

DZ6601 SOD882

1

2

100PF

5% 25V NP0-CERM 2 0201

ESDALC5-1BM2 1

2

CRITICAL

1

SOD882

100PF

5% 25V NP0-CERM 2 0201

DZ6602 SOD882

1

SHELL PINS

C6607 100PF

SOD882

CRITICAL

2

C6608 1

2

5% 25V NP0-CERM 2 0201

ESDALC5-1BM2 1

A

CRITICAL

DZ6604

100PF

DZ6605 SOD882

0.1UF

10% 6.3V 2 CERM-X5R 0201

OPERATING VOLTAGE 3.3 POF 12 13 14 15

5% 25V 2 NP0-CERM 0201

ESDALC5-1BM2 1

C6606 1

CRITICAL

CRITICAL

DZ6606

ESDALC5-1BM2

ESDALC5-1BM2 1

2

DZ6603

100PF

5% 2 25V NP0-CERM 0201

DZ6607

R6601 10K

1

CRITICAL

C6601

1

B

VIN VDD GND

ESDALC5-1BM2 1

SOD882

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

AUDIO: JACK TRANSLATORS DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

66 OF 120 SHEET

50 OF 78

1

A

8

7

6

MagSafe DC Power Jack

5

4

2

3

1

CRITICAL

F7005

6AMP-32V-0.0095OHM 1

PPDCIN_G3H

2

52 65 68

0603

PP3V42_G3H 1

NO STUFF 1

WTB-PWR-M82 M-RT-SM

TC7SZ08FEAPE 5

C7005

10% 50V 2 X7R 603-1

A

2

SMC_BC_ACOK

D

36 37 52

IN

Y B

1

3

SMC_BC_ACOK_VCC

65 52 40

BLEEDER CRITICAL 1

R7029

U7000 SC70-5

5 EXT

SBR0330CW

5% 1/16W MF-LF 2 402

MAX9940 ADAPTER_SENSE

D7020

2.0K

VCC

SOT-323 1

3

SYS_ONEWIRE

INT 4

BI

36

CRITICAL

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.20MM 1

C7020

0.1UF BLEEDER

10% 50V 2 X7R 603-1

3

GND

BLEEDER

2

NC

1-Wire OverVoltage Protection The chassis ground will otherwise float and can send transients onto ADAPTER_SENSE when AC is connected.

DCIN_ISOL_BLEEDER_PSRC

2

1

R7012

1

R7030 1K

NC

Q7010

2

5% 1/16W MF-LF 2 402

S

1

G

DCIN_ISOL_BLEEDER_R

SI5419DU

Q7020

POWERPAK

SOT23-HF1

S

1

D 3

2N7002

G

1

G

Q7030

D

DCIN_ISOL_BLEEDER_NGATE MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.20MM

2

BLEEDER 1

R7021

5% 1/16W MF-LF 2 402

R7010

C7012

100K

5% 1/20W MF 2 201

1

40.047UF 10% 25V 2 X5R 0402

1

DCIN_ISOL_GATE_R

10K

2

1% 1/20W MF 201

DCIN_ISOL_GATE K

D7010 GDZT2R6.8

a

GDZ-0201

in

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=18.5V

.c

B

PPBUS_G3H_R

2

5% 1/8W MF-LF 805

2

PPVIN_G3H_P3V42G3H

P3V42G3H_BOOST

BAT-J44

C7092 1 C7091 1 C7090 1 4.7UF

10% 25V X6S-CERM 2 0603

4.7UF

10% 25V X6S-CERM 2 0603

VIN

4.7UF

10% 25V X6S-CERM 2 0603

10 11 12 13 14 15 16 17 18

PPVBAT_G3H_CONN

52 68

BI

36 39 52 68 76

BI

36 39 52 68 76

SYS_DETECT_L

DFN 8 SHDN*

NC

R7080

w

C7050 0.1UF

10% 25V 2 X5R 402

C7060 1UF

1

2

RCLAMP2402B SC-75

10% 25V 2 X5R 603-1

CRITICAL GND

0

1/20W MF 2 201

1

R7050 10K

C7094 1 0.22UF

CRITICAL 10% 10V CERM 2 40210UH-20%-0.85A-0.46OHM 1 2 P3V42G3H_SW Vout MIN_LINE_WIDTH=0.5 mm 2520 MIN_NECK_WIDTH=0.25 mm

L7095

SWITCH_NODE=TRUE DIDT=TRUE

FB 1 THRM PAD

P3V42G3H_SHDN_L NO STUFF STUFF 1 R7081 NO C7080 1 49.9K 1000PF 1%

CRITICAL 1

7 NC

SW 4 BIAS 2

1

68

D7050

BOOST

U7090

5% 1/20W MF 2 0201

SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

1

PWR PWR PWR SMBUSSCL SMBUSSDA SYSDETL GND GND GND

SWITCH_NODE=TRUE

LT3470AED

= 3.425V

300MA MAX OUTPUT (Switcher limit)

1

1 C7095 R7095 348K

22PF

5% 50V 2 NP0-C0G-CERM 0201

1% 1/20W MF 201 2

CRITICAL 1

C7099 22UF

P3V42G3H_FB 1

R7096

20% 6.3V 2 X5R 0603

200K

5% 25V CERM 2 0402

1% 1/20W MF 201 2

5% 1/16W MF-LF 2 402

Vout = 1.25V * (1 + Ra / Rb)

3

NC NC

1 2 3 4 5 6 7 8 9

w

F-ST-TH

B

DIDT=TRUE

NO_TEST=TRUE

w

CRITICAL

65 68 17 30 33 34 36 37 38 39 45 51 52 61

Supply needs to guarantee 3.31V delivered to SMC VRef generator

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V

518-0394

J7050

PP3V42_G3H

3.425V "G3Hot" Supply 3

5

10

1

SOT-323 1

6

h

MIN_NECK_WIDTH=0.25 mm VOLTAGE=18.5V

R7005 PPBUS_G3H

A

PP18V5_DCIN_CONN_R D7005 SBR0330CW MIN_LINE_WIDTH=0.6 mm

2

1% 1/3W MF 805

68 65 58 52 40 25

C

CRITICAL

R7020 47

When input voltage is 2V the FET will be off blocking the leakage path and 22.1K can be properly detected. When input voltage is at 16V+, FET will conduct and power charger and 3.42V reg

R7011

6.8V Zener

1

Input impedance of 68K meets sparkitecture requirements for both MPM4 and MPM5.

1

5

fi

10K

1% 1/20W MF 2 201

5A

SOT23

BLEEDER

3

C

BLEEDER AO3407A

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.20MM

68K

3

20% 10V CERM 2 402

9

1

0.1UF

m

C7000 1

518S0508

PPDCIN_G3H_ISOL

o

TP_TDM_ONEWIRE_MPM

68

PLACE_NEAR=U7001.5:1MM

SOT665 4

0.1UF

S

1 2 3 4 5 6

U7001

.c

J7000

20% 2 10V CERM 402

CRITICAL

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.20MM VOLTAGE=18.5V

D

D

0.1UF

PP18V5_DCIN_FUSE

x

68

CRITICAL

17 30 33 34 36 37 38 39 45 51 52 61 65 68

C7008

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

DC-In & Battery Connectors DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

70 OF 120 SHEET

51 OF 78

1

A

8

7

6

5

4

2

3

1

Reverse-Current Protection NOSTUFF

R7192 1

MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm

P5V1_VIN

2

MF-LF 5% 402 1/16W

SWITCH_NODE=TRUE

1

VIN

4.7UF

C7180

CHGR_AGATE_DIV

S

D

2

1

(CHGR_DCIN)

2

39 76 39 76

36 68

IN

36 68

BI

61

IN

Float CELL for 1S 1

21.5K

2

1% 1/16W MF-LF 402

1

R7115

77

100K

77

1% 1/16W MF-LF 2 402

1

6 3

ACIN

11 10 4

CHGR_ICOMP CHGR_VCOMP CHGR_VNEG CHGR_CSO_P CHGR_CSO_N

5 7 8 18 17

ICOMP VCOMP VNEG CSOP CSON

C7150 1UF

CHGR_VCOMP_R 2 1

C7115

10% 16V X5R 402

DCIN SGATE AGATE CSIP CSIN

2

52

26 1 28 77 27 77

CHGR_BOOT CHGR_UGATE

BOOT UGATE PHASE

25

LGATE

21

CHGR_LGATE

BGATE 20V/V AMON 36V/V BMON (OD) ACOK

16

CHGR_BGATE CHGR_AMON CHGR_BMON SMC_BC_ACOK

24

CRITICAL 1

22UF 2

CRITICAL 1

C7130

2

CRITICAL 1

C7131 22UF

20% 25V POLY-TANT CASE-D2-SM

1

C7132 22UF

20% 2 25V POLY-TANT CASE-D2-SM

20% 2 25V POLY-TANT CASE-D2-SM

2

C7135

1

C7136

1.0UF

1.0UF

10% 50V X5R 0603

10% 50V X5R 0603

2

C7137

1

0.001UF 20% 50V CERM 0402

2

C PLACE_NEAR=C7136.1:3mm

0.22UF 2

Max Current = 8.5A (L7130 limit) f = 400 kHz

CRITICAL

2

10% 10V CERM 402

Q7130

PLACE_NEAR=U7100.23:2MM 1

RJK03P0DPA

CRITICAL

WPAK

9 15 14

OUT

CHGR_PHASE

1

40

OUT

36 37 51

(GND)

2

2

1

3

4

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V

CRITICAL 1

w

10% 16V X7R-CERM 0402

2

2

C7100 1UF 10% 10V X5R 402-1

C7105

2

10% 50V X7R-CERM 0402

CRITICAL

R7150

Q7155

0.005

SI7137DP

1% 1W MF 0612-2

(CHGR_CSO_N)

R7152

SO-8

2

1

4

3

PPVBAT_G3H_CHGR_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V

3

2.2

1

2

77 42

5%

0

1

2

C7155

5%

C7156

1

0.1UF 2

10% 25V X5R 402

C7157

1

D

2

10% 50V X7R-CERM 0402

5

PPVBAT_G3H_CONN

51 68

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V

1

0.01UF

G 2

4

CHGR_CSO_R_P 1/16W

77 42

S

2 1

B

TO/FROM BATTERY

SYM-VER-2

MF-LF

402

CHGR_CSO_R_N 1/16W

MF-LF

402

(PPVBAT_G3H_CHGR_R) (CHGR_BGATE)

C7126

1

0.001UF 10% 50V X7R-CERM 0402

2

52

C7145 0.001UF

20% 2 16V POLY-TANT CASE-D2E-SM

CRITICAL

R7151

0.22UF

10% 50V X5R-CERM 0603-1

1

C7140 68UF

(CHGR_CSO_P)

1

25 40 51 58 65 68

PPVBAT_G3H_CHGR_REG

5

10% 25V X5R 402

w 0.01UF

10% 10V X5R-CERM 0402

1

w

C7111

0.068UF

1

PPBUS_G3H

6

PLACE_NEAR=U7100.22:1MM

10% 50V CERM 0402

2

1206

1UF

C7116

TO SYSTEM

F7140 12AMP-32V

PIME103T-4R7MS

DIDT=TRUE

40

OUT

CRITICAL

L7130 4.7UH-20%-8.5A-18.3MOHM

7

2

C7142

1% 1/20W MF 201

Vout = 1.25V * (1 + Ra / Rb)

PLACE_NEAR=Q7130.2:1MM

SWITCH_NODE=TRUE

353S2929

CHGR_ICOMP_RC

2

C7125

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm DIDT=TRUE MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE DIDT=TRUE

SM 1

1

SWITCH_NODE=TRUE

DIDT=TRUE

(PPVBAT_G3H_CHGR_R)

1

10% 25V X5R 402

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

23

470PF 2

C7121

2

0 5% 1/16W MF-LF 402 2

XW7100

CHGR_VNEG_R 1

2

R7125 1

1

3.01K 1% 1/16W MF-LF 402

1

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

CHGR_DCIN CHGR_SGATE CHGR_AGATE CHGR_CSI_P CHGR_CSI_N

PLACE_NEAR=U7100.29:1MM

R7116

0.5% 1W MF RL1632W

2

2

NO_XNET_CONNECTION=TRUE

5% 50V COG 402

1K

2

4

DIDT=TRUE

R7142 1% 1/16W MF-LF 402

R7120

.c

2 1

Vout = 5.50V 250MA MAX OUTPUT (Switcher limit)

CHGR_BOOT_R

330PF

B

3 1

0.1UF

VDDP

VHST CRITICAL SMB_RST_N SCL U7100 TQFN SDA VFRQ CELL

13

CHGR_ACIN

R7111

20% 25V X5R-CERM 0603

fi

5% 51 1/16W MF-LF 51 402

1% 1/16W MF-LF 2 402

12

CHGR_RST_L SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA CHGR_VFRQ CHGR_CELL

2

CHGR_CSI_R_N

a

0

1

77

in

SMC_RESET_L

IN

2

SWITCH_NODE=TRUE

VDD

R7100 68 38 36 37 45

2

1

20

5% 1/16W MF-LF 2 402

52

ISL6259

68.1K

2

10% 25V X5R 402

PGND

R7110

0.1UF

10% 10V X5R 402

R7102

(AGND) THRM_PAD

1

2

C7122

1

1UF

100K

GND_CHGR_AGND

CHGR_CSI_R_P

5% 1/16W MF-LF 402

NO_XNET_CONNECTION=TRUE

C7101

22

10% 10V X5R 402

1K 1% 1/16W MF-LF 402

1

1UF

1

10

77

0.02

R7122

PP5V1_CHGR_VDDP

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V

29

R7112

10UF

20% 25V X5R-CERM 0603

2

C7199

PPDCIN_G3H_CHGR

52

NO STUFF

1

10% 10V X5R-CERM 0402

1

2

19

C7102

C7120

R7101 5% 1/16W MF-LF 402

C

1% 1/20W MF 201 2

5% 50V NP0-C0G-CERM 0201

1

10UF

200K

h

51 45 39 38 37 36 34 33 30 17 68 65 61

681K

22PF

D

CRITICAL

C7198

2 5% 1/16W MF-LF 402

0.047UF 2

4.7

C7195

52

R7196 1

CRITICAL 1

30mA max load 1

1 R7195

PP5V1_CHGR_VDDP

10 1

Divider sets ACIN threshold at 13.55V

PP5V1_CHGR_VDD

CRITICAL 1

2

(CHGR_SGATE) R7121

5% 1/16W MF-LF 402

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V

1

DP418C-SM

P5V1_BIAS

2

o

20

CHGR_DCIN_D_R

ACIN pin threshold is 3.2V, +/- 50mV

PP3V42_G3H

1

m

2

2

Input impedance of ~90K meets sparkitecture requirements

FB THRM PAD

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE

0

P5V1_FB

5% 1/16W MF-LF 402

52

GND

.c

3

2

52

MF-LF 5% 402 1/16W

MIN_NECK_WIDTH=0.25 mm 2 MIN_LINE_WIDTH=0.5 mm

R7181

1% 1/16W MF-LF 402

(CHGR_AGATE) R7105

1

1

P5V1_SW

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm

62K

SOT-323

L7195

CHGR_SGATE_DIV 1

1

BIAS

CRITICAL

R7180

332K

SBR0330CW

4

CHGR_DCIN

R7191

CRITICAL

x

D7105

SW

5

G CRITICAL

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm

CRITICAL

NC

5% 1/16W MF-LF 2 402

R7186 1

PPDCIN_G3H_ISOL

7

NC

100K

6

2

1

DIRECTFET-MC

1% 1/16W MF-LF 402

2

33UH-20%-0.39A-0.435OHM

SHDN*

PPDCIN_G3H_INRUSH MIN_LINE_WIDTH=0.1 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=18.5V

2

NOSTUFF G

10% 25V X5R 402

LT3470A 8

10% 25V X6S-CERM 0603

IRF9395TRPBF

470K

0.1UF 2

D

R7185

C7185

3

1

Q7180

S

1

10% 10V CERM 402

DFN

4.7UF

D

65 51 40

1

2

5% 402 1/16W

0.22UF

BOOST

U7190

2

1

9

5

4

9

8

7

10

PPDCIN_G3H

2

1

FROM ADAPTER 68 65 51

10% 25V X6S-CERM 0603

NCNCNCNC

C7194

0

1

MF-LF

DIDT=TRUE NO_TEST=TRUE

C7190

R7190 (P5V1_BIAS)

P5V1_BOOST 3

Inrush Limiter

0

CHGR_DCIN_D_R

6

52

For Erp Lot6 spec

MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm

2

GND_CHGR_AGND MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

PBus Supply & Battery Charger DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

71 OF 120 SHEET

52 OF 78

1

A

8

7

6

5

4

2

3

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

353S4170

1

IC,ISL95826R6200,PWM,PGOOD,SCREN,32P,QFN

U7200

CRITICAL

1

BOM OPTION

D

D PP5V_S0

61 60 58 54 45 44 41 32 17 16 68 65

R7201

R7202

1

10

1

2

PP5V_S0_CPUVR_VDD

1

PLACE_NEAR=U7200.16:2mm

2

2

2

2

R7279 1

1

130

1% 1/20W MF 201

1% 1/20W MF 201

2

PLACE_NEAR=U7200.32:2mm

70 8

OUT

70 8

IN

CPU_VIDSOUT CPU_VIDALERT_L CPU_VIDSCLK

54

IN

CPUVR_ISUMP

70 8

BI

1% 1/20W MF 201

2

2

2

17 8

IN

28 27 26

1

CPU_VR_EN

IN

4

OMIT_TABLE VR_HOT*

29

32 6

CPUVR_COMP

C7215

R7215 1

845

1

1

CPUVR_ISUMN_RC

201 MF

1% 1/20W

2

C7216

820PF

2

1

CPUVR_ISUMN

1

316

0201 X7R-CERM

2

5% 25V

7

CPUVR_FB CPUVR_FB2

22PF

2

10% 25V

R7210

13

CPU_RTN

201 NP0-C0G

8

(CPUVR_ISUMP)

15 14

CPUVR_ISUMN_R

2

1% 1/20W MF 201

54

CPU_PROCHOT_L

OUT

NTC

31

220PF

IN

70 37 36 6

5

30

10% 25V X7R-CERM 201

54

ISL95826

CPUVR_NTC

CPUVR_PROG1 CPUVR_PROG2 CPUVR_PROG3

PLACE_NEAR=U7200.30:2mm

C7214

IN

6.04K

1% 1/20W MF 201

CPUVR_SLOPE

NO_XNET_CONNECTION=TRUE

54

34K

1% 1/20W MF 201

x

C

9.31K

1% 1/20W MF 201

R7280

54.9

2

16.9K

U7200

42

CPUVR_ISEN1 CPUVR_ISEN2

3

CPUVR_IMON

OUT

12 11

0.01UF 10% 10V X7R-CERM 0201

2

C7211

C7240

0.01UF

1.2NF

2

10% 10V X7R-CERM 0201

+/-10% 10V CERM 0201-1

1

2

C7241

NOSTUFF FCCM

18

PWM3 PWM2 PWM1

23

20

CPUVR_PWM2 CPUVR_PWM1

DRSEL

25

CPUVR_DRSEL

CPUVR_FCCM

OUT

54

1

0

SLOPE PROG1 PROG2 PROG3

R7225

22

NC

2

OUT

54

OUT

54

5% 1/20W MF 0201

VR_ON

R7224

SDA ALERT* SCLK CRITICAL COMP

PGOOD

NC NC NC NC

RTN FB FB2

2

9 19 21 24

CPU_VR_READY

0 1

OUT

8 17

C

2 5% 1/20W MF 0201

NC NC NC NC

ISUMP ISUMN IMON ISEN1 ISEN2 ISEN3

33

C7210

1

in

10

1

PLACE_NEAR=U7200.17:2mm 2

LLP

.c

10% 6.3V CERM-X5R 0201

R7220

fi

1

0.1UF

1

R7221

a

C7278 PLACE_NEAR=R7279.1:3mm

1

R7222

o

2

PP1V05_S0

61 60 57 37 17 16 15 11 8 6 68 65

1

R7223

40 54 55 57 65

THRM PAD

1

0201

PPBUS_S5_HS_COMPUTING

FCCM = 1: Forced CCM FCCM = 0: DCM FCCM = FLOATING: PS4

VDD VIN

100KOHM

2

5% 1/16W MF-LF 402

17

16

(GND)

R7237

95.3K

C7202 10% 25V X7R 0402

10% 10V X5R 402-1

m

1

R7236 1

1

1

0.22UF

C7201

1% 1/20W MF 201

PLACE_NEAR=Q7310.3:3MM PLACE_NEAR=L7310.1:3MM

1% 1/20W MF 201

2

7.5K 1

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.9V

1UF

R7235 CPUVR_NTC_R

PPVIN_S0_CPUVR_VIN

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

5% 1/16W MF-LF 402

1

39PF 5% 25V NP0-C0G 201

C7213

R7240

1

2

C7230

1

10% 10V X7R 0201

R7230 95.3K

1500PF 2 2

1% 1/20W MF 201

B

2

.c

B

1% 1/20W MF 201

1

2

NO_XNET_CONNECTION=TRUE

75K

0.1UF 10% 6.3V CERM-X5R 0201

1

h

CPUVR_COMP_RC

NO_XNET_CONNECTION=TRUE

R7241 CPU_VCCSENSE_P_R

NO_XNET_CONNECTION=TRUE

1

IN

NO_XNET_CONNECTION=TRUE

0

CPU_VCCSENSE_P

1

2

C7242 100PF

5% 1/20W MF 0201

2

1

5% 25V NP0-CERM 0201

IN

CPU_VCCSENSE_N

2

CPU_VCCSENSE_P_RC

XW7261

NOSTUFF NO_XNET_CONNECTION=TRUE

R7242

R7250

1K 2

2K 1

1% 1/20W MF 201

1

2

CPUVR_FB_RC

1% 1/20W MF 201

NOSTUFF 1

SM

w

70 9

w

70 8

1.69K 1% 1/20W MF 201

R7243

1

330PF 2 2

NO_XNET_CONNECTION=TRUE

C7260 330PF

2

10% 16V X7R-CERM 0201

1

10% 16V X7R-CERM 0201

C7261 330PF

w

1

C7250

2

10% 16V X7R-CERM 0201

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

CPU VR12.6 VCC Regulator IC DRAWING NUMBER

Apple Inc.

REVISION

R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

BRANCH

PAGE

72 OF 120 SHEET

53 OF 78

1

SIZE

D

A

8

7

65 57 55 53 40

6

5

4

2

3

Additonal Input Bulk Caps

PPBUS_S5_HS_COMPUTING CRITICAL

1

NOSTUFF CRITICAL

CRITICAL

1

C7313

68UF

1

C7314

1

C7315

10UF

68UF

THESE TWO CAPS ARE FOR EMC

NOSTUFF CRITICAL

1

C7316

10UF

C7317

1

1.0UF

C7318

1

C7319

C7370

33UF

0.001UF 0.001UF

20% 2 16V POLY-TANT CASED12-SM

CRITICAL CRITICAL

Q7310

G

SISA18DN PWRPAK-SM

PILE063T-SM 152S1821 77 41

IN

IN

CPUVR_FCCM

7 FCCM

R73151

OMIT_TABLE

4

9

353S3942

5 THRM LGATE PAD

CPUVR_LGATE1

4

2.2

1

60 58 54 53 45 44 41 32 17 16 68 65 61

CRITICAL

1

NOSTUFF CRITICAL

CRITICAL

68UF

R7320

OMIT_TABLE CRITICAL

7 FCCM

PWRPAK-SM

OUT

53 54

OMIT_TABLE

D 4

2

2.2

MF-LF

SISA12DN PWRPAK-SM

CPUVR_ISNS2_N

OUT

Vout = 1.85V max 40A MAX OUTPUT F = 800KHZ

41 54 77

1.00

1% 1/20W MF-LF 2 0201

OMIT

CPUVR_ISUMN

R73251 1K

1% 1/20W MF 201 2

1

8 10 42 65 68

OUT

53 54

R7327

CPUVR_ISNS1_N NOSTUFF 1 2

NO_XNET_CONNECTION=TRUE

R7326 200K

NONE NONE NONE 0201

1% 1/20W MF 2 201

CPUVR_ISEN2

OUT

53

CPUVR_ISUMP

OUT

53 54

41 54 77

NO_XNET_CONNECTION=TRUE

S

R7321 CPUVR_BOOT2

MIN_LINE_WIDTH=0.25 MM 5% MIN_NECK_WIDTH=0.2 MM 1/16W DIDT=TRUE

CRITICAL

Q7321

G

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE GATE_NODE=TRUE

PPVCC_S0_CPU

2 4

DIDT=TRUE NOSTUFF

C7322

5

B

CPUVR_ISNS2_P

CPUVR_PH2_SNUB

0.001UF

CPUVR_LGATE2

1 3

C

R7324

10% 2 50V X7R-CERM 0402

1 2 3

1 CPUVR_BOOT2_RC MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

C7321 402 0.22UF

B

2

w

1

53

1

1

UGATE 1

9

4

77 41

S 1 2 3

PHASE 8

353S3942

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.8V

a

5% 1/10W MF-LF 603 2

SISA18DN

BOOT 2

5 THRM LGATE PAD

1% 1W MF 0612

2.2

CRITICAL

GND

152S1821

R73221

Q7320

G

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE GATE_NODE=TRUE

2 PILE063T-SM

h

CPUVR_FCCM

41 54 77

NO_XNET_CONNECTION=TRUE

.c

IN

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE SWITCH_NODE=TRUE NOSTUFF

PPVCC_S0_CPU_PH2

in

6 54 53

DFN

0.00075

1

CPUVR_PHASE2 5

CPUVR_UGATE2 4

3 PWM

CASE-D2E-SM

THESE TWO CAPS ARE FOR EMC

NOSTUFF CRITICAL

68UF

L7320

ISL6208D CPUVR_PWM2

OUT

1

0.4UH-20%-23A

D

IN

OUT

CPUVR_ISUMP

CRITICAL

10% 16V X6S-CERM 2 0402

53

CASE-D2E-SM

10% 20% 20% 10% 10% 20% 20% 50V 16V 35V 50V 16V 16V 2 POLY-TANT 2 POLY-TANT 2 X6S-CERM 2 16V X6S-CERM 2 CERM-X6S 2 X7R-CERM 2 X7R-CERM 0603 0402 0402 0402 CASE-D2E-SMCASE-D2E-SM0603

2

1UF

U7320

CASE-D2E-SM

D

68UF

20% 16V 2 POLY-TANT

1 C7326 1 C7327 1 C7328 1 C7329 C7323 C7324 C7325 10UF 10UF 1.0UF 0.001UF 0.001UF 1

CRITICAL

VCC

20% 16V 2 POLY-TANT

C7375

1 2 3

C7320 1

PHASE 2

CPUVR_ISEN1

CPUVR_BOOT1_RC

10% 16V CERM 402

PP5V_S0

NONE NONE NONE 0201

1% 1/20W MF 2 201

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

0.22UF

C

NOSTUFF 1 2 CPUVR_ISNS2_N

200K

PWRPAK-SM

C7311 402 1

68UF

20% 2 16V POLY-TANT

CRITICAL

1

R7317

53 54

R7316

1% 1/20W MF 201 2

S

2

MF-LF

68UF

C7374

SISA12DN

R7311 CPUVR_BOOT1

CRITICAL

1

C7373

OMIT OUT

NO_XNET_CONNECTION=TRUE

Q7311

G

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE GATE_NODE=TRUE

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM 5% 1/16W DIDT=TRUE

1

1K

CRITICAL

D

CASE-D2E-SM

1% 1/20W MF-LF 2 0201

CPUVR_ISUMN

C7312

10% 2 50V X7R-CERM 0402

5

PHASE 8

OUT

20% 2 16V POLY-TANT

41 54 77

CRITICAL

1

C7372

68UF

DIDT=TRUE NOSTUFF

1

CRITICAL

CASED12-SM

1.00

0.001UF

GND

CRITICAL

1

CPUVR_ISNS1_N

CPUVR_PH1_SNUB

BOOT 2 UGATE 1

20% 16V 2 POLY-TANT

CASED12-SM

m

54 53

DFN

3 PWM

33UF

20% 2 16V POLY-TANT

CASED12-SM

C7380

R7314

ISL6208D CPUVR_PWM1

CASED12-SM

CRITICAL

1

C7378

33UF

20% 20% 16V 2 16V 2 POLY-TANT POLY-TANT

1 3

CPUVR_ISNS1_P

OUT

33UF

1

5% 1/10W MF-LF 603 2

U7310 53

2 4

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.8V

2.2

1 2 3

VCC

2

R73121

S

6

PHASE 1

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE SWITCH_NODE=TRUE NOSTUFF

PPVCC_S0_CPU_PH1

CRITICAL

1

C7376

o

CPUVR_UGATE1 4 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE GATE_NODE=TRUE

1

CPUVR_PHASE1

CRITICAL

1

.c

D

D

33UF

x

10% 16V X6S-CERM 2 0402

CRITICAL

C7371

1% 1W MF 0612

0.4UH-20%-23A

OMIT_TABLE

1UF

fi

C7310

0.00075

L7310

5

1

1

Note: C7377, C7379, C7381 were removed. Area where the pads used to reside was preserved.

R7310

PP5V_S0

NOSTUFF CRITICAL

CRITICAL

1

20% 20% 10% 10% 10% 20% 20% 16V 16V 50V 50V 16V 2 16V 2 35V CERM-X6S 2 X7R-CERM 2 X7R-CERM POLY-TANT 2 POLY-TANT 2 X6S-CERM 2 X6S-CERM 0603 0402 0402 0402 CASE-D2E-SMCASE-D2E-SM0603 68 65 61 44 41 32 17 16 60 58 54 53 45

1

w

w

10% 16V CERM 402

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

CPU VR12.5 VCC Power Stage DRAWING NUMBER

Apple Inc. R



NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

.

BRANCH

PAGE

73 OF 120 SHEET

54 OF 78

1

A

8

7

6

5

4

2

3

1

D

D

PPBUS_S5_HS_COMPUTING

65 57 54 53 40

PLACE_NEAR=Q7430.2:1MM

1

CRITICAL 1

C7431

C7434

68UF

73 65 55 41 22 21 20 19 17

PP1V35_S3

C7401

DDRREG_FB MEMVTT_PWR_EN DDRREG_EN

VTT Enable VDDQ/VTTREF Enable

DDRREG_1V8_VREF 1

R7415 19.6K

DDRREG_MODE DDRREG_TRIP

1% 1/16W MF-LF 402 2

16

TPS51916

VREF

8

REFIN

18

DDRREG_VBST DDRREG_DRVH DDRREG_LL

15 14 13

MODE TRIP

DRVL CRITICAL PGOOD VDDQSNS VTT VTTSNS VTTREF

1% 1/16W MF-LF 402

0.01UF 1% 10% 1/16W 16V 2 X7R-CERM MF-LF 402 0402 2PLACE_NEAR=U7400.8:5mm PLACE_NEAR=U7400.8:1MM

2

DDRREG_P1V35_L

Q7419 SSM3K15FV

GATE_NODE=TRUE

20 9 3

1

R7417 200K

1

5

DDRREG_VTTSNS 73 68 65

4

20% 25V X5R-CERM 0603

C7460, C7461 close 2

XW7400

C7450

1

0.22UF 10% 10V CERM 402

15

1.0UH-20%-15A-0.0066OHM

10% 25V X5R 402

PHASE

7

2

152S1822

RES,MTL FILM,1/16W,100K,1,0402,SMD,LF

R7416

114S0391

1

RES,MTL FILM,1/16W,60.4K,1,0402,SMD,LF

R7416

376S0612

1

MOSFET,N-CH,30V,100MA,7.0OHM,SOT-723,HF

Q7419

114S0428

1

RES, MTL FILM,1/16W,150k,0402,SMD,LF

R7419

XW7450 SM

PPDDR_S3_REG_R

1

2

PP1V35_S3

VOLTAGE=1.35V MIN_LINE_WIDTH=0.8 MM MIN_NECK_WIDTH=0.1 MM

CRITICAL

6 1

1

1

3

4

CRITICAL

5

(DDRREG_DRVL)

1

2

CRITICAL

C7442 330UF

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

20% 2 2.0V POLY-TANT CASE-B2-SM1

C7461 10UF

2

2

20% 25V X5R-CERM 0603

17 19 20 21 22 41 55 65 73

VOUT = 1.35V 9A MAX OUTPUT f = 400 kHz

C7440 330UF 20% 2.0V POLY-TANT CASE-B2-SM1

1

C7446 0.001UF

CRITICAL

2 1

1

20% 2.0V 2 POLY-TANT CASE-B2-SM1

2

C7441

C7445

10% 50V X7R-CERM 0402

10UF

330UF

20% 25V X5R-CERM 0603

PLACE_NEAR=C7460.1:4mm

2

XW7401

to memory

SM (DDRREG_VDDQSNS)

77 41

77 41

OUT

NC_ISNS_DDR_S3P 1

OUT

NC_ISNS_DDR_S3N

B R7401 1

w

REFERENCE DES

1

2

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

2

5% 1/20W MF 201

DDRREG_VDDQSNS_R MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

BOM OPTION

CRITICAL

PPDDR:1V5

CRITICAL

PPDDR:1V35

CRITICAL

PPDDR:1V5

CRITICAL

PPDDR:1V5

w

QTY

w

DESCRIPTION

114S0411

1 PIME063T-SM

10

PART NUMBER

L7430

PLACE_NEAR=C7442.1:2MM

PLACE_NEAR=U7400.21:1MM

IN

CRITICAL

PLACE_NEAR=C7461.1:4mm

1% 1/16W MF-LF 2 402

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0V

MEM_VDD_SEL_1V5_L

C CRITICAL

POWER56 1

.c

B

CRITICAL

R7418

GND_DDRREG_SGND

2

2

PPVTTDDR_S3

1

2

1

PLACE_NEAR=C7461.1:3mm

SM

S

XW7460

10UF

SOD-VESM-HF

G

61

C7460

CRITICAL

1

(DDRREG_LL)

1

SM 1

51.1K

1% 1/16W MF-LF 2 402

CRITICAL FDMS3602S

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

VTT THRM GND PAD

PLACE_NEAR=U7400.18:3MM

3

OMIT_TABLE

DIDT=TRUE

DDRREG_DRVL DIDT=TRUE DDRREG_PGOOD OUT DDRREG_VDDQSNS PP0V675_S0_DDRVTT

11

PLACE_NEAR=U7400.19:3MM

D

SWITCH_NODE=TRUE

21

100K

C7416

10

1

7

PGND GND

OMIT_TABLE

R7416

150K

GATE_NODE=TRUE DIDT=TRUE

10mA max load

1

DDRREG_VBST_RC MIN_NECK_WIDTH=0.17 mm MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

PLACE_NEAR=U7400.6:1MM

R7419 1

0

Q7430

0.1UF

SWITCH_NODE=TRUE

QFN

6

19

VBST DRVH SW

U7400

S3 S5

PLACE_NEAR=U7400.8:5MM

OMIT_TABLE

PLACE_NEAR=C7435.1:3MM

2

C7425

MF-LF 1/16W 2

in

2

20% 50V CERM 0402

h

0.1UF

17

V5IN

NO_TEST=TRUE

402 5% 1

fi

12

1

0.001UF 2

PLACE_NEAR=Q7430.5:3MM

x

MIN_NECK_WIDTH=0.17 mm MIN_LINE_WIDTH=0.6 mm DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

R7425

SWITCH_NODE=TRUE

10% 16V X7R-CERM 0402

2

C7433

1

(DDRREG_DRVH)

VLDOIN

C7415

PLACE_NEAR=Q7430.5:3mm

2

C IN

10% 35V CERM-X6S 0402

2

PLACE_NEAR=U7400.12:1MM

IN

1.0UF

PLACE_NEAR=U7400.2:1MM

2

20% 10V X5R-CERM 0402-1

IN

C7435

10% 35V CERM-X6S 0402

.c

20% 10V X5R-CERM 0402-1

1

10UF

61

1

1.0UF

1

a

C7400

17

2

C7432

10UF

CRITICAL

19

20% 2 16V POLY-TANT CASE-D2E-SM

CRITICAL

PP5V_S4

66 65 63 62 60 57 56 46 33 32 68

1

68UF

20% 2 16V POLY-TANT CASE-D2E-SM

o

CRITICAL

m

DDR3L (1V35 S3) REGULATOR

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

1.35V DDR3 SUPPLY DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

74 OF 120 SHEET

55 OF 78

1

A

8

7

6

5

4

2

3

1

D

D

C7540

CRITICAL 1

20% 16V 2 POLY-TANT CASE-D2E-SM

1

C7542

68UF

1

68UF

20% 16V 2 POLY-TANT CASE-D2E-SM

20% 16V 2 POLY-TANT CASE-D2E-SM

2

C7541

1

0.001UF

10% 25V X6S-CERM 0603

20% 50V CERM 0402

2

PP5V_S5

C7570

4.7UF

C7500 1UF 10% 25V X5R 603-1

1

CRITICAL

C7550

1

6

P5VS4_VSW MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

1 PLACE_NEAR=C7553.1:3MM

BG

1

2

SM 1

P5VS4_VFB1_R 2

R7522

XW7520 SM 1

5

PGND 9

1

SWITCH_NODE=TRUE

NO STUFF

C7599 10% 50V CERM 402

1

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUE

R7556 1

2

XW7521

1% 1/16W MF-LF 402

SM

13

22

29

23

2

20% 10V X5R-CERM 402

2

DRVH1 SW1

30

DRVL1

8 11

P5VS4_VFB1 P5VS4_COMP1 61

IN

61

OUT

9 10

P5VS4RS3_EN P5VS4RS3_PGOOD

SMC_PM_G2_EN

IN

1

R7536 1

R7537

12.1K

10K 2 2

DIDT=TRUE

DRVH2

24

SW2

25

P3V3S5_DRVH

4 5

CSP2 CSN2

CSP1 CSN1 MODE VFB1 COMP1

RF VFB2 COMP2

EN1 PGOOD1

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

P5VS4_COMP1_R

2

EN2 PGOOD2

18 17

3 16 15 21 20

GATE_NODE=TRUE

P3V3S5_LL

0.001UF 20% 50V CERM 0402

2

376S0958

1.0UH-22A

2

PCMC063T-SM

CRITICAL

C7572

PHASE

NO STUFF 6

R7598

OUT

3

4

5% 1/10W MF-LF 603 2

5

12.1K

2

P3V3S5_SNUBR MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

10% 16V X7R-CERM 0402

R7506 1

SWITCH_NODE=TRUE

NO STUFF 1

165K

R7546 1

1.82K 1% 1/16W MF-LF 402

2

2

1

10K

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

C7598 0.001UF

2

R7539 1

R7538

1

10

1

1% 1/16W MF-LF 402

C 2

CRITICAL

7

0.1UF

36 61

10% 50V X7R-CERM 0402

POWER56

1

1

0.001UF

FDMS3602S

C7588

61

10.5A MAX OUTPUT

CRITICAL

C7590

1

10UF

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

IN

59 60 61 65 68 8 11 13 15 16 17 18 26 27 29 77

F = 600 KHZ

L7560

1

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

S5_PWR_EN S5_PWRGD

10% 50V X7R-CERM 0402

R7516

2

5.23K

2

2

XW7560

1% 1/16W MF-LF 402

P3V3S5_CSP2_R

P3V3S5_COMP2_R

SM

C7583

2

VOUT = 3.3V

MM MM

P3V3S5_RF P3V3S5_VFB2 P3V3S5_COMP2

XW7500

2

10% 25V X6S-CERM 0603

CRITICAL

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE GATE_NODE=TRUE

GATE_NODE=TRUE

P3V3S5_CSP2 P3V3S5_CSN2

2

1

P3V3S5_TG

2

SWITCH_NODE=TRUE

P3V3S5_DRVL

1

1

4.7UF

Q7560

0

THRM_PAD

2

10% 50V X7R 603-1

R7563

5% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.2

SWITCH_NODE=TRUE

DIDT=TRUE

27

C7581

152S0754 C7564 0.1UF

36 37 61

P3V3S5_VBST

DIDT=TRUE

DRVL2

GND

2

1% 1/16W MF-LF 402

26

1

20% 16V 2 POLY-TANT CASE-D2E-SM

PP3V3_S5

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

1

VBST2

1

68UF

o .c

VREF2

VREG3

VREG5

VIN

VBST1

32

7

2

SM 1

2

1

1

5% 50V CERM 402

R7520

C7536

1

C7538

4700PF 2

2

10% 100V CERM 402

(P5VP3V3_VREF2)

1% 1/16W MF-LF 402

1

1

4700PF

10% 100V CERM 402

C7592 330UF

20% 25V X5R-CERM 0603

2

20% 6.3V POLY-TANT CASE-D3L-SM

2

XW7562 SM 1

P3V3S5_VFB2_R 2

XW7561 1

R7562

SM

10

1

5% 1/16W MF-LF 2 402

DIDT=TRUE

PLACE_NEAR=U7501.28:1MM

C7537

41.2K

2

EN

12

2

DIDT=TRUE

P5VS4_CSP1 P5VS4_CSN1

3.01K

1

U7501

C7582

20% 16V 2 POLY-TANT CASE-D2E-SM

2.2UF

10% 10V CERM 402

DIDT=TRUE

P5VS4_DRVL

150PF 1

1

P5VS4_LL

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

2.49K

0.22UF

CRITICAL

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

5VS4_VFB1_RR

B

31

P5VS4_DRVH GATE_NODE=TRUE

R7547 2

SKIPSEL1 SKIPSEL2 OCSEL

SWITCH_NODE=TRUE

DIDT=TRUE

1

0.0033UF

P5VS4_CSP1_R

P5VS4_VBST

2

10% 16V X7R-CERM 0402

20% 16V 2 POLY-TANT CASE-D2E-SM

C7503

QFN

0.1UF

P5VS4_SNUBR

19 14

C7518

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

10

5% 1/16W MF-LF 2 402

4

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

R7599

5% 1/10W MF-LF 2 603

XW7522

1

TGR

5% 1/16W MF-LF 402

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE DIDT=TRUE

8

6

P5VP3V3_SKIPSEL

1

P5VS4_TG

NO STUFF 1

PLACE_NEAR=L7520.2:3MM

2

PLACE_NEAR=L7520.1:3MM

20% 25V X5R-CERM 0603

20% 6.3V 2 POLY-TANT CASE-D3L-SM

3

VSW

7

10UF

330UF

TG

1

1

x

2

R7544

28

2

CRITICAL

C7552

10% 50V X7R-CERM 0402

10% 50V X7R 603-1

h

20% 2 6.3V POLY-TANT CASE-D3L-SM

1

2

CSD58872Q5D VIN SON5X6

1

fi

0.001UF

330UF

0.1UF

Q7520

PCMB103T-1R0MS

C7571

C7524

2

a

1.0UH-21A-0.006OHM 1

C7553

5% 1/20W MF 0201 2

CRITICAL 1

68UF

20% 6.3V X5R 603

33

CRITICAL

5% 1/20W MF 0201

TPS51980

L7520

CRITICAL

C

1

0

1

0

in

CRITICAL

F = 600 KHZ

R7500

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

V5SW

152S0688

1

C7501

.c

10.8A MAX OUTPUT

1

R7501 1

SKIP_5V3V3:AUDIBLE

C7580

10UF

SKIP_5V3V3:INAUDIBLE

VOUT = 5.0V

CRITICAL 1

68UF

C7505

2

P5VP3V3_VREF2

PP5V_S4

C7584

CRITICAL

2

P5VP3V3_VREG3 57 56 55 46 33 32 68 66 65 63 62 60

CRITICAL 34 65 68

VOUT = 5V 100MA MAX OUTPUT

1

PLACE_NEAR=C7592.1:3MM

1

68UF

PLACE_NEAR=L7560.1:3MM

CRITICAL

C7543

PP5V_S4

65 63 62 60 57 56 55 46 33 32 68 66

1

CRITICAL

PPBUS_S5_HS_OTHER3V3

2

65 40

PLACE_NEAR=L7560.2:3MM

PPBUS_S5_HS_OTHER5V

m

65 40

C7539

P3V3S5_VFB2_RR

47PF 2

2

5% 50V CERM 402

B

R7560 1 23.2K

(P5VP3V3_VREF2)

0.5% 1/16W MF-LF 0402

2

1

w

GND_5V3V3_AGND

R7521 10.0K

R7561

1

10.0K 0.5% 1/16W MF 402

2

w

w

2

0.5% 1/16W MF 402

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

5V / 3.3V Power Supply DRAWING NUMBER

Apple Inc.

REVISION

R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

BRANCH

PAGE

75 OF 120 SHEET

56 OF 78

1

SIZE

D

A

8

7

6

5

4

2

3

1

D

D

m

1.05V S0 Regulator

PPBUS_S5_HS_COMPUTING

PP1V05_S0

P1V05S0_BOOT_RC

66 65 63 62 60 56 55 46 33 32 68

PP5V_S4

C7601

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

1

1

10UF

C7600 10UF 20% 10V X5R 603

5% 25V CERM 0402

1

2

2

1

C7619

C7624 1.0UF

68UF 20%

2

16V POLY-TANT CASE-D2E-SM

10% 35V CERM-X6S 0402

PLACE_NEAR=Q7630.8:1.5mm

0.1UF

20% 10V X5R 603

1

1

1000PF

C7630 10% 16V

1

2

2

R7630 5% 1/10W

2

MF-LF

603

C

X7R-CERM 0402

2.2

BYPASS=U7600.2:1mm

x

C

C7622

.c

60 57 53 37 17 16 15 11 8 6 68 65 61

o

65 55 54 53 40

2

2

BYPASS=U7600.12:1mm

CRITICAL

Q7630 FDPC1012S

61 P1V05S0_EN

16

P1V05_S0_VREF

6

S3 S5

TPS51916

CRITICAL

35.7K 2

P1V05S0_FB

8

REFIN

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

P1V05S0_MODE

1% 1/20W MF 201 2

19

P1V05S0_TRIP

18

MODE TRIP

VTTREF

1% 1/20W MF 201 2 PLACE_NEAR=U7600.8:5mm

0.01UF 2

1

10% 16V X7R-CERM 0402

R7610

1

1K

BYPASS=U7600.8:1mm

2

1% 1/20W MF 201

1

R7613 47.5K

2

2

R7614

5% 1/16W

MF-LF

P1V05S0_VTT

1

P1V05S0_PGOOD

1% 1w CYN 0612-SHORT

1.0UH-20%-11A-0.011OHM

3

1

4

2 PP1V05_S0_REG_R FDSD0630-SM

NOSTUFF 1

CRITICAL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

1 3

Vout = 1.05V CRITICAL

R7632

7

LSG

C7649

2

5% 1/10W MF-LF 603

2

PLACE_NEAR=U7600.18:3mm

XW7600

.c

B P1V05S0_AGND

C7650

5A MAX OUTPUT F = 400 KHZ

20%

C7623

1

2.0V

2

POLY-TANT

1000PF 77 41

OUT

ISNS_1V05_S0_P

OUT

ISNS_1V05_S0_N

5% 25V CERM 0402

DIDT=TRUE 61

1

330UF

PLACE_NEAR=L7630.2:1.5mm

P1V05S0_LL_SNUB

OUT

53 57 60 6 8 11 15 16 17 37 61 65 68

PP1V05_S0

2 4

2.2

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

5

VTT THRM GND PAD 4

L7630 SW

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

9

0.003

1 2

402

P1V05S0_VTTREF

1% 1/20W MF 201

PLACE_NEAR=U7600.19:3mm

HSG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

NOSTUFF

C7632

1

77 41

CASE-B2-SM1

2

CRITICAL 1

0.001UF

14.7K

1% 1/20W MF 201

OMIT

R7640

P1V05S0_DRVH_R

P1V05S0_LL

20

h

49.9K

C7616

10

1

7

PGND GND

R7612

2

P1V05S0_DRVL

PLACE_NEAR=U7600.8:5mm

1

11

3

1

10% 50V X7R-CERM 0402

5

BYPASS=U7600.6:1mm

R7611

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

6

1

P1V05S0_DRVH

13

10

10% 16V X7R-CERM 0402

Short Rsense

0

21

1

0.1UF

DRVL PGOOD VDDQSNS VTT VTTSNS

9

V+ V+

R7631

14

QFN

VREF

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

C7615

15

8

GND GND GND

17

U7600

a

P1V05S3_EN

VBST DRVH SW

V5IN

Scrub S3 & S5 pins connections!

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

in

12

P1V05S0_VBST

fi

LLP

VLDOIN

C7648 330UF 20%

2

2

PLACE_NEAR=C7648.1:1mm

2

XW7610 SM

2.0V POLY-TANT CASE-B2-SM1

1

1

0.22UF

SM 1

10% 10V CERM 402

B

2

PLACE_NEAR=U7600.21:1mm

R7641

w

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

10

P1V05S0_VDDQSNS 1

P1V05S0_VDDQSNS_R 2

5% 1/20W MF 201

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

w

w

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

1.05V S0 Power Supply DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

76 OF 120 SHEET

57 OF 78

1

A

8

7

6

5

4

2

3

1

Page Notes Power aliases required by this page: - =PPVIN_S0SW_LCDBKLTFET

(9-12.6V LCD BACKLIGHT INPUT)

- =PP5V_S0_BKLT

(5V BACKLIGHT DRIVER INPUT)

- =PP5V_S0SW_KBDLED

(5V KEYBOARD BACKLIGHT INPUT)

BOM options provided by this page: BKLT:ENG - Stuffs 10.2 ohm series R for engineering builds BKLT:PROD - Stuffs 0 ohm series R for production

PPVIN_S0SW_LCDBKLT_F 1 3

SSOT6-HF

58

4

PPVIN_S0SW_LCDBKLT_R

PLACE_NEAR=Q7701.5:3MM

1

C7700

1

152S1527 CRITICAL

2

OUT

OUT

ISNS_LCDBKLT_P

NOSTUFF

R7701 1

80.6K

10% 16V X7R-CERM 0201 2

3

1% 1/16W MF-LF 402

2

R7702 63.4K

65 61 60 58 41 32 17 16 54 53 45 44 68

L7710

0.001UF

22UH-20%-2.4A-0.105OHM

10% 50V CERM 402

1

D7710

1

C7710

2

R7744 1

1

0

A

58

C7711

C7712

1

4.7UF

0.1UF

10% 25V X6S-CERM 0603

10% 25V X6S-CERM 0603

10% 25V X5R 402

2

2

R7745 PLACEMENT_NOTE:

5% 1/16W MF-LF 2 402

58

1

4.7UF

0

5% 1/16W MF-LF 402 2

SANDWICH C7710 AND C7711 PLACE_NEAR=L7710.1:5MM

PP5V_S0_BKLT_A PP5V_S0_BKLT_D

PLACE_NEAR=L7710.1:5MM 58

PLACE_NEAR=L7710.1:5MM

DFLS2100

1

2

2

C7741

1UF 10% 10V X5R 402-1

PLACE_NEAR=U7700.18:5MM

1UF 10% 10V X5R 402-1

18

5

R7740

19

BKLT_SENSE_OUT

PLATFORM_RESET NO LONGER GATES THE BKLT_EN AS BOTH COME FROM PCH NOW

17

R7742 0

BKLT_EN_R

2

NO STUFF

5% 1/20W MF 0201

1

16

C7742 33PF 5% 25V NPO-C0G 0201

GND_SW GND_SW GND_SW2 GNDD GNDA

2

GND_BKLT_SGND

IN

1

BKLT_PWM_KEYB

2

7

NO STUFF

5% 1/20W MF 0201

1

C7747

2

5% 25V NPO-C0G 0201

w

1

R7753

2.4K

2.4K

5% 1/20W MF 201

5% 1/20W MF 201

2

14

IN

I2C_BKLT_SCL

1

0

I2C_BKLT_SDA

1

I2C ID DEDICATED.ONLY CONNECTS TO JERRY

0

5% 1/20W MF 0201

2

w

BI

1

PP5V_S0_BKLT_A

2

C

150K

PLACE_NEAR=U7700.1:3MM

2

1% 1/16W MF-LF 402

10.2 2

PART NUMBER

BKLT:ENG

QTY

116S0004

1

R7721 1

CRITICAL

10.2 2

BOM OPTION

CRITICAL

R7720,R7721

BKLT:PROD

35 68

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

BKLT:ENG PLACE_NEAR=U7700.14:10MM

KBDLED_CATHODE2

35 68

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

0.1% 1/16W TF 402

R7741

REFERENCE DES

RES,MTL FILM,0 OHM,1A MAX,0402,SMD

KBDLED_CATHODE1

8

1

DESCRIPTION

PLACE_NEAR=U7700.13:10MM

31.6K

2

1% 1/20W MF 201

PLACE_NEAR=U7700.20:5MM

58 58

B

PPVOUT_BKLT_FB2 PP5V_S0_KBDBKLT_SW 2

XW7720 GND_BKLT_SGND

SM

PLACE_NEAR=U7700.6:5MM

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

1

152S1701 CRITICAL

1

BKLT_SCL

2

C7720

1

C7721

1

A

35 58 68

K

2.2UF

0.1UF

10% 25V X5R-CERM 603

10% 25V X5R-CERM 603

10% 16V X5R-CERM 0201

2

2

RB160M-60G

C7722

2.2UF

1

PLACE_NEAR=L7720.2:5MM 2

PLACEMENT_NOTE:

C7723

1

C7724

1

C7725

1

C7726

1.0UF

1.0UF

0.001UF

1.0UF

10% 50V X7R 0805

10% 50V X7R 0805

10% 50V X7R-CERM 0402

10% 50V X7R 0805

2

2

2

PLACEMENT_NOTE:

1

C7727 1.0UF

2

10% 50V X7R 0805

T-BONE C7726 AND C7727 PLACE_NEAR=D7720.K:9MM

SANDWICH C7720 AND C7721 PLACE_NEAR=L7720.1:5MM

PLACE_NEAR=L7720.1:5MM

58

LCDBKLT_FET_DRV_R

58

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=5V DIDT=TRUE GATE_NODE=TRUE 58

PLACE_NEAR=D7720.K:5MM

LCDBKLT_FET_DRV

LCDBKLT_SW

58

PPVIN_SW_LCDBKLT_SW

58

PPVOUT_S0_LCDBKLT MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=53V

58

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=12.9V

PPVOUT_BKLT_FB

PP5V_S0_KBDBKLT_SW

4

PLACE_NEAR=D7720.K:5MM

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

LCD AND KBD BKLT DRIVER DRAWING NUMBER

58

PPVOUT_S0_KBDBKLT 58 62 68

Apple Inc.

35 58 68

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=40V

PPVOUT_BKLT_FB2 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=40V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=53V

5

58

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=40V DIDT=TRUE SWITCH_NODE=TRUE

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=53V DIDT=TRUE SWITCH_NODE=TRUE

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=12.9V

PPVIN_S0SW_LCDBKLT

PLACE_NEAR=D7720.K:5MM

KBD BKLT LINE WIDTHS

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=53V DIDT=TRUE SWITCH_NODE=TRUE

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=5V DIDT=TRUE GATE_NODE=TRUE

PPVIN_S0SW_LCDBKLT_FET

PLACE_NEAR=D7720.K:9MM

SANDWICH C7723 AND C7724 PLACE_NEAR=L7720.1:5MM

LCD BKLT LINE WIDTHS

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=12.9V

6

PPVOUT_S0_KBDBKLT

SOD-123

2

BKLT_SDA

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=12.9V

58

D7720

10UH-20%-1.4A-0.17OHM

PP5V_S0

PLACE_NEAR=D7720.K:2MM

371S0572 CRITICAL

PST041H-SM

PPVIN_S0SW_LCDBKLT_R

7

2 402

3

1

PPVIN_S0SW_LCDBKLT_F

58

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=5V

8

R7731

PWRPK-1212-8

L7720 53 45 44 41 32 17 16 68 65 61 60 58 54

5% 1/20W MF 0201 PLACE_NEAR=U7700.16:10MM

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=5V

PP5V_S0_BKLT_D

10% 100V X7R-CERM 0603

PLACE_NEAR=D7710.K:5MM PLACE_NEAR=D7710.K:5MM PLACE_NEAR=D7710.K:5MM PLACE_NEAR=D7710.K:5MM PLACE_NEAR=D7710.K:5MM

1

0.1% 1/16W TF 402

PBUS LINE WIDTHS

A

C7717 1000PF

2

R7732

PLACE_NEAR=U7700.15:10MM

R7751 68 66 62

1

10% 100V X7R 1210-1

1 1 2

5% 1/16W MF-LF 402

R7720

6

R7750 68 66 62

2

2

w

2

R7752

BKLT_KEYB1 BKLT_KEYB2

SM

1

PP5V_S0

1

BKLT_ISET_KEYB

13

XW7700

GND_BKLT_SGND

58

60 58 54 53 45 44 41 32 17 16 68 65 61

20

C7716 2.2UF

10% 100V X7R 1210-1

33PF

B 58

23

SMC_SYS_KBDLED

THRM PAD

.c

36

0

24

R7747

LCDBKLT_FB LCDBKLT_FET_DRV

h

58

15

4 58

25

1

3

EDP_BKLT_PSR_EN

22

IN

12

LCDBKLT_SW

1 21

1

2.2UF

fi

9 10

2 58

a

BKLT_SD

62

2

LLP

11

LP8548B1SQ_-04 SD SW VSENSE_N SW FB VSENSE_P GD SENSE_OUT ISET_KEYB EN PWM_KEYB KEYB1 KEYB2 SCL (IPU) SDA (IPU) SW2 FB2 CRITICAL 353S4160

C7715

2

1% 1/16W MF-LF

SI7812DN

0

U7700

5% 1/20W MF 201

1

10% 100V X7R 1210-1

2

PLACEMENT_NOTE:

13.3K

R7733

in

2

C7714 2.2UF

10% 100V X7R 1210-1

SANDWICH C7713 AND C7714 SANDWICH C7715 AND C7716

CRITICAL

1

1M

1

2.2UF

1

4

LCDBKLT_FET_DRV_R

VDDA

VDDD

1

58

C7713

2

PLACE_NEAR=D7710.K:2MM SM

Q7701

GND_BKLT_SGND

58

C

1

2

XW7710

.c

1

x

PLACE_NEAR=U7700.5:5MM

58 62 68

K

5

C7740

PPVOUT_S0_LCDBKLT

POWERDI-123

2 DEM8030C-SM

PP5V_S0

1% 1/16W MF-LF 2 402

371S0704 CRITICAL

C7701

LCDBKLT_EN_L

ISNS_LCDBKLT_N 1

PLACE_NEAR=L7710.2:3MM

2 1

1000PF

77 40

6 5

2 4

0603

77 40

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=12.9V MAKE_BASE=TRUE

m

58

PPVIN_S0SW_LCDBKLT

LCDBKLT_TB_XWR

2

58

o

1

FDC638APZ_SBMS001

1% 1W MTL 0612

F7700 PPBUS_G3H

D

Q7700

0.025

3AMP-32V 65 52 51 40 25 68

CRITICAL

R7700

PPVIN_SW_LCDBKLT_SW

D

SENSOR ON PAGE 54 USES R7700 TO MEASURE THE POWER GOING TO LCD BACKLIGHT

740S0159 CRITICAL

3

R

58

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

2

SIZE

D REVISION

BRANCH

PAGE

77 OF 120 SHEET

58 OF 78

1

A

8

7

6

5

4

2

3

1

1.05V SUS LDO 1.5V S0 Switcher 29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 56

Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active. Pull-ups (3) must be 51 ohms to support XDP (not required in production). 70mA is required to support pull-ups. Alternative is strong voltage dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

PP3V3_S5 CRITICAL

C7870

CRITICAL

L7870

2.2UH-2A-0.155-OHM

61

IN OUT

P1V5S0_EN P1V5S0_PGOOD

353S2535

CRITICAL

LX 8

3 POR

VFB 6

4 SKIP

RSI 5

GND 7

P1V5_S0_SW MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

1

PP1V5_S0

8 47 60 61 63 65 68

U7840

2 2512

Vout = 1.508V

1

R7882

SWITCH_NODE=TRUE DIDT=TRUE

10

CRITICAL 1

10PF

5% 50V C0G-CERM 2 0402

P1V5_S0_FB

1

R7880 100K

1% 1/16W MF-LF 2 402

C7873 22UF

20% 2 6.3V X5R 0603

CRITICAL 1

C7874 22UF

20% 6.3V 2 X5R 0603



1

R7881 113K

1% 1/16W MF-LF 2 402



C

PP1V05_SUS

SON

16 65

4 BIAS

Freq = 1.6MHZ

P1V5_S0_FB_R

C7876 1

TPS720105

PP3V3_SUS

MAX CURRENT = 0.6A

5% 1/16W MF-LF 2 402

THRM_PAD 9

65 61 60 45 14 11 8

m

DFN 61

CRITICAL XDP_CONN

6 IN

OUT 1

3 EN

NC 2

XDP

C7840 1 1UF

GND 5

Vout = 1.05V Max Current = 0.35A NC

XDP

THRM PAD 7

1

C7841 2.2UF

10% 6.3V 2 CERM 402

10% 2 6.3V X5R 402

o

ISL8009B 2 EN

D

152S1051

22UF

20% 2 6.3V X5R 0603

U7870

.c

D

1

1 VIN

C

h

in

a

fi

x

Vout = 0.8V * (1 + Ra / Rb)

B

w

w

w

.c

B

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

Misc Power Supplies DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

78 OF 120 SHEET

59 OF 78

1

A

8 7 1.5V S0 Audio Switch (BYPASSED) 0

1

PP1V5_S0SW_AUDIO_HDA

2

NOSTUFF

A1 B1

61

CRITICAL

C1

1

TPS22924C

Type

Load Switch

R(on) @ 1.8V

19.6 mOhm Typ 21.8 mOhm Max

Current

2A Max

1

PP3V3_SUS

3

EDP: 167mA

NC

4

8 11 14 45 59 61 65

D

NC

U8020 Part

TPS22934

Type

Load Switch

R(on) @ 3.6V

63 mOhm Typ 77 mOhm Max

Current

1A Max

CSP

A1 B1 C1

3.3V SSD Switch

0.002

PP3V3_S4_FET_R VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

1% 1W MF 0612-SHORT 1 2

PP3V3_S4

3

EDP: 2.4A

4

NC

61 58 54 53 45 44 41 32 17 16 68 65

18 29 34 37 38 42 63 64 65 68 29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

NC

61 57 53 37 17 16 15 11 8 6 68 65

PP3V3_S5

1.05V PCH HSIO Switch PP5V_S0

PP1V05_S0

U8000

D1

GND

C8070

1

1

D2 ON

S4_PWR_EN

IN

Part

TPS22920

Type

Load Switch

0.1UF

VDD

10% 6.3V CERM-X5R 0201

2

U8070 SLG5AP1453V

1.0UF

5.5 MOHM TYP 8.8 MOHM MAX

Current

20% 6.3V X5R 0201-1

C8071

4A MAX

IN

TDFN

7 CAP

P3V3S0SW_SSD_FET_RAMP 1 30 15 61

CRITICAL

2 ON

SSD_PWR_EN

4700PF

2

10% 10V X7R 201

D

3

S

5

15

PP3V3_S0SW_SSD_FET VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM

GND 2

NOSTUFF

3.3V S3 Switch

IN

1

2

Type

5% 1/20W MF 0201

OMIT

R8011

U8010 TPS22924

PP3V3_S5

PP3V3_S3_FET_R

CSP A2 B2

VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

A1

VOUT

VIN

B1

PP3V3_S3

3

EDP: 1.02A

4

NC

P3V3S3_EN

C2

ON

NC

U8010

GND

C8010

C1

IN

1

TPS22924C

Part

1.0UF Type

Load Switch

R(on) @ 2.5V

18.5 mOhm Typ 25.8 mOhm Max

Current

2A Max

41 65

A1

VIN

VOUT

EDP: 1A

B1

U8030

CRITICAL P3V3S0_EN

C2

ON C1

GND 1

Part

TPS22924C

Type

Load Switch

R(on) @ 2.5V

18.5 mOhm Typ 25.8 mOhm Max

Current

2A Max

w

B2

2

w

1.0UF 20% 6.3V X5R 0201-1

Current

5.3A Max

WCSP A2 VIN

66 65 63 62 57 56 55 46 33 32 68

9.8 mOhm Typ TBD mOhm Max

Current

6A Max

1

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm

1

0

1

5% 1/16W MF-LF 402

CRITICAL

2

C8080 0.1UF

2

U8080

R8050 PP3V3_S4SW_SNS_FET_R

10% 16V X5R-CERM 0201

SLG5AP1443V PP3V3_S4SW_SNS

40 41 42 65

P5VS0_FET_RAMP

7

CAP

2

ON

EDP: 50mA

C8081

1

61

IN

P5VS0_EN

4700PF GND

C8050

Load Switch

R(on) @ 4V Vgs

PP5V_S4

10% 10V X7R 201

U8050

TDFN

CRITICAL

D

3

S

5

SYNC_MASTER=J44

Power FETs

41 65

EDP: 1.1A

GND 2

SYNC_DATE=08/12/2013

PAGE TITLE

PP5V_S0_FET

DRAWING NUMBER

U8080

8

B2 ON

SMC_SENSOR_PWR_EN

VOUT A1

B1

IN

SLG5AP1417V

Type

5V S0 Switch 1

U8050 TPS22934

PP3V3_S5

8 13 17 27 59 65

40 38 36

Part

REMOVED THE ANALOG POWER GATE AS SLG5AP1471 SHOULD BE AVAILABLE BY THEN

VDD

A

U8005

10% 10V X5R 2 402

B

3.3V Sensor Switch 77 61 56 26 16 11 15 18 29 60 68

1UF

w

PP3V3_S0_FET

CSP A2

C8030

C8005 1

Sense R on sensor page

U8030 TPS22924

PP3V3_S5

IN

7.8 mOhm Typ 8.5 mOhm Max

Part

TPS22934

Part

SLG5AP1443V

Type

Load Switch

Type

Load Switch

Apple Inc. R

8

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

2

R(on) @ 3.6V

63 mOhm Typ 77 mOhm Max

R(on)

Current

1A Max

Current

7

6

5

4

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

15 mOhm Typ 17 mOhm Max 2.5A

3

2

SIZE

D REVISION

1.0UF 20% 6.3V X5R 0201-1

C

8 11 65

EDP: 1.84A

.c

3.3V S0 Switch

61 60

PP1V05_S0SW_PCH_HSIO

2

B

65 61 60 27 26 18 13 11 8 17 16 15 59 56 29 77 68

5 7

Load Switch

h

20% 6.3V X5R 0201-1

S

GND

EDP: 5A Sense R on sensor page

R(on) @ 25C

15 18 19 39 42 65 68

CRITICAL 61

S

in

77 59 56 29 27 15 13 11 8 26 18 17 16 68 65 61 60

1% 1W MF 0612-SHORT 1 2

CRITICAL

2 3

a

0.002

9 ON

PCH_HSIO_PWR_EN

D

SLG5AP1453V

Part

0

P3V3S0_EN

IN

41 65

U8070

R8070 61 60

TDFN

x

R(on) @ 3.6V

1

SLG5AP1471V D

fi

C8000

8

C

VDD

U8005

8

CRITICAL 61 27 26 18

.c

1

VOUT

2

OMIT

U8000

VIN

20% 6.3V X5R 0201-1

R8000

TPS22920 A2 B2 C2

C8020

Part

1% 1W MF 0612-SHORT 1 2

1.0UF

2

PP3V3_S5

VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

GND

3.3V S4 Switch 77 59 56 29 27 15 13 11 8 26 18 17 16 68 65 61 60

B2 ON

P3V3SUS_EN

U8040

1.0UF 20% 6.3V X5R 0201-1

IN

PP3V3_SUS_FET_R

VOUT A1

CRITICAL

GND

NOSTUFF

C8040

WCSP A2 VIN

EDP: 0.5A

C2 ON

P1V5S0SW_AUDIO_EN

IN

TPS22934

PP3V3_S5

29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

CSP NOSTUFF VIN VOUT

A2 B2

2

0.002

U8020

U8040

TPS22924

D 61

OMIT

R8020

o

5% 1/20W MF 201

3.3V SUS Switch

1

10K

1

8 11 17 60

8 11 17 60

B1

R8040

2

3

Loading specs per J41/43_PowerBudget_Riviera_rev0.99e

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE

5% 1/20W MF 0201

4

m

PP1V5_S0

5

PP1V5_S0SW_AUDIO_HDA

R8042 68 59 47 8 65 63 61

6

PAGE

80 OF 120 SHEET

60 OF 78

1

A

8

7

6

5

4

2

3

S5 Enables

S3 Enables

PLACE_NEAR=U7501.21:7mm 56 37 36 61

OUT

SMC_PM_G2_EN

56 37 36 61

IN

SMC_PM_G2_EN

63 61 36 29 18 13

R8140 100

1

MAKE_BASE=TRUE

29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

2 61 56

S5_PWR_EN

S5_PWR_EN

OUT

MAKE_BASE=TRUE

5% 1/20W MF 201

C8170

1

0.1UF 10% 6.3V CERM-X5R 0201

0.47UF 10% 6.3V CERM-X5R 402

D

1

Standby Enables

NOSTUFF

C8142

1

PM_SLP_S4_L

IN

PP3V3_S5

56 61

NOSTUFF

2

2

S5 Power Good

IN

PM_SLP_S5_L

2

IN

SMC_S4_WAKESRC_EN

1

74LVC1G32

S4_PWR_EN

OUT

18 26 27 60 61

S4_PWR_EN

OUT

18 26 27 60 61

SOT891

S4_PWR_EN

S4_PWR_EN

OUT

18 26 27 60 61

1

2

0 2

SMC-->PM_DSW_PWRGD

OUT

MAKE_BASE=TRUE

2

5% 1/20W MF 201

USB_PWR_EN

USB_PWR_EN

0

1

P5VS4RS3_EN_RC

2

5% 1/20W MF 0201

15 30 60 61

A

NO STUFF

1

D8175

2

R8175

SM-201

0

RB521ZS-30

5% 1/20W MF 0201

K

NO STUFF

2

R8176

C8114 10% 6.3V CERM-X5R 402 PLACE_NEAR=U4600.4:6mm

PLACE_NEAR=U7501.4:15mm

240

P5VS4RS3_EN_D

1

2

5V needs to be held up so 1.05V can fall after 1.5V

60 61

DDRREG_EN

DDRREG_EN

OUT

55 61

D

NO STUFF

0.47UF

20% 10V CERM 402

10% 6.3V CERM-X5R 402

2

1

C8113 0.47UF

2

PLACE_NEAR=U8010.C2:6mm

10% 6.3V CERM-X5R 402 PLACE_NEAR=U4801.4:6mm

Mobile System Power State Table

0.47UF

PLACE_NEAR=U7501.4:15mm

o

OUT

MAKE_BASE=TRUE

1

.c

PM_SLP_S4_L

63 61 36 29 18 13

IN

NO STUFF

R8179

SSD_PWR_EN

34

OUT

33 61

OUT

MAKE_BASE=TRUE

SSD_PWR_EN

OUT

P3V3S3_EN

R8117

PLACE_NEAR=U4600.4:6mm

61 33

61 60 30 15

P3V3S3_EN

100

36 56 61

SSD Enable

PLACE_NEAR=U4801.4:6mm

C8112

1

0.1UF

PLACE_NEAR=U7400.16:6mm

1

5% 1/20W MF 0201

S5_PWRGD-->SMC

C8111

m

1

100K

S5_PWRGD

PLACE_NEAR=U8010.C2:6mm

5% 1/20W MF 201

MAKE_BASE=TRUE

R8115

1

2

2

NO STUFF

3

NC

S5_PWRGD

3.3K

61 55

MAKE_BASE=TRUE NC

PLACE_NEAR=U7501.20:7mm

61 56 36

2

R8113

TPAD_VBUS_EN

5

5% 1/20W MF 201

5% 1/20W MF 0201

MAKE_BASE=TRUE

PP3V42_G3H

R8141

0

5% 1/20W MF 201

61 60

U8170 4

37 36

1

R8112

20K

NOSTUFF 6

36 13

1

R8111

PLACE_NEAR=U7400.16:6mm

2

BYPASS=U8170.6:2.3mm

PLACE_NEAR=U7501.21:7mm

61 52 51 45 34 33 30 17 39 38 37 36 68 65

1

P5VS4RS3_EN

5% 1/20W MF 201

56

OUT

NO STUFF 1

PLACE_NEAR=U7501.4:15mm

C

C8175

State

SMC_ADAPTER_EN

SMC_PM_G2_ENABLE

SMC_S4_WAKESRC_EN

PM_SUS_EN

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

Run (S0)

X

1

1

1

1

1

1

Sleep (S3AC)

1

1

1

1

1

1

0

Sleep (S3)

0

1

1

1

1

1

0

Deep Sleep (S4AC)

1

1

1

0

0

0

0

Deep Sleep (S4)

0

1

1

0

0

0

0

Deep Sleep (S5AC)

1

1

0

0

0

0

0

Deep Sleep (S5)

0

1

0

0

0

0

0

Battery Off (G3HotAC)

toggle 3Hz

0

0

0

0

0

0

Battery Off (G3Hot)

1

0

0

0

0

0

0

C

10% 6.3V X5R 402

29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

x

2.2UF 2

PP3V3_S5

PLACE_NEAR=U7501.4:15mm

BYPASS=U8180.6:3mm

C8180

R8178

S0 Rail PGOOD (BJT Version) 68 63 36 18 17 13

PP5V_S0

R8156

54.9K

1K 1

2

S0PGD_C 1

1UF

1% 1/20W MF 201

10% 10V X5R 402

2

PLACE_NEAR=U8040.C2:7mm

PP3V3_S0

Q1

R8154

5

AUD_PWR_EN

IN

ASMCC0179

NOSTUFF

DFN2015H4-8

D8146 K

A

P1V5CODEC_EN_D

NC

2 1

Q4

3

1% 1/20W MF 201

S0 Enables

PM_SLP_S3_BUF_L

3

NO STUFF

A

1

D8185

R8180 330K 5% 1/20W MF 201

1

R8184

R8186

1

330

39K

0

RB521ZS-30

5% 1/20W MF 0201

5% 1/20W MF 201

5% 1/20W MF 201

5% 1/20W MF 0201

NO STUFF

R8138

2

2

PLACE_NEAR=U7600.16:6mm

P3V3S0_EN_D

820

P1V05_EN_D

D8184

PLACE_NEAR=U8030.C2:6mm

1

SM-201

K

2

2

PLACE_NEAR=U8030.C2:6mm

A

PLACE_NEAR=U7870.2:6mm

P1V5S0_EN_D

61 60

P3V3S0_EN

OUT

59 61

OUT

60 61

P3V3S0_EN

OUT

60 61

P1V05S0_EN OUT

57 61

PLACE_NEAR=U7870.2:6mm

MAKE_BASE=TRUE

PLACE_NEAR=U7600.16:6mm

60

1

NOSTUFF

1

C8185

2

0.1UF 10% 25V X5R 402

1

0.1UF

0.22UF

C8146

C8186

10% 10V CERM 402

2

20% 10V CERM 402

PLACE_NEAR=U8030.C2:6mm

P1V05S0_EN MAKE_BASE=TRUE

NO STUFF

NO STUFF

2

2

P1V5S0_EN P5VS0_EN

MAKE_BASE=TRUE

61 57

1

P1V5S0_EN

PLACE_NEAR=U8030.C2:6mm

1K

1% 1/20W MF 201

A

RB521ZS-30

MAKE_BASE=TRUE

RB521ZS-30

5% 1/20W MF 201

PLACE_NEAR=U7870.2:6mm

SM-201

K

61 59

P5VS0_EN

2 5% 1/20W MF 201

2

D8183

PLACE_NEAR=U8080.2:6mm

61 60

26 27 46 61

R8188 68K

5% 1/20W MF 2 201

R8187

0

PLACE_NEAR=U7600.16:6mm

K

1

R8185

SM-201

NOSTUFF 1

1

R8183 330

MAKE_BASE=TRUE

NOSTUFF 1

2

OUT

PM_SLP_S3_BUF_L OUT 1

R8146

PLACE_NEAR=U8040.C2:7mm

3.3V Divider: 1.07V

C8187

1

0.68UF 2

C8188 0.1UF

10% 6.3V CERM 402

2

20% 10V CERM 402

B

PLACE_NEAR=U7870.2:6mm

PLACE_NEAR=U8080.2:6mm

PLACE_NEAR=U7600.16:6mm

3.3V SUS Detect

PLACE_NEAR=U8040.C2:7mm

29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

PP3V3_S5

S0PGD_BJT_GND_R

VMON_Q4_BASE

5% 1/20W MF 201

Vbe 0.7V max @ 2mA Vce(sat) 0.1V max @ 1mA Q1 Vth 0.7~1V @Id 250uA

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

PP3V3_S0 56

PP1V05_S0

S0PGOOD_ISL

C8160

1

P1V5S0_PGOOD

w

IN

(ISL version used for development)

PP1V5_S0

IN

100

10% 6.3V CERM-X5R 0201

5V Divider: 3.19V @ 4.5Vmin 2

R8160

R8170

R8172

6.04K

15K

6.04K

1% 1/20W MF 201

1% 1/20W MF 201

1% 1/20W MF 201

2

2

S0PGOOD_ISL 1

0.723V @ 1.02Vmin

2

R8161

S0PGOOD_ISL 1

R8171

U8160 55

1

5 6

V2MON CRITICAL V3MON V4MON

(IPU)

MR*

RST*

1

8

15K

1% 1/20W MF 201

1% 1/20W MF 201

2

GND

R8173

15K

1% 1/20W MF 201

RESET*

6

R8131 1 330K

PM_RSMRST_L

OUT

QFN

CT

GND

C8131

MR*

4

5% 1/20W MF 201

13 72

VFRQ Low: Fix Frequency

TP_SUS_PGOOD_MR_L

1

S0PGOOD_ISL

NC

R8162

CHGR_VFRQ

Q8131

ALL_SYS_PWRGD_R

1

2

S

2

OUT

52

SYM_VER_2

61

100

G

PM_SLP_S3_R_L

R8164 100

SUS Enables

2

5% 1/20W MF 201

61 40 13

IN

PM_SLP_SUS_L

PM_SLP_SUS_L

MAKE_BASE=TRUE 1

2

ALL_SYS_PWRGD

OUT

13 40 61

SYNC_MASTER=J44

Power Control

OUT

5% 1/20W MF 0201

P3V3SUS_EN

61 60

16 17 36 61

DRAWING NUMBER

P3V3SUS_EN

MAKE_BASE=TRUE

NO STUFF 1

5

4

SYNC_DATE=08/12/2013

PAGE TITLE

R8190 0

5% 1/20W MF 201

2

6

3

DFN1006H4-3

5% 1/20W MF 201

THRM_PAD

D

DMN32D2LFB4

10% 16V X7R-CERM 0201

2

330

2

VFRQ High: Variable Frequency

THRM PAD

Apple Inc. OUT

60 61

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

10% 25V X5R 402

3

REVISION

R

NOTICE OF PROPRIETARY PROPERTY:

C8190 0.1UF

7

PP3V42_G3H

2

1

DDRREG_PGOOD

353S2310

TDFN 3

IN

2

U8130

51 45 39 38 37 36 34 33 30 17 68 65 61 52

100

R8168

ISL88042IRTEZ

SENSE

5% 1/20W MF 201

1000PF 2

P1V05S0_PGOOD

S0PGOOD_ISL 1

15K

2

IN

100K

2

1

S0PGOOD_ISL

4

0.718V @ 1.45Vmin

1

5% 1/20W MF 201

57

3

NO STUFF

2

1

2

2

SUS_PGOOD_CT

R8165

VDD

P5V_DIV_VMON P1V5_DIV_VMON P1V05_DIV_VMON

1.5V Divider:

7

S0PGOOD_ISL 1

2

S0PGOOD_ISL 1

PP3V3_SUS

CHGR VFRQ Generation

8 11 14 45 59 60 61 65

R8133

TPS3808G33

5% 1/20W MF 201

P5VS4RS3_PGOOD

9

S0PGOOD_ISL 1

2

65 61 60 59 45 14 11 8

5% 1/20W MF 201

1

VDD

R8167 10K

0.1UF

PP5V_S0

8

CRITICAL 1

S0 Rail PGOOD Circuitry

60 57 53 37 17 16 15 11 8 6 68 65

1.05V Divider:

PM_SLP_S3_BUF_L

61 46 27 26

2

R8169

Thresholds: VDD: 2.734V-3.010V V2MON: 2.815V-3.099V V3MON: 0.572V-0.630V V4MON: 0.572V-0.630V

10% 6.3V CERM-X5R 0201

7

5% 1/20W MF 201

PP3V3_SUS

1

0.1UF 1

PP1V5_S0

68 65 63 61 60 59 47 8

2

C8130

U8130 Sense input threhold is 3.07V

w

1K 1

1

100

BYPASS=U8130.6:2.3mm

No stuff C8131, 12ms Min delay time

w

R8157

R8155

A

P1V5S0SW_AUDIO_EN

2 1% 1/20W MF 201

SM-201

R8159

68 65 63 61 60 59 47 8 68 60 58 45 44 17 16 41 32 54 53 65 61

1

376S0854

Q3

7.15K

2

100K

RB521ZS-30

5% 1/20W MF 201

1% 1/20W MF 201

13

8 7

VMON_Q3_BASE

2

Q2

Q8150

VMON_3V3_DIV 1

U8180

4 46 27 61 26

5

2

NC

1K

1

R8158 15K

B

NOSTUFF

R8145

CRITICAL

VMON_Q2_BASE

2

1.5V Codec Enable(BYPASSED NOW)

9ms RC delay

62 64 65 68 77 37 38 39 40 41 8 11 12 13 15 17 18 24 28 30 42 43 44 46 47 50 61

16 17 36 61

10% 6.3V CERM-X5R 0201

SC70-HF

2

h

C8159

5% 1/20W MF 201

6

R8152

ALL_SYS_PWRGD

0.1UF

MC74VHC1G08

1

in

1% 1/20W MF 201 2

R8153

15K

1

5% 1/20W MF 201

1

5.0V Divider: 1.07V

2

PM_SLP_S3_R_L

150K

1% 1/20W MF 201

VMON_5V_DIV 1

2 61

.c

2

1

PP3V3_S5

R8151

4

1

5

100

PM_SLP_S3_L

IN

a

61 65 68 16 17 32 41 44 45 53 54 58 60 29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

fi

1

2

BRANCH

PAGE

81 OF 120 SHEET

61 OF 78

1

SIZE

D

A

8

7

6

5

4

2

3

1

LCD PANEL INTERFACE (eDP) NEEDS FINAL CHECK AGAINST UPDATE FOR NEW PANEL PP3V3_S0

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

C8330 1 0.1UF

LCD_PSR_EN

15

5 6

EDP_PANEL_PWR

13

SOT833 A Y B

1 2

EDP_BKLT_PSR_EN

7

74LVC2G32GT A B

3

Y

EDP_PANEL_PWR_OR_PSR_EN

4

0 2

R8331 1

2

R83101

R83091

5% 1/16W MF-LF 402 2

5% 1/16W MF-LF 402 2

100K

1/20W

1

R83401

62 68

OUT

68

BI

EDP_PANEL_PWR_OR_PSR_EN DP_INT_AUXCH_C_P

C8328

BI

DP_INT_AUXCH_C_N

C8329

68 62

1 1

0.1UF DP_INT_ML_C_P<0>

C8320

1

74 5

IN

DP_INT_ML_C_N<0>

C8321

74 5

IN

DP_INT_ML_C_P<1>

C8322

1

0.1UF 1

0.1UF 74 5

IN

DP_INT_ML_C_N<1>

C8323

1

0.1UF 74 5

IN

DP_INT_ML_C_P<2>

C8324

1

0.1UF

PP5V_S4 74 5

IN

DP_INT_ML_C_N<2>

C8325

1

0.1UF IN

DP_INT_ML_C_P<3>

C8326

1

0.1UF 74 5

IN

DP_INT_ML_C_N<3>

C8327

1

0.1UF

U8300

ON

CRITICAL

5% 1/20W MF 201

5

PP5VR3V3_SW_LCD_ISNS MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

GND

C8310 1

10% 6.3V 2 CERM 402

10% 10V 2 X7R 201

4700PF

1

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=5V

C8311 0.1UF

10% 2 16V X7R-CERM 0402

1

C8312 10UF

20% 2 6.3V X5R 603

Load Switch

R(on)

15 mOhm Typ 17 mOhm Max

Current

2 16V 0201 10% X5R-CERM 2 16V 0201 10% X5R-CERM 2 16V 0201 10% X5R-CERM

0 1 W MF 0612-SHORT

1 3

OMIT Short Rsense

2 4

w

Type

2 16V 0201 10% X5R-CERM

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

PP3V3_S0

2.5A 1

R8303 1M

DP_INT_AUX_P DP_INT_AUX_N

DP_INT_ML_P<0>

74 68 62

DP_INT_ML_N<0>

74 68 62

DP_INT_ML_P<1>

74 68 62

DP_INT_ML_N<1>

74 68 62

DP_INT_ML_P<2>

74 68 62

DP_INT_ML_N<2>

74 68 62

DP_INT_ML_P<3>

74 68 62

DP_INT_ML_N<3>

L8300

PP5VR3V3_SW_LCD_UF

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

10% 16V X5R-CERM 2 0201

OUT

42 77

OUT

42 77

74 68 62

DP_INT_AUX_N

74 68 62

DP_INT_AUX_P

2

68

PP5VR3V3_SW_LCD

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

0805

C8301 1 0.1UF

1

1

R8301

5% 1/20W MF 2 201

0.1UF

10% 16V X5R-CERM 2 0201

C8300 1

1000PF

1000PF

10% 100V X7R-CERM 2 0603

DP_INT_ML_P<0>

1

1M

C8358 9.1PF

+/-0.1PF 25V 2 COH 0201

EDP_LS_CAP

1

C8359 9.1PF

+/-0.1PF 25V 2 COH 0201

D

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

C

74 68 62

10% 100V X7R-CERM 2 0603

NO_XNET_CONNECTION=TRUE

R8312

DP_INT_ML_N<0>

DP_INT_ML_P<1>

1M

1

2

5% 1/20W MF 201 74 68 62

NO_XNET_CONNECTION=TRUE

R8314

DP_INT_ML_N<1>

1

DP_INT_ML_P<2>

1

1M

R8302 1M

5% 1/20W MF 2 201

74 68 62

74 68 62

NO_XNET_CONNECTION=TRUE

DP_INT_ML_N<2>

DP_INT_ML_P<3>

R8316 1

1

1M

DP_INT_ML_N<3> NO_XNET_CONNECTION=TRUE

5

4

1M

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

eDP Display Connector

2

5% 1/20W MF 201

DRAWING NUMBER

Apple Inc. NOTICE OF PROPRIETARY PROPERTY:

TRUE

R8318 1

1M

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

2

5% 1/20W MF 201

3

2

SIZE

D REVISION

R

2

5% 1/20W MF 201 74 68 62

2

2

5% 1/20W MF 201

1

1M

5% 1/20W MF 201

NO_XNET_CONNECTION=TRUE

74 68 62

2

5% 1/20W MF 201

R8313 74 68 62

1M

1

NO_XNET_CONNECTION=TRUE

5% 1/20W MF 2 201

6

B

518S0829

2

5% 1/20W MF 201

R8317

7

+/-0.1PF 25V 2 COH 0201

EDP_LS_CAP

1

32

C8303 1

NO_XNET_CONNECTION=TRUE

8

9.1PF

C8302 1

R8315 1M

C8357

R8311

NO_XNET_CONNECTION=TRUE

A

1

33 34 35 36 37 38 39 40 41

CRITICAL

74 68 62

w

LCD Panel HPD & AUX strapping LCD_HPD_CONN

NC

FERR-220-OHM

NO_XNET_CONNECTION=TRUE

68 62

+/-0.1PF 25V 2 COH 0201

EDP_LS_CAP

NO_XNET_CONNECTION=TRUE

w

SLG5AP1443V

2 16V 0201 10% X5R-CERM

ISNS_LCDPANEL_N ISNS_LCDPANEL_P

U8300 Part

2 16V 0201 10% X5R-CERM

.c

C8319 1 1UF

S

74 68 62

2 16V 0201 10% X5R-CERM

0

EDP: 1 A

8

B

2 16V 0201 10% X5R-CERM

R8320

SLG5AP1443V 2

74 68 62

h

1

74 5

10% 16V X7R-CERM 2 0402

VDD

2 EDP_PANEL_PWR_EN_RC

9.1PF

1

0.1UF

1K

74 68 62

in

C8309

I2C_BKLT_SCL 66 58 I2C_BKLT_SDA 66 58 LCD_IRQ_L 68 15 SMBUS_SMC_0_S0_SCL 39 36 76 SMBUS_SMC_0_S0_SDA 39 36 76 EDP_BKLT_PWM 68 13 68 62 LCD_HPD_CONN

x

IN

0.1UF

EDP_PANEL_PWR_OR_PSR_EN 1

PPVOUT_S0_LCDBKLT

fi

74 5

2 0201 10% 16V X5R-CERM 2 0201 10% 16V X5R-CERM

a

C

68 62

C8356

F-RT-SM

68

74 5

R8319

+/-0.1PF 25V 2 COH 0201

EDP_LS_CAP

1

J8300

0.1UF

3

9.1PF

BYPASS=U8340.5:3MM

DP_INT_HPD

74 5

D

+/-0.1PF 25V 2 COH 0201

C8355

CRITICAL

0201

TDFN

+/-0.1PF COH 25V 2 0201

EDP_LS_CAP

1

20525-130E-01

LCD_HPD_CONN IS A 2.5V SIGNAL NEEDS TO BE LEVEL SHIFTED TO 3.3V

0201

CAP

9.1PF

31

PANEL USES EDP_PANEL_PWR_PSR_EN TO DISCHARGE THE LCD BEFORE POWER GOES AWAY

7

C8354

1

9.1PF

C 6

68

PP5V_S0_LCD_FETCAP

C8353

GND 2

68

MF

1

100K

13

63 60 57 56 55 46 33 32 68 66 65

+/-0.1PF 25V 2 COH 0201

68 58

MF

1/20W

9.1PF

+/-0.1PF COH 25V 2 0201

NO STUFF 5%

C8352

B 1

C8340

10% 16V 2 X5R-CERM 0201

5% 1/16W MF-LF 402 2

1

9.1PF

A 3

0.1UF

100K

NO STUFF 5%

0

58

Y = B

GND

R8330 1

SOT891 5 VCC 4 Y

EDP_LS_CAP

EDP_LS_CAP EDP_LS_CAP

C8351

o

EDP_BKLT_EN

13

+/-0.1PF COH 25V 2 0201

EDP_LS_CAP

1

m

U8330

9.1PF

U8340 74AUP1T97

NOSTUFF

C8350

1

CRITICAL

.c

8 VCC

D

EDP_LS_CAP

10% 6.3V CERM-X5R 2 0201 BYPASS=U8330.8:3MM

BRANCH

PAGE

83 OF 120 SHEET

62 OF 78

1

A

8

7

6

5

4

2

3

1

RIO Power Connector PLACE_NEAR=J9510.1:2.54MM

518S0882

C9533 1 2

PCIE_AP_R2D_C_P

0.1UF

IN

J9500

14 68 70

10% 16V X7R-CERM 0402 70 68 63

OUT

PCIE_AP_R2D_P

70 68 63

OUT

PCIE_AP_R2D_N

504050-0491 M-RT-SM 5

1 10%

2 0.1UF 16V

PCIE_AP_R2D_C_N

1 IN

14 68 70

2

C9532 X7R-CERM

D

65 64 60 42 38 37 34 29 18 68 65 62 60 57 56 55 46 33 32 68 66

0402

PP3V3_S4 PP5V_S4

D

3 4

PLACE_NEAR=J9510.3:2.54MM PLACE_NEAR=J9500.2:2.5MM

1

C9591

1

0.1UF

70 68 63 14

IN

70 68 63 14

IN

PCIE_AP_D2R_P PCIE_AP_D2R_N

OUT OUT

6

C9592 0.1UF

10% 2 16V X5R-CERM 0201

10% 2 16V X5R-CERM 0201

CRITICAL

PLACE_NEAR=J9500.1:2.5MM

L9501 90-OHM-50MA TCM0605-1 OUT

PCIE_CLK100M_AP_CONN_P

1

4

PCIE_CLK100M_AP_P

IN

12 68 70

70 63

OUT

PCIE_CLK100M_AP_CONN_N

2

3

PCIE_CLK100M_AP_N

IN

12 68 70

m

SYM_VER-1

70 63

64 63

IN

HDMI_HPD 1

R9530 300K

PLACE_NEAR=J9510.42:2.54MM

.c

o

5% 1/20W MF 2 201

C

PP1V5_S0

PP1V5_S0

C

PLACE_NEAR=J9510.39:2.54MM

1

x

RIO FLEX CONNECTOR

68 65 63 61 60 59 47 8

C9593 0.1UF

fi

10% 2 16V X5R-CERM 0201

J9510

DF40BG-70DP-0.4V

a

M-ST-SM

516S1059

CRITICAL

OUT

74 68 64 63

OUT

74 68 64 63

OUT

63 63

=HDMI_DATA_C_N<0> =HDMI_DATA_C_P<0>

=HDMI_DATA_C_N<2> =HDMI_DATA_C_P<2>

OUT

BI

71 63 29

BI

71 68 14

OUT

71 68 14

OUT

GND_VOID=TRUE

HDMI_IG_DATA_C_N<1>GND_VOID=TRUE HDMI_IG_DATA_C_P<1>GND_VOID=TRUE

OUT

71 63 29

GND_VOID=TRUE

GND_VOID=TRUE GND_VOID=TRUE

USB_BT_CONN_P USB_BT_CONN_N USB3_EXTB_R2D_C_P USB3_EXTB_R2D_C_N

GND_VOID=TRUE GND_VOID=TRUE

(USB3_EXTB_R2D caps on RIO) 64 63

71 68 14

IN

71 68 14

IN

71 14 71 14

70 68 63 14

IN

GND_VOID=TRUE GND_VOID=TRUE

USB_EXTB_N USB_EXTB_P

BI

IN

70 63

USB3_EXTB_D2R_P USB3_EXTB_D2R_N

BI

70 68 63 14

70 63

HDMI_HPD

IN

PCIE_AP_D2R_N PCIE_AP_D2R_P

GND_VOID=TRUE GND_VOID=TRUE

PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N

OUT OUT

A

70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2

71

72

PM_SLP_S3_L PM_SLP_S4_L XDP_USB_EXTB_OC_L AP_RESET_L SD_RESET_L

OUT OUT IN

SMBUS_PCH_CLK SMBUS_PCH_DATA SMC_WIFI_PWR_EN HDMI_IG_DDC_CLK HDMI_IG_DDC_DATA

GND_VOID=TRUE

15

14 16 19 39 63 68 72 14 16 19 39 63 68 72

OUT

36 38

OUT

63 64

BI

63

OUT

63

OUT

74 68 64 63

OUT

74 68 64 63

OUT

63

OUT

63

OUT

74 68 64 63

OUT

74 68 64 63

OUT

63 64

8 47 59 60 61 63 65 68

AP_PCIE_WAKE_L AP_CLKREQ_L

GND_VOID=TRUE

15

BI

SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA WIFI_EVENT_L SD_PWR_EN SDCONN_STATE_CHANGE_RIO

GND_VOID=TRUE GND_VOID=TRUE

13 18 29 36 61

OUT

OUT

PP1V5_S0

13 17 18 36 61 68

14 16

OUT

OUT

USB3RPCIE_SD_D2R_P USB3RPCIE_SD_D2R_N

BI

OUT

OUT

IN

36 39 43 63 76 36 39 43 63 76

15

71 63 29

BI

18 63

71 63 29

BI

1 TP 1 TP 1 TP 1 TP

BEAD-PROBE BEAD-PROBE BEAD-PROBE BEAD-PROBE BEAD-PROBE BEAD-PROBE BEAD-PROBE BEAD-PROBE

SM SM SM SM SM SM SM SM

MAKE BASE

=HDMI_DATA_C_P<2> =HDMI_DATA_C_N<2>

TRUE TRUE

HDMI_IG_DATA_C_P<2> HDMI_IG_DATA_C_N<2>

IN

64 68 74

IN

64 68 74

HDMI_IG_DATA_C_P<1> HDMI_IG_DATA_C_N<1>

TRUE TRUE

HDMI_IG_DATA_C_P<1> HDMI_IG_DATA_C_N<1>

IN

63 64 68 74

IN

63 64 68 74

=HDMI_DATA_C_P<0> =HDMI_DATA_C_N<0>

TRUE TRUE

HDMI_IG_DATA_C_P<0> HDMI_IG_DATA_C_N<0>

IN

64 68 74

IN

64 68 74

HDMI_IG_CLK_C_P HDMI_IG_CLK_C_N

TRUE TRUE

HDMI_IG_CLK_C_P HDMI_IG_CLK_C_N

IN

63 64 68 74

IN

63 64 68 74

USB_BT_CONN_P USB_BT_CONN_N

TRUE TRUE

USB_BT_CONN_P USB_BT_CONN_N

BI

TRUE TRUE

PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N

IN

63 70

IN

29 63 72

IN

12

IN

14 63 68 71

IN

14 63 68 71

BI

B

29 63 71 29 63 71

70 63

OUT

70 63

OUT

PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N

IN

63 70

72 68 63 39 19 16 14

OUT

SMBUS_PCH_CLK

SMBUS_PCH_CLK

IN

14 16 19 39 63 68 72

SMBUS_PCH_DATA

SMBUS_PCH_DATA

BI

MAKE BASE FOR I2C IS ON I2C PAGE

USB3RPCIE_SD_R2D_C_P OUT USB3RPCIE_SD_R2D_C_N OUT

72 68 63 39 19 16 14

14 63 71

BI

TRUE TRUE

64 63

OUT

64 63

BI

HDMI_IG_DDC_CLK HDMI_IG_DDC_DATA

76 63 43 39 36

OUT

SMBUS_SMC_3_SCL

SMBUS_SMC_3_SCL

IN

76 63 43 39 36

BI

SMBUS_SMC_3_SDA

SMBUS_SMC_3_SDA

BI

63 18

IN

SDCONN_STATE_CHANGE_RIO

TRUE

SDCONN_STATE_CHANGE_RIO

USB3RPCIE_SD_D2R_P USB3RPCIE_SD_D2R_N

TRUE TRUE

USB3RPCIE_SD_D2R_P USB3RPCIE_SD_D2R_N

OUT

USB3RPCIE_SD_R2D_C_P USB3RPCIE_SD_R2D_C_N

TRUE TRUE

USB3RPCIE_SD_R2D_C_P USB3RPCIE_SD_R2D_C_N

IN

AP_PCIE_WAKE_L

TRUE

AP_PCIE_WAKE_L

14 63 71

HDMI_IG_DDC_CLK HDMI_IG_DDC_DATA

IN BI

14 16 19 39 63 68 72

63 64 63 64

36 39 43 63 76

MAKE BASE FOR I2C IS ON I2C PAGE GND_VOID=TRUE GND_VOID=TRUE

PCIE_AP_R2D_N PCIE_AP_R2D_P

OUT

63 68 70

OUT

63 68 70

71 68 63 14

IN

71 68 63 14

IN

NOTE: This connector is shielded 70P Hirose Plug APN 516S1059, mates with APN 516S1058. 72 63 29

7

1 TP 1 TP

BP9500 BP9501 BP9502 BP9503 BP9504 BP9505 BP9506 BP9507

36

71 63 14

8

1 TP 1 TP

in

OUT

63

69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

h

63

HDMI_IG_CLK_C_N HDMI_IG_CLK_C_P

.c

OUT

w

OUT

74 68 64 63

w

B

74 68 64 63

74

w

73

6

5

OUT

4

36 39 43 63 76

OUT

18 63

OUT

14 63 68 71

OUT

14 63 68 71

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

RIO Connector DRAWING NUMBER

IN

14 63 71

IN

14 63 71

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: OUT

3

BRANCH



29 63 72

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

2

SIZE

D REVISION

PAGE

95 OF 120 SHEET

63 OF 78

1

A

8

7

6

5

4

2

3

1

DISPLAY MUX: DP OR HDMI

PP3V3_S0

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

1

0.1UF

DP 1:2 ANALOG DEMUX

74 23

BI

74 23

BI

TOWARDS PORTS

C

OUT

74 68 63

OUT

74 68 63

OUT

74 68 63

OUT

74 68 63

OUT

74 68 63

OUT

74 68 63

OUT

74 68 63

OUT

A9 H9 J9

64 28

OUT

64 28

BI

H8

DP_TBTSNK1_DDC_CLK DP_TBTSNK1_DDC_DATA

J8

B8 B9

DB0(P) DB0(N)

HDMI_IG_DATA_C_P<1> HDMI_IG_DATA_C_N<1>

D8

HDMI_IG_DATA_C_P<0> HDMI_IG_DATA_C_N<0>

E8 E9

DB2(P) DB2(N)

HDMI_IG_CLK_C_P HDMI_IG_CLK_C_N

F8 F9

DB3(P) DB3(N)

H6 J6

AUXB(P) AUXB(N)

OUT

64 63

BI

64 63

J5 H3

HDMI_HPD

IN

1

R9753

H5

HDMI_IG_DDC_CLK HDMI_IG_DDC_DATA

PP3V3_S0

66 74

DP_HDMI_TBT_ML_P<1> DP_HDMI_TBT_ML_N<1>

IN

66 74

IN

66 74

DC2(P) E2 DC2(N) E1

DP_HDMI_TBT_ML_P<2> DP_HDMI_TBT_ML_N<2>

IN

66 74

IN

66 74

DC3(P) F2 DC3(N) F1

DP_HDMI_TBT_ML_P<3> DP_HDMI_TBT_ML_N<3>

IN

66 74

100K 5% 1/20W MF 201

IN

66 74

64

B7

OE

2

DP_HDMI_TBT_AUX_P DP_HDMI_TBT_AUX_N

HPDC J1

64 28

BI

64 28

BI

D 3

DFN1006H4-3 SYM_VER_2

TOWARDS CPU

BI

13 66 74

BI

13 66 74

DP_HDMI_TBT_DDC_CLK DP_HDMI_TBT_DDC_DATA DPMUX_AUX_DDC_SEL

S 2

D 3

DMN32D2LFB4

7 D+ 6 D8

HDMITBTMUX_SEL_TBT

SEL 10

OE*

C9700 1 0.1UF

10% 6.3V CERM-X5R 2 0201

OMIT_TABLE

R9752 IN BI 64

100K

13 64 66 13 64 66

2

U9700

5% 1/20W MF 201

SLG4APXXX TDFN

64 23

64 63

66 64 13

DP_TBTSNK1_HPD HDMI_HPD HDMITBTMUX_LATCH

1 VDD

IO_8 8

DISP_MUX_EN

2 IO_2

IO_7 7

HDMITBTMUX_SEL_TBT

3 IO_3

IO_6 6

4 IO_4

GND 5

w

PP3V3_S0

1

w

77 68 65 64 62 61 50 47 46 28 24 18 17 15 13 12 11 8 44 43 42 41 40 39 38 37 30

1

R9701

R9703

100K 5% 1/20W MF 201

510K 5% 1/20W MF 201

2

DISP_MUX_PRIORITY

2

DPMUX_AUX_DDC_SEL

64

68 65 64 62 61 50 47 46 28 24 18 17 15 13 12 11 8 44 43 42 41 40 39 38 37 30 77

QTY 1

0.1UF

5% 1/20W MF 201

U9775

CRITICAL

U9700

CRITICAL

2

64 23

DP_TBTSNK1_HPD

1 2 3 4 5 6

DISP_MUX_PRIORITY

VDD GPI(2) GPIO(3) GPIO(4) GPIO(5) GPIO(6)

GPIO(12) GPIO(11) GPIO(10) GPIO(9) GPIO(8) GND

12 11 10 9 8 7

NC NC

HDMITBTMUX_FLAG_L

15 64

DISP_MUX_EN 64 HDMITBTMUX_SEL_TBT 15

23 64 66

DISP MUX SEL SEL 0 = HDMI SEL 1 = DP

HDMITBTMUX_LATCH

SYNC_MASTER=J44

5% 1/20W MF 201

SYNC_DATE=08/12/2013

PAGE TITLE

Display Mux: HDMI vs DP

510K

2

BOM OPTION

TDFN

HDMI_HPD

66 64 13

REFERENCE DES

100K

13

1

DESCRIPTION IC, SAK,AP4179,DP MUX CTRLR,TDFN-8

R9754

NOSTUFF CRITICAL

NC

R9704

B

DRAWING NUMBER

Apple Inc.

2

PRIORITY 0 = HDMI WINS OVER DP PRIORITY 1 = DP WINS OVER HDMI

AUX_SEL 0 = AUX ONLY AUX_SEL 1 = DDC ONLY AUX_SEL Vdd/2 = AUX & DDC

7

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

6

5

4

3

2

SIZE

D REVISION

R

NOTICE OF PROPRIETARY PROPERTY:

8

15 64

1

10% 6.3V CERM-X5R 2 0201

THRM_PAD 1 5% 1/20W MF 201

15 23 64 66

PP3V3_S0

SLG46400V

64 63

64

100K

HDMITBTMUX_FLAG_L

C9775 1

64

A R9702

64

9

343S0666

PP3V3_S4

NOSTUFF

DISP MUX SEL SEL 0 = HDMI SEL 1 = DP

PP3V3_S0

PART NUMBER

68 65 63 60 42 38 37 34 29 18

PP3V3_S0

15 23 64 66

GND

.c

S 2

HDMITBTMUX_SEL_TBT

68 65 64 62 61 50 47 46 28 24 18 17 15 13 12 11 8 44 43 42 41 40 39 38 37 30 77

TOWARDS CPU

TQFN

NOTE: HDMI ML SWIZZLED INTENTIONALLY AS PER TABLE 9-1 HASWELL-ULT PDG

w

23 15 66 64

13 64 66

THRM PAD

SYM_VER_2

1 G

13 64 66

BI

CRITICAL

DFN1006H4-3

B

BI

C

13 66

OUT

DP_HDMI_TBT_DDC_CLK DP_HDMI_TBT_DDC_DATA

SIGNAL_MODEL=MOJO_MUX

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

1

AUX_SEL C2

DISP_MUX_EN

Y+ 1 Y- 2

U9725

PI3USB102ZLE

DP_TBTSNK1_DDC_CLK DP_TBTSNK1_DDC_DATA

NO STUFF

DPMUX_HPD_OUT

DDCCLK_C J3 DDCDAT_C J7

DISP_MUX_EN DISP MUX SEL_L SEL_L 0 = DP SEL_L 1 = HDMI

AUXC(P) H2 AUXC(N) H1

HPDB

DX_SEL

BI

NO STUFF

2

1 G

DDCCLK_B DDCDAT_B

A1

64 63

5 M+ 4 M-

HDMI_IG_DDC_CLK HDMI_IG_DDC_DATA

h

Q9700

66 74

IN

Q9701

DB1(P) DB1(N)

DISP_MUX_SEL_L 100K 5% 1/20W MF 201

IN

64

64 63

BI

R9755

DMN32D2LFB4

HDMI_IG_DATA_C_P<2> HDMI_IG_DATA_C_N<2>

D9

DP_HDMI_TBT_ML_P<0> DP_HDMI_TBT_ML_N<0>

64 63

DISP_MUX_EN_L

DC1(P) D2 DC1(N) D1

DDCCLK_A DDCDAT_A HPDA

NC NC

47 46 44 43 42 41 18 17 15 13 12 11 8 40 39 38 37 30 28 24 77 68 65 64 62 61 50

AUXA(P) AUXA(N)

DP_TBTSNK1_HPD

IN

1

DC0(P) B2 DC0(N) B1

DA3(P) DA3(N)

J2

5% 1/20W MF 2 201

9

A8

DP_TBTSNK1_AUXCH_C_P DP_TBTSNK1_AUXCH_C_N

64 23

74 68 63

DP_TBTSNK1_ML_C_P<3> DP_TBTSNK1_ML_C_N<3>

NO STUFF

3

OUT

A6

R9727

VCC

BGA

CRITICAL

o

OUT

74 23

HD3SS213ZQE

DA2(P) DA2(N)

1

10K

5% 1/20W MF 2 201

.c

74 23

B6

A5

R9726 10K

5% 1/20W MF 2 201

PP3V3_S0

x

OUT

DP_TBTSNK1_ML_C_P<2> DP_TBTSNK1_ML_C_N<2>

1

TOWARDS PORTS 68 65 64 62 61 50 47 46 28 24 18 17 15 13 12 11 8 44 43 42 41 40 39 38 37 30 77

U9750

fi

74 23

DA1(P) DA1(N)

10K

20% 16V X6S-CERM 2 0201

a

OUT

B5

R9725

0.1UF

0.1UF

20% 2 10V X7R-CERM 0402

in

OUT

DP_TBTSNK1_ML_C_P<1> DP_TBTSNK1_ML_C_N<1>

D NO STUFF 1

C9725 1

C9751

G2

74 23

74 23

DA0(P) DA0(N)

VDD A2 VDD J4

OUT

B4 A4

H4 H7

74 23

DP_TBTSNK1_ML_C_P<0> DP_TBTSNK1_ML_C_N<0>

20% 10V 2 X7R-CERM 0402

1

GND GND GND GND GND GND

OUT

G8

OUT

74 23

B3 C8

74 23

C9750

PP3V3_S0

m

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

D

BRANCH

PAGE

97 OF 120 SHEET

64 OF 78

1

A

7

6

PPBUS_S5_HS_COMPUTING

40 53 54 55 57 65

65 56 40

PPBUS_S5_HS_OTHER5V

40 53 54 55 57 65 40 53 54 55 57 65 40 53 54 55 57 65

PPBUS_S5_HS_OTHER5V

40 56 65

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.6V MAKE_BASE=TRUE

PPBUS_S5_HS_OTHER3V3

PPBUS_S5_HS_OTHER3V3

40 56 65

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.6V MAKE_BASE=TRUE

PP3V3_S4

8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77 8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77 8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77 65 60 41 8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77

8 11 13 15 16 17 18 26 27 29 59 60 61 65 68 77 8 11 13 15 16 17 18 26 27 29 59 60 61 65 68 77 65 41 30 8 11 13 15 16 17 18 26 27 29 59 60 61 65 68 77 8 11 13 15 16 17 18 26 27 29 59 60 61 65 68 77

52 51 68 65

PPDCIN_G3H

PPDCIN_G3H MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V MAKE_BASE=TRUE

PPDCIN_G3H 68 51 37 30 34 39 61

65 45 36 17 33 38 52

PP3V42_G3H

PP3V42_G3H MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V MAKE_BASE=TRUE

PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H

13 12 8 65 17

PPVRTC_G3H

PPVRTC_G3H MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3V MAKE_BASE=TRUE

B

PPVRTC_G3H

5V Rails 68 65 56 34

PP5V_S5

PP5V_S5

40 51 52 65

PP3V3_SUS

40 51 52 65

PP3V3_SUS PP3V3_SUS

51 52 65 68

51 52 65 68

PP3V3_S3

PP3V3_S3

PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3

17 52 17 52 17 52 17 52

30 61 30 61 30 61 30 61

33 65 33 65 33 65 33 65

34 68 34 68 34 68 34 68

36 37 38 39 45 51

17 52 17 52

30 61 30 61

33 65 33 65

34 36 37 38 39 45 51 68 34 36 37 38 39 45 51 68

36 37 38 39 45 51 36 37 38 39 45 51 36 37 38 39 45 51

68 45 44 41 32 17 16 65 61 60 58 54 53

PP5V_S4

PP5V_S0

PP5V_S4 PP5V_S4 PP5V_S4 PP5V_S4 PP5V_S4 PP5V_S4 PP5V_S4 PP5V_S4 PP5V_S0 MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE

PP5V_S0

A

17 30 33 34 36 37 38 39 45 51 52 61 65 68

8 12 13 17 65

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37 77 68 65 64 62 61 50 8 39 38 37 30 28 24 18 17 15 13 12 11 61 50 47 46 44 43 42 41 40 77 68 65 64 62

PP3V3_S0 PP3V3_S0

PP3V3_S0 PP3V3_S0

32 66 32 66 32 66

33 46 55 56 57 60 62 63 65 68 33 46 55 56 57 60 62 63 65 68 33 46 55 56 57 60 62 63 65 68

32 66 32 66 32 66 32 66 32 66

33 68 33 68 33 68 33 68 33 68

46 55 56 57 60 62 63 65 46 55 56 57 60 62 63 65 46 55 56 57 60 62 63 65 46 55 56 57 60 62 63 65

PP0V675_S0_DDRVTT

73 68 65 55 22 15 18 19 39 42 60 65 68 15 18 19 39 42 60 65 68 15 18 19 39 42 60 65 68

65 60 41

PP5V_S0_FET

15 18 19 39 42 60 65 68

PPVTTDDR_S3

65 55 73 68

PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0

47 50 61 62 64 65 68 65 59 16 8 11 12 13 15 17 18 24 28 30 37 40 41 42 43 44 46

PP1V05_SUS

16 17 32 41 44 45 53 54 58 60 61 65 68

PP0V675_S3_MEM_VREFDQ_A

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50 61 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50 62 64 65 68 77 68 65 63 61 60 59 47 8

PP1V5_S0

16 17 32 41 44 45 53 54 58 60 61 65 68

PP0V675_S3_MEM_VREFCA_A

16 61 16 54

PP0V675_S3_MEM_VREFDQ_B

17 65 17 58

PP0V675_S3_MEM_VREFCA_B

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

PP1V05_S0

8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50 61 62 64 65 68 77 8 37 38 39 ? mA 40 11 12 13 15 17 18 24 28 30 12 40 41 42 43 44 46 47 50 61 8 62 64 65 68 77 64 65 68 77 11 13 15 17 18 24 28 30 37 38 39 41 42 43 44 46 47 50 61 62 61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

6

17 19 20 21 22 41 55 65 73

PP0V675_S0_DDRVTT MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.675V MAKE_BASE=TRUE

22 55 65 68 73

CPU "VCORE" RAILS 22 55 65 68 73 22 55 65 68 73

68 65 54 42 10 8

PPVCC_S0_CPU

PPVCC_S0_CPU

PPVTTDDR_S3

55 65 68 73

PP1V05_SUS

PPVCC_S0_CPU

8 10 42 54 65 68

16 59 65

PP1V05_SUS

16 59 65

PP1V5_S0

8 47 59 60 61 63 65 68

B

8 47 59 60 61 63 65 68 8 47 59 60 61 63 65 68 8 47 59 60 61 63 65 68 8 47 59 60 61 63 65 68 8 47 59 60 61 63 65 68

PP1V05_S0

Digital Ground

6 8 11 15 16 17 37 53 57 60 61 65 68

GND VOLTAGE=0V MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM

PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0

6 8 11 15 16 17 37 53 57 60 61 65 68 6 8 11 15 16 17 37 53 57 60 61 65 68 6 8 11 15 16 17 37 53 57 60 61 65 68 6 8 11 15 16 17 37 53 57 60 61 65 68 6 8 11 15 16 17 37 53 57 60 61 65 68 6 8 11 15 16 17 37 53 57 60 61 65 68 6 8 11 15 16 17 37 53 57 60 61 65 68 6 8 11 15 16 17 37 53 57 60 61 65 68 6 8 11 15 16 17 37 53 57 60 61 65 68 6 8 11 15 16 17 37 53 57 60 61 65 68 6 8 11 15 16 17 37 53 57 60 61 65 68 6 8 11 15 16 17 37 53 57 60 61 65 68

41 60 65

41 60 65

8 10 42 54 65 68

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

77 42 43 44 46 47 50 61 62 64 65 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 68 61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50 61 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50 68 62 64 65 68 77 8 37 38 39 40 41 42 40 11 12 13 15 17 18 24 28 30 12 43 44 46 47 50 61 62 64 65 8 77 64 65 68 77 11 13 15 17 18 24 28 30 37 38 39 41 42 43 44 46 47 50 61 62

41 60 65

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE 65 60 11 8

PP1V05_S0SW_PCH_HSIO

VOLTAGE=0.6V

PP0V675_S3_MEM_VREFCA_A VOLTAGE=0.6V

PP0V675_S3_MEM_VREFDQ_B VOLTAGE=0.6V

PP0V675_S3_MEM_VREFCA_B VOLTAGE=0.6V

5

PP1V05_S0SW_PCH_HSIO MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

1.84A 41 60 65

PP0V675_S3_MEM_VREFDQ_A

MAKE_BASE=TRUE

17 19 20 21 22 41 55 65 73

PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0

77 42 43 44 46 47 50 61 62 64 65 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 68 61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

PP5V_S0_FET

MAKE_BASE=TRUE

17 19 20 21 22 41 55 65 73 17 19 20 21 22 41 55 65 73

PP1V5_S0

77 42 43 44 46 47 50 61 62 64 65 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 68 61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

PP3V3_S0_FET

MAKE_BASE=TRUE

32 41 44 45 53 54 58 60 68 32 41 44 45 53 60 61 65 68

17 19 20 21 22 41 55 65 73

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

PP3V3_S0 PP3V3_S0 PP3V3_S0

MAKE_BASE=TRUE

17 19 20 21 22 41 55 65 73

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

VOLTAGE=3.3V 38 39 MAKE_BASE=TRUE 77

PP3V3_S0_FET

16 17 32 41 44 45 53 54 58 60 61 65 68

C

PP1V35_S3 PP1V35_S3 PP1V35_S3 PP1V35_S3 PP1V35_S3 PP1V35_S3

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.675V MAKE_BASE=TRUE

15 18 19 39 42 60 65 68

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE

16 17 32 41 44 45 53 54 58 60 61 65 68

17 18 23 24 65

8 10 41 65 73

15 18 19 39 42 60 65 68

PP5V_S0_FET

16 17 32 41 44 45 53 54 58 60 61 65 68

17 18 23 24 65

8 10 41 65 73

15 18 19 39 42 60 65 68

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V MAKE_BASE=TRUE

PP3V3_S0_FET

PP3V3_TBTLC MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE PP3V3_TBTLC

17 19 20 21 22 41 55 65 73

PP0V675_S0_DDRVTT PP0V675_S0_DDRVTT

15 18 19 39 42 60 65 68

16 17 32 41 44 45 53 54 58 60 61 65 68

16 17 32 41 44 45 53 54 58 60 61 65 68

7

15 18 19 39 42 60 65 68

VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S0

46 55 56 57 60 62 63 65

73 65 21 19

8

8 11 14 45 59 60 61 65

w

32 33 46 55 56 57 60 62 63 65 66 68

16 17 32 41 44 45 53 54 58 60 61 65 68

PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0

8 11 14 45 59 60 61 65

PP3V3_S0

16 17 32 41 44 45 53 54 58 60 61 65 68

PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0

8 11 14 45 59 60 61 65

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.20MM

w

PP5V_S4

8 11 14 45 59 60 61 65

17 30 33 34 36 37 38 39 45 51 52 61 65 68

PP3V3_S0

PP1V35_S3

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.35V MAKE_BASE=TRUE

8 11 14 45 59 60 61 65

17 30 33 34 36 37 38 39 45 51 52 61 65 68

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

23 24 25 42 65

8 11 14 45 59 60 61 65

PP3V3_S3

17 30 33 34 36 37 38 39 45 51 52 61 65 68

25 26 27 65 25 26 27 65

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.35V MAKE_BASE=TRUE

8 11 14 45 59 60 61 65

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM

17 30 33 34 36 37 38 39 45 51 52 61 65 68

25 26 27 65

PP15V_TBT PP15V_TBT

23 24 25 42 65

PP1V35_S3_CPUDDR

PP1V35_S3_CPUDDR

PP1V35_S3

73 65 55 41 22 21 20 19 17 8 11 14 45 59 60 61 65

17 30 33 34 36 37 38 39 45 51 52 61 65 68 68 65 60 42 39 19 18 15

34 56 65 68

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.175 MM VOLTAGE=5V MAKE_BASE=TRUE

VOLTAGE=3.3V MAKE_BASE=TRUE

PP15V_TBT

1.5V/1.35V/1.05V RAILS

8 11 14 45 59 60 61 65

PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS

w

57 56 55 46 33 32 68 66 65 63 62 60

PP5V_S4

18 29 34 37 38 42 60 63 64 65 68 73 65 41 10 8 18 29 34 37 38 42 60 63 64 65 68

25

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=15V MAKE_BASE=TRUE

VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S4_TBT

18 29 34 37 38 42 60 63 64 65 68

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE

57 56 55 46 33 32 68 66 65 63 62 60

18 29 34 37 38 42 60 63 64 65 68 18 29 34 37 38 42 60 63 64 65 68 18 29 34 37 38 42 60 63 64 65 68

PP15V_TBT

30 41 65

PP3V3_S4_TBT MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V 68 MAKE_BASE=TRUE

PP3V3_SUS

34 56 65 68

PP5V_S5

VOLTAGE=3.3V MAKE_BASE=TRUE

PP1V35_S3_CPUDDR

PP3V3_SUS

PPVIN_SW_TBTBST

65 27 26 25

PP3V3_S4_TBT

D

30 41 65

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM

PP3V3_S0SW_SSD

40 51 52 65

65 61 60 59 45 14 11 8

41 60 65

56

a

C

TBT RAILS (OFF WHEN NO CABLE) 41 60 65

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V

PP3V3_S0SW_SSD

PP3V3_S0SW_SSD

56

18 29 34 37 38 42 60 63 64 65

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM

in

PPDCIN_G3H_ISOL PPDCIN_G3H_ISOL

56

8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77

h

PPDCIN_G3H_ISOL MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=18.5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM

56

8 11 13 15 16 17 65 42 25 24 23 18 26 27 29 56 59 60 61 65 68 77 8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77

PP3V3_S4

PP3V3_S0SW_SSD_FET

PP3V3_S0SW_SSD_FET

8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77

.c

PPDCIN_G3H_ISOL

PP3V3_S0SW_SSD_FET

8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77 8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77

PP3V3_S4 PP3V3_S4 PP3V3_S4 PP3V3_S4 PP3V3_S4 PP3V3_S4 51 40 65 52

40 41 42 60 65

8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77 8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77 8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77

PP3V3_S5 PP3V3_S5

65 64 63 60 42 38 37 34 29 18 68

40 41 42 60 65

m

25 40 51 52 58 65 68 25 40 51 52 58 65 68

PPBUS_S5_HS_COMPUTING PPBUS_S5_HS_COMPUTING PPBUS_S5_HS_COMPUTING 65 56 40

PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5

25 40 51 52 58 65 68 25 40 51 52 58 65 68

VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S4SW_SNS PP3V3_S4SW_SNS

8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77 8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77

PP3V3_S5

25 40 51 52 58 65 68

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.6V MAKE_BASE=TRUE

D

1

40 41 42 60 65

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V59 60 MAKE_BASE=TRUE

PP3V3_S5

25 40 51 52 58 65 68

PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_S5_HS_COMPUTING

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.20MM

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

65 60 42 41 40 8 11 13 15 16 17 18 26 27 29 56 61 65 68 77

PP3V3_S5

PP3V3_S5

o

25 40 51 52 58 65 68 29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

PPBUS_G3H PPBUS_G3H PPBUS_G3H

54 53 40 65 57 55

2

3

.c

PPBUS_G3H MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=8.6V MAKE_BASE=TRUE

4

x

PPBUS_G3H

68 51 40 25 65 58 52

5 3.3V Rails

fi

8

"G3Hot" (Always-Present) Rails

8 11 60 65

DRAWING NUMBER

Apple Inc.

PP1V05_S0SW_PCH_HSIO PP1V05_S0SW_PCH_HSIO

19 20 65 73

Power Aliases 8 11 60 65 8 11 60 65

R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

19 20 65 73

19 21 65 73

19 21 65 73

4

3

2

SIZE

D REVISION

BRANCH

PAGE

100 OF 120 SHEET

65 OF 78

1

A

8

7

6

MEMORY ADDRESS/CTRL

7 7 7

D

66 22 20 7 73 7 7 7 7 7 7 7 7

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

20 22 73

5

20 22 73

5

20 22 73

5

20 22 73

5

20 22 73

5

20 22 73

5

7 20 22 66 73

5

20 22 73

5

20 22 73

74 66 64 13

20 22 73

74 66 64 13

20 22 73

66 64 13

20 22 73

66 64 13

20 22 73

66 64 13

=DP_TBTSNK1_ML_C_P<0> =DP_TBTSNK1_ML_C_N<0> =DP_TBTSNK1_ML_C_P<1> =DP_TBTSNK1_ML_C_N<1> =DP_TBTSNK1_ML_C_P<2> =DP_TBTSNK1_ML_C_N<2> =DP_TBTSNK1_ML_C_P<3> =DP_TBTSNK1_ML_C_N<3> DP_HDMI_TBT_AUX_P DP_HDMI_TBT_AUX_N DP_HDMI_TBT_DDC_CLK DP_HDMI_TBT_DDC_DATA DPMUX_HPD_OUT

TRUE

DP_HDMI_TBT_ML_P<0>

TRUE

DP_HDMI_TBT_ML_N<0>

TRUE

DP_HDMI_TBT_ML_P<1>

64 74

TRUE

DP_HDMI_TBT_ML_N<1>

64 74

TRUE

DP_HDMI_TBT_ML_P<2>

64 74

TRUE

DP_HDMI_TBT_ML_N<2>

64 74

TRUE

DP_HDMI_TBT_ML_P<3>

64 74

7 7 7 7 66 22 21 7 73 7 7 7 7 7 7 7 7

64 74

D

TRUE

DP_HDMI_TBT_ML_N<3>

64 74

TRUE

DP_HDMI_TBT_AUX_P

13 64 66 74

TRUE

DP_HDMI_TBT_AUX_N

TRUE

DP_HDMI_TBT_DDC_CLK DP_HDMI_TBT_DDC_DATA DPMUX_HPD_OUT

TRUE TRUE

13 64 66 74 13 64 66 13 64 66 13 64 66

20 22 73

HDMITBTMUX_SEL_TBT

HDMITBTMUX_SEL_TBT MAKE_BASE=TRUE

15 23 64 66

HDMITBTMUX_SEL_TBT MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14>

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

21 22 73 66 64 13

HDMITBTMUX_LATCH

HDMITBTMUX_LATCH MAKE_BASE=TRUE

21 22 73

15 23 64 66

13 64 66

21 22 73 21 22 73

EPD PANEL

21 22 73 21 22 73

MAKE_BASE 7 21 22 66 73 68 66 62 58 21 22 73 68 66 62 58

I2C_BKLT_SCL I2C_BKLT_SDA

TRUE

I2C_BKLT_SCL

58 62 66 68

TRUE

I2C_BKLT_SDA

58 62 66 68

21 22 73 21 22 73

.c

7

64 74

20 22 73

66 64 23 15

=MEM_B_A<0> =MEM_B_A<1> =MEM_B_A<2> =MEM_B_A<3> =MEM_B_A<4> =MEM_B_A<5> MEM_B_A<6> =MEM_B_A<7> =MEM_B_A<8> =MEM_B_A<9> =MEM_B_A<10> =MEM_B_A<11> =MEM_B_A<12> =MEM_B_A<13> =MEM_B_A<14>

21 22 73 21 22 73 21 22 73 21 22 73 21 22 73

MAKE_BASE

7

TRUE TRUE TRUE TRUE TRUE TRUE TRUE

MEM_A_ODT_CPU0 MEM_A_RAS_L MEM_A_WE_L MEM_A_CAS_L MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

7 22 66 7 20 22 66 73

fi

66 22 20 7 73

MEM_A_ODT_CPU0 MEM_A_RAS_L MEM_A_WE_L MEM_A_CAS_L =MEM_A_BA<0> MEM_A_BA<1> =MEM_A_BA<2>

7 20 22 66 73 7 20 22 66 73 20 22 73 7 20 22 66 73

UNUSED SIGNALS

20 22 73

a

66 22 7

66 22 20 7 73 66 22 20 7 73 7

MAKE_BASE

TRUE TRUE TRUE TRUE

7 22 66 7 21 22 66 73 7 21 22 66 73 7 21 22 66 73 21 22 73 7 21 22 66 73 21 22 73

MAKE_BASE 66 12 66 12 66 14 66 14

66 22 6

MEM_RESET_HSW_L

MAKE_BASE TRUE

66 14

MEM_RESET_HSW_L

66 14

6 22 66

B

66 12 66 12 71 66 14 71 66 14 71 66 14 71 66 14 71 66 14 71 66 14

UNUSED MEMORY SIGNALS

66 12 66 13 66 14

NO_TEST 66 7 7 66 7 66 7 66 7 7 66 7

NC_MEM_A_CLKN<1> NC_MEM_A_CLKP<1> MEM_A_CKE<2> NC_MEM_A_CKE<3> NC_MEM_B_CLKN<1> NC_MEM_B_CLKP<1> MEM_B_CKE<2> NC_MEM_B_CKE<3>

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC_MEM_A_CLKN<1> NC_MEM_A_CLKP<1> NC_MEM_A_CKE<2> NC_MEM_A_CKE<3> NC_MEM_B_CLKN<1> NC_MEM_B_CLKP<1> NC_MEM_B_CKE<2> NC_MEM_B_CKE<3>

7 66

66 14

7 66

66 14

NC_PCIE_CLK100M_ENETSDP NC_PCIE_CLK100M_ENETSDN NC_USB_IRP NC_USB_IRN NC_USB_CAMERAP NC_USB_CAMERAN NC_USB_SDP NC_USB_SDN NC_HDA_SDIN1 NC_PCI_PME_L NC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L

7 66

TRUE TRUE TRUE TRUE

NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE

TRUE TRUE

NO_TEST=TRUE NO_TEST=TRUE

NC_PCIE_CLK100M_FWP NC_PCIE_CLK100M_FWN NC_PCIE_FW_D2RP NC_PCIE_FW_D2RN NC_PCIE_FW_R2D_CP NC_PCIE_FW_R2D_CN

12 66 12 66 14 66 14 66 14 66 14 66

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE

NC_PCIE_CLK100M_ENETSDP 12 NC_PCIE_CLK100M_ENETSDN 12 NC_USB_IRP 14 66 71 NC_USB_IRN 14 66 71 NC_USB_CAMERAP 14 66 71 NC_USB_CAMERAN 14 66 71 NC_USB_SDP 14 66 71 NC_USB_SDN 14 66 71

TRUE TRUE TRUE TRUE TRUE

NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE

NC_HDA_SDIN1 NC_PCI_PME_L NC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L

B

66 66

12 66 13 66 14 66 14 66 14 66

7 66 7 66

7 66

w

66 7

NC_PCIE_CLK100M_FWP NC_PCIE_CLK100M_FWN NC_PCIE_FW_D2RP NC_PCIE_FW_D2RN NC_PCIE_FW_R2D_CP NC_PCIE_FW_R2D_CN

in

7

TRUE

MEM_B_ODT_CPU0 MEM_B_RAS_L MEM_B_WE_L MEM_B_CAS_L MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>

h

66 22 21 7 73

TRUE

.c

7

TRUE

w

66 22 21 7 73 66 22 21 7 73

MEM_B_ODT_CPU0 MEM_B_RAS_L MEM_B_WE_L MEM_B_CAS_L =MEM_B_BA<0> MEM_B_BA<1> =MEM_B_BA<2>

w

66 22 7 66 22 21 7 73

C

x

C 66 22 20 7 73

1

MAKE_BASE

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14>

TRUE

MAKE_BASE 7

2

m

7

3

o

7

=MEM_A_A<0> =MEM_A_A<1> =MEM_A_A<2> =MEM_A_A<3> =MEM_A_A<4> =MEM_A_A<5> MEM_A_A<6> =MEM_A_A<7> =MEM_A_A<8> =MEM_A_A<9> =MEM_A_A<10> =MEM_A_A<11> =MEM_A_A<12> =MEM_A_A<13> =MEM_A_A<14>

4

HDMI VS TBT

MAKE_BASE 7

5

NC_SMC_TRST_L NC_SMC_MD1

66 45 66 45

TRUE TRUE

NO_TEST=TRUE NO_TEST=TRUE

NC_SMC_TRST_L NC_SMC_MD1

45 66 45 66

A

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

PAGE TITLE 65 63 62 60 57 56 55 46 33 32 68

Signal Aliases

PP5V_S4

DRAWING NUMBER

GND MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

Apple Inc.

XWA202 SM 1

R

2

XWA203

PP5V_S0_AUDIO_AMP_L

48

NOTICE OF PROPRIETARY PROPERTY:

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

SM

Digital Ground

1

2

PP5V_S0_AUDIO_AMP_R

48

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

102 OF 120 SHEET

66 OF 78

1

A

8

7

6

5

4

3

2

1

D

D Memory Bit/Byte Swizzle

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 67 20 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

C

B

A

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 67 20 7

TRUE

73 67 20 7

TRUE

73 7

TRUE

73 7

TRUE

MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7>

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20 20 20 20 20

=MEM_A_DQS_P<7> =MEM_A_DQS_N<7> =MEM_A_DQS_P<5> =MEM_A_DQS_N<5> =MEM_A_DQS_P<2> =MEM_A_DQS_N<2> =MEM_A_DQS_P<4> =MEM_A_DQS_N<4> =MEM_A_DQS_P<3> =MEM_A_DQS_N<3> =MEM_A_DQS_P<1> =MEM_A_DQS_N<1> MEM_A_DQS_P<6> MEM_A_DQS_N<6> =MEM_A_DQS_P<0> =MEM_A_DQS_N<0>

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 67 21 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20 20 7 20 67 68 73

20 20 20 20 20

20 20

20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 67 21 7

TRUE

20 20 7 20 67 73

73 67 21 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

7 20 67 73

MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7>

21 21 21 21

m

TRUE

73 68 7

=MEM_B_DQ<8> =MEM_B_DQ<14> =MEM_B_DQ<11> =MEM_B_DQ<9> =MEM_B_DQ<12> =MEM_B_DQ<10> =MEM_B_DQ<15> =MEM_B_DQ<13> =MEM_B_DQ<24> =MEM_B_DQ<30> =MEM_B_DQ<29> =MEM_B_DQ<27> =MEM_B_DQ<28> =MEM_B_DQ<26> =MEM_B_DQ<25> =MEM_B_DQ<31> =MEM_B_DQ<5> =MEM_B_DQ<1> =MEM_B_DQ<6> =MEM_B_DQ<3> =MEM_B_DQ<4> =MEM_B_DQ<7> =MEM_B_DQ<0> =MEM_B_DQ<2> =MEM_B_DQ<21> =MEM_B_DQ<17> =MEM_B_DQ<20> =MEM_B_DQ<22> =MEM_B_DQ<23> =MEM_B_DQ<19> =MEM_B_DQ<18> =MEM_B_DQ<16> MEM_B_DQ<32> =MEM_B_DQ<40> =MEM_B_DQ<45> =MEM_B_DQ<43> =MEM_B_DQ<46> =MEM_B_DQ<42> =MEM_B_DQ<47> =MEM_B_DQ<41> =MEM_B_DQ<60> =MEM_B_DQ<56> =MEM_B_DQ<63> =MEM_B_DQ<61> =MEM_B_DQ<62> =MEM_B_DQ<58> =MEM_B_DQ<59> =MEM_B_DQ<57> =MEM_B_DQ<38> =MEM_B_DQ<37> =MEM_B_DQ<32> =MEM_B_DQ<33> =MEM_B_DQ<35> =MEM_B_DQ<36> =MEM_B_DQ<34> =MEM_B_DQ<39> =MEM_B_DQ<51> =MEM_B_DQ<53> =MEM_B_DQ<48> =MEM_B_DQ<55> =MEM_B_DQ<50> =MEM_B_DQ<49> =MEM_B_DQ<54> =MEM_B_DQ<52>

o

TRUE

73 68 7

20

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

x

73 68 7

TRUE

fi

TRUE

TRUE

73 68 7

a

73 68 7

73 68 7

in

TRUE

TRUE

20 20

h

73 68 7

73 68 7

.c

TRUE

20

w

TRUE

73 68 7

=MEM_A_DQ<60> =MEM_A_DQ<56> =MEM_A_DQ<57> =MEM_A_DQ<61> =MEM_A_DQ<62> =MEM_A_DQ<58> =MEM_A_DQ<59> =MEM_A_DQ<63> =MEM_A_DQ<44> =MEM_A_DQ<40> =MEM_A_DQ<45> =MEM_A_DQ<47> =MEM_A_DQ<46> =MEM_A_DQ<42> =MEM_A_DQ<41> =MEM_A_DQ<43> =MEM_A_DQ<20> =MEM_A_DQ<18> =MEM_A_DQ<23> =MEM_A_DQ<19> =MEM_A_DQ<17> =MEM_A_DQ<21> =MEM_A_DQ<22> =MEM_A_DQ<16> =MEM_A_DQ<38> =MEM_A_DQ<36> =MEM_A_DQ<37> =MEM_A_DQ<39> =MEM_A_DQ<34> =MEM_A_DQ<32> =MEM_A_DQ<35> =MEM_A_DQ<33> MEM_A_DQ<32> =MEM_A_DQ<24> =MEM_A_DQ<25> =MEM_A_DQ<29> =MEM_A_DQ<30> =MEM_A_DQ<26> =MEM_A_DQ<31> =MEM_A_DQ<27> =MEM_A_DQ<12> =MEM_A_DQ<8> =MEM_A_DQ<11> =MEM_A_DQ<15> =MEM_A_DQ<14> =MEM_A_DQ<10> =MEM_A_DQ<9> =MEM_A_DQ<13> =MEM_A_DQ<53> =MEM_A_DQ<55> =MEM_A_DQ<50> =MEM_A_DQ<54> =MEM_A_DQ<52> =MEM_A_DQ<48> =MEM_A_DQ<51> =MEM_A_DQ<49> =MEM_A_DQ<2> =MEM_A_DQ<1> =MEM_A_DQ<6> =MEM_A_DQ<4> =MEM_A_DQ<0> =MEM_A_DQ<3> =MEM_A_DQ<7> =MEM_A_DQ<5>

w

73 68 7

MAKE_BASE

MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

w

TRUE

.c

MAKE_BASE 73 68 7

=MEM_B_DQS_P<1> =MEM_B_DQS_N<1> =MEM_B_DQS_P<3> =MEM_B_DQS_N<3> =MEM_B_DQS_P<0> =MEM_B_DQS_N<0> =MEM_B_DQS_P<2> =MEM_B_DQS_N<2> =MEM_B_DQS_P<5> =MEM_B_DQS_N<5> =MEM_B_DQS_P<7> =MEM_B_DQS_N<7> MEM_B_DQS_P<6> MEM_B_DQS_N<6> =MEM_B_DQS_P<6> =MEM_B_DQS_N<6>

21 21 21 21 21 21 21 21 21 21 21 21 21 21 21

C

21 21 21 21 21 21 21 21 21 21 21 21 21 7 21 67 68 73 21 21 21 21 21 21 21 21 21 21 21 21 21

B

21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21

21 21 21 21 21 21 21 21

SYNC_MASTER=J44 21

SYNC_DATE=01/03/2013

PAGE TITLE

Memory Bit/Byte Swizzle

21 21

DRAWING NUMBER 21

Apple Inc.

7 21 67 73 7 21 67 73 21

R

NOTICE OF PROPRIETARY PROPERTY:

8

7

6

5

4

BRANCH



21

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

3

2

SIZE

D REVISION

PAGE

103 OF 120 SHEET

67 OF 78

1

A

6

Functional Test Points

70 23 14

J6050 (LEFT FAN CONN) FUNC_TEST PP5V_S0 TRUE

70 68 23 12

3 TPs per Fan

FAN_LT_PWM FAN_LT_TACH

SM

1

70 32 14

SM

1

70 68 30 12

PP

P2MM SM 1P2MM PP

PCIE_SSD_D2R_P<0> PCIE_SSD_D2R_N<0>

70 68 30 12

PP

P2MM SM 1P2MM PP

PCIE_CAMERA_D2R_P PCIE_CAMERA_D2R_N

70 32 14

D

PCIE_CLK100M_TBT_P PCIE_CLK100M_TBT_N

SM

1

PP

PPA423 PPA424 PPA402 PPA403 PPA404 PPA405

P2MM J4002 (ALS/CAMERA CONN)

70 68 63 14

SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA TRUE PP5V_S3RS0_ALSCAM_F TRUE MIPI_CLK_CONN_N TRUE MIPI_CLK_CONN_P TRUE TRUE CAM_SENSOR_WAKE_L_CONN TRUE MIPI_DATA_CONN_N TRUE MIPI_DATA_CONN_P TRUE I2C_CAM_SCK TRUE I2C_CAM_SDA TRUE

PP

P2MM SM 1P2MM PP

14 32 36 39 43 72 76

USB3RPCIE_SD_D2R_P USB3RPCIE_SD_D2R_N

14 32 36 39 43 72 71 63 14 76 71 63 14 32

SM

1

32 75

PP

PPA410 PPA411 PPA420 PPA421

P2MM

32 75

1

HDA_SDIN0

72 47 12

SM

PP

32

PPA408

PLACE_NEAR=U0500.AY10:6MM 32 75 32 75

75 32 31

31 32

SM

1P2MM PP SM 1

MIPI_CLK_N MIPI_CLK_P

PP P2MM SM 1P2MM PP

31 32 75 32 31

J9500 (RIO POWER PINS) PP3V3_S4 TRUE PP5V_S4 TRUE PP1V5_S0 TRUE

MIPI_DATA_N MIPI_DATA_P

1

SM

PP

PPA441 PPA442 PPA443 PPA444

18 29 34 37 38 42 60 63 64 65 68

P2MM

PM_SLP_S3_L PP0V675_S0_DDRVTT

TRUE

PP1V05_S0

1

PP

PPA419

TRUE

TRUE TRUE

C

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

J6601 (AUDIO 2-MIKE CONN)

TRUE TRUE

DMIC_SDA3 DMIC_SDA2

TRUE

SMBUS_PCH_CLK SMBUS_PCH_DATA

14 16 19 39 63 72

TRUE

34

DMIC_CLK3

TRUE

SMBUS_SMC_2_S3_SDA SMBUS_SMC_2_S3_SCL PP3V3_TPAD_CONN PP5V_S4_CUMULUS Z2_CLKIN PSOC_SCLK PSOC_MOSI Z2_SCLK PSOC_MISO Z2_MISO Z2_MOSI PSOC_F_CS_L Z2_CS_L Z2_KEY_ACT_L PICKB_L Z2_HOST_INTN

34

PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_AP_D2R_P PCIE_AP_D2R_N

34 34 34

TRUE

J7715 (KBD BACKLIGHT CONN) PPVOUT_S0_KBDBKLT TRUE KBDLED_CATHODE1 TRUE KBDLED_CATHODE2 TRUE

TRUE 35 58

TRUE

GND

TRUE

34

35 58

TRUE

PCIE_SSD_R2D_P<3..0> PCIE_SSD_R2D_N<3..0>

TRUE

34

TRUE

PP3V3_S0

61 62 64 65 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

TRUE

PP3V3_S3 PP3V3_S5

15 18 19 39 42 60 65

34 34 34

TRUE 34

TRUE

TRUE

PPVCC_S0_CPU

TRUE 34

TRUE 34

TRUE 34

TRUE 34

TRUE 34

36 37 17 30 33 34 36 37 38 39 45 51 52 61 65 68 16 17 32 41 44 45 53 54 58 60 61 65 68 32 33 46 55 56 57 60 62 63 65 66 68

34 36 39 76

25 40 51 52 58 65 51 52 65

8 10 42 54 65

TRUE

PPVTTDDR_S3

NC_PM_SLP_A_L

55 65 68 73

34 36 39 76

34

NO_TESTs

USB3_EXTA_D2R_P USB3_EXTA_D2R_N

34 34

TBTBPWRSW_ISET_V3P3

TRUE MAKE_BASE=TRUE

NC_PM_SLP_A_L

13 68

USB3_EXTA_R2D_C_P USB3_EXTA_R2D_C_N USB3_EXTA_R2D_N USB3_EXTA_R2D_N USB3_EXTB_D2R_P USB3_EXTB_D2R_N USB3_EXTB_R2D_C_P USB3_EXTB_R2D_C_N

27

TBTBPWRSW_ISET_S0_R TBTBPWRSW_ISET_S3

34 34

23 70 14 23 70

TRUE TRUE

14 23 70 23 70

TRUE 23 70

14 33 71

TRUE 14 33 71

14 33 71

TRUE 14 33 71

TRUE 33 68 71

TRUE 33 68 71

C

14 63 71

TRUE 14 63 71

TRUE 14 63 71

TRUE 14 63 71

TRUE

27

TRUE

PCIE_CLK100M_SSD_P PCIE_CLK100M_SSD_N

27

TRUE

34

23 70

TRUE TRUE

TRUE

TRUE

34

14 23 70

TRUE

TRUE

34

34

14 23 70

TRUE

TRUE

34

34

12 30 68 70

PCIE_TBT_R2D_C_P<3..0> PCIE_TBT_R2D_C_N<3..0> PCIE_TBT_R2D_P<3..0> PCIE_TBT_R2D_N<3..0> PCIE_TBT_D2R_P<3..1> PCIE_TBT_D2R_N<3..1> PCIE_TBT_D2R_C_P<3..1> PCIE_TBT_D2R_C_N<3..1>

34 56 65

34

12 30 68 70

TRUE TRUE

8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 77

PP3V3_S5_AVREF_SMC PP3V42_G3H PP5V_S0 PP5V_S4 PP5V_S5 PPBUS_G3H PPDCIN_G3H

TRUE 34

12 30 70

TRUE 12 30 70

TRUE 34

TBTAPWRSW_ISET_V3P3

34

TBT_A_R2D_C_P<1..0> TBT_A_R2D_C_N<1..0> TBT_A_R2D_P<1..0> TBT_A_R2D_N<1..0>

51 51

GND

TRUE

30 70

PCIE_SSD_D2R_P<3..0> PCIE_SSD_D2R_N<3..0>

34

TDM_ONEWIRE_MPM ADAPTER_SENSE PP18V5_DCIN_FUSE

35 58

30 70

TRUE TRUE

J7000 (DC POWER CONN)

48 50 77

12 30 70

34

48 50 77

TRUE

D

12 30 70

TRUE

4 TPs 34

TBTAPWRSW_ISET_S3 TBTAPWRSW_ISET_S3_R

TRUE

14 63 68 70

TRUE

34

47 50

48 50 77

14 63 68 70

PCIE_SSD_R2D_C_P<3..0> PCIE_SSD_R2D_C_N<3..0>

34

J6603 (AUDIO RIGHT SPEAKER CONN)

TBT_A_D2R_C_P<1> TBT_A_D2R_C_N<1> TBT_A_D2R_C_P<0> TBT_A_D2R_C_N<0>

MEM_A_DQ<63..0>

26

7 20 67 73

PCIE_CLK100M_TBT_P PCIE_CLK100M_TBT_N

TRUE

TRUE

TBTAPWRSW_ISET_S0

47 50

14 63 70

TRUE TRUE

47 50

48 50 77

14 63 70

TRUE TRUE

34

h

TRUE

High Speed NO_TEST

34

J6602 (AUDIO LEFT SPEAKER CONN) SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_L_ID SPKRCONN_SL_OUT_P SPKRCONN_SL_OUT_N

6 8 11 15 16 17 37 53 57 60 61 65

34

50

14 16 19 39 63 72

22 55 65 73

x

LPC_CLK24M_SMC

NC NO_TEST 13 17 18 36 61 63

34

J4800 (TPAD CONN)

SM

TRUE

TRUE

TRUE

34

1

fi

U5000 CHARZ TPS 72 36 17

TRUE

FUNC_TEST

17 30 33 34 36 37 38 39 45 51 52 61 65 68 TRUE

32 33 46 55 56 57 60 62 63 65 66 68 8 47 59 60 61 63 65

GND

TRUE

SM 1P2MM PP SM 1

PCIE_AP_D2R_P PCIE_AP_D2R_N

70 68 63 14

18 29 34 37 38 42 60 63 64 65 68

2

3 ICT Test Points

a

TRUE

PP

P2MM SM 1P2MM PP

PPA400 PPA401

4 POWER RAILS

in

TRUE

P2MM SM 1P2MM PP SM 1

PCIE_TBT_D2R_P<0> PCIE_TBT_D2R_N<0>

70 23 14

5 J4813 (KEY BOARD CONN) PP3V3_S4 TRUE PP3V42_G3H TRUE WS_KBD1 TRUE WS_KBD2 TRUE WS_KBD3 TRUE WS_KBD4 TRUE WS_KBD5 TRUE WS_KBD6 TRUE WS_KBD7 TRUE WS_KBD8 TRUE WS_KBD9 TRUE WS_KBD10 TRUE WS_KBD11 TRUE WS_KBD12 TRUE WS_KBD13 TRUE WS_KBD14 TRUE WS_KBD15_CAP TRUE WS_KBD16_NUM TRUE WS_KBD17 TRUE WS_KBD18 TRUE WS_KBD19 TRUE WS_KBD20 TRUE WS_KBD21 TRUE WS_KBD22 TRUE WS_KBD23 TRUE WS_KBD_ONOFF_L TRUE WS_LEFT_SHIFT_KBD TRUE WS_LEFT_OPTION_KBD TRUE WS_CONTROL_KBD TRUE

m

U0500 CHARZ TPS

o

7

.c

8

26

TRUE

12 23 68 70

TRUE 12 23 68 70

TRUE

PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N PCIE_CLK100M_CAMERA_P PCIE_CLK100M_CAMERA_N

26

TRUE 26

PPVTTDDR_S3

TRUE

55 65 68 73

TRUE 23 26 74

TRUE

12 63 70

TRUE 12 63 70

TRUE 12 32 70

TRUE

12 32 70

TRUE 23 26 74

TRUE 26 74

TRUE 26 74

MEM_B_DQ<63..0>

TRUE

7 21 67 73

TRUE 26 74

TRUE 26 74

TRUE 26 74

TRUE 26 74

TRUE

SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N SPKRCONN_R_ID SPKRCONN_SR_OUT_P SPKRCONN_SR_OUT_N

TRUE

GND

TRUE

B

TRUE TRUE TRUE

48 50 77 48 50 77

TRUE

47 50

TRUE

48 50 77 48 50 77

J7050 (MAIN BATT CONN) PPVBAT_G3H_CONN TRUE SMBUS_SMC_5_G3_SCL TRUE SMBUS_SMC_5_G3_SDA TRUE

TRUE

TRUE

51

TRUE

TRUE

J6601 (2 MIC CONN)

TRUE

TRUE TRUE

CON_DMIC_PWR CON_DMIC_SDA1 CON_DMIC_CLK

TRUE TRUE TRUE TRUE TRUE TRUE

A

PCH_VSS_NCTF<19> PCH_VSS_NCTF<19>

TRUE TRUE

TRUE 68

TRUE 68

TRUE

J4600 (LEFT USB CONN) PP5V_S3_LTUSB_A_F TRUE USB_LT1_N TRUE USB_LT1_P TRUE

TRUE TRUE

33

I2C_BKLT_SCL I2C_BKLT_SDA LCD_HPD_CONN LCD_IRQ_L EDP_BKLT_PWM SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA EDP_PANEL_PWR_OR_PSR_EN DP_INT_AUX_P DP_INT_AUX_N DP_INT_ML_P<0> DP_INT_ML_N<0> DP_INT_ML_P<1> DP_INT_ML_N<1> DP_INT_ML_P<2> DP_INT_ML_N<2> DP_INT_ML_P<3> DP_INT_ML_N<3>

TRUE TRUE

58 62 66

TRUE

58 62 66

TRUE

62

TRUE

15 62

TRUE 13 62

TRUE

36 39 62 76 36 39 62 76

TRUE

62

TRUE

62 74

TRUE TRUE

TRUE

62 74

16 17 32 41 44 45 53 54 58 60 61 65 68 17 45 72 14 36 45 72 14 36 45 72

23 26 74

23 27 74

TRUE 23 27 74

TRUE

TRUE

SMC_TX_L

TRUE

LPC_FRAME_L SPIROM_USE_MLB PM_CLKRUN_L

62 74 62 74

TRUE 62 74

TRUE

HDMI_IG_CLK_C_P HDMI_IG_CLK_C_N HDMI_IG_DATA_C_P<2..0> HDMI_IG_DATA_C_N<2..0>

27 74

TRUE 27 74

TRUE 27 74

TRUE

27 74

TRUE TRUE TRUE

GND

TRUE TRUE TRUE

6

TRUE 63 64 74

27 74 27 74

TRUE 23 27 74

TRUE

FW_PWR_EN FW_PME_L ENET_MEDIA_SENSE

23 27 74

TRUE 23 27 74

TRUE 23 27 74

14 36 45 72

TRUE

15 16 45

TRUE

18 45

TRUE

36 37 45

PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_AP_R2D_P PCIE_AP_R2D_N

14 63 68 70 63 70 63 70

68

36 37 45

68

14 36 45 72

68

15 45 72 13 36 45 68

68

68

15 36 45 13 36 45

68

36 37 45 68 36 37 45

NC_XDP_PCH_HOOK4 NC_XDP_PCH_HOOK5 TP_XDP_PCH_OBSFN_B<0> NC_XDP_PCH_OBSFN_B<1> TP_XDP_PCH_OBSFN_A<0> NC_XDP_PCH_OBSFN_A<1> TP_XDP_PCH_OBSFN_D<0> NC_XDP_PCH_OBSFN_D<1> NC_XDP_PCH_TRST_L

68

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC_XDP_PCH_HOOK4 NC_XDP_PCH_HOOK5 NC_XDP_PCH_OBSFN_B<0> NC_XDP_PCH_OBSFN_B<1> NC_XDP_PCH_OBSFN_A<0> NC_XDP_PCH_OBSFN_A<1> NC_XDP_PCH_OBSFN_D<0> NC_XDP_PCH_OBSFN_D<1> NC_XDP_PCH_TRST_L

15 15

NC_1V05_S0_PCH_VCCAPLLEXP TRUE MAKE_BASE=TRUE NC_AUD_CODEC_MICBIAS TRUE MAKE_BASE=TRUE

NC_AUD_MIC_INRP NC_AUD_MIC_INRN

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC_AUD_MIC_INRP NC_AUD_MIC_INRN

37 45 36 37 45 36 37 45

4

3

68 68

13 13 13 13 13 12

68

68

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

Functional / ICT Test

68 68

DRAWING NUMBER

NC_1V05_S0_PCH_VCCAPLLEXP NC_AUD_CODEC_MICBIAS

36 37 38 45 52

5

15

ODD_PWR_EN_L ENET_LOW_PWR AUD_IP_PERIPHERAL_DET AUD_I2C_INT_L AUD_IPHS_SWITCH_EN ENETSD_CLKREQ_L

14 63 68 70

68

71

(Nets with offpages not used on this project) HDD_PWR_EN 15 WOL_EN 14 BT_PWRRST_L 15

63 64 74

TRUE

62 74

LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_ROMBOOT SMC_RX_L SMC_TMS

63 64 74

TRUE

TRUE

TRUE

62 74

TRUE

Unused nets with offpage

63 64 74

TRUE

TRUE

14 36 45 72

TRUE

XDP_LPCPLUS_GPIO LPCPLUS_RESET_L SMC_TDO

TRUE TRUE

TBT_B_R2D_C_P<1..0> TBT_B_R2D_C_N<1..0> TBT_B_R2D_P<1..0> TBT_B_R2D_N<1..0> TBT_B_D2R_C_P<0> TBT_B_D2R_C_N<0> TBT_B_D2R_C_P<1> TBT_B_D2R_C_N<1> TBT_B_D2R_P<0> TBT_B_D2R_N<0> TBT_B_D2R_P<1> TBT_B_D2R_N<1>

62 74

71

7

65 68 17 30 33 34 36 37 38 39 45 51 52 61

23 26 74 23 26 74

62 74

6 TPs

8

PP3V42_G3H PP5V_S0 LPC_CLK24M_LPCPLUS LPC_AD<0> LPC_AD<2> LPC_AD<1> LPC_AD<3>

B

23 26 74

TRUE TRUE

68

GND GND TRUE

34 36 37

TBT_A_D2R_P<1> TBT_A_D2R_N<1> TBT_A_D2R_P<0> TBT_A_D2R_N<0>

62 74

TRUE

FUNC_TEST

13 17 36 72

J6100 (LPC + SPI CONN) 2 TP needed

w

SYS_DETECT_L

TRUE

TRUE

58 62

w

TRUE

TRUE

PPVOUT_S0_LCDBKLT

36 39 51 52 76

TRUE

TRUE

62

51 52 36 39 51 52 76

SMC_ONOFF_L

13 36 45 68

w

TRUE

J8300 (EDP CONN) PP5VR3V3_SW_LCD

PM_CLKRUN_L PM_SYSRST_L

.c

TRUE

Apple Inc.

68 R

68

68 68

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

2

SIZE

D REVISION

BRANCH

PAGE

104 OF 120 SHEET

68 OF 78

1

A

8

7

6

5

4

3

2

1

J44 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS TABLE_BOARD_INFO

BOARD LAYERS

BOARD AREAS

BOARD UNITS (MIL or MM)

ALLEGRO VERSION

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

NO_TYPE,BGA,P65BGA,BGA_MEM

MM

16.5 TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

DEFAULT

*

Y

=45_OHM_SE

=45_OHM_SE

10 MM

0 MM

0 MM

STANDARD

*

Y

=DEFAULT

=DEFAULT

10 MM

=DEFAULT

=DEFAULT

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

D

D TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

*

*

BGA

P072_SPACE

*

*

P65BGA

P075_SPACE

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

50_OHM_SE

TOP,BOTTOM

Y

0.095 MM

0.095 MM

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

50_OHM_SE

*

Y

0.066 MM

0.066 MM

=STANDARD

=STANDARD

=STANDARD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

45_OHM_SE

TOP,BOTTOM

Y

0.116 MM

0.116 MM

m

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

DEFAULT

*

0.1 MM

?

STANDARD

*

=DEFAULT

?

P072_SPACE

*

0.071 MM

?

P075_SPACE

*

0.075 MM

?

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

45_OHM_SE

*

Y

LAYER

ALLOW ROUTE ON LAYER?

0.083 MM

0.083 MM

=STANDARD

=STANDARD

=STANDARD

TABLE_SPACING_RULE_ITEM

PHYSICAL_RULE_SET

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

TABLE_SPACING_RULE_ITEM

DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM

40_OHM_SE

TOP,BOTTOM

Y

TABLE_SPACING_RULE_ITEM

0.095 MM

0.145 MM

40_OHM_SE

*

Y

0.102 MM

0.090 MM

=STANDARD

=STANDARD

=STANDARD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

37_OHM_SE

TOP,BOTTOM

Y

0.165 MM

0.095 MM

37_OHM_SE

*

Y

0.118 MM

0.090 MM

=STANDARD

=STANDARD

=STANDARD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

.c

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

Stackup-Defined Spacing Rules

C

TABLE_PHYSICAL_RULE_HEAD

Note: Outer dielectric is 0.058 mm nominal, Inner dielectric is 0.053 mm nominal.

x

C

o

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

27P4_OHM_SE TOP,BOTTOM

Y

0.265 MM

0.095 MM

27P4_OHM_SE

*

Y

0.186 MM

0.090 MM

=STANDARD

=STANDARD

=STANDARD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

TABLE_PHYSICAL_RULE_HEAD

*

N

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

1:1_SPACING

*

0.1 MM

?

SPACING_RULE_SET

LAYER

TABLE_PHYSICAL_RULE_ITEM

72_OHM_DIFF

fi

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

72_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

Y

0.105 MM

0.105 MM

0.120 MM

0.120 MM

72_OHM_DIFF ISL2,ISL11

Y

0.105 MM

0.105 MM

0.120 MM

0.120 MM

a

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

72_OHM_DIFF TOP,BOTTOM

Y

0.146 MM

0.146 MM

0.120 MM

0.120 MM

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

WEIGHT

1x_DIELECTRIC TOP,BOTTOM

0.058 MM

?

1x_DIELECTRIC

0.053 MM

?

0.101 MM

?

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

ISL3,ISL4,ISL9,ISL10

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

80_OHM_DIFF

*

N

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

80_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

Y

0.092 MM

0.092 MM

0.120 MM

0.120 MM

80_OHM_DIFF ISL2,ISL11

Y

0.092 MM

0.092 MM

0.120 MM

0.120 MM

80_OHM_DIFF TOP,BOTTOM

Y

0.125 MM

0.125 MM

0.155 MM

0.155 MM

in

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

1X_DIELECTRIC

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

TABLE_SPACING_RULE_ITEM

h

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

85_OHM_DIFF

*

N

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

85_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

Y

0.080 MM

0.080 MM

0.120 MM

0.120 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE

AREA_TYPE

PHYSICAL_RULE_SET

*

P65BGA

P65_BGA

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

85_OHM_DIFF ISL2,ISL11

Y

0.080 MM

0.080 MM

0.120 MM

0.120 MM

85_OHM_DIFF TOP,BOTTOM

Y

0.105 MM

0.105 MM

0.125 MM

0.125 MM

TABLE_PHYSICAL_RULE_ITEM

.c

TABLE_PHYSICAL_ASSIGNMENT_ITEM

B

B

TABLE_PHYSICAL_RULE_HEAD

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

90_OHM_DIFF

*

N

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

90_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

Y

0.078 MM

0.078 MM

0.200 MM

0.200 MM

90_OHM_DIFF ISL2,ISL11

Y

0.078 MM

0.078 MM

0.200 MM

0.200 MM

90_OHM_DIFF TOP,BOTTOM

Y

0.101 MM

0.101 MM

0.180 MM

0.180 MM

w

PHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

w

w

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

P65_BGA

*

Y

0.071MM

0.071MM

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

1TO1_DIFFPAIR

*

Y

=STANDARD

=STANDARD

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

0.075MM

0.126MM

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

=STANDARD

0.1 MM

0.1 MM

TABLE_PHYSICAL_RULE_ITEM

A

SYNC_MASTER=J44

TABLE_PHYSICAL_RULE_HEAD

SYNC_DATE=08/12/2013

PAGE TITLE

PCB Rule Definitions

TABLE_PHYSICAL_RULE_ITEM

DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

110 OF 120 SHEET

69 OF 78

1

A

8

7

6

5

CPU Signal Constraints ALLOW ROUTE ON LAYER?

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

ELECTRICAL CONST SET

DIFFPAIR NECK GAP

2

3

CPU Signal Properties TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

4

1

PCI Express Properties

NET TYPE PHYSICAL SPACING

ELECTRICAL CONST SET

NET TYPE PHYSICAL SPACING

TABLE_PHYSICAL_RULE_ITEM

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD

*

=27P4_OHM_SE

=27P4_OHM_SE

=27P4_OHM_SE

=27P4_OHM_SE

7 MIL

7 MIL

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

TABLE_SPACING_RULE_HEAD

WEIGHT

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

D

CPU_VCCSENSE

*

25 MIL

TABLE_SPACING_RULE_ITEM

?

CPU_08MIL

*

0.203 MM

? TABLE_SPACING_RULE_ITEM

CPU_12MIL

*

0.305 MM

? TABLE_SPACING_RULE_ITEM

CPU_18MIL

*

0.457 MM

?

CPU_25MIL

*

0.635 MM

?

TABLE_SPACING_RULE_ITEM

PCI Express Constraints ALLOW ROUTE ON LAYER?

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S

CPU_18MIL CPU_18MIL CPU_18MIL

CPU_VCCST_PWRGD CPU_VCCST_PWRGD CPU_BPM CPU_BPM_TP

CPU_45S CPU_45S CPU_45S CPU_45S

CPU_08MIL CPU_08MIL CPU_08MIL

CPU_RCOMP_SM CPU_RCOMP_EDP CPU_RCOMP_OPI

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

XDP_TCK0 XDP_TCK0 XDP_TCK1 XDP_TDO XDP_TDO XDP_TDI XDP_TDI XDP_TMS XDP_TMS XDP_TRST_L XDP_TRST_L XDP_PRDY_L XDP_PREQ_L

DIFFPAIR NECK GAP

CPU_27P4S CPU_27P4S CPU_27P4S

CPU_25MIL CPU_25MIL CPU_12MIL

TABLE_PHYSICAL_RULE_ITEM

PCIE_85D

*

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

CLK_PCIE_85D

*

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

WEIGHT

=3X_DIELECTRIC

?

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

PCIE_2SAME

*

TABLE_SPACING_RULE_ITEM

PCIE_2SAME

TOP,BOTTOM =4X_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

C

PCIE_TXRX

*

=6X_DIELECTRIC

?

PCIE_2OTHER

*

=4X_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

PCIE_TXRX

TOP,BOTTOM =10X_DIELECTRIC

?

PCIE_2OTHER

TOP,BOTTOM =6X_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

PCIE_2CLK

=7X_DIELECTRIC

*

?

PCIE_2CLK

TOP,BOTTOM =10X_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

PCIECLK_2OTHER

*

=7X_DIELECTRIC

CPU_VIDALERT CPU_VIDALERT CPU_VIDSCLK CPU_VIDSCLK CPU_VIDSOUT CPU_VIDSOUT CPU_PECI CPU_PECI CPU_PECI_SMC CPU_PECI_SMC

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

PCIECLK_2OTHER TOP,BOTTOM =10X_DIELECTRIC

?

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_*

*

*

PCIE_2OTHER

PCIE_*

=SAME

*

PCIE_2SAME

TABLE_SPACING_ASSIGNMENT_ITEM

CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S

CPU_18MIL CPU_18MIL CPU_18MIL CPU_18MIL CPU_18MIL CPU_18MIL CPU_18MIL CPU_18MIL CPU_18MIL CPU_18MIL

x

LAYER

CPU_08MIL CPU_08MIL CPU_08MIL

fi

SPACING_RULE_SET

TABLE_SPACING_RULE_HEAD

CPU_45S CPU_45S CPU_45S

CPU_VCCST_PWRGD XDP_CPU_VCCST_PWRGD XDP_BPM_L<1..0> XDP_BPM_L<7..2>

CPU_SM_RCOMP<2..0> MCP_EDP_RCOMP CPU_OPI_RCOMP

CPU_PROCHOT_L CPU_PROCHOT_R_L CPU_CATERR_L

.c

TABLE_SPACING_RULE_HEAD

CPU_PROCHOT CPU_PROCHOT CPU_CATERR

XDP_CPU_TCK PCH_JTAGX XDP_PCH_TCK XDP_CPU_TDO XDP_PCH_TDO XDP_CPU_TDI XDP_PCH_TDI XDP_CPU_TMS XDP_PCH_TMS XDP_TRST_L XDP_CPUPCH_TRST_L XDP_CPU_PRDY_L XDP_CPU_PREQ_L

6 16 12 16 12 16 6 16 12 16 6 16 12 16 6 16 12 16

CPU_VIDALERT_L CPU_VIDALERT_R_L CPU_VIDSCLK CPU_VIDSCLK_R CPU_VIDSOUT CPU_VIDSOUT_R CPU_PECI CPU_PECI_R SMC_PECI_L SMC_PECI_L_R

PCIE_SSD_D2R PCIE_SSD_D2R PCIE_SSD_D2R_PP PCIE_SSD_D2R_PP

PCIE_85D PCIE_85D PCIE_85D PCIE_85D

PCIE_RX PCIE_RX PCIE_RX PCIE_RX

PCIE_SSD_D2R_P<3..1> PCIE_SSD_D2R_N<3..1> PCIE_SSD_D2R_P<0> PCIE_SSD_D2R_N<0>

PCIE_SSD_R2D PCIE_SSD_R2D PCIE_SSD_R2D PCIE_SSD_R2D

PCIE_85D PCIE_85D PCIE_85D PCIE_85D

PCIE_TX PCIE_TX PCIE_TX PCIE_TX

PCIE_SSD_R2D_C_P<3..0> PCIE_SSD_R2D_C_N<3..0> PCIE_SSD_R2D_P<3..0> PCIE_SSD_R2D_N<3..0>

PCIE_TBT_D2R_0 PCIE_TBT_D2R_0 PCIE_TBT_D2R_0 PCIE_TBT_D2R_0 PCIE_TBT_D2R PCIE_TBT_D2R PCIE_TBT_D2R PCIE_TBT_D2R PCIE_TBT_R2D PCIE_TBT_R2D PCIE_TBT_R2D PCIE_TBT_R2D

PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D

PCIE_RX PCIE_RX PCIE_RX PCIE_RX PCIE_RX PCIE_RX PCIE_RX PCIE_RX PCIE_TX PCIE_TX PCIE_TX PCIE_TX

PCIE_TBT_D2R_P<0> PCIE_TBT_D2R_N<0> PCIE_TBT_D2R_C_P<0> PCIE_TBT_D2R_C_N<0> PCIE_TBT_D2R_P<3..1> PCIE_TBT_D2R_N<3..1> PCIE_TBT_D2R_C_P<3..1> PCIE_TBT_D2R_C_N<3..1> PCIE_TBT_R2D_P<3..0> PCIE_TBT_R2D_N<3..0> PCIE_TBT_R2D_C_P<3..0> PCIE_TBT_R2D_C_N<3..0>

PCIE_AP_R2D PCIE_AP_R2D PCIE_AP_R2D PCIE_AP_R2D

PCIE_85D PCIE_85D PCIE_85D PCIE_85D

PCIE_TX PCIE_TX PCIE_TX PCIE_TX

PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N

PCIE_AP_D2R PCIE_AP_D2R

PCIE_85D PCIE_85D

PCIE_RX PCIE_RX

PCIE_AP_D2R_P PCIE_AP_D2R_N

CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE

PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N PCIE_CLK100M_CAMERA_P PCIE_CLK100M_CAMERA_N PCIE_CLK100M_CAMERA_C_P PCIE_CLK100M_CAMERA_C_N PCIE_CLK100M_SSD_P PCIE_CLK100M_SSD_N PCIE_CLK100M_TBT_P PCIE_CLK100M_TBT_N

PCIE_RX PCIE_RX PCIE_RX PCIE_RX PCIE_TX PCIE_TX PCIE_TX PCIE_TX

PCIE_CAMERA_D2R_P PCIE_CAMERA_D2R_N PCIE_CAMERA_D2R_C_P PCIE_CAMERA_D2R_C_N PCIE_CAMERA_R2D_P PCIE_CAMERA_R2D_N PCIE_CAMERA_R2D_C_P PCIE_CAMERA_R2D_C_N

12 30 68

D

12 30 68 12 30 68 12 30 68

16 6 12 16 6 16 6 16

8 16 17 16

12 30 68 12 30 68 30 68 30 68

6 16 6 16

m

*

o

CPU_45S CPU_27P4S

6 5 6

6 36 37 53 6 6 36

8 53 8 8 53

14 23 68 14 23 68 23 23 14 23 68 14 23 68 23 68 23 68 23 68 23 68 14 23 68 14 23 68

63 68

C

63 68 14 63 68 14 63 68

8 8 53 8 6 37

14 63 68 14 63 68

36 37 36 37 37

TABLE_SPACING_ASSIGNMENT_ITEM

CLK_*

*

PCIE_2CLK

a

PCIE_*

TABLE_SPACING_ASSIGNMENT_ITEM

CLK_PCIE

*

*

PCIECLK_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_TX

*_RX

*

PCIE_TXRX TABLE_SPACING_ASSIGNMENT_ITEM

*_TX

*

PCIE_TXRX

in

PCIE_RX

h

CPU_CFG CPU_CFG_PD CPU_CFG CPU_CFG_PD CPU_CFG_3 CPU_CFG CPU_CFG_PD

CPU_MEM_RESET

CPU_VCCSENSE CPU_VCCSENSE

CPU_45S

CPU_27P4S CPU_27P4S

CPU_08MIL

MEM_RESET_L

CPU_VCCSENSE CPU_VCCSENSE

CPU_VCCSENSE_P CPU_VCCSENSE_N

6 16 6 16 6 16 6 16 6 16

CLK_PCIE_85D CLK_PCIE_85D CLK_PCIE_85D CLK_PCIE_85D CLK_PCIE_85D CLK_PCIE_85D CLK_PCIE_85D CLK_PCIE_85D CLK_PCIE_85D CLK_PCIE_85D CLK_PCIE_85D CLK_PCIE_85D

63 63 12 63 68 12 63 68 12 32 68 12 32 68 31 32 31 32 12 30 68 12 30 68 12 23 68 12 23 68

6 16 6 16

20 21 22

8 53 9 53

PCIE_CAMERA_D2R PCIE_CAMERA_D2R PCIE_CAMERA_D2R PCIE_CAMERA_D2R PCIE_CAMERA_R2D PCIE_CAMERA_R2D PCIE_CAMERA_R2D PCIE_CAMERA_R2D

PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D

14 32 68 14 32 68 31 32

B

31 32 31 32 31 32 14 32 14 32

w

w

w

.c

B

CPU_CFG<19..11> CPU_CFG<10..8> CPU_CFG<7..5> CPU_CFG<4> CPU_CFG<3> CPU_CFG<2> CPU_CFG<1..0>

CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S

PCIE_CLK100M_AP PCIE_CLK100M_AP PCIE_CLK100M_AP PCIE_CLK100M_AP PCIE_CLK100M_CAM PCIE_CLK100M_CAM PCIE_CLK100M_CAM PCIE_CLK100M_CAM PCIE_CLK100M_SSD PCIE_CLK100M_SSD PCIE_CLK100M_TBT PCIE_CLK100M_TBT

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

CPU & PCIe Constraints DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

111 OF 120 SHEET

70 OF 78

1

A

7

6

5

4

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

PCH_USB_RBIAS

*

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

USB_85D

*

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

NET TYPE PHYSICAL SPACING

ELECTRICAL CONST SET

TABLE_PHYSICAL_RULE_ITEM

USB_BT USB_BT USB_BT USB_BT

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

WEIGHT

*

=4X_DIELECTRIC

?

LAYER

LINE-TO-LINE SPACING

*

=6X_DIELECTRIC

USB

TOP,BOTTOM =6X_DIELECTRIC

?

USB_RBIAS

TOP,BOTTOM =10X_DIELECTRIC

?

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

USB3_85D

*

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

SPACING_RULE_SET

LAYER

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_HEAD

WEIGHT

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

USB3_2SAME

TOP,BOTTOM =4x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

USB3_TXRX

*

=6X_DIELECTRIC

TABLE_SPACING_RULE_ITEM

?

USB3_TXRX

TOP,BOTTOM =10X_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

USB3_2OTHER

*

=4X_DIELECTRIC

I330 TABLE_SPACING_RULE_ITEM

?

USB3_2OTHER

TOP,BOTTOM =6X_DIELECTRIC

I331

?

USB_EXTA USB_EXTA USB_EXTA USB_EXTA USB_EXTA USB_EXTA USB_EXTB USB_EXTB USB_TPAD USB_TPAD USB_TPAD USB_TPAD

USB USB DEFAULT DEFAULT USB USB USB USB USB USB USB USB USB USB USB USB

USB3_EXTA_D2R USB3_EXTA_D2R USB3_EXTA_R2D USB3_EXTA_R2D USB3_EXTA_R2D USB3_EXTA_R2D USB3_EXTB_D2R USB3_EXTB_D2R USB3_EXTB_R2D USB3_EXTB_R2D

USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D

USB3_RX USB3_RX USB3_TX USB3_TX USB3_TX USB3_TX USB3_RX USB3_RX USB3_TX USB3_TX

USB3_EXTA_D2R_P USB3_EXTA_D2R_N USB3_EXTA_R2D_P USB3_EXTA_R2D_N USB3_EXTA_R2D_C_P USB3_EXTA_R2D_C_N USB3_EXTB_D2R_P USB3_EXTB_D2R_N USB3_EXTB_R2D_C_P USB3_EXTB_R2D_C_N

USB3_SD_D2R USB3_SD_D2R USB3_SD_R2D USB3_SD_R2D

USB3_85D USB3_85D USB3_85D USB3_85D

USB3_RX USB3_RX USB3_TX USB3_TX

USB3RPCIE_SD_D2R_P USB3RPCIE_SD_D2R_N USB3RPCIE_SD_R2D_C_P USB3RPCIE_SD_R2D_C_N

USB_NC USB_NC USB_NC USB_NC USB_NC USB_NC USB_NC USB_NC

USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D

USB USB USB USB USB USB USB USB

NC_USB_IRP NC_USB_IRN TP_USB_5P TP_USB_5N NC_USB_SDP NC_USB_SDN NC_USB_CAMERAP NC_USB_CAMERAN

AREA_TYPE

SPACING_RULE_SET

USB3_*

*

*

USB3_2OTHER

USB3_*

=SAME

*

USB3_2SAME

TABLE_SPACING_ASSIGNMENT_ITEM

C

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

USB3_TX

*_RX

*

USB3_TXRX

USB3_RX

*_TX

*

USB3_TXRX

fi

TABLE_SPACING_ASSIGNMENT_ITEM

a

System Clock Signal Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

CLK_25M_45S

*

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD

in

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=5x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

*

h

CLK_25M

x

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2

NET_SPACING_TYPE1

.c

B SATA Interface Constraints (Not Used)

USB_EXTA_P USB_EXTA_N SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N USB2_EXTA_MUXED_F_P USB2_EXTA_MUXED_F_N USB_LT1_P USB_LT1_N USB_EXTB_P USB_EXTB_N USB_TPAD_P USB_TPAD_N USB_TPAD_R_P USB_TPAD_R_N

USB_85D USB_85D DEFAULT DEFAULT USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D

.c

TABLE_PHYSICAL_RULE_HEAD

=3X_DIELECTRIC

29 63 29 63

D

USB 3 Interface Constraints

*

14 29

TABLE_SPACING_RULE_ITEM

USB_EXTA USB_EXTA

USB3_2SAME

14 29

TABLE_SPACING_RULE_ITEM

?

LINE-TO-LINE SPACING

USB_BT_P USB_BT_N USB_BT_CONN_P USB_BT_CONN_N

WEIGHT

TABLE_SPACING_RULE_ITEM

USB_RBIAS

USB USB USB USB

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

USB

USB_85D USB_85D USB_85D USB_85D

m

D

LAYER

1

USB Constraints

USB 2 Interface Constraints

SPACING_RULE_SET

2

3

o

8

14 33 14 33 33 36 37 33 36 37 33 33 33 33 68 68 14 63 14 63 14 34 14 34 34 34

14 33 68

C

14 33 68 33 33 68 14 33 68 14 33 68 14 63 68 14 63 68 14 63 68 14 63 68

14 63 68 14 63 68 14 63 14 63

14 66 14 66 14 14 14 66 14 66 14 66 14 66

B PCH_USB_RBIAS

PCH_USB_RBIAS

USB_RBIAS

SATA_85D SATA_85D SATA_85D SATA_85D

SATA_RX SATA_RX SATA_TX SATA_TX

PCH_USB_RBIAS

14

TABLE_PHYSICAL_RULE_HEAD

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

SATA_85D

*

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

SATA_45SE

*

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

SPACING_RULE_SET

LAYER

w

PHYSICAL_RULE_SET

ALLOW ROUTE ON LAYER?

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

*

=3X_DIELECTRIC

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM

?

SATA_2SAME

TOP,BOTTOM =4x_DIELECTRIC

SATA_TXRX

TOP,BOTTOM =10X_DIELECTRIC

SATA_2OTHER

TOP,BOTTOM =6X_DIELECTRIC

?

=6X_DIELECTRIC

TABLE_SPACING_RULE_ITEM

? TABLE_SPACING_RULE_ITEM

SATA_2OTHER

*

=4X_DIELECTRIC

?

w

*

Notes: This is here to keep the SATA rules.

WEIGHT

TABLE_SPACING_RULE_ITEM

SATA_TXRX

DUMMY_SATA_D2R_P DUMMY_SATA_D2R_N DUMMY_SATA_R2D_P DUMMY_SATA_R2D_N

TABLE_SPACING_RULE_HEAD

WEIGHT TABLE_SPACING_RULE_ITEM

SATA_2SAME

w

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

?

SYSCLK_CLK25M SYSCLK_CLK25M SYSCLK_CLK25M

CLK_25M_45S CLK_25M_45S CLK_25M_45S

CLK_25M CLK_25M CLK_25M

SYSCLK_CLK25M_X1 SYSCLK_CLK25M_X2 SYSCLK_CLK25M_X2_R

17 17 17

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM

SATA_*

*

*

SATA_2OTHER

SATA_*

=SAME

*

SATA_2SAME

TABLE_SPACING_ASSIGNMENT_ITEM

A

TABLE_SPACING_ASSIGNMENT_ITEM

SATA_TX

*_RX

*

SATA_TXRX

SATA_RX

*_TX

*

SATA_TXRX

TABLE_SPACING_ASSIGNMENT_ITEM

SYSCLK_CLK25M_CAM SYSCLK_CLK25M_CAM SYSCLK_CLK25M_CAM SYSCLK_CLK25M_CAM SYSCLK_CLK25M_CAM SYSCLK_CLK25M_CAM

CLK_25M_45S CLK_25M_45S CLK_25M_45S CLK_25M_45S CLK_25M_45S CLK_25M_45S

CLK_25M CLK_25M CLK_25M CLK_25M CLK_25M CLK_25M

SYSCLK_CLK25M_CAMERA CLK25M_CAM_CLKP CLK25M_CAM_XTALP_R CLK25M_CAM_XTALP CLK25M_CAM_XTALN CLK25M_CAM_CLKN

SYSCLK_CLK25M_TBT SYSCLK_CLK25M_TBT

CLK_25M_45S CLK_25M_45S

CLK_25M CLK_25M

SYSCLK_CLK25M_TBT SYSCLK_CLK25M_TBT_R

17 32 31 32 32 32 32

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

USB Constraints

31 32

DRAWING NUMBER 17 23

Apple Inc.

23 R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

112 OF 120 SHEET

71 OF 78

1

A

8

7

6

5

LPC Bus Constraints LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

*

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

2

1

DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM

LPC_45S

3

PCH Net Properties

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

4

=STANDARD

ELECTRICAL CONST SET

=STANDARD

NET TYPE PHYSICAL SPACING

TABLE_PHYSICAL_RULE_ITEM

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD

LPC_AD LPC_AD LPC_CLK24M_SMC LPC_CLK24M_SMC LPC_CLK24M_LPCPLUS LPC_CLK24M_LPCPLUS

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

6 MIL

?

TABLE_SPACING_RULE_ITEM

LPC

*

TABLE_SPACING_RULE_ITEM

CLK_LPC

D

*

8 MIL

?

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

SMB_45S

*

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD

SPACING_RULE_SET

LAYER

LPC LPC CLK_LPC CLK_LPC CLK_LPC CLK_LPC

SMB_45S SMB_45S SMB_45S SMB_45S SMB_45S SMB_45S

SMB SMB SMB SMB SMB SMB

SMBUS_PCH_CLK SMBUS_PCH_DATA SML_PCH_0_CLK SML_PCH_0_DATA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA

HDA_BIT_CLK HDA_BIT_CLK HDA_SYNC HDA_SYNC HDA_RST HDA_RST HDA_SDIN HDA_SDIN HDA_SDOUT HDA_SDOUT

HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S

HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA

HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 CS4208_HDA_SDOUT0_R HDA_SDOUT HDA_SDOUT_R

SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB_IO2 SPI_MLB_IO2 SPI_MLB_IO3 SPI_MLB_IO3 SPI_MLB_IO3

SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S

SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI

SPI_ALT_CLK SPI_CLK SPI_CLK_R SPI_MLB_CLK SPI_SMC_CLK SPI_ALT_CS_L SPI_CS0_L SPI_CS0_R_L SPI_MLB_CS_L SPI_SMC_CS_L SPI_ALT_MISO SPI_MISO SPI_MISO_R SPI_MLB_MISO SPI_SMC_MISO SPI_ALT_MOSI SPI_MOSI SPI_MOSI_R SPI_MLB_MOSI SPI_SMC_MOSI SPI_IO<2> SPIROM_WP_L SPI_IO<3> SPIROM_HOLD_L SPIROM_USE_MLB

SMBUS_PCH SMBUS_PCH SML_PCH_0 SML_PCH_0

SMBus Interface Constraints TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

WEIGHT TABLE_SPACING_RULE_ITEM

SMB

*

=2x_DIELECTRIC

?

HD Audio Interface Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM

HDA_45S

*

SPACING_RULE_SET

LAYER

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD

?

SPI Interface Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM

C

SPI_45S

*

SPACING_RULE_SET

LAYER

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

WEIGHT TABLE_SPACING_RULE_ITEM

SPI

*

8 MIL

?

PCH Single Net Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

PCH_45S

*

=45_OHM_SE

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

PCH_27P4S

*

SPACING_RULE_SET

LAYER

=27P4_OHM_SE

=27P4_OHM_SE

=27P4_OHM_SE

=27P4_OHM_SE

7 MIL

7 MIL

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

WEIGHT TABLE_SPACING_RULE_ITEM

PCH_12MIL

*

0.305 MM

?

PCH_15MIL

*

0.381 MM

?

in

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

*

PCH_18MIL

0.457 MM

? TABLE_SPACING_RULE_ITEM

*

0.508 MM

?

14 36 45 68 14 36 45 68 12 17 17 36 68 17 45 68 12 17

D

14 16 19 39 63 68 14 16 19 39 63 68 14 39 14 39 14 32 36 39 43 68 76 14 32 36 39 43 68 76

12 47 12 12 47 12 12 12 47 12 47 68 47 12 47 12 17

45 45 14 45 45 36 45 45 45 14 45

C

45 36 45 45 14 45 45 45 36 45 45 45 14 45 45 36 45 14 45 45 14 45 45 15 45 68

h

PCH_20MIL

x

*

fi

=2x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

HDA

a

WEIGHT

.c

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LPC_AD<3..0> LPC_FRAME_L LPC_CLK24M_SMC_R LPC_CLK24M_SMC LPC_CLK24M_LPCPLUS LPC_CLK24M_LPCPLUS_R

LPC_45S LPC_45S CLK_LPC_45S CLK_LPC_45S CLK_LPC_45S CLK_LPC_45S

m

*

o

CLK_LPC_45S

PCH_RTCX PCH_SRTCRST PCH_RTCRST

PCH_45S PCH_45S PCH_45S

PCH_15MIL PCH_15MIL PCH_15MIL

PCH_CLK32K_RTCX1 PCH_SRTCRST_L RTC_RESET_L

PCH_THRMTRIP PCH_THRMTRIP

PCH_45S PCH_45S

PCH_18MIL PCH_18MIL

PM_THRMTRIP_L PM_THRMTRIP_R_L

PCH_45S PCH_45S PCH_45S PCH_45S PCH_45S PCH_45S

PCH_15MIL PCH_15MIL PCH_15MIL PCH_15MIL PCH_15MIL PCH_15MIL

PCH_INTRUDER_L PCH_INTVRMEN PCH_DSWVRMEN PM_RSMRST_L PM_SYSRST_L XDP_DBRESET_L

PCH_45S PCH_45S PCH_45S PCH_45S PCH_45S PCH_45S PCH_45S

PCH_15MIL PCH_15MIL PCH_15MIL PCH_15MIL PCH_15MIL PCH_15MIL PCH_15MIL

PM_PCH_SYS_PWROK XDP_SYS_PWROK SYS_PWROK_R PM_PCH_PWROK PM_S0_PGOOD SMC_DELAYED_PWRGD PM_DSW_PWRGD

PCH_45S PCH_45S PCH_45S PCH_45S PCH_45S PCH_45S

PCH_15MIL PCH_15MIL PCH_15MIL PCH_15MIL PCH_15MIL PCH_15MIL

PM_PWRBTN_L XDP_CPU_PWRBTN_L PCIE_WAKE_L AP_PCIE_WAKE_L CAM_PCIE_WAKE_L TBT_CIO_PLUG_EVENT_L

PCH_45S PCH_45S PCH_45S

PCH_20MIL PCH_20MIL PCH_20MIL

PCH_CLK24M_XTALIN PCH_CLK24M_XTALOUT PCH_CLK24M_XTALOUT_R

w

w

w

.c

B

A

12 17

B

12 12

15 37 37

12 12 13 13 61 13 17 36 68 16 17

13 16 17 36 16 17 13 17 17 17 24 25 36 37 13 36

13 16 36 16 13 29 31 29 63 31

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

PCH Constraints

15 18 23

DRAWING NUMBER

PCH_CLK24M_XTAL PCH_CLK24M_XTAL PCH_CLK24M_XTAL

12 17

Apple Inc.

12 17 R

PCH_RCOMP_PCIE PCH_RCOMP_OPI PCH_RCOMP_SATA

8

7

6

5

PCH_27P4S PCH_27P4S PCH_27P4S

PCH_12MIL PCH_12MIL PCH_12MIL

4

PCH_PCIE_RCOMP PCH_OPI_COMP PCH_SATA_RCOMP



17

NOTICE OF PROPRIETARY PROPERTY: 14 15 12

3

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

2

SIZE

D REVISION

BRANCH

PAGE

113 OF 120 SHEET

72 OF 78

1

A

8

7

6

5

4

Memory Bus Constraints

2

3

1

Memory Net Properties TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

MEM_40S

*

=40_OHM_SE

=40_OHM_SE

=40_OHM_SE

=40_OHM_SE

=STANDARD

=STANDARD

MEM_72D

*

=72_OHM_DIFF

=72_OHM_DIFF

=72_OHM_DIFF

=72_OHM_DIFF

=72_OHM_DIFF

=72_OHM_DIFF

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

*

MEM_45S

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

NET TYPE PHYSICAL SPACING

ELECTRICAL CONST SET

TABLE_PHYSICAL_RULE_ITEM

=STANDARD

MEM_A_CLK MEM_A_CLK MEM_A_CTL

MEM_72D MEM_72D MEM_40S

MEM_CLK MEM_CLK MEM_CTL

MEM_A_CLK_P<0> MEM_A_CLK_N<0> MEM_A_CKE<0>

MEM_A_CTL

MEM_40S

MEM_CTL

MEM_A_CS_L<0>

7 20 22

MEM_A_ODT0

MEM_40S

MEM_CTL

MEM_A_ODT<0>

20 22

MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_DQBYTE0 MEM_A_DQBYTE1 MEM_A_DQBYTE2 MEM_A_DQBYTE3 MEM_A_DQBYTE4 MEM_A_DQBYTE5 MEM_A_DQBYTE6 MEM_A_DQBYTE7 MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7

MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D

MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_A_DQBYTE_0 MEM_A_DQBYTE_1 MEM_A_DQBYTE_2 MEM_A_DQBYTE_3 MEM_A_DQBYTE_4 MEM_A_DQBYTE_5 MEM_A_DQBYTE_6 MEM_A_DQBYTE_7 MEM_A_DQS_0 MEM_A_DQS_0 MEM_A_DQS_1 MEM_A_DQS_1 MEM_A_DQS_2 MEM_A_DQS_2 MEM_A_DQS_3 MEM_A_DQS_3 MEM_A_DQS_4 MEM_A_DQS_4 MEM_A_DQS_5 MEM_A_DQS_5 MEM_A_DQS_6 MEM_A_DQS_6 MEM_A_DQS_7 MEM_A_DQS_7

MEM_A_A<15..0> MEM_A_BA<2..0> MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DQ<7..0> MEM_A_DQ<15..8> MEM_A_DQ<23..16> MEM_A_DQ<31..24> MEM_A_DQ<39..32> MEM_A_DQ<47..40> MEM_A_DQ<55..48> MEM_A_DQ<63..56> MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7>

MEM_B_CLK MEM_B_CLK MEM_B_CTL

MEM_72D MEM_72D MEM_40S

MEM_CLK MEM_CLK MEM_CTL

MEM_B_CLK_P<0> MEM_B_CLK_N<0> MEM_B_CKE<0>

MEM_B_CTL

MEM_40S

MEM_CTL

MEM_B_CS_L<0>

MEM_B_ODT0

MEM_40S

MEM_CTL

MEM_B_ODT<0>

MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_DQBYTE0 MEM_B_DQBYTE1 MEM_B_DQBYTE2 MEM_B_DQBYTE3 MEM_B_DQBYTE4 MEM_B_DQBYTE5 MEM_B_DQBYTE6 MEM_B_DQBYTE7 MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7

MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D

MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_B_DQBYTE_0 MEM_B_DQBYTE_1 MEM_B_DQBYTE_2 MEM_B_DQBYTE_3 MEM_B_DQBYTE_4 MEM_B_DQBYTE_5 MEM_B_DQBYTE_6 MEM_B_DQBYTE_7 MEM_B_DQS_0 MEM_B_DQS_0 MEM_B_DQS_1 MEM_B_DQS_1 MEM_B_DQS_2 MEM_B_DQS_2 MEM_B_DQS_3 MEM_B_DQS_3 MEM_B_DQS_4 MEM_B_DQS_4 MEM_B_DQS_5 MEM_B_DQS_5 MEM_B_DQS_6 MEM_B_DQS_6 MEM_B_DQS_7 MEM_B_DQS_7

MEM_B_A<15..0> MEM_B_BA<2..0> MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ<7..0> MEM_B_DQ<15..8> MEM_B_DQ<23..16> MEM_B_DQ<31..24> MEM_B_DQ<39..32> MEM_B_DQ<47..40> MEM_B_DQ<55..48> MEM_B_DQ<63..56> MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7>

MEM_PWR MEM_PWR MEM_PWR MEM_PWR

PP1V35_S3 PP1V35_S3_CPUDDR PP0V675_S0_DDRVTT PPVTTDDR_S3

MEM_12MIL MEM_12MIL MEM_12MIL MEM_12MIL MEM_12MIL MEM_12MIL MEM_12MIL

CPU_DIMMA_VREFDQ CPU_DIMMA_VREFDQ_A_ISOL CPU_DIMMB_VREFDQ CPU_DIMMB_VREFDQ_B_ISOL CPU_DIMM_VREFCA CPU_DIMM_VREFCA_A_ISOL CPU_DIMM_VREFCA_B_ISOL

MEM_12MIL MEM_12MIL MEM_12MIL MEM_12MIL

PP0V675_S3_MEM_VREFDQ_A PP0V675_S3_MEM_VREFDQ_B PP0V675_S3_MEM_VREFCA_A PP0V675_S3_MEM_VREFCA_B

7 20 22 7 20 22 7 20 22

TABLE_PHYSICAL_RULE_ITEM

MEM_80D

*

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

TABLE_PHYSICAL_RULE_ITEM

=50_OHM_SE

=STANDARD

=STANDARD TABLE_PHYSICAL_RULE_ITEM

MEM_85D

D

*

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

Spacing Rule Sets TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

TABLE_SPACING_RULE_HEAD

WEIGHT

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

MEM_DATA2SELF

*

=2x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

?

MEM_DATA2SELF

TOP,BOTTOM

=5x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

*

MEM_DQS2OWNDATA

=2x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

?

MEM_DQS2OWNDATA

TOP,BOTTOM

=5x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

MEM_CMD2CMD

*

=2x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

?

MEM_CMD2CMD

TOP,BOTTOM

=5x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

MEM_CMD2CTL

*

=2x_DIELECTRIC

?

MEM_CTL2CTL

*

=2x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

MEM_CMD2CTL

TOP,BOTTOM

=5x_DIELECTRIC

?

MEM_CTL2CTL

TOP,BOTTOM

=5x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MEM_CLK2CLK

*

=4x_DIELECTRIC

?

MEM_2OTHERMEM

*

=4x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

MEM_CLK2CLK

TOP,BOTTOM

=8x_DIELECTRIC

?

MEM_2OTHERMEM

TOP,BOTTOM

=8x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MEM_2PWR

*

=2x_DIELECTRIC

?

MEM_2GND

*

=2x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

MEM_2PWR

TOP,BOTTOM

=4x_DIELECTRIC

?

MEM_2GND

TOP,BOTTOM

=4x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MEM_2OTHER

*

TABLE_SPACING_RULE_ITEM

?

=6x_DIELECTRIC

MEM_2OTHER

TOP,BOTTOM

=10x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

MEM_CMD2CMD_BM

*

=2x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

?

MEM_CMD2CMD_BM

TOP,BOTTOM

=3x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

MEM_CMD2CTL_BM

*

=2x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

?

MEM_CMD2CTL_BM

TOP,BOTTOM

=3x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

MEM_CTL2CTL_BM

*

=2x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

?

MEM_CTL2CTL_BM

TOP,BOTTOM

=3x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

MEM_12MIL

*

0.305 MM

?

C Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

*

*

MEM_2OTHER

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_A_DQS_0

MEM_A_DQBYTE_0

*

MEM_DQS2OWNDATA

MEM_A_DQS_1

MEM_A_DQBYTE_1

*

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_*_DQS_*

*

*

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD

*

*

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS_2

MEM_A_DQBYTE_2

*

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTL

*

*

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS_3

MEM_A_DQBYTE_3

*

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK

*

*

MEM_2OTHER

fi

NET_SPACING_TYPE2

MEM_A_DQS_4

MEM_A_DQBYTE_4

*

MEM_DQS2OWNDATA

MEM_A_DQS_5

MEM_A_DQBYTE_5

*

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

=SAME

*

MEM_DATA2SELF

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS_6

MEM_A_DQBYTE_6

*

MEM_DQS2OWNDATA

MEM_A_DQS_7

MEM_A_DQBYTE_7

*

MEM_DQS2OWNDATA

MEM_B_DQS_0

MEM_B_DQBYTE_0

*

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

in

NET_SPACING_TYPE1

MEM_*_DQBYTE_*

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_DQS_1

MEM_B_DQBYTE_1

*

MEM_DQS2OWNDATA

MEM_B_DQS_2

MEM_B_DQBYTE_2

*

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_HEAD

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD

MEM_CMD

*

MEM_CMD2CMD

MEM_CMD

MEM_CTL

*

MEM_CMD2CTL

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_DQS_3

MEM_B_DQBYTE_3

*

MEM_DQS2OWNDATA

MEM_B_DQS_4

MEM_B_DQBYTE_4

*

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTL

MEM_CTL

*

MEM_CTL2CTL

MEM_CLK

MEM_CLK

*

MEM_CLK2CLK

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_DQS_5

MEM_B_DQBYTE_5

*

MEM_DQS2OWNDATA

MEM_B_DQS_6

MEM_B_DQBYTE_6

*

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

B

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_*

MEM_*

*

MEM_2OTHERMEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_DQS_7

MEM_B_DQBYTE_7

*

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD

MEM_CMD

BGA_MEM

MEM_CMD2CMD_BM

MEM_CMD

MEM_CTL

BGA_MEM

MEM_CMD2CTL_BM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTL

BGA_MEM

MEM_CTL2CTL_BM

Unit

Min Length

Max Length

CTLmax - CTLmin CTL to CLK CMDi to CMDj CMD to CLK (DQmax - DQmin) per byte (DQS - DQmax) per byte DQS to DQS# DQS to CLK (Rule 1) Max(CLK-DQS) - Min(CLK-DQS) CLK to CLK#

mils mils mils mils mils mils mils mils mils mils

0 CLK - 500 CMDj - 100 CLK - 500 0 -100 -5 CLK - 6500 0 -5

100 CLK + 500 CMDj + 100 CLK + 500 250 150 5 CLK + 500 5500 5

w

DDR3 Signal Group

w

Haswell ULT Memory Down DDR3L 1x8 Length Matching

w

MEM_CTL

h

AREA_TYPE

.c

NET_SPACING_TYPE2

NET_SPACING_TYPE1

A Memory to Power Spacing TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

D 7 20 22 66 7 20 22 66 7 20 22 66 7 20 22 66 7 20 22 66 7 67 68 7 67 68 7 67 68 7 67 68 7 20 67 68 7 67 68 7 67 68 7 67 68 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 20 67

C

7 20 67 7 67 7 67

7 21 22 7 21 22 7 21 22

7 21 22

TABLE_SPACING_ASSIGNMENT_ITEM

a

NET_SPACING_TYPE1

MEM_*_DQBYTE_*

TABLE_SPACING_ASSIGNMENT_HEAD

m

=50_OHM_SE

o

=50_OHM_SE

=50_OHM_SE

.c

*

x

MEM_50S

SPACING_RULE_SET

I146

21 22

7 21 22 66 7 21 22 66 7 21 22 66 7 21 22 66 7 21 22 66 7 67 68 7 67 68 7 67 68 7 67 68 7 21 67 68 7 67 68 7 67 68 7 67 68 7 67

B

7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 21 67 7 21 67 7 67 7 67

17 19 20 21 22 41 55 65 8 10 41 65 22 55 65 68 55 65 68

7 19 19 7 19 19 7 19 19 19

SYNC_MASTER=J44

MEM_PWR

MEM_*

*

MEM_2PWR

MEM_PWR

*

*

DEFAULT

TABLE_SPACING_ASSIGNMENT_ITEM

Memory to GND Spacing

Memory Constraints

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM

GND

MEM_*

8

*

MEM_2GND

7

DRAWING NUMBER 19 20 65

Apple Inc.

19 21 65 19 20 65 19 21 65

6

5

4

3

2

SIZE

D REVISION

R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

SYNC_DATE=01/03/2013

PAGE TITLE

TABLE_SPACING_ASSIGNMENT_ITEM

BRANCH

PAGE

114 OF 120 SHEET

73 OF 78

1

A

8

7

6

5

4

Thunderbolt, DP, HDMI Constraints

ELECTRICAL CONST SET

Thunderbolt SPI Signal Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM

*

TBT_SPI_45S

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=45_OHM_SE

=STANDARD

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TBT_SPI

*

=2x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

D

I355

Thunderbolt & DisplayPort Constraints

I354 I353

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

2

3

1

Thunderbolt, DP, HDMI Net Properties

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

I352

NET TYPE PHYSICAL SPACING

TBT_A_R2D TBT_A_R2D TBT_A_R2D TBT_A_R2D

TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D

TBTDP_TX TBTDP_TX TBTDP_TX TBTDP_TX

TBT_A_R2D_C_P<1..0> TBT_A_R2D_C_N<1..0> TBT_A_R2D_P<1..0> TBT_A_R2D_N<1..0>

DP_A_LSX_ML DP_A_LSX_ML DP_A_LSX_ML DP_A_LSX_ML DP_A_LSX_ML DP_A_LSX_ML DP_TBTPA_ML DP_TBTPA_ML DP_TBTPA_ML DP_TBTPA_ML

DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D

DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT

DP_TBTPA_ML_C_P<1> DP_TBTPA_ML_C_N<1> DP_TBTPA_ML_P<1> DP_TBTPA_ML_N<1> DP_A_LSX_ML_P<1> DP_A_LSX_ML_N<1> DP_TBTPA_ML_C_P<3> DP_TBTPA_ML_C_N<3> DP_TBTPA_ML_P<3> DP_TBTPA_ML_N<3>

TBT_A_D2R_0 TBT_A_D2R_0 TBT_A_D2R_0 TBT_A_D2R_0 TBT_A_D2R_1 TBT_A_D2R_1 TBT_A_D2R_1 TBT_A_D2R_1 TBT_A_D2R_1 TBT_A_D2R_1

TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D

TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX

TBT_A_D2R_C_P<0> TBT_A_D2R_C_N<0> TBT_A_D2R_P<0> TBT_A_D2R_N<0> TBT_A_D2R_C_P<1> TBT_A_D2R_C_N<1> TBT_A_D2R_P<1> TBT_A_D2R_N<1> TBT_A_D2R1_AUXDDC_P TBT_A_D2R1_AUXDDC_N

DP_TBTPA_AUXCH DP_TBTPA_AUXCH DP_TBTPA_AUXCH DP_TBTPA_AUXCH

DP_85D DP_85D DP_85D DP_85D

23 26 68 23 26 68 26 68 26 68

23 26 23 26 26

D

26 26 26 23 26 23 26 26 26

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

TABLE_SPACING_RULE_HEAD

WEIGHT

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

TBTDP_2SAME

*

=3X_DIELECTRIC

TABLE_SPACING_RULE_ITEM

?

TBTDP_2SAME

TOP,BOTTOM

=4x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

TBTDP_TXRX

*

=6X_DIELECTRIC

?

TBTDP_2OTHER

*

=4X_DIELECTRIC

?

I343 TABLE_SPACING_RULE_ITEM

TBTDP_TXRX

TOP,BOTTOM

=10X_DIELECTRIC

?

TBTDP_2OTHER

TOP,BOTTOM

=6X_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

I342 I341

TABLE_SPACING_RULE_ITEM

I340

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

TBTDP_*

*

*

TBTDP_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TBTDP_*

=SAME

*

TBTDP_2SAME TABLE_SPACING_ASSIGNMENT_ITEM

TBTDP_TX

*_RX

*

TBTDP_TXRX TABLE_SPACING_ASSIGNMENT_ITEM

TBTDP_RX

*_TX

*

TBTDP_TXRX

DisplayPort & HDMI Constraints LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

DP_85D

*

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

HDMI_85D

*

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

TBT_B_R2D TBT_B_R2D TBT_B_R2D TBT_B_R2D

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHT

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

*

=3x_DIELECTRIC

?

DP_2OTHER

*

=4x_DIELECTRIC

?

DP_2SAME

TOP,BOTTOM

=4x_DIELECTRIC

?

DP_2OTHER

TOP,BOTTOM

=6x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

HDMICLK_2OTHER

*

=7x_DIELECTRIC

?

HDMICLK_2DPHDMI

*

=4x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

HDMICLK_2OTHER

TOP,BOTTOM

=10x_DIELECTRIC

?

HDMICLK_2DPHDMI

TOP,BOTTOM

=6x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

HDMIDATA_2SAME

*

=3x_DIELECTRIC

?

HDMIDATA_2OTHER

*

=4x_DIELECTRIC

?

I351

TABLE_SPACING_RULE_ITEM

I350

TABLE_SPACING_RULE_ITEM

HDMIDATA_2SAME

TOP,BOTTOM

=4x_DIELECTRIC

?

HDMIDATA_2OTHER

TOP,BOTTOM

=6x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

I348 I349

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

HDMI_DATA

*

*

HDMIDATA_2OTHER

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

DISPLAYPORT

*

*

DP_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

HDMI_DATA

=SAME

*

HDMIDATA_2SAME

HDMI_DATA

TBTDP_TX

*

HDMIDATA_2SAME

TABLE_SPACING_ASSIGNMENT_ITEM

DISPLAYPORT

=SAME

*

DP_2SAME

DISPLAYPORT

HDMI_DATA

*

DP_2SAME

TABLE_SPACING_ASSIGNMENT_ITEM

TBTDP_RX

*

TBTDP_TXRX

HDMI_CLK

*

*

HDMICLK_2OTHER

I346

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

HDMI_DATA

I347

TABLE_SPACING_ASSIGNMENT_ITEM

DISPLAYPORT

TBTDP_TX

*

DP_2SAME

DISPLAYPORT

TBTDP_RX

*

TBTDP_TXRX

TABLE_SPACING_ASSIGNMENT_ITEM

HDMI_DATA

*

HDMICLK_2DPHDMI TABLE_SPACING_ASSIGNMENT_ITEM

HDMI_CLK

DISPLAYPORT

*

HDMICLK_2DPHDMI

HDMI_CLK

TBTDP_TX

*

HDMICLK_2DPHDMI

TABLE_SPACING_ASSIGNMENT_ITEM

23 26 68 23 26 68 26 68 26 68 23 26 68 23 26 68 26 26

23 26 23 26 26 26

Notes: AUX and DDC was removed from DISPLAYPORT or TBTDP_RX/TX because it’s not high speed, and to save routing space.

I345

I338 I339

DP_85D DP_85D DP_85D DP_85D

DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT

DP_TBTSRC_ML_C_P<3..0> DP_TBTSRC_ML_C_N<3..0> DP_TBTSRC_AUXCH_C_P DP_TBTSRC_AUXCH_C_N

SPI_TBT_CLK SPI_TBT_MOSI SPI_TBT_MISO SPI_TBT_CS_L

TBT_SPI_45S TBT_SPI_45S TBT_SPI_45S TBT_SPI_45S

TBT_SPI TBT_SPI TBT_SPI TBT_SPI

TBT_SPI_CLK TBT_SPI_MOSI TBT_SPI_MISO TBT_SPI_CS_L

DP_HDMI_TBT_ML DP_HDMI_TBT_ML DP_HDMI_TBT_AUX DP_HDMI_TBT_AUX

DP_85D DP_85D DP_85D DP_85D

DISPLAYPORT DISPLAYPORT

DP_HDMI_TBT_ML_P<3..0> DP_HDMI_TBT_ML_N<3..0> DP_HDMI_TBT_AUX_P DP_HDMI_TBT_AUX_N

I336

w

NET TYPE PHYSICAL SPACING

I337 I335 I334 I324

Only used on hosts supporting Thunderbolt video-in

23

w

ELECTRICAL CONST SET

I333

I332 I330 I331

23

I328

23

I329

23

I327 I325

I315 I314 I313 I312

64 66

I326

C

I309 I308 I311 I310

HDMI_IG_CLK_C_P HDMI_IG_CLK_C_N HDMI_IG_DATA_C_P<2..0> HDMI_IG_DATA_C_N<2..0>

7

DP_TBTPB_AUXCH DP_TBTPB_AUXCH DP_TBTPB_AUXCH DP_TBTPB_AUXCH

DP_85D DP_85D DP_85D DP_85D

DP_TBTSNK0_ML DP_TBTSNK0_ML DP_TBTSNK0_ML DP_TBTSNK0_ML DP_TBTSNK_AUXCH DP_TBTSNK_AUXCH DP_TBTSNK_AUXCH DP_TBTSNK_AUXCH

DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D

DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT

DP_TBTSNK1_ML DP_TBTSNK1_ML DP_TBTSNK1_ML DP_TBTSNK1_ML DP_TBTSNK_AUXCH DP_TBTSNK_AUXCH DP_TBTSNK_AUXCH DP_TBTSNK_AUXCH

DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D

DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT

DP_INT_ML DP_INT_ML DP_INT_ML DP_INT_ML DP_INT_AUXCH DP_INT_AUXCH DP_INT_AUXCH DP_INT_AUXCH

DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D

DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT

TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX

TBT_B_D2R_C_P<0> TBT_B_D2R_C_N<0> TBT_B_D2R_P<0> TBT_B_D2R_N<0> TBT_B_D2R_C_P<1> TBT_B_D2R_C_N<1> TBT_B_D2R_P<1> TBT_B_D2R_N<1> TBT_B_D2R1_AUXDDC_P TBT_B_D2R1_AUXDDC_N

27 68

23 27 23 27 27 27 27 27 23 27 23 27 27

Only used on dual-port hosts.

27

27 68 27 68 23 27 68 23 27 68 27 68 27 68 23 27 68 23 27 68 27

DP_TBTPB_AUXCH_C_P DP_TBTPB_AUXCH_C_N DP_TBTPB_AUXCH_P DP_TBTPB_AUXCH_N

27

B

23 27 23 27 27 27

DP_TBTSNK0_ML_C_P<3..0> DP_TBTSNK0_ML_C_N<3..0> DP_TBTSNK0_ML_P<3..0> DP_TBTSNK0_ML_N<3..0> DP_TBTSNK0_AUXCH_C_P DP_TBTSNK0_AUXCH_C_N DP_TBTSNK0_AUXCH_P DP_TBTSNK0_AUXCH_N DP_TBTSNK1_ML_C_P<3..0> DP_TBTSNK1_ML_C_N<3..0> DP_TBTSNK1_ML_P<3..0> DP_TBTSNK1_ML_N<3..0> DP_TBTSNK1_AUXCH_C_P DP_TBTSNK1_AUXCH_C_N DP_TBTSNK1_AUXCH_P DP_TBTSNK1_AUXCH_N

5 23 5 23 23 23 13 23 13 23 23 23

23 64 23 64 23 23 23 64 23 64 23 23

SYNC_DATE=08/12/2013

PAGE TITLE

63 64 68

I319

63 64 68

I320

63 64 68

I321

63 64 68

I322 I323

8

TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D

27 68

SYNC_MASTER=J44 13 64 66

I318

HDMI_CLK HDMI_CLK HDMI_DATA HDMI_DATA

TBT_B_D2R_0 TBT_B_D2R_0 TBT_B_D2R_0 TBT_B_D2R_0 TBT_B_D2R_1 TBT_B_D2R_1 TBT_B_D2R_1 TBT_B_D2R_1 TBT_B_D2R_1 TBT_B_D2R_1

DP_TBTPB_ML_C_P<1> DP_TBTPB_ML_C_N<1> DP_TBTPB_ML_P<1> DP_TBTPB_ML_N<1> DP_B_LSX_ML_P<1> DP_B_LSX_ML_N<1> DP_TBTPB_ML_C_P<3> DP_TBTPB_ML_C_N<3> DP_TBTPB_ML_P<3> DP_TBTPB_ML_N<3>

23 27 68

13 64 66

I317

HDMI_85D HDMI_85D HDMI_85D HDMI_85D

DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT

23 27 68

64 66

I316

HDMI_CLOCK HDMI_CLOCK HDMI_DATA HDMI_DATA

DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D

TBT_B_R2D_C_P<1..0> TBT_B_R2D_C_N<1..0> TBT_B_R2D_P<1..0> TBT_B_R2D_N<1..0>

Max Length 241.3mm.

w

DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. DisplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm. SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04. MAX LENGTH OF DISPLAYPORT/TMDS TRACES: 13 INCHES.

A

26 68

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

HDMI_CLK

I344

TBTDP_TX TBTDP_TX TBTDP_TX TBTDP_TX

DP_B_LSX_ML DP_B_LSX_ML DP_B_LSX_ML DP_B_LSX_ML DP_B_LSX_ML DP_B_LSX_ML DP_TBTPB_ML DP_TBTPB_ML DP_TBTPB_ML DP_TBTPB_ML

a

DP_2SAME

TABLE_SPACING_RULE_ITEM

in

LINE-TO-LINE SPACING

h

LAYER

TABLE_SPACING_RULE_HEAD

.c

SPACING_RULE_SET

TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D

fi

TABLE_PHYSICAL_RULE_ITEM

B

DP_TBTPA_AUXCH_C_P DP_TBTPA_AUXCH_C_N DP_TBTPA_AUXCH_P DP_TBTPA_AUXCH_N

26 68

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

x

C

o

*

.c

TBTDP_85D

m

TABLE_PHYSICAL_RULE_ITEM

6

5

4

DP_INT_ML_C_P<3..0> DP_INT_ML_C_N<3..0> DP_INT_ML_P<3..0> DP_INT_ML_N<3..0> DP_INT_AUXCH_C_P DP_INT_AUXCH_C_N DP_INT_AUX_P DP_INT_AUX_N

3

TBT,DP,HDMI Constraints

5 62

DRAWING NUMBER

5 62 62 68

Apple Inc.

62 68 R



5 62 5 62 62 68 62 68

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

2

SIZE

D REVISION

BRANCH

PAGE

115 OF 120 SHEET

74 OF 78

1

A

8

7

6

5

4

2

3

1

Camera Net Properties ELECTRICAL CONST SET

MIPI Interface Constraints

NET TYPE PHYSICAL SPACING

S2_MEM_CLK S2_MEM_CLK

S2_MEM_85D S2_MEM_85D

S2_MEM_CLK S2_MEM_CLK

MEM_CAM_CLK_P MEM_CAM_CLK_N

S2_MEM_CKE S2_MEM_CS S2_MEM_CMD S2_MEM_CMD S2_MEM_CMD S2_MEM_CMD S2_MEM_CMD S2_MEM_CMD S2_MEM_DQS0 S2_MEM_DQS0 S2_MEM_DQS1 S2_MEM_DQS1 S2_MEM_DATA_0 S2_MEM_DATA_1 S2_MEM_A

S2_MEM_45S S2_MEM_45S S2_MEM_45S S2_MEM_45S S2_MEM_45S S2_MEM_45S S2_MEM_45S S2_MEM_45S S2_MEM_45S S2_MEM_85D S2_MEM_85D S2_MEM_85D S2_MEM_85D S2_MEM_45S S2_MEM_45S S2_MEM_45S

S2_MEM_CTRL S2_MEM_CTRL S2_MEM_CTRL S2_MEM_CTRL S2_MEM_CTRL S2_MEM_CMD S2_MEM_CMD S2_MEM_CMD S2_MEM_CMD S2_MEM_DQS0 S2_MEM_DQS0 S2_MEM_DQS1 S2_MEM_DQS1 S2_MEM_DATA0 S2_MEM_DATA1 S2_MEM_CMD

MEM_CAM_CKE MEM_CAM_CS_L MEM_CAM_ODT MEM_CAM_CAS_L MEM_CAM_RAS_L MEM_CAM_WE_L MEM_CAM_BA<0> MEM_CAM_BA<1> MEM_CAM_BA<2> MEM_CAM_DQS_P<0> MEM_CAM_DQS_N<0> MEM_CAM_DQS_P<1> MEM_CAM_DQS_N<1> MEM_CAM_DM<0> MEM_CAM_DM<1> MEM_CAM_A<14..0>

S2_MEM_DATA_0 S2_MEM_DATA_1

S2_MEM_45S S2_MEM_45S

S2_MEM_DATA0 S2_MEM_DATA1

MEM_CAM_DQ<7..0> MEM_CAM_DQ<15..8>

MIPI_DATA_S2 MIPI_DATA_S2 MIPI_DATA_S2 MIPI_DATA_S2

MIPI_85D MIPI_85D MIPI_85D MIPI_85D

31 32 31 32

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

MIPI_85D

*

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

SPACING_RULE_SET

LAYER

TABLE_PHYSICAL_RULE_ITEM

D

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

WEIGHT

=4X_DIELECTRIC

?

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

MIPI_2OTHER

*

TABLE_SPACING_RULE_ITEM

MIPI_2OTHER

TOP,BOTTOM =6X_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

MIPI_2CLK

*

=6X_DIELECTRIC

TABLE_SPACING_RULE_ITEM

?

MIPI_2CLK

TOP,BOTTOM =8X_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

MIPICLK_2OTHER

*

=7X_DIELECTRIC

TABLE_SPACING_RULE_ITEM

?

MIPICLK_2OTHER

TOP,BOTTOM =10X_DIELECTRIC

?

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM

MIPI_DATA

*

*

MIPI_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM

MIPI_DATA

CLK_MIPI

*

MIPI_2CLK TABLE_SPACING_ASSIGNMENT_ITEM

CLK_MIPI

*

*

MIPICLK_2OTHER

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM

S2_MEM_45S

*

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=45_OHM_SE

=STANDARD TABLE_PHYSICAL_RULE_ITEM

S2_MEM_85D

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF MIPI_CLK_S2 MIPI_CLK_S2 MIPI_CLK_S2 MIPI_CLK_S2

Spacing Rule Sets TABLE_SPACING_RULE_HEAD

WEIGHT

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

S2_DATA2SELF

*

=2x_DIELECTRIC

?

S2_DQS2OWNDATA

*

=2x_DIELECTRIC

?

S2_CMD2CMD

*

=2x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

S2_DATA2SELF TOP,BOTTOM =4x_DIELECTRIC

?

S2_DQS2OWNDATA TOP,BOTTOM =4x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

S2_CMD2CTRL

*

=2x_DIELECTRIC

?

*

=2x_DIELECTRIC

?

TOP,BOTTOM =4x_DIELECTRIC

? TABLE_SPACING_RULE_ITEM

TOP,BOTTOM =4x_DIELECTRIC

?

S2_CTRL2CTRL TOP,BOTTOM =4x_DIELECTRIC

S2_CMD2CTRL

?

S2_2OTHERMEM TOP,BOTTOM =6x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

S2_2OTHERMEM

*

=4x_DIELECTRIC

?

*

=2x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

S2MEM_2PWR

TOP,BOTTOM =4x_DIELECTRIC

?

S2MEM_2GND

TOP,BOTTOM =4x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

S2MEM_2GND

*

=2x_DIELECTRIC

?

S2MEM_2OTHER

*

=6x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

S2_MEM_DQS1

S2_MEM_DATA1

*

S2_DQS2OWNDATA

S2_MEM_DQS0

S2_MEM_DATA0

*

S2_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

S2_MEM_DATA*

*

*

S2MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

S2_MEM_DQS*

*

*

S2MEM_2OTHER

S2_MEM_CMD

*

*

S2MEM_2OTHER

S2_MEM_CTRL

*

*

S2MEM_2OTHER

S2_MEM_CLK

*

*

S2MEM_2OTHER

S2_MEM_DATA*

=SAME

*

S2_DATA2SELF

S2_MEM_CMD

S2_MEM_CMD

*

S2_CMD2CMD

31 32 31 32 31 32 31 32 31 32 31 32 31 32 31 32 31 32 31 32

31 32 31 32

31 32 68 31 32 68 32 68 32 68

31 32 68 31 32 68 32 68

C

32 68

PP0V675_MEM_CAM_VREFCA PP0V675_MEM_CAM_VREFDQ

31 32 31 32 32 32

h

NET_SPACING_TYPE2

31 32

TABLE_SPACING_RULE_ITEM

S2MEM_2OTHER TOP,BOTTOM =10x_DIELECTRIC

Memory Bus Spacing Group Assignments NET_SPACING_TYPE1

PP1V35_CAM PP0V675_CAM_VREF

31 32

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

S2MEM_2PWR

I149

TABLE_SPACING_RULE_ITEM

S2_CMD2CMD TABLE_SPACING_RULE_ITEM

S2_CTRL2CTRL

S2_MEM_PWR S2_MEM_PWR S2_MEM_PWR S2_MEM_PWR

31 32

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

x

LINE-TO-LINE SPACING

CLK_MIPI CLK_MIPI CLK_MIPI CLK_MIPI

MIPI_CLK_P MIPI_CLK_N MIPI_CLK_CONN_P MIPI_CLK_CONN_N

D

32

fi

LAYER

MIPI_DATA_P MIPI_DATA_N MIPI_DATA_CONN_P MIPI_DATA_CONN_N

31 32

a

SPACING_RULE_SET

MIPI_85D MIPI_85D MIPI_85D MIPI_85D

MIPI_DATA MIPI_DATA MIPI_DATA MIPI_DATA

31 32

in

C

*

.c

Memory Bus Constraints

o

PHYSICAL_RULE_SET

m

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

B

.c

B

Memory to Power Spacing TABLE_SPACING_ASSIGNMENT_HEAD

S2_MEM_CMD

S2_MEM_CTRL

*

S2_CMD2CTRL

S2_MEM_CTRL

S2_MEM_CTRL

*

S2_CTRL2CTRL

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

S2_MEM_PWR

S2_MEM_*

*

S2MEM_2PWR

S2_MEM_PWR

*

*

DEFAULT

w

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

S2_MEM_*

S2_MEM_*

*

S2_2OTHERMEM

w

Memory to GND Spacing

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

GND

S2_MEM_*

*

S2MEM_2GND

w

TABLE_SPACING_ASSIGNMENT_ITEM

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

Camera Constraints DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

116 OF 120 SHEET

75 OF 78

1

A

8

7

6

5

4

2

3

1

SMC SMBus & Charger Net Properties NET TYPE PHYSICAL

ELECTRICAL CONST SET SMBUS_SMC_2 SMBUS_SMC_2 SMBUS_SMC_1 SMBUS_SMC_1 SMBUS_SMC_0 SMBUS_SMC_0 SMBUS_SMC_5 SMBUS_SMC_5 SMBUS_SMC_3 SMBUS_SMC_3

SPACING SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB

SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA

34 36 39 68 34 36 39 68 14 32 36 39 43 68 72 14 32 36 39 43 68 72 36 39 62 68

D

36 39 62 68 36 39 51 52 68 36 39 51 52 68 36 39 43 63 36 39 43 63

.c

o

m

D

SMB_45S SMB_45S SMB_45S SMB_45S SMB_45S SMB_45S SMB_45S SMB_45S SMB_45S SMB_45S

C

h

in

a

fi

x

C

B

w

w

w

.c

B

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

SMC Constraints DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

117 OF 120 SHEET

76 OF 78

1

A

8

7

6

5

4

2

3

1

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

SENSE_45S

*

=1TO1_DIFFPAIR

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

0.1 MM

0.1 MM

THERM_45S

*

=1TO1_DIFFPAIR

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

0.1 MM

0.1 MM

DIG_AUDIO

*

=1TO1_DIFFPAIR

0.1 MM

0.1 MM

TABLE_PHYSICAL_RULE_ITEM

J44 Specific Net Properties

TABLE_PHYSICAL_RULE_ITEM

ELECTRICAL CONST SET TABLE_PHYSICAL_RULE_ITEM

=1TO1_DIFFPAIR =1TO1_DIFFPAIR =1TO1_DIFFPAIR

NET TYPE PHYSICAL

J44 Specific Net Properties ELECTRICAL CONST SET

SPACING

NET TYPE PHYSICAL

SPACING

TABLE_PHYSICAL_RULE_ITEM

ANL_AUDIO

*

=1TO1_DIFFPAIR

0.1 MM

0.1 MM

10 MM

0.1 MM

0.1 MM

ANL_AUDIO_WIDE

*

=1TO1_DIFFPAIR

0.3 MM

0.3 MM

10 MM

0.1 MM

0.1 MM

D TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

*

=2X_DIELECTRIC

THERM THERM THERM THERM THERM THERM

TBTTHMSNS_D1_P TBTTHMSNS_D1_N CPUTHMSNS_D1_P CPUTHMSNS_D1_N CPUTHMSNS_D2_P CPUTHMSNS_D2_N

23 43 43 43 43 43

NET_SPACING_TYPE2

NET_SPACING_TYPE1

AREA_TYPE

SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM

?

CPU_VCCSENSE

GND

*

GND_P2MM

TABLE_SPACING_RULE_ITEM

THERM

*

=2X_DIELECTRIC

?

SENSE_45S SENSE_45S SENSE_45S SENSE_45S

TABLE_SPACING_RULE_ITEM

AUDIO

*

=2X_DIELECTRIC

?

SENSE_DP SENSE_DP

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

CLK_PCIE

GND

*

GND_P2MM

SENSE SENSE SENSE SENSE

NC_ISNS_CAMERAP NC_ISNS_CAMERAN ISNS_CPUDDR_P ISNS_CPUDDR_N

42 42

41

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

*

=STANDARD

?

GND

PCIE_*

*

GND_P2MM

GND

SATA_*

*

GND_P2MM

SENSE_DP_LCDBKLT SENSE_DP_LCDBKLT SENSE_DP_TBT SENSE_DP_TBT SENSE_DP SENSE_DP

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

USB

GND

*

GND_P2MM

CLK_PCIE

SB_POWER

*

PWR_P2MM

SB_POWER

SATA_*

*

PWR_P2MM

USB

SB_POWER

*

PWR_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

GND_P2MM

*

0.20 MM

1000

SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S

SENSE SENSE SENSE SENSE SENSE SENSE

ISNS_LCDBKLT_P ISNS_LCDBKLT_N ISNS_TBT_P ISNS_TBT_N ISNS_LCDPANEL_P ISNS_LCDPANEL_N

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

PWR_P2MM

*

0.20 MM

1000

40 58 40 58 42

42 62 42 62

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM

MEM_45S

*

OVERRIDE

OVERRIDE

MEM_40S

*

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

0.070 MM

100 MIL

OVERRIDE

OVERRIDE

0.090 MM

100 MIL

OVERRIDE

OVERRIDE

0.090 MM

100 MIL

OVERRIDE

OVERRIDE

0.090 MM

100 MIL

OVERRIDE

SENSE SENSE SENSE SENSE SENSE SENSE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

*

OVERRIDE

OVERRIDE

MEM_85D

*

SENSE_DP_CPUVR SENSE_DP_CPUVR SENSE_DP_CPUVR SENSE_DP_CPUVR

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE

OVERRIDE

PCIE_85D

*

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

0.090 MM

10 MM

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE

OVERRIDE

SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S

TABLE_PHYSICAL_RULE_ITEM

TOP

0.100 MM

500 MIL

a

USB_85D

TABLE_PHYSICAL_RULE_ITEM

CPU_27P4S

BOTTOM

0.230 MM

100 MIL

USB3_85D

TOP

0.100 MM

500 MIL

SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE

TABLE_PHYSICAL_RULE_ITEM

CPUVR_ISNS_P CPUVR_ISNS_N CPUVR_ISNS_R_P CPUVR_ISNS_R_N CPUVR_ISNS1_P CPUVR_ISNS1_N CPUVR_ISNS2_P CPUVR_ISNS2_N

fi

MEM_72D

40 42 40 42

40 40 40

41

0.075 MM

0.090 MM

DP_85D

ISL9

0.075 MM

0.090 MM

TABLE_PHYSICAL_RULE_ITEM

SENSE_DP SENSE_DP SENSE_DP SENSE_DP SENSE_DP SENSE_DP

TABLE_PHYSICAL_RULE_ITEM

ISL10

0.075 MM

0.090 MM

SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S

SENSE SENSE SENSE SENSE SENSE SENSE

ISNS_1V05_S0_P ISNS_1V05_S0_N ISNS_SSD_P ISNS_SSD_N ISNS_TPAD_P ISNS_TPAD_N

DDR3 Loaded Segment Constraint Relaxations Alternate single ended and differential impedances between devices. PHYSICAL_RULE_SET TABLE_PHYSICAL_ASSIGNMENT_ITEM

MEM_40S

BGA_MEM

MEM_45S TABLE_PHYSICAL_ASSIGNMENT_ITEM

MEM_72D

BGA_MEM

SENSE_DP SENSE_DP SENSE_DP SENSE_DP

SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S

SENSE SENSE SENSE SENSE SENSE SENSE

NC_ISNS_DDR_S3P NC_ISNS_DDR_S3N ISNS_PP3V3S0_P ISNS_PP3V3S0_N ISNS_PP5VS0_P ISNS_PP5VS0_N

SENSE_DP_CPUHIGAIN SENSE_DP_CPUHIGAIN SENSE_DP_CPUHIGAIN SENSE_DP_CPUHIGAIN

SENSE_45S SENSE_45S SENSE_45S SENSE_45S

SENSE SENSE SENSE SENSE

ISNS_CPUHIGAIN_P ISNS_CPUHIGAIN_N ISNS_CPUHIGAIN_R_P ISNS_CPUHIGAIN_R_N

SENSE_DP_CHGR_CSI SENSE_DP_CHGR_CSI SENSE_DP_CHGR_CSI SENSE_DP_CHGR_CSI SENSE_DP_CHGR_CSO SENSE_DP_CHGR_CSO SENSE_DP_CHGR_CSO SENSE_DP_CHGR_CSO

SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S

SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE

CHGR_CSI_P CHGR_CSI_N CHGR_CSI_R_P CHGR_CSI_R_N CHGR_CSO_P CHGR_CSO_N CHGR_CSO_R_P CHGR_CSO_R_N

.c

B

AREA_TYPE

MEM_85D

AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO

AUD_LO2_R_P AUD_LO2_R_N AUD_SPKRAMP_RIN_P AUD_SPKRAMP_RIN_N SPKRAMP_RIN_P SPKRAMP_RIN_N

AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB

ANL_AUDIO ANL_AUDIO ANL_AUDIO ANL_AUDIO ANL_AUDIO ANL_AUDIO

AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO

AUD_LO3_L_P AUD_LO3_L_N AUD_SPKRAMP_LSUBIN_P AUD_SPKRAMP_LSUBIN_N LSUBIN_P LSUBIN_N

AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB

ANL_AUDIO ANL_AUDIO ANL_AUDIO ANL_AUDIO ANL_AUDIO ANL_AUDIO

AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO

AUD_LO3_R_P AUD_LO3_R_N AUD_SPKRAMP_RSUBIN_P AUD_SPKRAMP_RSUBIN_N RSUBIN_P RSUBIN_N

AUDIO_DP_SPKSUB AUDIO_DP_SPKSUB AUDIO_DP_SPKSUB AUDIO_DP_SPKSUB AUDIO_DP_SPKTWT AUDIO_DP_SPKTWT AUDIO_DP_SPKTWT AUDIO_DP_SPKTWT

DIG_AUDIO DIG_AUDIO DIG_AUDIO DIG_AUDIO DIG_AUDIO DIG_AUDIO DIG_AUDIO DIG_AUDIO

AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO

SPKRCONN_SL_OUT_P SPKRCONN_SL_OUT_N SPKRCONN_SR_OUT_P SPKRCONN_SR_OUT_N SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N

AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC

ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE

AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO

AUD_CH_HS_GND AUD_CONN_HS_MIC_P AUD_CONN_SLEEVE AUD_CONN_SLEEVE_XW AUD_HP_PORT_REFCH AUD_HS_MIC_P CODEC_HS_MIC_P HS_MIC_P

AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC

ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE

AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO

AUD_CONN_HS_MIC_N AUD_CONN_RING2 AUD_CONN_RING2_XW AUD_HP_PORT_REFUS AUD_HS_MIC_N AUD_US_HS_GND HS_MIC_N CODEC_HS_MIC_N

SB_POWER SB_POWER

PP3V3_S5 PP3V3_S0

48 48

D

48 48

46 48 46 48 48 48 48 48

46 48 46 48 48 48 48 48

46 48 46 48 48 48 48 48

48 50 68 48 50 68

C

48 50 68 48 50 68 48 50 68 48 50 68 48 50 68 48 50 68

41 41 54 41 54 41 54 41 54

46 50

50 49 50 46 50 49 50 46 46 49

41 57 41 57 41 41

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE

ANL_AUDIO ANL_AUDIO ANL_AUDIO ANL_AUDIO ANL_AUDIO ANL_AUDIO

46 48

41

h

PCIE_85D

in

ISL10

AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT

46 48

41

TABLE_PHYSICAL_RULE_ITEM

USB3_85D

AUD_LO2_L_P AUD_LO2_L_N AUD_SPKRAMP_LIN_P AUD_SPKRAMP_LIN_N SPKRAMP_LIN_P SPKRAMP_LIN_N

40

OVERRIDE TABLE_PHYSICAL_RULE_ITEM

OVERRIDE

ISNS_HS_COMPUTING_P ISNS_HS_COMPUTING_N ISNS_HS_OTHER5V_P ISNS_HS_OTHER5V_N ISNS_HS_OTHER3V3_P ISNS_HS_OTHER3V3_N

x

C

SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S

.c

TABLE_SPACING_ASSIGNMENT_ITEM

SENSE_DP SENSE_DP SENSE_DP SENSE_DP SENSE_DP SENSE_DP

AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO

42

o

GND

TABLE_SPACING_ASSIGNMENT_ITEM

m

LAYER

ANL_AUDIO ANL_AUDIO ANL_AUDIO ANL_AUDIO ANL_AUDIO ANL_AUDIO

41

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT

43

TABLE_SPACING_ASSIGNMENT_HEAD

WEIGHT TABLE_SPACING_RULE_ITEM

SENSE

THERM_45S THERM_45S THERM_45S THERM_45S THERM_45S THERM_45S

THERM_DP_TBT_D1 THERM_DP_TBT_D1 THERM_DP_CPU_D1 THERM_DP_CPU_D1 THERM_DP_CPU_D2 THERM_DP_CPU_D2

TABLE_PHYSICAL_RULE_ITEM

50 49 50 46 50 49 50 46 50 46 49 46

B

41 55 41 55 41 41 41

8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 61 62 64 65 68 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

41

w

Allow 0.127 mm necks for >0.127 mm lines for ARD fanout. TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

TABLE_PHYSICAL_RULE_ITEM

MEM_72D

BOTTOM

0.127 MM

6.35 MM

TABLE_PHYSICAL_RULE_ITEM

TOP

0.100 MM

6.35 MM

w

MEM_85D

DP, SATA, HDMI, PCIE CONSTRAINT RELAXATIONS

w

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff) TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE

AREA_TYPE

PHYSICAL_RULE_SET TABLE_PHYSICAL_ASSIGNMENT_ITEM

DP_85D

BGA

P65_BGA

PCIE_85D

BGA

P65_BGA

42 43 42 43 42 42

52 52 52 52 52 52 42 52

GND

GND

42 52

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

CLK_PCIE_85D

BGA

P65_BGA

HDMI_85D

BGA

P65_BGA

NET_PHYSICAL_TYPE

AREA_TYPE

PHYSICAL_RULE_SET

SENSE_45S

*

SENSE_45S

THERM_45S

*

THERM_45S

DIG_AUDIO

*

DIG_AUDIO

ANL_AUDIO

*

ANL_AUDIO

1TO1_DIFFPAIR

*

1TO1_DIFFPAIR

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

A

SYNC_MASTER=J44

TABLE_PHYSICAL_ASSIGNMENT_ITEM

SYNC_DATE=08/12/2013

PAGE TITLE

Project Specific Constraints

TABLE_PHYSICAL_ASSIGNMENT_ITEM

DRAWING NUMBER

TABLE_PHYSICAL_ASSIGNMENT_ITEM

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

118 OF 120 SHEET

77 OF 78

1

A

8

7

6

5

4

3

2

1

Change List: J44 HW EE SCHEMATIC | PROTO 0

D

D

Kismet: AFP://KISMET.APPLE.COM/KISMET-PROJECTS/J44

Useful Wiki Links:

m

Schematic Conventions - https://hmts.ecs.apple.com/wiki/index.php/User:Wferry/SchConventions Schematic Design Wiki - https://hmts.ecs.apple.com/wiki/index.php/Schematic_Design

HW HW HW HW HW HW

| | | | | |

Task Schematic New Bugs Layout Investigation Architecture

.c

MobileMac MobileMac MobileMac MobileMac MobileMac MobileMac

C

x

C



o

MobileMac HW Radar:

fi

Other Info:

h

in

a

Page Allocations - 2012 Schematic Page Allocations

B

w

w

w

.c

B

A

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PAGE TITLE

Reference DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

SIZE

D REVISION

BRANCH

PAGE

120 OF 120 SHEET

78 OF 78

1

A