8 bit Load Group Mnemonic LD r, r’ LD p, p’*
Symbolic Operation r r’ p p’
Flags S Z YF H XF P/V N C • • • • • • • • • • • • • • • •
LD q, q’*
q q’
• •
•
•
•
•
•
•
LD r, n
rn
• •
•
•
•
•
•
•
LD p, n*
pn
• •
•
•
•
•
•
•
LD q, n*
qn
• •
•
•
•
•
•
•
LD r, (HL) LD r, (IX + d)
r (HL) r (IX + d)
• • • •
• •
• •
• •
• •
• •
• •
LD r, (IY + d)
r (IY + d)
• •
•
•
•
•
•
•
LD (HL), r LD (IX + d), r
(HL) r (IX + d) r
• • • •
• •
• •
• •
• •
• •
• •
LD (IY + d), r
(IY + d) r
• •
•
•
•
•
•
•
LD (HL), n
(HL) n
• •
•
•
•
•
•
•
LD (IX + d), n
(IX + d) n
• •
•
•
•
•
•
•
LD (IY + d), n
(IY + d) n
• •
•
•
•
•
•
•
LD A, (BC) LD A, (DE) LD A, (nn)
A (BC) A (DE) A (nn)
• • • • • •
• • •
• • •
• • •
• • •
• • •
• • •
LD (BC), A LD (DE), A LD (nn), A
(BC) A (DE) A (nn) A
• • • • • •
• • •
• • •
• • •
• • •
• • •
• • •
LD A, I
AI
0
IFF2 0
•
LD A, R
AR
0
IFF2 0
•
Opcode 76 543 210 01 r r’ 11 011 101 01 p p’ 11 111 101 01 q q’ 00 r 110 n 11 011 101 00 p 110 n 11 111 101 00 q 110 n 01 r 110 11 011 101 01 r 110 d 11 111 101 01 r 110 d 01 110 r 11 011 101 01 110 r d 11 111 101 01 110 r d 00 110 110 n 11 011 101 00 110 110 d n 11 111 101 00 110 110 d n 00 001 010 00 011 010 00 111 010 n n 00 000 010 00 010 010 00 110 010 n n 11 101 101 01 010 111 11 101 101 01 011 111
No. of M Cycles 1 2
No. of T States 4 8
T States
DD
No. of Bytes 1 2
FD
2
2
8
4,3
2
2
7
4,3
DD
3
3
11
4,3,3
FD
3
3
11
4,3,3
DD
1 3
2 5
7 19
4,3 4,4,3,5,3
FD
3
5
19
4,4,3,5,3
Hex
4 4,4
DD
1 3
2 5
7 19
4,3 4,4,3,5,3
FD
3
5
19
4,4,3,5,3
36
2
3
10
4,3,3
DD 36
4
5
19
4,4,3,5,3
FD 36
4
5
19
4,4,3,5,3
0A 1A 3A
1 1 3
2 2 4
7 7 13
4,3 4,3 4,3,3,3
02 12 32
1 1 3
2 2 4
7 7 13
4,3 4,3 4,3,3,3
ED 57 ED 5F
2
2
9
4,5
2
2
9
4,5
Comments r, r’ Reg. 000 B 001 C 010 D 011 E 100 H 101 L 111 A p, p’ 000 001 010 011 100 101 111
Reg. B C D E IXH IXL A
q, q’ 000 001 010 011 100 101 111
Req. B C D E IYH IYL A
R is read after it is increased.
LD I, A
IA
• •
•
•
LD R, A
RA
• •
•
•
Notes:
Flag Notation:
•
•
•
•
11 101 101 ED 2 2 9 01 000 111 47 • • • • 11 101 101 ED 2 2 9 01 001 111 4F r, r’ means any of the registers A, B, C, D, E, H, L. p, p’ means any of the registers A, B, C, D, E, IXH, IXL. q, q’ means any of the registers A, B, C, D, E, IYH, IYL. ddL, ddH refer to high order and low order eight bits of the register respectively.. = flag is set according to the result of the operation, IFF2 = the interrupt flip-flop 2 is copied.
4,5 4,5
R is written after it is increased.
16 bit Load Group Mnemonic LD dd, nn
Symbolic Operation dd nn
Flags S Z YF H XF P/V N C • • • • • • • •
LD IX, nn
IX nn
• •
•
•
•
•
•
•
LD IY, nn
IY nn
• •
•
•
•
•
•
•
LD HL, (nn)
L (nn) H (nn+1)
• •
•
•
•
•
•
•
LD dd, (nn)
ddL (nn) ddH (nn+1)
• •
•
•
•
•
•
•
LD IX, (nn)
IXL (nn) IXH (nn+1)
• •
•
•
•
•
•
•
LD IY, (nn)
IYL (nn) IYH (nn+1)
• •
•
•
•
•
•
•
LD (nn), HL
(nn) L (nn+1) H
• •
•
•
•
•
•
•
LD (nn), dd
(nn) ddL (nn+1) ddH
• •
•
•
•
•
•
•
LD (nn), IX
(nn) IXL (nn+1) IXH
• •
•
•
•
•
•
•
LD (nn), IY
(nn) IYL (nn+1) IYH
• •
•
•
•
•
•
•
LD SP, HL
SP HL
• •
•
•
•
•
•
•
Opcode 76 543 210 00 dd0 001 n n 11 011 101 00 110 001 n n 11 111 101 00 110 001 n n 00 101 010 n n 11 101 101 01 dd1 011 n n 11 011 101 00 101 010 n n 11 111 101 00 101 010 n n 00 100 010 n n 11 101 101 01 dd0 011 n n 11 011 101 00 100 010 n n 11 111 101 00 100 010 n n 11 111 001
No. of Bytes 3
No. of M Cycles 3
No. of T States 10
T States
DD 21
4
4
14
4,4,3,3
FD 21
4
4
14
4,4,3,3
2A
3
5
16
4,3,3,3,3
ED
4
6
20
4,4,3,3,3,3
DD 2A
4
6
20
4,4,3,3,3,3
FD 2A
4
6
20
4,4,3,3,3,3
22
3
5
16
4,3,3,3,3
DD
4
6
20
4,4,3,3,3,3
DD 22
4
6
20
4,4,3,3,3,3
FD 22
4
6
20
4,4,3,3,3,3
F9
1
1
6
6
Hex
4,3,3
Comments dd Pair 00 BC 01 DE 10 HL 11 SP
LD SP, IX
SP IX
• •
•
•
•
•
•
•
LD SP, IY
SP IY
• •
•
•
•
•
•
•
11 011 101 11 111 001 11 111 101 11 111 001
PUSH qq
SP SP - 1 (SP) qqH SP SP - 1 (SP) qqL SP SP - 1 (SP) IXH SP SP - 1 (SP) IXL SP SP - 1 (SP) IYH SP SP - 1 (SP) IYL
• •
•
•
•
•
•
•
11 qq0 101
• •
•
•
•
•
•
•
11 011 101 11 100 101
• •
•
•
•
•
•
•
11 111 101 11 100 101
(SP) qqL SP SP + 1 (SP) qqH SP SP + 1 (SP) IXL SP SP + 1 (SP) IXH SP SP + 1 (SP) IYL SP SP + 1 (SP) IYH SP SP + 1
• •
•
•
•
•
•
•
11 qq0 001
• •
•
•
•
•
•
•
11 011 101 11 100 001
• •
•
•
•
•
•
•
11 111 101 11 100 001
PUSH IX
PUSH IY
POP qq
POP IX
POP IY
Notes: Flag Notation:
DD F9 FD F9
2
2
10
4,6
2
2
10
4,6
1
3
11
5,3,3
DD E5
2
4
15
4,5,3,3
FD E5
2
4
15
4,5,3,3
1
3
10
4,3,3
DD E1
2
4
14
4,4,3,3
FD E1
2
4
14
4,4,3,3
dd is any of the register pair BC, DE, HL, SP. qq is any of the register pair BC, DE, HL, AF. • = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation.
qq 00 01 10 11
Pair BC DE HL AF
Exchange, Block Transfer and Search Groups Mnemonic EX DE, HL EX AF, AF’ EXX
EX (SP), HL EX (SP), IX EX (SP), IY LDI
LDIR
LDD
LDDR
CPI
CPIR
CPD
CPDR
Notes:
Flag Notation:
Symbolic Operation DE HL AF AF’ BC BC’ DE DE’ HL HL’ (SP+1) H (SP) L (SP+1) IXH (SP) IXL (SP+1) IYH (SP) IYL (DE) (HL) DE DE + 1 HL HL + 1 BC BC - 1 (DE) (HL) DE DE + 1 HL HL + 1 BC BC – 1 (DE) (HL) DE DE - 1 HL HL - 1 BC BC – 1 (DE) (HL) DE DE - 1 HL HL - 1 BC BC – 1 A - (HL) HL HL + 1 BC BC -1 A - (HL) HL HL + 1 BC BC -1 Repeat until: A = (HL) or BC = 0 A - (HL) HL HL - 1 BC BC -1 A - (HL) HL HL - 1 BC BC -1 Repeat until: A = (HL) or BC = 0
S • • •
Z YF H • • • • • • • • •
Flags XF P/V • • • • • •
C • • •
Opcode 76 543 210 11 101 011 00 001 000 11 011 001
Hex EB 08 D9
No.of Bytes 1 1 1
No.of M Cycles 1 1 1
No.of T States 4 4 4
T States
N • • •
Comments 4 4 4
• •
•
•
•
•
•
•
11 100 011
E3
1
5
19
4,3,4,3,5
• •
•
•
•
•
•
•
6
23
4,4,3,4,3,5
•
•
•
•
•
•
2
6
23
4,4,3,4,3,5
• •
1 0
2 3 0
•
DD E3 FD E3 ED A0
2
• •
11 011 101 11 100 011 11 111 101 11 100 011 11 101 101 10 100 000
2
4
16
4,4,3,5
• •
1 0
2 0
0
•
11 101 101 10 110 000
ED B0
2 2
5 4
21 16
4,4,3,5,5 4,4,3,5
if BC 0 if BC = 0
Repeat until BC=0 • •
1 0
2 3 0
•
11 101 101 10 101 000
ED A8
2
4
16
4,4,3,5
• •
1 0
2 0
0
•
11 101 101 10 111 000
ED B8
2 2
5 4
21 16
4,4,3,5,5 4,4,3,5
4 4 5 4 6 3 1
•
11 101 101 10 100 001
ED A1
2
4
16
4,4,3,5
4 4 5 4 6 3 1
•
11 101 101 10 110 001
ED B1
2
5
21
4,4,3,5,5
2
4
16
4,4,3,5
if BC 0 if BC = 0
Repeat until BC=0
4 4 5 4 6 3 1
•
11 101 101 10 101 001
ED A9
2
4
16
4,4,3,5
4 4 5 4 6 3 1
•
11 101 101 10 111 001
ED B9
2
5
21
4,4,3,5,5
2
4
16
4,4,3,5
1
YF is a copy of bit 1 of A + last transferred byte, thus (A + (HL))1 XF is a copy of bit 3 of A + last transferred byte, thus (A + (HL))3 3 P/V flag is 0 if the result of BC - 1 = 0, otherwise P/V = 1. 4 These flags are set as in CP (HL) 5 YF is copy of bit 1 of A - last compared address - H, thus (A - (HL) - H)1. H is as in F after the comparison. 6 XF is copy of bit 3 of A - last compared address - H, thus (A - (HL) - H)3. H is as in F after the comparison. • = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation. 2
if BC 0 and A (HL). if BC = 0 or A = (HL)
if BC 0 and A (HL). if BC = 0 or A = (HL)
8 bit Arithmetic and Logical Group Mnemonic ADD A, r ADD A, p*
Symbolic Operation AA+r AA+p
Flags S Z YF H XF P/V N C V 0 V 0
ADD A, q*
AA+q
V
0
ADD A, n
AA+n
V
0
ADD A, (HL) ADD A, (IX + d)
A A + (HL) A A + (IX + d)
V V
0 0
ADD A, (IY + d)
A A + (IY + d)
V
0
ADC A, s SUB A, s SBC A, s AND s OR s XOR s CP s INC r INC p*
A A + s + CY AA- s A A - s - CY A A AND s A A OR s A A XOR s A-s rr+1 p p+1
1
1
V V V P P P V V V
0 1 1 0 0 0 1 0 0
0 0 0 • •
INC q*
q q+1
V
0
•
INC (HL) INC (IX + d)
(HL) (HL) + 1 (IX + d) (IX + d) + 1
V V
0 0
• •
INC (IY + d)
(IY + d) (IY + d) + 1
V
0
•
DEC m
mm-1
V
1
•
Notes: Flag Notation:
1
1 0 0
Opcode 76 543 210 10 000 r 11 011 101 10 000 p 11 111 101 10 000 q 11 000 110 n 10 000 110 11 011 101 10 000 110 d 11 111 101 10 000 110 d 001 010 011 100 110 101 111 00 r 100 11 011 101 00 p 100 11 111 101 00 q 100 00 110 100 11 011 101 00 110 100 d 11 111 101 00 110 100 d 101
No.of M Cycles 1 2
No.of T States 4 8
T States
DD
No.of Bytes 1 2
FD
2
2
8
4,4
2
2
7
4,3
DD
1 3
2 5
7 19
4,3 4,4,3,5,3
FD
3
5
19
4,4,3,5,3
Hex
4 4,4
Comments r Reg. 000 B 001 C 010 D 011 E 100 H 101 L 111 A
p 000 001 010 011 100 101 111
Reg. B C D E IXH IXL A
s is any of r, n, (HL), (IX+d), (IY+d), p, q as shown for the ADD instruction. The underlined bits replace the underlined bits in the ADD set. DD
1 2
1 2
4 8
4 4,4
FD
2
2
8
4,4
DD
1 3
3 6
11 23
4,4,3 4,4,3,5,4,3
FD
3
6
23
4,4,3,5,4,3
q 000 001 010 011 100 101 111
Reg. B C D E IYH IYL A
m is any of r, p, q, (HL), (IX+d), (IY+d), as shown for the INC instruction. DEC same format and states as INC. Replace 100 with 101 in opcode.
XF and YF are copied from the operand (s), not from the result of (A - s). The V symbol in the P/V flag column indicates that the P/V flags contains the overflow of the operation. Similarly the P symbol indicates parity. • = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation.
16 bit Arithmetic Group Mnemonic ADD HL, ss ADC HL, ss
Symbolic Operation HL HL + ss HL HL + ss + CY
SBC HL, ss
HL HL - ss - CY
ADD IX, pp
IX IX + pp
ADD IY, rr
IY IY + rr
INC ss INC IX
ss ss + 1 IX IX + 1
INC IY
IY IY + 1
DEC ss DEC IX
ss ss - 1 IX IX - 1
DEC IY
IY IY - 1
Flags S Z YF H XF P/V N C • • 2 2 2 • 0 1 1 1 2 2 2 V 1 0 1
Opcode No.of No.of M No.of T T States 76 543 210 Hex Bytes Cycles States 00 ss1 001 1 3 11 4,4,3 11 101 101 ED 2 4 15 4,4,4,3 01 ss1 010 11 101 101 ED 2 4 15 4,4,4,3 1 1 2 2 2 V 1 1 1 01 ss0 010 11 011 101 DD 2 4 15 4,4,4,3 • • 2 2 2 • 0 1 00 pp1 001 11 111 101 FD 2 4 15 4,4,4,3 • • 2 2 2 • 0 1 00 rr1 001 • • • • • • • • 00 ss0 011 1 1 6 6 • • • • • • • • 11 011 101 DD 2 2 10 00 100 011 23 • • • • • • • • 11 111 101 FD 2 2 10 4,6 00 100 011 23 • • • • • • • • 00 ss1 011 1 1 6 6 • • • • • • • • 11 011 101 DD 2 2 10 4,6 00 101 011 2B • • • • • • • • 11 111 101 FD 2 2 10 4,6 00 101 011 2B 16 bit additions are performed by first adding the two low order eight bits, and then the two high order eight bits. 1 Indicates the flag is affected by the 16 bit result of the operation. 2 Indicates the flag is affected by the 8 bit addition of the high order eight bits
Notes:
Comments ss Reg. 00 BC 01 DE 10 HL 11 SP pp 00 01 10 11
Reg. BC DE IX SP
rr 00 01 10 11
Reg. BC DE IY SP
General Purpose Arithmetic and CPU Control Groups Mnemonic DAA CPL NEG4 CCF SCF NOP HALT DI3 EI3 IM 04 IM 14 4
IM 2
Notes:
Flag Notation:
Symbolic Operation Adjust A __ AA A0-A __ CY CY CY 1 No operations CPU halted IFF1 0 IFF2 0 IFF1 1 IFF2 1 Set interrupt mode 0 Set interrupt mode 1 Set interrupt mode 2
Flags S Z YF H XF P/V N C 1 1 P •
Opcode 76 543 210 00 100 111
Hex 27
• •
1 1 1
1 • 1 V
1 1
•
• • • • •
1 1 • • •
2 0 • • •
1 1 • • •
• • • • •
0 0 • • •
1 • • •
00 101 111 11 101 101 01 000 100 00 111 111 00 110 111 00 000 000 01 110 110 11 110 011
• •
•
•
•
•
•
•
11 111 011
• •
•
•
•
•
•
•
• •
•
• •
•
• • • • •
No.of Bytes 1
No.of M Cycles 1
No.of T States 4
T States
2F ED 44 3F 37 00 76 F3
1 2
1 2
4 8
4 4,4
One’s complement. Two’s complement.
1 1 1 1 1
1 1 1 1 1
4 4 4 4 4
4 4 4 4 4
Complement carry flag.
FB
1
1
4
4
Comments 4
11 101 101 ED 2 2 8 4,4 01 000 110 46 • • • • • 11 101 101 ED 2 2 8 4,4 01 010 110 56 • • • • • 11 101 101 ED 2 2 8 4,4 01 011 110 5E 1 XF and YF are a copy of bit 5 and 3 of register A _ 2 H contains the previous carry state (after instruction H C) 3 No interrupts are issued directly after a DI or EI. 4 This instruction has other unofficial opcodes, see Opcodes list. • = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation.
Rotate and Shift Group Mnemonic RLCA RLA RRCA RRA RLC r
Symbolic Operation
S • • • •
Z YF H • 0 • 0 • 0 • 0 0
Flags XF P/V • • • • P
N 0 0 0 0 0
C
RLC (HL)
0
P
0
RLC (IX + d)
0
P
0
RLC (IY + d)
0
P
0
LD r,RLC (IX + d)*
r (IX + d) RLC r (IX + d) r
0
P
0
LD r,RLC (IY + d)*
r (IY + d) RLC r (IY + d) r
0
P
0
RL m RRC m RR m SLA m SLL m* SRA m SRL m RLD
P P P P P P P P
0 0 0 0 0 0 0 0
•
RRD
P
0
•
Notes: Flag Notation:
0 0 0 0 0 0 0 0
0
Opcode 76 543 210 00 000 111 00 010 111 00 001 111 00 011 111 11 001 011 00 000 r 11 001 011 00 000 110 11 011 101 11 001 011 d 00 000 110 11 111 101 11 001 011 d 00 000 110 11 011 101 11 001 011 d 00 000 r 11 111 101 11 001 011 d 00 000 r 010 001 011 100 110 101 111 11 101 101 01 101 111 11 101 101 01 100 111
No. of Bytes 1 1 1 1 2
No. of M Cycles 1 1 1 1 2
No. of T States 4 4 4 4 8
T States
Hex 07 17 0F 1F CB CB
2
4
15
4,4,4,3
DD CB
4
6
23
4,4,3,5,4,3
FD CB
4
6
23
4,4,3,5,4,3
DD CB
4
6
23
4,4,3,5,4,3
FD CB
4
6
23
4,4,3,5,4,3
Comments 4 4 4 4 4,4
r 000 001 010 011 100 101 111
Reg. B C D E H L A
Instruction format and states are the same as RLC. Replace 000 with new number.
ED 6F ED 67
2
5
18
4,4,3,4,3
2
5
18
4,4,3,4,3
The P symbol in the P/V flag column indicates that the P/V flags contains the parity of the result. • = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation.
Bit Manipulation Group Symbolic Operation _ Z rb ___ Z (HL)b _____ Z (IX + d)b
Flags S Z YF H XF P/V N C 1 2 1 3 4 0 •
BIT b, (IY + d)5
Mnemonic BIT b, r
1
2 1
3 4 0
•
1
2 1
3 4 0
•
_____ Z (IY + d)b
1
2 1
3 4 0
•
SET b, r
rb 1
• •
•
•
•
•
•
•
SET b, (HL)
(HL)b 1
• •
•
•
•
•
•
•
SET b, (IX + d)
(IX + d)b 1
• •
•
•
•
•
•
•
SET b, (IY + d)
(IY + d)b 1
• •
•
•
•
•
•
•
LD r,SET b, (IX + d)*
r (IX + d) rb 1 (IX + d) r
• •
•
•
•
•
•
•
LD r,SET b, (IY + d)*
r (IY + d) rb 1 (IY + d) r
• •
•
•
•
•
•
•
RES b, m
mb 0 m r, (HL), (IX+d), (IY+d)
• •
•
•
•
•
•
•
BIT b, (HL) BIT b, (IX + d)5
Notes:
Flag Notation:
Opcode 76 543 210 11 001 011 01 b r 11 001 011 01 b 110 11 011 101 11 001 011 d 01 b 110 11 111 101 11 001 011 d 01 b 110 11 001 011 11 b r 11 001 011 11 b 110 11 011 101 11 001 011 d 11 b 110 11 111 101 11 001 011 d 11 b 110 11 011 101 11 001 011 d 11 b r 11 111 101 11 001 011 d 11 b r 10
No. of Bytes 2
No. of M Cycles 2
No. of T States 8
T States
Hex CB CB
2
3
12
4,4,4
DD CB
4
5
20
4,4,3,5,4
FD CB
4
5
20
4,4,3,5,4
CB
2
2
8
4,4
CB
2
4
15
4,4,4,3
DD CB
4
6
23
4,4,3,5,4,3
FD CB
4
6
23
4,4,3,5,4,3
DD CB
4
6
23
4,4,3,5,4,3
FD CB
4
6
23
4,4,3,5,4,3
4,4
The notation mb indicates bit b (0 to 7) of location m. BIT instructions are performed by an bitwise AND. 1 S is set if b = 7 and Z = 0 2 YF is set if b = 5 and Z = 0 3 XF is set if b = 3 and Z = 0 4 P/V is set like the Z flag 5 This instruction has other unofficial opcodes • = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation.
Comments r Reg. 000 B 001 C 010 D 011 E 100 H 101 L 111 A
b 000 001 010 011 100 101 110 111
Bit. 0 1 2 3 4 5 6 7
To form new opcode replace 11 of SET b, s with 10. Flags and states are the same.
Input and Output Groups Mnemonic IN A, (n)
Symbolic Operation A (n)
Flags S Z YF H XF P/V N C • • • • • • • •
IN r, (C)
r (C)
0
P
0
•
IN (C)* or IN F, (C)* INI
0
P
0
•
OUT (n), A
Just affects flags, value is lost. (HL) (C) HL HL + 1 BB-1 (HL) (C) HL HL + 1 BB-1 Repeat until B=0 (HL) (C) HL HL - 1 BB-1 (HL) (C) HL HL - 1 BB-1 Repeat until B=0 (n) A
OUT (C), r
INIR
IND
1 1 1 3 1 3 2 3
No.of Bytes 2
No.of M Cycles 3
No.of T States 11
T States
Hex DB ED
2
3
12
4,4,4
ED 70 ED A2
2
3
12
4,4,4
2
4
16
4,5,4,3
4,3,4
3 2 3
11 101 101 10 110 010
ED B2
2 2
5 4
21 16
4,5,4,3,5 4,5,4,3
1 1 1 4 1 3 2 4
11 101 101 10 101 010
ED AA
2
4
16
4,5,4,3
0 1
0
3 0
Opcode 76 543 210 11 011 011 n 11 101 101 01 r 000 11 101 101 01 110 000 11 101 101 10 100 010
0 1
0
4 0
3 2 4
11 101 101 10 111 010
ED BA
2 2
5 4
21 16
4,5,4,3,5 4,5,4,3
• •
•
•
•
•
•
•
D3
2
3
11
4,3,4
(C) r
• •
•
•
•
•
•
•
ED
2
3
12
4,4,4
OUT (C), 0*
(C) 0
• •
•
•
•
•
•
•
3
12
4,4,4
(C) (HL) HL HL + 1 BB-1 (C) (HL) HL HL + 1 BB-1 Repeat until B=0 (C) (HL) HL HL - 1 BB-1 (C) (HL) HL HL - 1 BB-1 Repeat until B=0
1 1 1 3 1 3 2 3
ED 71 ED A3
2
OUTI
11 010 011 n 11 101 101 01 r 001 11 101 101 01 110 001 11 101 101 10 100 011
2
4
16
4,5,4,3
3 2 3
11 101 101 10 110 011
ED B3
2 2
5 4
21 16
4,5,4,3,5 4,5,4,3
1 1 1 3 1 3 2 3
11 101 101 10 101 011
ED AB
2
4
16
4,5,4,3
11 101 101 10 111 011
ED BB
2 2
5 4
21 16
4,5,4,3,5 4,5,4,3
INDR
OTIR
OUTD
OTDR
Notes:
0 1
0 1
0
0
3 0
3 0
3 2 3
Comments r Reg. 000 B 001 C 010 D 011 E 100 H 101 L 111 A if B 0 if B = 0
if B 0 if B = 0
if B 0 if B = 0
if B 0 if B = 0
The V symbol in the P/V flag column indicates that the P/V flags contains the overflow of the operation. Similarly the P symbol indicates parity. r means any of the registers A, B, C, D, E, H, L. 1 flag is affected by the result of B B - 1 as in DEC B. 2 N is a copy bit 7 of the last value from the input (C). 3 This flag is bizarre, see section 4.3.
Jump Group Symbolic Operation PC nn
Flags S Z YF H XF P/V N C • • • • • • • •
Opcode 76 543 210 11 000 011 n n
JP cc, nn
if cc is true, PC nn
• •
•
•
•
•
•
•
11 ccc 010 n n
JR e
PC PC + e
• •
•
•
•
•
•
•
00 011 000 e -2
JR ss, e
if ss is true PC PC + e
• •
•
•
•
•
•
•
00 1ss 000 e -2
JP HL JP IX
PC HL PC IX
• • • •
• •
• •
• •
• •
• •
• •
11 101 001 11 011 101 11 101 001
JP IY
PC IY
• •
•
•
•
•
•
•
DJNZ e
BB-1 if B 0 PC PC + e
• •
•
•
•
•
•
•
Mnemonic JP nn
Notes:
Flag Notation:
No.of Bytes 3
No.of M Cycles 3
No.of T States 10
T States
3
3
10
4,3,3
2
3
12
4,3,5
ccc 000 001 010 011 100 101 110 111
2 2
3 2
12 7
4,3,5 4,3
if ss is true if ss is false
E9 DD E9
1 2
1 2
4 8
4 4,4
11 111 101 11 101 001
FD E9
2
2
8
4,4
00 010 000 e -2
10
2 2
2 3
8 13
5,3 5,3,5
Hex C3
18
Comments 4,3,3
e is a signed two-complement number in the range <-126, 129> e - 2 in the opcode provides an effective number of PC + e as PC incremented by 2 prior to the addition of e. ccc is a 3-bit condition ss is a 2-bit condition • = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation.
ss 11 10 01 00
Condition NZ Z NC C PO PE P M
Condition C NC Z NZ
if B = 0 if B 0
Call and Return Group Symbolic Operation SP SP - 1 (SP) PCH SP SP - 1 (SP) PCL PC nn
Flags S Z YF H XF P/V N C • • • • • • • •
Opcode 76 543 210 11 001 101 n n
CALL cc, nn
if cc is true, SP SP - 1 (SP) PCH SP SP - 1 (SP) PCL PC nn
• •
•
•
•
•
•
•
11 ccc 100 n n
RET
PCL (SP) SP SP + 1 PCH (SP) SP SP + 1
• •
•
•
•
•
•
•
11 001 001
RET cc
if cc is true, PCL (SP) SP SP + 1 PCH (SP) SP SP + 1
• •
•
•
•
•
•
•
11 ccc 000
RETI2
PCL (SP) SP SP + 1 PCH (SP) SP SP + 1
• •
•
•
•
•
•
•
11 101 101 01 001 101
RETN1,2
PCL (SP) SP SP + 1 PCH (SP) SP SP + 1 IFF1 IFF2
• •
•
•
•
•
•
•
11 101 101 01 000 101
RST p
SP SP - 1 (SP) PCH SP SP - 1 (SP) PCL PC p
• •
•
•
•
•
•
•
11 t 111
Mnemonic CALL nn
Notes:
1
No.of M Cycles 5
No.of T States 17
T States
3 3
3 5
10 17
4,3,3 4,3,4,3,3
1
3
10
4,3,3
1 1
1 3
5 11
5 5,3,3
if cc is false if cc is true
ED 4D
2
4
14
4,4,3,3
ED 45
2
4
14
4,4,3,3
ccc 000 001 010 011 100 101 110 111
Condition NZ Z NC C PO PE P M
1
3
11
5,3,3
t 000 001 010 011 100 101 110 111
p 0h 8h 10h 18h 20h 28h 30h 38h
C9
Comments 4,3,4,3,3
This instruction has other unofficial opcodes, see Opcode list. RETI and RETN are internally the same instruction. Instruction also IFF1 IFF2 cc is a 3-bit condition • = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation. 2
Flag Notation:
No.of Bytes 3
Hex CD
if cc is false if cc is true
![T t #T]](https://p.pdfkul.com/img/300x300/t-t-t_59b403851723dda273d98c57.jpg)
![T t #T]](https://p.pdfkul.com/img/300x300/t-t-t_59f2fd371723dde8232f9fec.jpg)
