9.3 A 12b, 50MS/s Fully Differential Zero-Crossing Based ADC Without CMFB Lane Brooks and Hae-Seung Lee Massachusetts Institute of Technology
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Outline • • • • • • • •
Review of zero-crossing based circuits Fully-differential implementation Common-mode control Chopper offset estimation Reference voltage switching Output range enhancement Results Conclusion
Op-amp Based Transfer Phase • •
Op-amp forces virtual ground condition Exponential settling to virtual ground
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Op-amp Based Circuit Issues •
Op-amp must provide high gain and reasonable output swing simultaneously. – Difficult to achieve in scaled CMOS – Requires cascading, gain enhancement, etc. – Added devices contribute noise
•
Op-amp must be stable under feedback. – High gain requirement conflicts with stability
•
Fast, high accuracy settling requires high bandwidth, thus large noise bandwidth.
•
The combined result is high power consumption.
Zero-Crossing Based Circuits (ZCBCs) •
Current source sweeps the output voltage
•
Zero-Crossing Detector (ZCD) detects virtual ground condition and turns off current source
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Same output voltage is obtained
•
Sub kT/C noise
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Previous ZCBC Pipelined ADC
•
Brooks & Lee, “A Zero-Crossing Based 8b, 200MS/s Pipelined ADC”, ISSCC, Feb 2007.
– Typically have large common-mode gain – Require common-mode feedback
•
Zero-crossing based implementations:
– Common-mode is reset at the output of each stage – Small common mode variation caused by current source mismatch
– Common-mode feedback is unnecessary
Power Supply Noise
•
ZCD tracks & nulls low frequency supply noise
•
High frequency noise feeds to the output node
Replica Dummy Current Sources •
Replica current sources added for symmetry
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Dummy current sources are always off
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Creates matching parasitics on output nodes
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High frequency noise couples symmetrically
Differential ZCD
Offset Compensation •
ZCBC is not compatible with traditional closed loop offset sampling
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Closed loop offset compensation doubles power consumption and noise
•
Chopper Offset Estimation (COE) was developed for this design
Traditional Chopper Stabilization
•
Offset is modulated out of band
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Output is digitally demodulated
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Low-pass filter removes offset
Chopper Offset Estimation
• •
COE is narrow band LPF Poly-phase decomposition of COE realizes significant hardware savings
Input Referred COE
•
Offset estimate fed back into analog domain
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Nulls offset at the source to recover lost signal range
•
Offset Controller (OC) converts measured digital offset to analog nulling factor
COE for Pipelined ADCs
•
Systematic offset due to overshoot is nulled at each stage with single controller
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Also removes random offset due to mismatch
ZCD With Offset Compensation
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Switches create programmable current gain mirror
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Provides power efficient digital offset adjustment
Measured ZCD Offset Range
Reference Switching Issue
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1.5b/stage example
•
Different voltage drops across reference voltage switches cause DNL
Alternative Switching Scheme
•
Splitting C1 and driving differentially eliminates middle voltage Vrefc
•
Voltage drop no longer creates non-linearity
•
Leaves bit decisions thermometer encoded
Output Range Enhancement •
9 Bit Decision Comparators per stage (3.3 bits/stage)
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4x gain per stage (1.3 bit redundancy)
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Reference voltages set to power supply levels
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Input range is 83% the reference range
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Output range is 33% the reference range
Bit Decision Comparator (BDC)
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BDC offsets were larger than predicted
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BDC offset limits overall linearity
Linearity
50MS/s Frequency Response
Performance vs Sampling Freq.
SNR Sensitivity To I/O Voltage
Chip Micrograph • 90nm CMOS • 0.3mm2
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Performance Summary Technology
90nm CMOS
Area Input Voltage Range
0.3 mm2 2V (differential)
Power Supply Sampling Frequency
1.2V 25MS/s
50MS/s
Differential Non-linearity
±0.5 LSB12
+0.68/-0.4
DNL/INL
±2.0 LSB12
+3.0/-2.7
3.8mW
4.5mW
Dynamic Range
72dB
72dB
SFDR
73dB
68dB
SNDR
66dB
62dB
ENOB
10.6b
10.0b
98 fJ/step
88 fJ/step
Power Consumption
Figure of Merit
FOM Comparison Resolution
ENOB
Type
Year
(Bits)
Sampling FOM Rate(MS/s) (fJ/step)
(Bits) 13
10.5
250
280
Pipe
VLSI ‘08
12
10.5
20
310
Pipe
ISSCC ‘08
12
10.3
50
360
Pipe
VLSI ’08
12
10
40
389
Pipe
VLSI ‘07
12
10
50
88
Pipe
This work
- Complete list of published non-interleaved ADC’s with FOM < 500fJ/step and ENOB ≥ 10 Bits, through 2008 - Excludes delta-sigma converters and converters with sampling rates < 1MS/s
Conclusions •
Demonstrated a 12b, 50MS/s Pipelined ADC:
– Zero-crossing based circuit – Fully differential signal path – No CMFB required – Chopper offset compensation – Split reference voltage switching scheme – Output range enhancement
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Acknowledgements •
Funding for this research was provided by
– MIT Center for Integrated Circuits and Systems – National Defense Science & Engineering Fellowship – DARPA Grant N66001-06-2046
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