A Report On

Design of Fully Differential Two Stages Operational Amplifier

Submitted By

Raj Kumar Singh Parihar

2002A3PS013

B.E. (Hons.) Electrical & Electronics

Submitted To Prof. (Dr.) Anu Gupta EEE, BITS - Pilani

BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE PILANI, RAJ. - 333 031 May, 2006

1

Design Problem: Design a Fully Differential version of Two Stage CMOS op-amp with the following specifications: Sl. No. 1 2 3 4 5 6 7 8 9 10 11 12 13

Specifications Technology Supply (Vdd) Load Capacitance (CL) Power Budget (PD) Differential DC gain (Av) Small signal BW (UGB) Phase Margin (PM) Output Swing Slew rate (SR) CMRR PSRR ICMR Linear range of operation

Value tsmcmm018 3.3V 1pF (differential) < = 2.5mW > = 95 dB > = 130 MHz > = 55 Degree >= 5V (Differential) >= 100 V/µs >= 125dB >= 125 dB >= 1.5V >= 1.5 V

Theory: Operational amplifiers (op amps) are an integral part of many analog and mixed-signal systems. Op amps with vastly different level of complexity are used to realize functions ranging from dc bias generation to high-speed amplification or filtering. In an Op amp the cascoding of transistors increases the gain while limiting the output swings. In some applications the gain and/or the output swings provided by Cascode op amps are not adequate. In such cases, we resort to "two-stage" op amps, with the first stage providing a high gain and the second, large swing. In contrast to Cascode op amps, a two-stage configuration isolates the gain and swing requirements. Here the potential problem of stability comes into the picture. Each gain stage introduces at least one pole in the open-loop transfer function, making it difficult to guarantee stability in a feedback system using op amp. For this reason op amps having more than two stages are rarely used. To make these op amps stable we need to have some phase margin. There are various techniques which can improve it. I have implemented RC compensation technique to get the desired phase margin of 55 degree.

2

Design Steps: 1.Power Budget: Vdd = 3.3v; PD < = 2.5 mW; PD = Vdd * Itotal ; Itotal <= 2.5 m/ 3.3 ~= 750 uA This is the total current from rail to rai . This current is divided into five branches. Current Distribution == (150, 50, 50, 300, 150) in uA => 700 uA This division of current has been considered after taking SR and good UGB into account. 2.Output Swings: Total output swing >= 2 (Vdd- Vod6-Vod7) 2.5 V >= Vdd- Vod6 -Vod7 Therefore, Vod6 + Vod7 <= 0.8 V Generally, the overdrive of PMOS should be higher than NMOS as mobility of PMOS is approx. 2.5 times less than NMOS. Let us assume Vod6 = 0.3V, Vod7 = 0.2V 3. Input common mode range: (ICMR) >= 1.5 V Vin,max = VDD - Vgs3 + Vt1 = 3.3 - ( 0.3 + 0.7 ) + 0.7 = 3 V Vin,min = Vod1 +Vt1+ Vod5 = 0.2 + 0.7 + 0.3 = 1.2 V assumed Vt of both nmos and pmos 0.7 V, also assumed overdrive voltages of all transistor according to their current capability. Vod3 = Vod4 = 0.3V Vod1 = Vod2 = 0.2V Vod5 = 0.3V we set a Vicm = 1.6 v for which the output DC level is 1.59 v 4. Calculation of (W/L): The initial W/L values (in um) can be get by using the current expression in Saturation region operation assumed un* Cox = 150 uA/v2 and up* Cox = 60 uA/v2 After Calculation: (for L= 1um) (W/L)1 = (W/L)2 = 50/ 1 (W/L)3 = (W/L)4 = 55/ 1 (W/L)5 = 45/ 1 (W/L)6 = (W/L)8 = 55/ 1 (W/L)7 = (W/L)9 = 50/ 1

3

After taking into account the Rout of the transistors for high effective gain the new sizing is as following. Av = gm1,2 * (Ro2 || Ro4) * gm6,7 * (Ro6 || Ro7 )

----> {1}

Ro = 1/ (Lmda * ID ) ----> {2} 1.Lambda of PMOS is half of the NMOS so the L of PMOS should be roughly double of NMOS to get the equal Rp and Rn for maximum possible gain. 2.To get the high gain the Gm of input transistors should be high, thus the W/L should be also high. (W/L)1

= (W/L)2 = 50/ 0.72 = (W/L)4 = 70.6/ 1.44 (W/L)5 = 60/ 0.72 (W/L)6 = (W/L)8 = 88.5/ 0.9 (W/L)7 = (W/L)9 = 22.5/ 0.54 Size of Current Mirror's Transistors (W/L)mbn1 = (W/L)mbn2 = 10/ 0.72 (W/L)mbp = 24.5/ 1.44 (W/L)3

all (W/L)s are in uM/uM 5. Phase Margin: Because of High gain the phase margin was 3 degree. To improve this I did employ an RC compensation technique After many iteration the values of R and Cc which gave around 53 degrees Phase margin are as following: Rz = 5.2 Kohm and Cc = 0.9pF Here the notacible fact is:  Increment in Cc value improves the PM, whereas  Increment in Rz value improves the UGB To realize the Rz of 5.2 K a PMOS transister operating in linear region of size (7.3/ 0.72) um/um has been used. 6. Tansient Analysis: For calculation of Acm and Adm a sinusoidal signal of small Mag. (10uV) has been used, which was having an offset of DC input bias.

4

Specification Obtained: S.No. 1 2 3 4 5 6 7 8 9 10 11 12 13

Specifications Technology Supply (Vdd) Load Caps (CL) Power Dissipation DC gain (Av) BW (UGB) Phase Margin (PM) Output Swing Slew rate (SR) CMRR PSRR ICMR Linear range

Value(Sepecified) tsmcmm018 3.3V 1pF (diff.) < = 2.5mW > = 95 dB > = 130 MHz > = 55 Degree >= 5V (Diff.) >= 100 V/µs >= 125dB >= 125 dB >= 1.5V >= 1.5 V

Model File: rf018.eldo; TT_3V ; NCH3 and PCH3 Vicm = 1.6 V Vocm = 1.59 V

Symbol: two Stage Op amps

5

Value(Obtained) Used 3.3V 1PF (Diff.) 2.288 mW 95.278 dB 135.34 MHz 52.8 Degree 5.9 V 131.74 V/ uS Inf. Inf. 1.4 V 1.55 V

Schematic: Two Stage CMOS op amp

6

DC Analysis: 1.ViCM = 1.6 V; VoCM = 1.59 V 2.Power Dissipation = 2.288 mW

Transient Analysis: Asig = 10uV ; fsig = 1KHz Av = (Vout2-Vout1)/ (Vin2-Vin1) = 1.1611/ 20u = 58055 V/V Gain (in dB) = 20log(Av) = 95.278 dB

7

CMRR: Adm = 98055 V/V => 95.278 dB Acm = (Vout2 - Vout1) = 0 V/V For a fully differential topology ideally the CMRR should be (inf.) because if there is no mismatch the output differential gain would be zero. CMRR = inf.

8

PSRR: PSRR = Adm/ Avdd = Inf. Because any flactuation in Supply is same and in same direction at both the output

when output node voltage crosses the Vocm a glitch is introduced which has peak value of 652pV.

9

Slew Rate: SR1 = 1.29 V/ nS SR2 = 131.74 V/ uS

10

FFT Analysis: Here the input and output's frequency components are exactly the same. This implies that there is no signal distortation. Also the signal component at 1KHz is more than 50dB from noise components.

11

AC Analysis: (Without Compensation) UGB = 219.4 Mhz ; PM = 1.74 Degree Single Sided Mid band gain Av1 = 89.46 dB Differential Mid band gain Av= Av1 + 20 log 2 = 89.46 + 6.02 = 95.48 dB To improve the phase response a compensation technique should be employed. An RC compensation techniques has been employed here.

12

With Compensation Technique: Cc = 0.9pF ; Rz = 2.5 Kohm new UGB = 135.34 Mhz new PM = 52.8 degree

13

Now Implementation of these compensation resistor will consume a huge area on silicon. The other alternative could be possibly implement these resisters using mos. Any MOS operating in Triode region behave like a resistor. This particular nature will be utilized to make this circuit more compact. Revised UGB = 133. 50 Mhz; PM = 50.5 Degree

14

Schematic with RC Compensation:

15

Layout: Without Compensation

DRC Report

All

the errors are density error, which are not critical from design point of view

16

With Compensation Capacitor

17

Schematic for LVS: made in Cadence Schematic composer

18

LVS: Results 1. Opamp_lvs.cdl file ************************************************************************ * auCdl Netlist: * * Library Name: sche_opamp * Top Cell Name: opamp_schematic * View Name: schematic * Netlisted on: May 8 12:19:27 2006 ************************************************************************ *.EQUATION *.SCALE METER *.MEGA .PARAM ************************************************************************ * Library Name: sche_opamp * Cell Name: opamp_schematic * View Name: schematic ************************************************************************ .SUBCKT opamp_schematic GND IREF VDD VIN1 VIN2 VOUT1 VOUT2 *.PININFO IREF:I VIN1:I VIN2:I VOUT1:O VOUT2:O GND:B VDD:B MM12 net48 net48 VDD VDD P W=24.5u L=1.44u MM11 VOUT1 net22 VDD VDD P W=88.5u L=900.0n MM10 net22 net48 VDD VDD P W=70.6u L=1.44u MM8 VOUT2 net60 VDD VDD P W=88.5u L=900.0n MM7 net60 net48 VDD VDD P W=70.6u L=1.44u MM6 VOUT2 IREF GND GND N W=22.5u L=540.00n MM5 net67 IREF GND GND N W=60u L=720.00n MM4 net48 IREF GND GND N W=10u L=720.00n MM3 VOUT1 IREF GND GND N W=22.5u L=540.00n MM2 IREF IREF GND GND N W=10u L=720.00n MM1 net60 VIN1 net67 GND N W=50u L=720.00n MM0 net22 VIN2 net67 GND N W=50u L=720.00n .ENDS

19

LVS: Report

********************************************************************************************************* OVERALL COMPARISON RESULTS *********************************************************************************************************

# # # # ## #

################### # # # CORRECT # # ###################

#

_ _ * * | \___/

---------------------------------------------------------------------------------------------INITIAL NUMBERS OF OBJECTS --------------------------

Ports:

Layout Source Component Type ------ ------------------7 7

Nets:

11

11

Instances:

46 7 * MN (4 pins) 45 5 * MP (4 pins) ------ -----Total Inst: 91 12

NUMBERS OF OBJECTS AFTER TRANSFORMATION ---------------------------------------

Ports:

Layout Source Component Type ------ ------------------7 7

Nets:

11

11

Instances:

7 7 MN (4 pins) 5 5 MP (4 pins) ------ -----Total Inst: 12 12 = Number of objects in layout different from number in source.

20

PEX: Net list * File: 2stageopamp_no_cc.pex.netlist * Created: Mon May 8 12:26:45 2006 * Program "Calibre xRC" * Version "v9.3_5.11" * *.subckt 2STAGEOPAMP_NO_CC VDD GND VOUT1 VOUT2 IREF VIN1 VIN2 .connect GND 0 .include input2stageopamp.txt mM0 GND IREF 2 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=2.4e-12 PD=5.54e-06 + PS=1.096e-05 NRD=0.054 NRS=0.096 mM1 IREF IREF GND GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM2 GND IREF IREF GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM3 2 IREF GND GND nch3 L=7.2e-07 W=5e-06 AD=2.6e-12 AS=1.35e-12 PD=1.104e-05 + PS=5.54e-06 NRD=0.104 NRS=0.054 mM4 GND IREF 9 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=2.4e-12 PD=5.54e-06 + PS=1.096e-05 NRD=0.054 NRS=0.096 mM5 9 IREF GND GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM6 GND IREF 9 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM7 9 IREF GND GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM8 9 VIN2 3 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=2.4e-12 PD=5.54e-06 + PS=1.096e-05 NRD=0.054 NRS=0.096 mM9 GND IREF 9 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM10 5 VIN1 9 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM11 9 IREF GND GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM12 9 VIN1 5 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM13 GND IREF 9 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM14 3 VIN2 9 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM15 9 IREF GND GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM16 9 VIN2 3 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM17 GND IREF 9 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM18 5 VIN1 9 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM19 9 IREF GND GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM20 9 VIN1 5 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM21 GND IREF 9 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06

21

+ PS=5.54e-06 NRD=0.054 NRS=0.054 mM22 3 VIN2 9 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM23 9 IREF GND GND nch3 L=7.2e-07 W=5e-06 AD=2.4e-12 AS=1.35e-12 PD=1.096e-05 + PS=5.54e-06 NRD=0.096 NRS=0.054 mM24 9 VIN2 3 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM25 5 VIN1 9 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM26 9 VIN1 5 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM27 GND IREF VOUT2 GND nch3 L=5.4e-07 W=4.5e-06 AD=1.215e-12 AS=2.16e-12 + PD=5.04e-06 PS=9.96e-06 NRD=0.06 NRS=0.106667 mM28 3 VIN2 9 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM29 VOUT1 IREF GND GND nch3 L=5.4e-07 W=4.5e-06 AD=1.215e-12 AS=1.215e-12 + PD=5.04e-06 PS=5.04e-06 NRD=0.06 NRS=0.06 mM30 9 VIN2 3 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM31 GND IREF VOUT1 GND nch3 L=5.4e-07 W=4.5e-06 AD=1.215e-12 AS=1.215e-12 + PD=5.04e-06 PS=5.04e-06 NRD=0.06 NRS=0.06 mM32 5 VIN1 9 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM33 VOUT2 IREF GND GND nch3 L=5.4e-07 W=4.5e-06 AD=1.215e-12 AS=1.215e-12 + PD=5.04e-06 PS=5.04e-06 NRD=0.06 NRS=0.06 mM34 9 VIN1 5 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM35 GND IREF VOUT2 GND nch3 L=5.4e-07 W=4.5e-06 AD=1.215e-12 AS=1.215e-12 + PD=5.04e-06 PS=5.04e-06 NRD=0.06 NRS=0.06 mM36 3 VIN2 9 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM37 VOUT1 IREF GND GND nch3 L=5.4e-07 W=4.5e-06 AD=1.215e-12 AS=1.215e-12 + PD=5.04e-06 PS=5.04e-06 NRD=0.06 NRS=0.06 mM38 9 VIN2 3 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM39 GND IREF VOUT1 GND nch3 L=5.4e-07 W=4.5e-06 AD=1.215e-12 AS=1.215e-12 + PD=5.04e-06 PS=5.04e-06 NRD=0.06 NRS=0.06 mM40 VOUT2 IREF GND GND nch3 L=5.4e-07 W=4.5e-06 AD=1.215e-12 AS=1.215e-12 + PD=5.04e-06 PS=5.04e-06 NRD=0.06 NRS=0.06 mM41 5 VIN1 9 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM42 GND IREF VOUT2 GND nch3 L=5.4e-07 W=4.5e-06 AD=1.215e-12 AS=1.215e-12 + PD=5.04e-06 PS=5.04e-06 NRD=0.06 NRS=0.06 mM43 9 VIN1 5 GND nch3 L=7.2e-07 W=5e-06 AD=1.35e-12 AS=1.35e-12 PD=5.54e-06 + PS=5.54e-06 NRD=0.054 NRS=0.054 mM44 VOUT1 IREF GND GND nch3 L=5.4e-07 W=4.5e-06 AD=2.16e-12 AS=1.215e-12 + PD=9.96e-06 PS=5.04e-06 NRD=0.106667 NRS=0.06 mM45 3 VIN2 9 GND nch3 L=7.2e-07 W=5e-06 AD=2.4e-12 AS=1.35e-12 PD=1.096e-05 + PS=5.54e-06 NRD=0.096 NRS=0.054 mM46 2 2 VDD VDD pch3 L=1.44e-06 W=4.9e-06 AD=1.323e-12 AS=2.352e-12 PD=5.44e-06 + PS=1.076e-05 NRD=0.055102 NRS=0.0979592 mM47 VDD 2 2 VDD pch3 L=1.44e-06 W=4.9e-06 AD=1.323e-12 AS=1.323e-12 PD=5.44e-06 + PS=5.44e-06 NRD=0.055102 NRS=0.055102 mM48 2 2 VDD VDD pch3 L=1.44e-06 W=4.9e-06 AD=1.323e-12 AS=1.323e-12 PD=5.44e-06 + PS=5.44e-06 NRD=0.055102 NRS=0.055102 mM49 VDD 2 2 VDD pch3 L=1.44e-06 W=4.9e-06 AD=1.323e-12 AS=1.323e-12 PD=5.44e-06

22

+ PS=5.44e-06 NRD=0.055102 NRS=0.055102 mM50 VDD 2 3 VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=3.3888e-12 + PD=7.6e-06 PS=1.508e-05 NRD=0.0382436 NRS=0.0679887 mM51 2 2 VDD VDD pch3 L=1.44e-06 W=4.9e-06 AD=2.352e-12 AS=1.323e-12 + PD=1.076e-05 PS=5.44e-06 NRD=0.0979592 NRS=0.055102 mM52 5 2 VDD VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12 + PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM53 VDD 2 5 VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12 + PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM54 VDD 3 VOUT1 VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=4.248e-12 + PD=9.39e-06 PS=1.866e-05 NRD=0.0305085 NRS=0.0542373 mM55 VOUT2 5 VDD VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM56 3 2 VDD VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12 + PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM57 VDD 5 VOUT2 VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM58 VDD 2 3 VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12 + PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM59 VOUT1 3 VDD VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM60 5 2 VDD VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12 + PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM61 VDD 3 VOUT1 VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM62 VOUT2 5 VDD VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM63 VDD 2 5 VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12 + PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM64 VDD 5 VOUT2 VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM65 3 2 VDD VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12 + PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM66 VOUT1 3 VDD VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM67 VDD 2 3 VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12 + PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM68 VDD 3 VOUT1 VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM69 VOUT2 5 VDD VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM70 5 2 VDD VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12 + PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM71 VDD 5 VOUT2 VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM72 VDD 2 5 VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12 + PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM73 VOUT1 3 VDD VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM74 VDD 3 VOUT1 VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM75 3 2 VDD VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12 + PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM76 VOUT2 5 VDD VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM77 VDD 2 3 VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12

23

+ PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM78 VDD 5 VOUT2 VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM79 5 2 VDD VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12 + PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM80 VOUT1 3 VDD VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM81 VDD 3 VOUT1 VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM82 VDD 2 5 VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12 + PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM83 VOUT2 5 VDD VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM84 3 2 VDD VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12 + PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM85 VDD 5 VOUT2 VDD pch3 L=9e-07 W=8.85e-06 AD=2.3895e-12 AS=2.3895e-12 + PD=9.39e-06 PS=9.39e-06 NRD=0.0305085 NRS=0.0305085 mM86 VDD 2 3 VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12 + PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM87 VOUT1 3 VDD VDD pch3 L=9e-07 W=8.85e-06 AD=4.248e-12 AS=2.3895e-12 + PD=1.866e-05 PS=9.39e-06 NRD=0.0542373 NRS=0.0305085 mM88 5 2 VDD VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12 + PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM89 VDD 2 5 VDD pch3 L=1.44e-06 W=7.06e-06 AD=1.9062e-12 AS=1.9062e-12 + PD=7.6e-06 PS=7.6e-06 NRD=0.0382436 NRS=0.0382436 mM90 3 2 VDD VDD pch3 L=1.44e-06 W=7.06e-06 AD=3.3888e-12 AS=1.9062e-12 + PD=1.508e-05 PS=7.6e-06 NRD=0.0679887 NRS=0.0382436 c_6 VDD 0 23.1279f c_14 2 0 11.3793f c_23 3 0 11.2717f c_32 GND 0 7.83297f c_43 5 0 9.46231f c_52 VOUT1 0 6.17945f c_63 VOUT2 0 4.72688f c_72 IREF 0 6.24896f c_81 9 0 3.86165f c_90 VIN1 0 3.043f c_99 VIN2 0 3.1124f * .include 2stageopamp_no_cc.pex.netlist.2STAGEOPAMP_NO_CC.pxi * .end * *

24

//Parasitic capacitances * File: 2stageopamp.pex.netlist.2STAGEOPAMP.pxi * Created: Fri May 5 00:08:00 2006 * cc_1 2 VDD 2.60572f cc_2 BOT VDD 0.352415f cc_3 4 VDD 4.56372f cc_4 DBNET2 VDD 10.4814f cc_5 GND VDD 0.789815f cc_6 TOP VDD 3.63598f cc_7 DBNET1 VDD 0.366703f cc_8 BOT 2 5.33201e-22 cc_9 4 2 0.683196f cc_10 DBNET2 2 0.516903f cc_11 GND 2 0.534262f cc_12 TOP 2 5.22283e-20 cc_13 IREF 2 0.0885317f cc_14 10 2 0.185337f cc_15 4 BOT 0.0164608f cc_16 DBNET2 BOT 0.474315f cc_17 GND BOT 0.12921f cc_18 TOP BOT 33.3156f cc_19 DBNET2 4 4.45561f cc_20 GND 4 0.0855438f cc_21 TOP 4 1.61354f cc_22 DBNET1 4 0.234346f cc_23 10 4 2.87903f cc_24 VIN1 4 0.00453565f cc_25 VIN2 4 0.536808f cc_26 GND DBNET2 2.32399f cc_27 TOP DBNET2 1.33687f cc_28 DBNET1 DBNET2 32.6917f cc_29 IREF DBNET2 0.217726f cc_30 10 DBNET2 3.92038f cc_31 VIN1 DBNET2 0.550561f cc_32 VIN2 DBNET2 0.100904f cc_33 TOP GND 1.507f cc_34 DBNET1 GND 0.05647f cc_35 IREF GND 2.36169f cc_36 10 GND 1.93426f cc_37 VIN1 GND 0.00690254f cc_38 VIN2 GND 0.0056187f cc_39 IREF TOP 0.157043f cc_40 10 TOP 0.645347f cc_41 VIN1 TOP 0.0306985f cc_42 VIN2 TOP 0.0273583f cc_43 10 IREF 0.429806f cc_44 VIN1 IREF 0.0202838f cc_45 VIN2 IREF 0.0026828f cc_46 VIN1 10 0.864314f cc_47 VIN2 10 0.939272f cc_48 VIN2 VIN1 2.52638f

25

Appendix 1.Opamp with Slight Modifications in (W/L)

26

New Sizing of transistors: (W/L)1 = (W/L)2 = 50/ 0.72 (W/L)3 = (W/L)4 = 70.8/ 1.44 (W/L)5 = 60/ 0.72 (W/L)6 = (W/L)8 = 90/ 1.08 (W/L)7 = (W/L)9 = 22.4/ 0.54 Size of Current Mirror's Transistors (W/L)mbn1 = (W/L)mbn2 = 7.5/ 0.54 (W/L)mbp = 8.2/ 0.54

AC Analysis

27

Schematic for LVS:

28

Layout: (2 Stage Op-amp)

29

2. Differential Amplifier Design

30

SCHEMATIC SIMULATION RESULTS Transient Analysis

Gain Av = 32.99/(0.1) ~= 330 V/V = 50.37 dB

31

AC Analysis

Av(Mid Band) = 50.368 dB; UGB = 443.44 MHz PM = 75 Degree ; F3dB = 2.348 Mhz

32

Slew Rate

SR1 = 394.23 V/ uS SR2 = 664.21 V/ uS SR = Min (SR1, SR2) = 394.23 V/ uS

33

Symbol: Differential Amplifier

34

Semi Custom Layout

LVS REPORT:

35

Schematic for LVS

36

POST-LAYOUT SIMULATION AC Analysis:

Av(Mid Band) = 50.357 dB; UGB = 452.17 MHz PM = 74.35 Degree ; F3dB = 2.9 Mhz 37

Transient Analysis:

gain Av = 32.95/(0.1) ~= 329.5 V/V = 50.35 dB Conclusion: After Postlayout simulation the results of AC and Transiesnt analysis are consistent with the schematic simulation. The discrepencies are less than 0.1%. 38

REFERENCES 1.Behzad Razavi, " Design of Analog CMOS Integrated Circuits ", Fifth Edition,TMH Edition. 2. David A. Johns & Ken Martin, " Analog Integrated Circuits Design", John Wiley & Sons. 3. P. E . Allen & D. R. Holberg, " CMOS Analog Circuit Design, Second Edition, Oxford University Press.

39