IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 60, NO. 11, NOVEMBER 2013

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A 0.45-V MOSFETs-Based Temperature Sensor Front-End in 90 nm CMOS With a Noncalibrated ±3.5 ◦C 3σ Relative Inaccuracy From −55 ◦C to 105 ◦C Li Lu, Student Member, IEEE, Scott T. Block, Student Member, IEEE, David E. Duarte, Member, IEEE, and Changzhi Li, Member, IEEE

Abstract—This brief presents a low-voltage subthreshold MOSFETs-based scattered relative temperature sensor that uses a simple regulated current mirror structure. NMOSFETs in the subthreshold region instead of bipolar junction transistors are used as sensing devices for low voltage purpose. Dynamic element matching is implemented to minimize the errors induced by device mismatches. The 3 × 3 sensor nodes with small size are remotely distributed across the chip, whereas the other parts are centralized and shared. Experimental results show that the minimum analog supply voltage can be 0.45 V from −55 ◦ C to 105 ◦ C in a 90-nm process implementation. The measured 3σ relative inaccuracy was less than ±3.5 ◦ C without any calibration. Furthermore, the multilocation thermal monitoring function has been experimentally demonstrated, and a 2.2 ◦ C/mm on-chip temperature gradient was detected. Compared with our previous design, superior line sensitivity and comparable relative accuracy are realized with simpler circuit implementation. Index Terms—Low voltage, multilocation thermal monitoring, relative accuracy, subthreshold MOSFETs, temperature sensor.

I. I NTRODUCTION

O

N-CHIP temperature sensors are widely used in VLSI power management and thermal monitoring for system performance optimization. Multilocation temperature monitoring in modern multicore processors makes it possible to limit leakage and improve computational capabilities through load balancing, and the relative sensing accuracy (intrachip) may be more important than the absolute accuracy (interchip) [1]. In the meantime, a low supply voltage operation is more and more desired for analog function blocks, such as temperature sensors, Manuscript received February 26, 2013; revised May 26, 2013; accepted August 21, 2013. Date of publication October 3, 2013; date of current version November 14, 2013. This work was supported in part by the Semiconductor Research Corporation and in part by the Texas Analog Center of Excellence under task ID: 1836.057. This brief was recommended by Associate Editor A. Bermak. L. Lu and C. Li are with the Department of Electrical and Computer Engineering, Texas Tech University, Lubbock, TX 79409 USA (e-mail: [email protected]; [email protected]). S. T. Block was with the Department of Electrical and Computer Engineering, Texas Tech University, Lubbock, TX 79409 USA. He is now with the Department of Electrical and Computer Engineering, University of California, Davis, CA 95616 USA (e-mail: [email protected]). D. E. Duarte is with Intel Corporation, Hillsboro, OR 79124 USA (e-mail: [email protected]). Color versions of one or more of the figures in this brief are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSII.2013.2281746

as the process technologies keep scaling down and the demand for battery-operation increases. Bipolar junction transistors (BJTs)-based temperature sensors have been studied for years [1]–[3]. With small process yields, BJT devices have been used in individual temperature sensors for which high absolute accuracy is necessary. Less than ±0.2 ◦ C 3σ absolute inaccuracy over military temperature range from −55 ◦ C to 125 ◦ C after one-point calibration has been realized by BJT-based individual temperature sensors in both the conventional 0.7-μm CMOS process and the modern 65-nm CMOS process [2], [3]. However, BJT-based temperature sensors require a high supply voltage or a large chip area, which cannot be easily scaled with process technologies. MOSFETs operating in the subthreshold region exhibit similar exponential I–V relationships to that of BJTs, and have been used in low-voltage reference circuit designs [4], [5], where a proportional-to-absolute-temperature (PTAT) voltage or current can be generated to represent the temperature that is being monitored. Due to the scalable threshold voltage, the operation voltage of the subthreshold MOSFETs can be lower than BJT devices, which enable low supply voltage operation. However, subthreshold MOFSETs exhibit much larger process spreads and mismatches, which limit the accuracy of temperature sensors and increase the calibration cost. In scattered temperature sensors for multilocation thermal monitoring, the sensing devices are distributed at various hot spots while sharing the same bias currents, and the local mismatches between the sensing MOSFETs instead of global process spreads dominate the relative accuracy. Therefore, with proper mismatch-error correction techniques such as dynamic element matching (DEM), reasonable relative accuracy becomes possible for scattered temperature sensors based on subthreshold MOSFETs although MOSFETs suffer from larger local mismatch and process variation than BJTs [6]. Recently, a subthreshold MOSFETs-based relative temperature sensor front-end with a bandgap-based structure has been developed in a 0.5-μm process [7]. The 5 × 5 sensing diode pairs were distributed across the chip, and less than ±2.5 ◦ C noncalibrated relative inaccuracy was obtained. The minimum analog supply was 1 V over the temperature range of interest. In this brief, a subthreshold MOSFETs-based relative temperature sensor front-end with a regulated current mirror

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MOSFETs and the current mirror. Compared with a bandgap structure with an error-corrected amplifier, as in the previous design [7], the error due to the op-amp offset is avoided in the adopted structure. DEM can be used to minimize the mismatch error Δ. Specifically, the positions of the devices, such as the subthreshold MOSFETs and the current mirror, are periodically exchanged so that the mismatch error can be averaged out. III. C IRCUIT D ESIGN D ETAILS A. Circuit Implementation Fig. 1. Simplified schematics of a PTAT voltage/current generator based on a regulated current mirror structure.

structure is investigated and implemented in an IBM 90-nm CMOS process. By utilizing a simple regulator, which is usually available on chip, the proposed sensor front-end achieves low supply voltage and improved supply sensitivity with a simpler implementation. Less than ±3.5 ◦ C relative inaccuracy without calibration from −55 ◦ C to 105 ◦ C is obtained. A simple one-point digital trimming is used to further improve the relative accuracy to ±2 ◦ C. This brief will be organized as follows. Section II explains the low voltage operation in the proposed design and the mismatch-induced error correction. Section III discusses the circuit design details and simulation results. The error sources that contribute to the relative inaccuracy are also carefully analyzed here. Section IV presents the experimental results. A conclusion is drawn in Section V. II. L OW VOLTAGE O PERATION AND E RROR C ORRECTION Fig. 1 shows the adopted structure for the PTAT voltage/ current generation in this brief. MOSFETs M1 and M2 work in the subthreshold region and have a size ratio of 1 : N (N = 3 in this brief), whereas M3 and M4 have the same size in this design. A simple loop amplifier and a regulator are used to reduce the transistor channel length modulations and optimize the line sensitivity. In the subthreshold region, the currents of M1 and M2 are decided by (ignore the body effect of M2 ) ID = 2nμCOX VT2 (W/L) exp [(VGS − VTH )/nVT ]

(1)

where n is the substrate factor in the EKV MOSFET model, μ is the carrier mobility, COX is the gate-oxide capacitance per unit area, VT is the thermal voltage, W and L are the channel width and length, respectively, VGS is the gate–source voltage, and VTH is the threshold voltage. The voltage over resistor R1 (ΔVGS ) is given by kT ln N (2) ΔVGS = n q which is a PTAT voltage assuming n has negligible temperature coefficient [4]. The currents are also PTAT and can be copied to the output for testing purpose. As indicated in (2), ΔVGS is insensitive to the device global process spreads if n is insensitive to process variation. However, the local device mismatches can introduce significant error and modify (2) as ΔVGS = nkT /q ln(N + Δ), where Δ is introduced by the local mismatches of the subthreshold

Fig. 2 shows the detailed block diagram of the proposed scattered relative temperature sensor front-end with the sensing MOSFETs remotely distributed. The line sensitivity can result in a relative sensing error given that the supply voltage can vary when reading the temperature. In order to reduce the transistor channel length modulations and relax the powersupply rejection ratio (PSRR) requirement on the regulator, a simple amplifier (M5 and M6 in Fig. 2) is added. The amplifier senses the current difference between M5 and M3 /M4 and feeds it back to M3 and M4 . The two loops (loop 1: M5 − M6 − M3 − M5 , loop 2: M5 − M6 − M4 − M2 − M1 − M5 ) force the potential at B (drain of M1 /M3 ) to be an accurate value to set the VGS of M5 (loop 1 is a positive feedback loop; loop 2 is a negative feedback loop but stronger than loop 1). Therefore, Vds1 is close to Vds2 , and Vds3 is close to Vds4 regardless of the supply voltage, which improves the supply sensitivity [8]. Capacitor C1 is added in the simple amplifier to avoid possible oscillation. The simulated PSRR of the sensor front-end without the regulator at the worst processvoltage-temperature (PVT) corner is 31 dB. Compared with the bandgap-based structure in [7], a complicated error correction amplifier and the corresponding offset error are avoided in this design. The start-up circuit functions as follows: When the sensor front-end is off, the potential at node A (VA ) is close to Vreg , and no current is in MS1 , MS2 , and RS . MS3 is thus turned on and pulls down VA to kick off the sensor. Once the circuit is started up, the PTAT current will be copied to the large resistor RS and make the VGS of MS3 close to zero to turn off MS3 . The regulator is a simple NMOS input differential pair structure with a second-stage PMOS current driver. With an input reference voltage of 0.35 V, the simulation results in the IBM 90-nm process show that the loaded regulator has a loop gain of 50 dB, a phase margin of 63◦ , and a PSRR of 60 dB at the worst PVT corner (VDD = 0.45 V, Temp. = −55 ◦ C). Fig. 3 presents the simulated line sensitivity comparison between three different versions of designs, namely, the one without the simple amplifier and the regulator; the one with the simple amplifier but without the regulator; and the one with both the amplifier and the regulator. The simple amplifier and the regulator improve the line sensitivity significantly (0.2 ◦ C/V). A more complicated regulator could improve the line sensitivity further, but would unnecessarily increase the design complexity. The sensor node contains only the subthreshold MOSFETs, R1 , and some switches for the DEM1_B and the enabling/ disabling (EN). The occupied area of the sensor nodes should be as small as possible because the area close to hot spots is usually

LU et al.: TEMPERATURE SENSOR FRONT-END IN CMOS WITH RELATIVE INACCURACY

Fig. 2.

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Block diagram of the proposed relative temperature sensor front-end.

It is desirable to minimize the number of long distance routings to avoid disturbing other function blocks and circuits on the chip-under-monitoring. B. Error Sources Analysis

Fig. 3.

Simulated line sensitivities of three different versions of designs.

Fig. 4. Clock signals for DEM1 and DEM2. The usage of clock signals for the error correction chopping as in [7] has been avoided in this design.

expensive. In addition, a smaller sensor node can be deployed closer to the hot spot, so that the measured temperatures are more reliable provided that the temperature gradient can be large at the hot spots [1]. For each sensor node, six analog signals (four for the MOSFETs, one for node G, and one for the analog ground) and 11 digital signals (eight for CLK_DEM1, one for the digital supply, one for the digital ground, and one for the enabling/disabling) are routed to the control center. It should be noted that ratio N can be also realized by the current mirror (M3 , M4 ) while keeping identical sizes for the two subthreshold MOSFETs, which may reduce the signal routings.

As previously discussed, the relative accuracy of the PTAT voltage ΔVGS among the sensor nodes is mainly decided by the mismatches between the subthreshold MOSFETs. In order to minimize the relative inaccuracy, DEM (DEM1_A and DEM1_B in Fig. 2) is applied to M1 and M2 in the sensor nodes, so that the error due to device mismatches can be averaged out. Specifically, M1 and M2 with a size ratio of 1 : 3 are divided into four unit diodes (M is the sensor nodes) with identical sizes. DEM1 is controlled by clocks with specific timing, as shown in Fig. 4. The arrangement of the four unit transistors is changed in a round robin fashion, so that each unit transistor is connected to the left branch exactly once per every four clock phases. DEM2 is implemented for the current mirror in the PTAT center. Fig. 4 includes the clock timing for DEM2. DEM1 is clocked at half the speed of DEM2, so that all the mismatch status can be exhausted and averaged. The clock frequency of the DEMs was set based on the tradeoff between the conversion speed and the settling error [7]. The sensor nodes can be disabled by controlling the “EN” signal and turning off all the eight switches in DEM1_B [7]. Detailed implementation of the enable/disable is shown in Fig. 2. The transmission gate (M9 and M10 ) either pass the DEM clock to control the switch M8 or isolate the clock signal from M8 , and M7 pulls the gate of M8 to ground to turn it off during disabling. It should be noted that, if ΔVGS is directly sampled by onchip analog-to-digital converter (ADC) with Kelvin sensing, the local mismatch on R1 among the sensor nodes does not contribute to the relative inaccuracy of ΔVGS . However, the PTAT current does suffer from the local mismatch of R1 , which

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 60, NO. 11, NOVEMBER 2013

TABLE I C RITICAL T RANSISTOR D IMENSIONS AND R ESISTOR VALUES

introduces additional inaccuracy to the tested PTAT voltage in this brief. Therefore, the tested relative inaccuracy in this brief should be considered conservative compared with a complete system with on-chip ADC. The traces and contacts connecting the PTAT center and the sensor nodes introduce parasitic resistances. In this brief, these resistances are in series with the large output impedances of the MOSFETs drain terminals and can be neglected. In addition, the leakage current of the switches in DEM1_B during disabling may be significant enough at high temperature to harm the PTAT characteristic of the output voltage. Therefore, the switches in DEM1_B have been carefully sized to avoid either significant on-resistance or large leakage current at high temperature (less than 1/50 leakage current and less than 0.5 ◦ C corresponding sensing error). Furthermore, the body effect of M2 in Fig. 1 has been neglected in the analysis, which would have modified the PTAT voltage ΔVGS in Eq. (2) and introduced curvature and error. Detailed mathematical derivation shows that the threshold voltage shift due to the body effect adds to the ΔVGS directly. However, Monte-Carlo simulations at PVT corners have shown that the body effect of M2 introduces negligible threshold voltage shift compared with ΔVGS and the corresponding error is insignificant. Finally, off-chip reference was used for the regulator in this work. An on-chip reference in real application can suffer from line and temperature sensitivities, which varies the regulated supply of the sensor and results in sensing error. However, the introduced error is negligible due to the power rejection of the PTAT center. Some remaining error sources exist. For example, the DEMs only eliminate the 1st order mismatch error, and the process spread/mismatch of the substrate factor n can cause errors. Besides, in thermal management applications of real multi-core digital processor, high frequency switching noise in the supply line and ground can generate high frequency noise in the PTAT output, which reduces the sensing resolution and the measured SNR. Decoupling capacitors should be implemented to address this issue. IV. E XPERIMENTAL R ESULTS The proposed scattered relative temperature sensor front-end was fabricated in an IBM 90-nm CMOS process with a typical N-/P-type threshold voltage of around 0.26 and 0.16 V at room temperature, respectively. Low-threshold PMOS devices have been used. Table I shows the resistor value and the critical transistor dimensions. Fig. 5 shows the chip photograph and the chamber test setup. The 3 × 3 sensor nodes are distributed across the chip, and each occupies an area of 46 × 23 μm2 . The packaged chips were mounted on printed circuit boards and placed in an aluminum box, which serves as a thermal mass to stabilize the temperature. The box was placed in an envi-

Fig. 5.

Chip photograph and the chamber testing setup.

Fig. 6.

Measured line sensitivities with sensor node 6 are enabled.

Fig. 7.

Averaged outputs versus temperature for the nine sensor nodes.

ronment chamber (ESPEC ECT-2) that controlled the testing temperature. A calibrated 100-Ω platinum resistance temperature detector (RTD 100) was used to provide the reference temperature during testing. The platinum resistance was monitored by a digital multimeter (Keithley 2001). The generated PTAT voltages were recorded by a mixed-signal oscilloscope (Agilent MOS9254A). The minimum analog supply voltage for the sensor front-end was measured as 0.45 V from −55 ◦ C to 105 ◦ C. The measured line sensitivities of the front-end with sensor node 6 enabled were 0.28 ◦ C/V, 0.48 ◦ C/V, and 0.48 ◦ C/V at −55 ◦ C, 25 ◦ C, and 105 ◦ C, respectively (see Fig. 6), which are well below significance. The recorded PTAT outputs for all the nine sensor nodes from −55 ◦ C to 105 ◦ C were recorded and averaged (the averaging was realized by an off-chip low-pass filter) (see Fig. 7), which indicates reasonable PTAT linearity. The output spread among the sensor nodes was used to evaluate the relative sensing accuracy. In order to increase the sample size and obtain more reliable 3σ values of the relative errors, three

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Fig. 9. Thermal maps of the chip during the heating experiments when the soldering iron is (a) 300 ◦ F and (b) 400 ◦ F.

Celcius, and the relative error information at room temperature was used to calibrate the map. Fig. 9 shows the thermal maps. The measured on-chip temperature gradients were around 2.2 and 3.5 ◦ C/mm for the three heating temperatures, respectively. V. C ONCLUSION

Fig. 8. (a) Measured relative inaccuracy among 27 sensor nodes from three chips. (b) Relative inaccuracy after one-point digital trimming at 25 ◦ C. TABLE II P ERFORMANCE S UMMARY OF THE P ROPOSED D ESIGN

A subthreshold MOSFETs-based scattered relative temperature sensor front-end with low supply voltage operation has been designed and characterized for low voltage multilocation thermal monitoring. Dynamic error correction techniques, such as DEMs, are used to minimize the error due to device mismatches. The error sources contributing to the relative inaccuracy have been analyzed and carefully minimized. The minimum supply voltage in an IBM 90-nm implementation was measured as 0.45 V from −55 ◦ C to 105 ◦ C. The line sensitivity of the scattered sensor has been improved by adding a simple amplifier consisting of two MOSFETs and powered by a simple two-stage regulator. The sensor node occupies a small area, and the measured 3σ relative inaccuracy is less than ±3.5 ◦ C without any calibration. The multilocation thermal monitoring function has been experimentally demonstrated, and a 2.2 ◦ C/mm temperature gradient was detected. R EFERENCES

chips have been characterized, and their relative inaccuracies without trimming are plotted in the same figure, as shown in Fig. 8(a). The relative inaccuracy (3σ) was less than ±3.5 ◦ C from −55 ◦ C to 105 ◦ C. It should be noted that the tested inaccuracy is conservative due to the local mismatch of resistor R1 in the sensor nodes, as discussed in Section III. Fig. 8(b) shows the relative inaccuracy after one-point trimming at 25 ◦ C and the 3σ relative inaccuracy decreases to ±2 ◦ C. In real applications, this one-point trimming can be easily realized in digital during an initialization phase of the measurement at arbitrary temperature. Table II summarizes the performance of the scattered temperature sensor front-end. After the chamber measurement, the testing board of the scattered temperature sensor front-end was set up at room temperature and a soldering iron was placed on the board close to the chip corner where sensor node 3 is located. This creates a temperature gradient on the chip and simulates the thermal behavior of multicore digital processors when one of the cores is overloaded. The soldering iron was heated to 300 ◦ F and 400 ◦ F, respectively, and the output of each sensor node was recorded. The recorded outputs were mapped to temperature in degrees

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