A Low-Noise, 8.95-11GHz All-Digital Frequency Synthesizer with a Metastability-Free Time-to-Digital Converter and a Sleepy Counter in 65nm CMOS Chen Jiang, Junren Liu, Yumei Huang* and Zhiliang Hong Department of Microelectronics, Fudan University Shanghai 201203, China *Email: [email protected] Abstract—A low-noise 8.95~11GHz all digital frequency synthesizer (ADPLL) with a metastability-free first-order noise shaping time-to-digital converter (TDC) and a high frequency resolution digitally controlled oscillator (DCO) is presented. An input stage for TDC is proposed to solve the problem of metastability and a specific technique is used to power down the high speed counter as soon as the ADPLL is about to lock for power saving consideration. The ADPLL is fabricated in 65nm CMOS technology and the core area is 0.385mm2. With about 8.5μs locking time, the measured phase noise performance at 1MHz offset is -106.4dBc/Hz from a carrier of 10GHz. The ADPLL core consumes 17.52mW from a supply of 1V.

I.

INTRODUCTION

All-digital phase-locked loops (ADPLLs) have emerged as an alternative to conventional analog PLLs recently, and have drawn tremendous research efforts [2][5-8]. The major advantages of ADPLLs over conventional analog PLLs are that ADPLL can avoid large on-chip capacitors and use more cost-effective digital filters instead of the analog loop filters in analog PLL. Also, ADPLLs are more readily to scale down and be fabricated in new processes. Thus, they are more attractive for SoC integration in advanced technologies.

Figure 1. The block diagram of ADPLL

A typical ADPLL architecture is shown in Figure 1. . The counter and time-to-digital converter (TDC) are used for phase detection and the phase error is processed by the loop filter to generate frequency tuning word for the digitally controlled oscillator (DCO) [1]. A ΣΔ modulator is used to enhance the effective frequency resolution of the DCO. In this structure, the resolution of TDC is critical to the in-band phase noise of ADPLL system. Typically resolution of a TDC is determined

by gate delay of the process used, but some techniques have been adopted to improve the resolution, such as vernier TDCs [3], gated-ring oscillator based TDCs [4] and so on. Another important building block is DCO. The frequency resolution and noise performance of the DCO are critical to the out-ofband phase noise of ADPLL system. In this paper, an ADPLL with an output frequency range of 8.95~11GHz will be presented. By utilizing a first-order noise shaping TDC and a fine frequency resolution DCO, a good phase noise performance is achieved. Several new techniques have also been introduced to improve the performance, which will be presented in the following sections. This paper is organized as follows. The ADPLL architecture and its key designing issues are presented in Section II. Details of circuit implementation of the major building blocks are described in Section III. The experimental results are demonstrated in section IV. Finally, a conclusion is drawn in section V. II.

In order to cover a wide output frequency range, the DCO has three separately tuned varactor banks: the coarse tuning bank, the acquisition bank and the tracking bank. Consequently, the total locking process is divided into three steps corresponding to the adjustment of the three frequency control words of DCO, thus TC, TA and TF (composed of integer part TF_I and fractional part TF_F) shown in Figure 2. . The LPM block is responsible for controlling the switches between different locking steps. The transfer function of the adaptive loop filter will be changed according to different locking steps to optimize locking time in coarse tuning as well

This work is supported by Important National Science and Technology Specific Projects of China (No. 2009ZX01031-003-002) and State Key Lab of ASIC & System, Fudan University.

978-1-4673-2213-3/12/$31.00 ©2012 IEEE

ADPLL ARCHITECTURE

The architecture of the proposed ADPLL is illustrated in Figure 2. , which is mainly composed of a high speed counter, a gated-ring oscillator based time-to-digital converter (GRO TDC), a digitally controlled oscillator (DCO) and some other digital parts such as adaptive loop filter (LPF) and lock process monitor (LPM).

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as acquisition steps, and phase noise performance in tracking step separately [1], in order to achieve both fast locking and good phase noise performance. The integer part and the fractional part of the digital phase detection are realized by the high speed counter and TDC, respectively. An asynchronous counter is used for power saving. A multi-path gated-ring oscillator based TDC is used here for its first order noise shaping characteristic [4], which is beneficial for the in-band phase noise of the system. A common problem in ADPLL is the potential in-band phase noise deterioration or spurs which may happen at integer frequency control word (FCW) channels. This corrupting effect is introduced by the non-uniformly spread quantization noise of conventional TDC [2]. While in this ADPLL system, as the inherent error scrambling mechanism in GRO TDC [4], this effect doesn’t exist.

In order to solve this problem, a simple TDC input stage is proposed. The circuit and its timing diagram are shown in Figure 3. It is composed of two DFFs and some inverters. In this circuit, although the problem of metastability may happen to the first DFF if the rising edges of REF and DIV are too close, the second DFF will not be affected and the input of TDC will be at least as large as one DIV period, which ensures the output of TDC to be always reliable. With this method, the TDC will be totally metastability free and noise shaping effect of the GRO TDC can be well preserved. This is very helpful for the system to achieve a good in-band noise performance. It should be noticed that, with this input stage, the output of TDC is one DIV cycle larger.

DCO Interface

When the ADPLL is about to be locked or already locked, the output frequency won’t change much. So with the reliable TDC output, the result of high speed counter is predictable. The relationship of the output frequency with the reference frequency can be expressed as: fout = N f = (N +N )f (1) int out ref frac ref In (1), Nint and Nfrac stand for integer and fractional part of Nout , which can be derived from the history record of phase detection results Φpd. The difference of the two consecutive phase detection results can be expressed as: ΔΦ pd = (Φint - Φint, prev ) - (Φ frac - Φ frac, prev ) = ΔΦ

Figure 2. ADPLL Architecture

In order to take advantage of the noise shaping feature of GRO TDC, an important problem needs to be addressed. As the problem of metastability, when the input signal of the TDC is too small, the TDC won’t be able to handle it correctly. As a consequence, when the rising edges of REF and DIV are too close to each other, the output of TDC will be imprecise. Even though some techniques can be used to avoid disturbance to ADPLL system [5] in metastability, the continuous precise GRO TDC output is disturbed, thus the noise shaping effect will be deteriorated.

int

+ ΔΦ

(2)

frac

As the output frequency will not change much, fout = ΔΦ pd f ≈ f (3) out ref From (1)-(3), the output of the high speed counter can be predicted as: ⎧Φint, prev + Nint −1, if ΔΦ frac − N frac >0.5 ⎪ ⎪⎪Φint, prev + Nint , if −0.5<ΔΦ frac − N frac ≤0.5 Φ int = ⎨ (4) ⎪Φint, prev + Nint +1, if −1.5<ΔΦ frac − N frac ≤−0.5 ⎪ ⎪⎩Φint, prev + Nint + 2, if ΔΦ frac − N frac ≤−1.5

As the output can be perfectly predicted, the high speed counter can be powered down for power saving in this situation. A ΣΔ modulator is used to improve the effective resolution of DCO, meanwhile a high frequency resolution DCO is still required to suppress the high frequency spur introduced by the quantization noise of ΣΔ modulator. The details of the high frequency resolution DCO will be presented in the next section.

(a)

(b) Figure 3. (a) Proposed TDC input stage circuit and (b) timing diagram

III.

CIRCUIT IMPLEMENTION

A. Multi-path gated-ring oscillator based TDC The block diagram of the multi-path gated-ring oscillator based TDC is shown in Figure 4. , which is composed of a multi-path gated-ring oscillator, a readout circuit, a sampling register and a control circuit. As the oscillator state is frozen between measurements, the residue of a given measurement result will be transferred to the next measurement interval, thus a first order noise shaping effect is realized [4].

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A multi-path ring oscillator can have a higher oscillating frequency compared to conventional ring oscillators, which means smaller delay per stage, hence a higher resolution of the TDC [4]. The schematic of the multi-path gated ring oscillator is shown in Figure 5. . The stage number N=29 is chosen. A large N may make the layout design cumbersome, while if N is too small, the oscillation may be not stable.

The structure of a 6-bit asynchronous high speed counter and its timing diagram are shown in Figure 6. . Due to the asynchronous structure and the high working frequency (about 2.5GHz), sampling the counter results correctly is not an easy task. In order to solve this problem, a sampling signal generation circuit is presented in Figure 6. (a). From the timing diagram shown in Figure 6. (b), it’s simple to find out that the sampled output is always 3 larger than the actual value. This offset can be easily calibrated. Also the 6-bit counter can be extended with the signal O_Carry. As the working frequency of the extended part is much lower, a synchronous structure can be used for simplicity. C. High frequency resolution DCO Figure 7. illustrates the high frequency resolution DCO which adopts an LC structure ， shown in Figure 7. (a). A differential planar inductor of 0.6nH is used. The quality factor of the inductor is about 19.4 at 10GHz. The capacitor is composed of three varactor banks and the structure of each type of varactors is shown in Figure 7. (b)(c)(d).

Figure 4. Block diagram of the multi-path GRO TDC

Figure 5. Multi-path gated ring oscillator

B. Asynchronous high speed counter

Figure 7. High frequency resolution DCO (a) DCO structure (b) Coarse tuning bank varactor (c) Acquisition bank varactor (d) Tracking bank varactor

The frequency resolution of the DCO is determined by the switchable capacitors of a single varactor in the tracking varactor bank. In order to achieve a high resolution, the varactor shown in Figure 7. (d) is used. In this structure, the switchable capacitance is determined by the differences between the accumulation and inversion region capacitance of each PMOS and NOMS pair. According to the measurement, a resolution of about 40 KHz is achieved.

(a)

In order to save area and reduce parasites, the 256 varactors in tracking bank are arranged in a 16x16 matrix. A decoder generates the row and column control signals of the matrix according to the DCO frequency tuning word. IV.

EXPERIMENTAL RESULTS

The ADPLL circuit has been fabricated in a 65nm CMOS process. Figure 8. shows the chip micrograph. The chip size is 1.36mm2, and the core area is 0.385mm2.

(b) Figure 6. (a) Schematic of the asynchronous high speed counter (b) Timing diagram

The ADPLL consumes 17.52mW from a 1V supply, among which the TDC consumes 1.50mW, the DCO

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dissipates 3.12mW, the DCO buffer and prescaler consume 4.53mW and the logic circuits dissipate 8.37mW. The high speed counter is powered down when ADPLL is locked and doesn’t consume any power.

proposed ADPLL features high output frequency, large output range and good phase noise performance. TABLE I. Reference Frequency Range(GHz) Reference Frequency(MHz) Loop Bandwidth(KHz) Phase Noise (dBc/Hz)

PERFORMANCE SUMMARY AND COMPARISON This [6] [7] [8] Work 9.75~10.17 2.1~2.8 3.0~3.6 8.95~11 (4.2%) (14.3%) (18.2%) (20.5%) 40

500

3200

About 500

-115 @1MHz

-103.36 @1MHz

-106.4 @ 1MHz

Locking Time (μs)

6.9

N/A

N/A

8.5

Supply(V)

1.0

1.2

1.2

1.0

Power Consumption(mW)

7.1

9.72

80

17.52

Core Area(mm2)

0.352

0.37

0.4

0.385

Technology

90nm

90nm

65nm

65nm

ACKNOWLEDGMENT The author would like to thank Renzhong Xie, Song Hu, Zhenfei Peng, Yaohua Pan, Ran Li and Zhongkai Wang for their sincere help and advices for this work. REFERENCES [1]

[3]

[4]

[5]

[6]

TABLE I. summarizes the ADPLL performance and comparison with the state of art in the literatures. The

CONCLUSION

This paper presents a low-noise 8.95~11GHz ADPLL with a GRO TDC and a high frequency resolution DCO. An input stage for the TDC is proposed to solve the problem of metastability and a specified counter output predict technique is presented to power down the high speed counter for power saving. The ADPLL features high output frequency, large output range and good phase noise performance.

[2]

The measured output frequency range is from 8.95GHz to 11.00GHz, which is about 2.05GHz and 20.5% compared with the central frequency. The locking time is approximately 8.5μs, which is slightly larger because of the three-step locking scheme.

50

N/A

V.

Figure 9. Phase noise performance

40

-100 @1MHz

Figure 8. ADPLL chip micrograph

The phase noise and output spectrum are measured using Agilent E4440A spectrum analyzer. With a 50MHz reference frequency and FCW=200, the measured phase noise from the 10GHz carrier is shown in Figure 9. . The loop bandwidth is about 500KHz. The in-band phase noise at 100KHz offset is about -89.4dBc/Hz, and the out-of-band phase noise at 1MHz is about -106.4dBc/Hz. Because of the inherent error scrambling mechanism in GRO TDC, a flat in-band phase noise performance without any deterioration or spur is achieved, even in integer FCW channels. With a high frequency resolution DCO, the high frequency spur caused by ΣΔ modulator quantization noise is well suppressed. The large spur at about 2MHz offset is probably caused by crosstalk with SPI clock on PCB board which can be removed in practical application.

40

[7]

[8]

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