A Single Supply RS232 Interface for Bipolar A to D Converters Design Note 29 Sean Gold system. Construction also requires close attention to the layout of the system grounds and other aspects of circuit board design to avoid noise problems.2
Designing circuitry for single supply operation is often an attractive simplification for reducing production costs. Yet many applications call for just a few additional supplies to solve simple interface problems. The example presented here describes how an advanced RS232 interface can simplify an A to D converter which processes bipolar signals.
To accommodate bipolar inputs (–5 < VIN < 5), the LTC1094’s negative rail must be biased beyond the extreme signal swing, but below absolute maximum ratings for supplies. A 5.6V Zener diode, D1, provides a sufficient bias because the V– pin draws very little current.
The LT®1180 RS232 transceiver includes a charge pump which produces low ripple supplies with sufficient surplus current to drive a CMOS A to D converter and precision voltage reference. The circuit in Figure 1 operates from a single 5V supply, and draws a total quiescent current of only 37mA. These features make the circuit ideal for applications which must process bipolar signals with minimal support electronics.
The A to D converter communicates with a remote controller via three wires, which carry the clock, the configuration word, and the output data. The chip select signal, CS, is generated from the incoming clock with a peak detector, constructed with a single PNP transistor. R and C are designed to hold the CS pin low for at least one clock period.
The LTC1094 serial A to D converter requires both a low noise supply and reference voltage for accurate operation.1 These design problems are solved with an LT1021 precision reference, which delivers a stable, low noise, 5V signal from the LT1180’s V+ output. Relatively large storage and filter capacitors must be used with the LT1180 to reduce the noise in the system below 1mV for a 12-bit
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
(NOTE 3) R 400kΩ
C 200pF
10µF
Note 1: Refer to the data sheets for the LTC1094/LTC1294. Note 2: An excellent reference on the subject of grounding and low noise circuit design is: “An IC Amplifier User’s Guide to Decoupling, Grounding, and Making Things Go Right for A Change,” by Paul Brokaw, Analog Devices Application Note.
2N3906 220
ANALOG INPUTS ±5V RANGE
2 3 4 5 6 7 8 9 10
LTC1094
20 19 18 17 16 15 14 13 12 11
+
1Ω
6
LT1021-5 4
2
10Ω
NC
10µF
+
4.7µF
1µF
1µF 10kΩ
1µF
D1 1N752A
+
(NOTE 1) 10k 1
4.7µF
+ +
1 2 3
18 17 16 15
4
14
5
LT1180
13
6
12
7 8 NC 9
11
ON/OFF 5V DATA OUT CLOCK IN
5V (NOTE 2)
10 A/D DATA IN DN29 F01
= CLEAN ANALOG GROUND = LOGIC GROUND
NOTE 1: 10kΩ CURRENT LIMIT RESISTORS CAN BE REMOVED IF THE INPUTS ARE GUARANTEED NOT TO EXCEED THE LT1094’s SUPPLY VOLTAGES. NOTE 2: DRIVER OUTPUTS CAN BE PARALLEL FOR GREATER CURRENT DRIVE. NOTE 3: SELECT RC = 4TCLOCK. MINIMIZE C.
Figure 1. A/D Converter Interface 12/89/29_conv
Assuming the logic threshold in the LTC1094 is 1.4V, two useful rules of thumb for selecting R and C are: Design RC to be at least four times the clock period. And select C as small as possible to start the converter quickly. Minor aberrations in the CS signal are unimportant because the CS pin is level sensitive. The PNP is biased from the clean reference supply so very little noise is coupled into the A to D. Additional buffers are unnecessary because the peak detector drives a CMOS input.
A single conversion cycle is shown in Figure 3. The LT1180’s maximum data rate limits the clock speed to 100k baud. The input voltage is 3.33V which generates a bit pattern of alternating 1’s and 0’s. Trace B shows the Chip Select signal, and Trace C shows the gating pulse for the system clock. The complete conversion cycle for a 12-bit converter using an LTC1294 is listed in Figure 4. For this example, the gating signals are adjusted to allow for the two extra bits of data.3
The operating sequence for the LTC1094 is shown in Figure 2. The CS signal switches to a low state less than 1µs after receiving the system clock, and the configuration word may be transmitted after one clock cycle. After the 18 clock cycles required to complete the conversion, the clock must shut off to allow CS to switch to a high state for at least 2µs — the minimum time between conversions. The operating sequence may then be repeated.
Note 3: The LTC1094 in Figure 1 was directly replaced with an LTC1294, with no changes to the circuit.
MSB First Data (MSPF = 1) tCYC CS
CLK START
SEL 1
UNI
DIN
DON’T CARE Hi-Z
DOUT
SFL/ ODD/ DIFF SIGN
SEL 0
MSBF B1
B9 tSMPL
B0
Hi-Z
FILLED WITH ZEROES
DC029 F02
tCONV
Figure 2. LTC1093/4 Operating Sequence Example: Differential Inputs (CH4+, CH5–), Bipolar Mode
A
LT1180 DRIVER OUTPUT
A 0V
B
CS INPUT
0V
0V
C GATING SIGNAL FOR THE SYSTEM CLOCK ALL TRACES 5V/DIV
0V
B
CS INPUT
LT1180 DRIVER OUTPUT
0V DN029 F03
Figure 3. 10-Bit Converter Interface
Data Sheet Download
www.linear.com/LT1180
Linear Technology Corporation
C GATING SIGNAL FOR THE SYSTEM CLOCK
0V
ALL TRACES 5V/DIV
DN029 F04
Figure 4. 12-Bit Converter Interface
For applications help, call (408) 432-1900 dn29f_conv IM/GP 1189 165K • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 1989
