An Ultra Low Noise High Speed CMOS Linescan Sensor for Scientific and Industrial Applications
Boyd Fowler, Janusz Balicki Dana How, Steve Mims Michael D. Godfrey∗ and John Canfield∗
Agilent Technologies Formerly of ∗ Pixel Devices Intl. Inc. Santa Clara, California USA
EI2004 5301A-29, January 2004
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Introduction
• CMOS image sensors have a significant market share in low cost low power applications such as cell phones, and PC cameras • Industrial and scientific applications are still dominated by CCDs • However, linear CMOS image sensors can offer higher performance than CCDs in high speed industrial and scientific applications – Pixel level bandlimiting reduces read noise – CMOS scaling enables ultra high speed readout EI2004 5301A-29, January 2004
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LNL2048
• 2048×1 linear CMOS image sensor implemented in a 0.35µm twin well 1P4M CMOS process • LFPN–CTIA pixel architecture – High sensitivity – Low noise • High speed non–destructive dual port read–out • Electronic shutter and horizontal anti-blooming drains • Programmable operation via JTAG – Multiple readout modes – Pixel level gain (1x, 10x) EI2004 5301A-29, January 2004
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Outline
⇒ • Sensor Architecture • Pixel Circuitry • Readout Circuitry • Measured Results • Summary
EI2004 5301A-29, January 2004
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LNL2048 Block Diagram
ODD PIXEL SHIFT REGISTER AOP AON
IMODE1 IMODE0 TX
2047
Pixels
2046
3
TDO
2
TDI
ODD PIXEL ANALOG PROCESSING
1
TMS
0
TCK
DIGITAL CONTROL
TRSTN
OUTPUT CTRL
EVEN PIXEL ANALOG PROCESSING
PD AEP AEN EVEN PIXEL SHIFT REGISTER
EI2004 5301A-29, January 2004
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Outline
• Sensor Architecture ⇒ • Pixel Circuitry • Readout Circuitry • Measured Results • Summary
EI2004 5301A-29, January 2004
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Pixel Circuitry
• Photodiode – 3µm×6µm nwell–psub – 7µm×9.7µm effective collection area • Low FPN Capacitive transimpedance amplifier (LFPN–CTIA) – High sensitivity / low read noise – Low gain FPN (PRNU) • Capacitive sampling network – Pixel amplifier bandlimiting – Correlated double sampling – Double buffering EI2004 5301A-29, January 2004
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Pixel Schematic RESET S1
A
RESET2
OUTN C5
C1
Output
C3
Mux C2 S2
A OUTP
Photodiode C6 −A LS S3
Pixel Amplifier
B
C4 C7
S4
B
LFPN CTIA C8
Capacitive Sampling Network EI2004 5301A-29, January 2004
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Read On Integration (ROI)
Line n
Line n+1
RESET RESET2 RESET3 S1 S2 S3 S4 A B LS READOUT ENABLE
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Multiple Readouts During Integration (MRDI)
Line n
Line n+1
RESET RESET2 RESET3 S1 S2 S3 S4 A B LS 0
1
2
3
0
1
READOUT ENABLE
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Outline
• Sensor Architecture • Pixel Circuitry ⇒ • Readout Circuitry • Measured Results • Summary
EI2004 5301A-29, January 2004
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Output Multiplexer Architecture Vdd
OUT IN
Vbias 64:1 Mux
16:1 Mux
OUTP
AEP Av=1
Av=1
Av=1
Sensor Output Pixel Ouput
OUTN
AEN Av=1
EI2004 5301A-29, January 2004
Av=1
Av=1
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Outline
• Sensor Architecture • Pixel Circuitry • Readout Circuitry ⇒ • Measured Results • Summary
EI2004 5301A-29, January 2004
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LNL2048 Measurement Setup
• Sensor output is amplified by a gain of 3.9 and then digitized by a 14 bit ADC • Sensor is controlled by an FPGA • Programmable delay line is used to optimize ADC sampling point • Data is captured using high speed CamLink interface • Sensor is configured in high gain mode (10x) • Vdd is set to 3.45V
EI2004 5301A-29, January 2004
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LNL2048 Measured Results vs Design Goals (ROI)
Design Goal Measured Offset FPN RMS <100 54.4 Offset FPN P-P <250 204 Gain FPN P-P <5 3 RMS Read Noise <20 14 Leakage <20 14.7 Nonlinearity <1 1 Conversion Gain 320 294∗ Full Well Capacity >5000 6800∗ Power Dissipation <500 350 Lag (dark to light) <1 0.6 Lag (light to dark) <1 0.6 Maximum Pixel Rate per Output 50 45 Maximum Line Rate 48.7 43.4
∗
Units electrons electrons % electrons e-/pixel/ms % µV/eelectrons mW % % MHz Klines/sec
Notes 22.3µs integration time 22.3µs integration time 70% of saturation 27◦ C
43.9Klines/sec 525nm LED, 0 to 83% Sat 525nm LED, 83% Sat to 0 60◦ C 60◦ C
10x gain mode
EI2004 5301A-29, January 2004
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LNL2048 Measured Results vs Design Goals (MRDI)
Design Goal Measured Offset FPN RMS <4 0.6 Offset FPN P-P <10 11.6 Gain FPN P-P <5 3 RMS Read Noise <3 1.2 Leakage <20 42 Nonlinearity <1 1 Conversion Gain 320 294∗ Full Well Capacity >5000 6800∗ Power Dissipation <500 350 Lag (dark to light) <1 0.6 Lag (light to dark) <1 0.6 Maximum Pixel Rate per Output 40 40 Maximum Line Rate 2.7 2.7
∗
Units electrons electrons % electrons e-/pixel/ms % µV/eelectrons mW % % MHz Klines/sec
Notes 316µs integration time 316µs integration time 70% of saturation 35◦ C
2.7Klines/sec 525nm LED, 0 to 83% Sat 525nm LED, 83% sat to 0 60◦ C 60◦ C
10x gain mode
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LNL2048 Photon Transfer Curve LNL2048SC Photon Transfer Curve (m=1.15, b=43.9, Av=3.9, 1DN=0.999mV) 900 line 1 800
Pixel Variance (DN^2)
700 600 500 400 300 200 100 0 0
100
200
300
400
500
600
700
Pixel Mean (DN)
• Conversion gain = 294µV/e• Read noise = 5.8e- RMS EI2004 5301A-29, January 2004
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LNL2048 Quantum Efficiency QE of PDI LNL2048SC with glass in LCC package_10nm_steps 0.7 line 1 0.6
0.5
QE
0.4
0.3
0.2
0.1
0 3e-07
4e-07
5e-07
6e-07
7e-07
8e-07
9e-07
1e-06
1.1e-06
1.2e-06
Wavelength
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Comparison of LNL2048 to other Published Results SLIS/PVS
60.0
Maximum Pixel Rate per Output Port (MHz)
Higher Performance
50.0
LNL2048SC/PDI ROI LNL2048SC/PDI
P4/DALSA
40.0 MRDI 13x
1.0
EI2004 5301A-29, January 2004
W/CDS
10.0 RMS Readnoise (e−) log scale
WO/CDS
100.0
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LNL2048 Test Image
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Conclusions
• This work demonstrates a 2048 linear CMOS image sensor that out–performs the best linescan CCDs available today. • In the fastest readout mode – 90Mpixel/sec (43.4Klines/sec), i.e. 45Mpixel/sec per output port, – 14e- RMS read noise • In lowest noise mode with 13x oversampling – 80Mpixel/sec (2.7Klines/sec), i.e. 40Mpixel/sec per output port – 1.2e- RMS read noise EI2004 5301A-29, January 2004
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Addendum
• Fairchild Imaging is now producing and selling the LNL2048 • The LNL2048 is used in the Fairchild OWL linescan cameras
EI2004 5301A-29, January 2004
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