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Proceedings 1997 IEEE InternationalSO1Conference, Oct. 1997

Experimental Exploration of Ultra-Low Power CMOS Design Space Using SOIAS Dynamic V, Control Technology Isabel Yang*, Anthony Lochtefeld, Siva Narendra, Anantha Chandrakasan, Dimitri A. Antoniadis Massachusetts Institute of Technology, 39-415, Cambridge, MA 02139 Introduction: Supply voltage scaling to 1V and below, with associated V, scaling, has been identified as a key approach for energy efficient high performance computing[ 1,2,3]. However, V, scaling is ultimately limited by increasing subthreshold leakage current. We experimentally explore the low VDD, VT design space using a variable threshold voltage CMOS technology, Silicon-On-Insulator-with-Active-Substrate (SOIAS), which we have developed [4,5]. Energy consumption modeling indicates that the dynamic V, control afforded by SOIAS can lead to significant energy savings without sacrificing performance for systems that operate in burst mode, for example when limited by user input rate. This is of particular importance in battery operated systems. Device Details: SOIAS CMOS, shown schematically in Figure 1, allows control of NMOS and PMOS threshold voltages through independent back-gate biasing. This enables the experimental evaluation of the ultra-low power design space using the same set of devices; hence, all measured quantities are self-consistent. The design parameters for the devices under study are: silicon thickness 35 nm, top gate oxide 7 nm, back-gate oxide 100 nm, and Le, -0.75um. The nominal (zero back-bias) VT for these devices were k340 mV. Both polarity back-gate biases were applied to achieve a full range of threshold voltages from k50 mV to +650 mV. V D D and VT Design Space Measurements: The delay per stage was obtained from 101-stage inverter ring oscillators, and the switching and static leakage currents were measured on identical inverter chains. Figure 2a-c shows the measured static leakage energy, dynamic switching energy and delay per gate as a function of varying VDD and V, Figure 3 shows the measured total energy for a 101-stage ring oscillator at three different frequencies, with VDD adjusted for constant delay. The trade-off between dynamic switching energy and static leakage energy is clearly evident; the optimal VTfor the chain in continuous operation at these frequencies is 200-250mV.

SOIAS Energy modeling: We applied the measured switching and static leakage currents to the SOIAS energy consumption model developed in [5] to find optimal V, and VDDfor various functional modules in burst-mode operation. For this we define the activity factor, as the fraction of time a module is actually computing; as an example, for an X-server with a user continuously entering data at a keyboard, is only 0.02 to 0.03 [ 6 ] . We consider two modes of operation: constant or dynamic V, For dynamic V , the back-gate is switched when a module is on standby to raise the V, (by 3250mV for -+3VB),cutting static energy dissipation by several orders of magnitude [4]. The energy cost for this is described by the last term in the energy model (Figure 4); only the first two terms, dynamic switching energy and low-V, static leakage energy, apply in constant V, mode. Table 1 lists the front and back-gate activity factors for an adder, shifter and multiplier, as obtained from profiling of a SPEC benchmark program. C,, for the model was extracted from measured dynamic switching currents; the Ioffvalues were measured directly. Table 2 shows the results for minimum total energy for one choice of and fclock. Two levels of optimization are suggested by these results. First, it is clear that in constant VT mode, V, and VDD should be tuned according to system activity, if possible. SOIAS allows VT tuning, and recent advances in high efficiency variable supply voltage generation [7] make it possible to adaptively adjust VDDas well. The dynamic V, strategy represents a second level of optimization, demonstrating extra energy savings of 60-SO%, for this example, by further reducing static energy dissipation.

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References: [ l ] K. Seta, H. Hara, T. Kuroda, M. Kakumu, and T. Sakurai, ISSCC Dig. of Tech. Papers, 1995, p318 [2] Y. Mii, S. Wind, Y.Taur, Y. Lii, D. Klaus, and J. Buchignano, VLSI Technology Symp., June 1994, p9 [3] J.B. Burr, and J. Shott, ISSCC Dig. of Tech. Papers, 1995, p84, [4] I.Y. Yang, C. Vieri, A. Chandrakasan, and D.A. Antoniadis, IEDM Tech. Dig., 1995, p877 [5] I.Y. Yang, C. Vieri, A. Chandrakasan, and D.A. Antoniadis, JEEE TED, May 1997, p822 [6] M. Srivastava, A. Chandrakasan, and R. Brodersen, IEEE Trans. on VLSI Systems, March 1996, p42 [7] V. Gutnik and A. Chandrakasan, VLSI Circuits Symp., June 1996 *Now with Motorola Corp., 3501 Ed Bluestein Blvd., Austin, TX 78721

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Proceedings 1997 IEEE International SO1 Conference, Oct. 1997

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Figure 1: SOIAS back-gated CMOS device schematic.

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